Automatic gain control circuit, microwave component and wireless communication equipment

Abstract

According to the automatic gain control circuit, the microwave assembly and the wireless communication equipment provided by the utility model, by virtue of the large attenuation capability of the first gain control loop and the fine adjustment capability of the second gain control loop, signal input from weak to extremely strong is dealt with, and the dynamic range is greatly widened; according to a high-precision feedback adjustment mechanism, the output signal strength can be stably controlled in a target interval, and the consistency and reliability of signal processing are ensured; meanwhile, for input signals with different sizes, the signal distortion risk is effectively avoided through the synergistic effect of the two stages of loops, noise interference is remarkably reduced, a solid guarantee is provided for stable operation of a wireless communication system, and the anti-distortion performance of the system is greatly improved.

Description

Technical Field

[0001] This utility model belongs to the field of integrated circuit technology, and in particular relates to an automatic gain control circuit, a microwave component, and a wireless communication device. Background Technology

[0002] The development of wireless communication has spurred the development of various microwave components. Microwave components are the core receiving modules in wireless communication systems, processing the signals received by the antenna. In actual communication, the received signal strength may fluctuate drastically due to distance, interference, and other factors. If the signal receiving link is a fixed-gain link, it may cause signal distortion or excessive noise.

[0003] Automatic gain control (AGC) circuitry is installed in the receiving module. It automatically adjusts the gain of the link to the signal based on the strength of the input signal, stabilizing the signal strength output by the receiving module at a suitable level and ensuring the reliability of subsequent processing. However, in traditional technology, AGC circuitry is limited by device power, resulting in a small dynamic range for signal gain adjustment and inability to operate under strong signal conditions. Utility Model Content

[0004] In view of this, the present invention provides an automatic gain control circuit, a microwave component, and a wireless communication device to solve the problems in the traditional technology where the automatic gain control circuit is limited by the power of the device, has a small dynamic range for signal gain adjustment, and cannot work under strong signal conditions.

[0005] The first aspect of this utility model provides an automatic gain control circuit, which includes a first gain control loop and a second gain control loop.

[0006] The first gain control loop includes a first voltage-controlled attenuator, an RF processing module, a first detector, and a first operational amplifier unit; the second gain control loop includes a first gain control module, a second gain control module, an intermediate frequency processing module, a second detector, and a second operational amplifier unit.

[0007] The input terminal of the first voltage-controlled attenuator serves as the signal input terminal, and the output terminal of the first voltage-controlled attenuator is connected to the input terminal of the radio frequency processing module. The first output terminal of the radio frequency processing module is connected to the input terminal of the first detector, and the output terminal of the first detector is connected to the control terminal of the first voltage-controlled attenuator via the first operational amplifier unit.

[0008] The second output terminal of the radio frequency processing module is connected to the input terminal of the first gain control module;

[0009] The first gain control module and the second gain control module are connected in series to the input terminal of the intermediate frequency processing module. The first output terminal of the intermediate frequency processing module is connected to the input terminal of the second detector. The output terminal of the second detector is connected to the control terminals of the first gain control module and the second gain control module via the second operational amplifier unit.

[0010] The second output terminal of the intermediate frequency processing module serves as the signal output terminal, outputting a signal.

[0011] In one possible implementation, the first gain control module includes a second voltage-controlled attenuator and a first amplifier; the second gain control module includes a third voltage-controlled attenuator and a second amplifier.

[0012] The second output terminal of the radio frequency processing module is connected to the input terminal of the second voltage-controlled attenuator.

[0013] The output of the second voltage-controlled attenuator is connected to the input of the first amplifier, the output of the first amplifier is connected to the input of the third voltage-controlled attenuator, the output of the third voltage-controlled attenuator is connected to the input of the second amplifier, and the output of the second amplifier is connected to the input of the intermediate frequency processing module.

[0014] The output of the second detector is connected to the control terminals of the second voltage-controlled attenuator and the third voltage-controlled attenuator via the second operational amplifier unit.

[0015] In one possible implementation, the radio frequency processing module includes a third amplifier, an attenuator, a mixer, a fourth amplifier, a first filter, and a first power divider connected in sequence.

[0016] The output of the first voltage-controlled attenuator is connected to the input of the third amplifier;

[0017] The first output terminal of the first power divider is connected to the input terminal of the first detector;

[0018] The second output terminal of the first power divider is connected to the input terminal of the second voltage-controlled attenuator.

[0019] In one possible implementation, the intermediate frequency processing module includes a fifth amplifier, a second filter, and a second power divider connected in sequence.

[0020] The output of the second amplifier is connected to the input of the fifth amplifier;

[0021] The first output terminal of the second power divider is connected to the input terminal of the second detector;

[0022] The second output terminal of the second power divider serves as the signal output terminal.

[0023] In one possible implementation, the first operational amplifier unit includes a first operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor; the first resistor, the second resistor, the third resistor, and the fourth resistor are variable resistors.

[0024] The first input pin of the first operational amplifier is connected to the first power supply through the first resistor, and the first input pin of the first operational amplifier is grounded through the second resistor.

[0025] The first inverting input pin of the first operational amplifier is connected to the first output pin of the first operational amplifier, and the first inverting input pin of the first operational amplifier is connected to the second inverting input pin of the first operational amplifier through the third resistor;

[0026] The second inverting input pin of the first operational amplifier is connected to the second output pin of the first operational amplifier through the fourth resistor;

[0027] The second input pin of the first operational amplifier is connected to the output terminal of the first detector, and the second output pin of the first operational amplifier is connected to the control terminal of the first voltage-controlled attenuator.

[0028] In one possible implementation, the first operational amplifier unit further includes a first capacitor, a second capacitor, a third capacitor, and a fifth resistor;

[0029] The power supply pin of the first operational amplifier is connected to the first power supply, and the power supply pin is grounded through the first capacitor and the second capacitor connected in parallel;

[0030] The ground pin of the first operational amplifier is grounded;

[0031] The second input pin of the first operational amplifier is connected to the output terminal of the first detector through the fifth resistor; the second output pin of the first operational amplifier is connected to the control terminal of the first voltage-controlled attenuator.

[0032] The second input pin of the first operational amplifier is grounded through the third capacitor.

[0033] In one possible implementation, the second operational amplifier unit includes a second operational amplifier, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor; the sixth resistor, the seventh resistor, the eighth resistor, and the ninth resistor are variable resistors.

[0034] The first input pin of the second operational amplifier is connected to the second power supply through the sixth resistor, and the first input pin of the second operational amplifier is grounded through the seventh resistor;

[0035] The first inverting input pin of the second operational amplifier is connected to the first output pin of the second operational amplifier.

[0036] The first inverting input pin of the second operational amplifier is connected to the second inverting input pin of the second operational amplifier through the eighth resistor;

[0037] The second inverting input pin of the second operational amplifier is connected to the second output pin of the second operational amplifier through the ninth resistor;

[0038] The second input pin of the second operational amplifier is connected to the output of the second detector, and the second output pin of the second operational amplifier is connected to the control terminal of the second voltage-controlled attenuator and the control terminal of the third voltage-controlled attenuator.

[0039] In one possible implementation, the second operational amplifier unit further includes a fourth capacitor, a fifth capacitor, a sixth capacitor, and a tenth resistor;

[0040] The power supply pin of the second operational amplifier is connected to the second power supply, and the power supply pin of the second operational amplifier is grounded through the fourth capacitor and the fifth capacitor connected in parallel;

[0041] The ground pin of the second operational amplifier is grounded;

[0042] The second input pin of the second operational amplifier is connected to the output terminal of the second detector through the tenth resistor; the second output pin of the second operational amplifier is connected to the control terminal of the second voltage-controlled attenuator and the control terminal of the third voltage-controlled attenuator.

[0043] The second input pin of the second operational amplifier is grounded through the sixth capacitor.

[0044] A second aspect of this utility model provides a microwave component, the microwave component including any of the automatic gain control circuits described in the first aspect.

[0045] The third aspect of this utility model provides a wireless communication device, which includes the microwave component as described in the second aspect.

[0046] The automatic gain control circuit, microwave components, and wireless communication equipment provided in this embodiment achieve hierarchical adjustment of signal gain through a two-stage series gain control loop: the first gain control loop uses a feedback system composed of a first voltage-controlled attenuator, a first detector, and a first operational amplifier unit to perform variable gain adjustment on the input signal. When the input signal is strong, the fast response characteristics of the voltage-controlled attenuator are used to quickly reduce the signal strength, preventing damage to subsequent processing modules due to overload; when the input signal is weak, the voltage-controlled attenuator is controlled to maintain a low attenuation state to ensure that the signal can enter the subsequent processing stage intact; the second gain control loop uses two gain control modules to perform in-depth optimization of the signal. The intermediate frequency (IF) processing module converts the radio frequency (RF) signal into an IF signal that is easier to process. The feedback system, consisting of the second detector and the second operational amplifier unit, can monitor the signal strength in real time and generate precise control signals to drive the two gain control modules to finely adjust the signal gain. In the entire signal transmission link, the second gain control loop prioritizes the initial optimization of the enhanced signal and stabilizes the signal strength by dynamically adjusting the gain control module. When the first gain control loop detects that the signal strength exceeds the set threshold, the first voltage-controlled attenuator quickly intervenes and works in conjunction with the second gain control loop.

[0047] In summary, the automatic gain control circuit provided in this embodiment can handle signal inputs ranging from weak to extremely strong by leveraging the large attenuation capability of the first gain control loop and the fine adjustment capability of the second gain control loop, significantly widening the dynamic range. Furthermore, the high-precision feedback adjustment mechanism of the second gain control loop can stably control the output signal strength within the target range, ensuring the consistency and reliability of signal processing. At the same time, when faced with input signals of different magnitudes, the synergistic effect of the two-stage loops effectively avoids the risk of signal distortion, significantly reduces noise interference, provides a solid guarantee for the stable operation of the wireless communication system, and greatly improves the system's anti-distortion performance. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a schematic diagram of an automatic gain control circuit provided in one embodiment of the present invention;

[0050] Figure 2 This is a schematic diagram of the first gain control loop provided in an embodiment of the present invention;

[0051] Figure 3 This is a schematic diagram of the second gain control loop provided in one embodiment of the present invention. Detailed Implementation

[0052] In the following description, specific details such as particular system structures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the present invention. However, those skilled in the art will understand that the present invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

[0053] To illustrate the technical solution of this utility model, specific embodiments are described below.

[0054] See Figure 1 , Figure 1 This is a schematic diagram of an automatic gain control circuit provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the automatic gain control circuit includes a first gain control loop 11 and a second gain control loop 12.

[0055] The first gain control loop 11 includes a first voltage-controlled attenuator 111, an RF processing module 112, a first detector 113, and a first operational amplifier unit 114.

[0056] The second gain control loop 12 includes a first gain control module 121, a second gain control module 122, an intermediate frequency processing module 123, a second detector 124, and a second operational amplifier unit 125.

[0057] In one feasible implementation, the input terminal of the first voltage-controlled attenuator 111 serves as the signal input terminal, and the output terminal of the first voltage-controlled attenuator 111 is connected to the input terminal of the radio frequency processing module 112. The first output terminal of the radio frequency processing module 112 is connected to the input terminal of the first detector 113, and the output terminal of the first detector 113 is connected to the control terminal of the first voltage-controlled attenuator 111 via the first operational amplifier unit 114.

[0058] The second output terminal of the radio frequency processing module 112 is connected to the input terminal of the first gain control module 121.

[0059] The first gain control module 121 and the second gain control module 122 are connected in series to the input terminal of the intermediate frequency processing module 123. The first output terminal of the intermediate frequency processing module 123 is connected to the input terminal of the second detector 124. The output terminal of the second detector 124 is connected to the control terminals of the first gain control module 121 and the second gain control module 122 via the second operational amplifier unit 125.

[0060] The second output terminal of the intermediate frequency processing module 123 serves as the signal output terminal, outputting a signal.

[0061] This embodiment employs a two-stage cascaded gain control loop in the signal transmission link. The first-stage gain control loop adjusts the gain at the input of the receiving link using a voltage-controlled attenuator, while the second-stage gain control loop adjusts the gain in the middle of the receiving link using two-stage gain control modules. As the input signal increases, the later-stage gain control loop initiates control first, followed by the earlier-stage loop. This ensures a large dynamic range and precise control for the entire automatic gain control circuit, while preventing distortion even with large signal inputs.

[0062] See Figure 2 , Figure 2 This is a schematic diagram of the first gain control loop provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the radio frequency processing module 112 includes a third amplifier 1121, an attenuator 1122, a mixer 1123, a fourth amplifier 1124, a first filter 1125, and a first power divider 1126 connected in sequence.

[0063] The output of the first voltage-controlled attenuator 111 is connected to the input of the third amplifier 1121;

[0064] The first output terminal of the first power divider 1126 is connected to the input terminal of the first detector 113;

[0065] The second output terminal of the first power divider 1126 is connected to the input terminal of the second gain control loop.

[0066] Specifically, the first voltage-controlled attenuator 111 includes pins 1-3. Pin 1 (RFin) is the RF signal input terminal, used to receive the input RF signal. It is the interface for the signal to enter the voltage-controlled attenuator and can be connected to a signal source or the output terminal of the pre-amplifier circuit. Pin 2 (RFout) is the RF signal output terminal. The RF signal after attenuation is output from this pin and is used to connect to the subsequent circuit or the target device. Pin 3 is the control terminal, used to connect the control voltage to control the attenuation amount. By changing the magnitude of the input control voltage, the attenuation degree of the attenuator on the input RF signal can be adjusted.

[0067] Specifically, the first voltage-controlled attenuator 111 has the model number NC1391C-2040.

[0068] In one feasible implementation, the third amplifier 1121 is model HGC344, including pins 1-3. Pin 1 (IN) is the signal input terminal, used to receive the input signal to be amplified, and is the interface for external signals to enter the amplifier; pin 2 (OUT) is the signal output terminal, which outputs the amplified signal to the subsequent circuit; pin 3 is the power supply pin, connected to a +5V power supply, to provide the power required for the operation of the amplifier's internal circuit.

[0069] The third amplifier 1121 also includes corresponding peripheral circuitry. Capacitors C6 and C7 are connected in parallel between the +5V power supply and ground to filter the power supply. Capacitor C6 is a high-frequency bypass capacitor that filters out high-frequency noise in the power supply; capacitor C7 is mostly a low-frequency filter capacitor that suppresses low-frequency ripple in the power supply, ensuring a stable and clean power supply to the amplifier, enabling the amplifier to operate stably.

[0070] In one feasible implementation, the attenuator 1122 is model IFA-123, including pins 1-6. Pins 1 and 2 (RF2) are a set of radio frequency signal ports. Pin 1 is the input terminal of this set of signals, used to receive radio frequency signals; pin 2 is the output terminal, which outputs the radio frequency signal after a certain attenuation. Pins 3 and 4 (RF1) are a set of radio frequency signal ports. Pin 3 is the input terminal, which receives the input radio frequency signal; pin 4 is the output terminal, which outputs the attenuated radio frequency signal. Pins 5 and 6 (RF3) are also a set of radio frequency signal ports. Pin 5 is the input terminal, and pin 6 is the output terminal, realizing the attenuation output of the input radio frequency signal.

[0071] In one feasible implementation, the mixer 1123 is model IMX-0743A, including pins 1-3. Pin 1 (RF) is the radio frequency signal input terminal, used to receive the radio frequency signal to be mixed, which usually comes from the antenna receiver or the pre-amplifier circuit, etc. Pin 2 (LO) is the local oscillator signal input terminal, which is connected to the local oscillator signal generated by the local oscillator. The local oscillator signal provides a stable reference frequency signal for the mixing process. Pin 3 is the intermediate frequency signal output terminal, which outputs the intermediate frequency signal after mixing. The frequency of this signal is the sum or difference frequency of the radio frequency signal and the local oscillator signal.

[0072] The intermediate frequency (IF) signal output from pin 3 of mixer 1123 is connected to an external circuit consisting of resistors R2, R3, and R4. Resistor R2 is connected in series in the signal path, while resistors R3 and R4 are connected in parallel to ground, together performing voltage division, biasing, or impedance matching on the IF signal.

[0073] Specifically, the fourth amplifier 1124, model number ILA-0003A-CQ4, includes pins 1-24. Pin 19 (Vdd) is the positive power input terminal, connected to an external +5V power supply, providing the power required for the amplifier's internal circuitry. Pins 1, 5, 6, 14, 15, 17, 22, and 23 are ground pins (GND), providing a stable low-potential reference for the amplifier, ensuring normal circuit operation, and also helping to filter noise. Pin 3 (RFin) is the RF signal input terminal, used to receive the RF signal to be amplified, serving as the interface for external signals to enter the amplifier. Pin 16 (RFout) is the RF signal output terminal, outputting the amplified RF signal to subsequent circuits. Pins 2, 4, 7-13, 18, 20, and 21 are no-connection pins (NC), and are not used for connection in this circuit.

[0074] The fourth amplifier 1124 also includes corresponding peripheral circuitry. In the power supply section, pin 19 (Vdd) is connected to a +5V power supply via inductor L1, which suppresses high-frequency noise and stabilizes the power supply. Simultaneously, capacitors C1 and C2 are connected in parallel between the power supply and ground, forming a filter circuit to further filter out high-frequency and low-frequency noise from the power supply, ensuring a clean and stable power supply to the amplifier. In the input section, pin 3 (RFin) is connected to an external RF signal source via capacitor C3, which blocks DC while allowing AC, preventing the DC component of the external signal source from affecting the amplifier's internal operating point and allowing only AC RF signals to enter the amplifier. In the output section, pin 16 (RFout) is connected to subsequent circuitry via inductor L2 and resistor R1. L2 may be used for impedance matching or signal filtering, while R1 serves for current limiting, voltage division, or impedance adjustment. Capacitor C4 is connected in series at the output, similarly blocking DC while allowing AC, ensuring the output AC RF signal is transmitted smoothly to the subsequent circuitry while blocking DC components.

[0075] The first filter 1125 is model BLLBP429-60-01A, which includes pin 1 and pin 2. Pin 1 (I) is the signal input terminal, which receives the signal from the detector and other pre-stage circuits. This signal contains RF signal amplitude information and possible noise. Pin 2 (O) is the signal output terminal, which outputs the filtered signal to generate the gain control signal.

[0076] The first power divider 1126 is model SBTC-2-10+. Pins 1 and 2 are ground pins, connected to ground (GND) to provide a stable potential reference for the circuit, suppressing noise, enhancing circuit grounding stability, and reducing interference. Pin 3 (P1): Output terminal, connected to the second gain control loop 12 via capacitor C5. Capacitor C5 acts as a DC-blocking and AC-passing capacitor, allowing AC signals to be smoothly transmitted to subsequent circuits while blocking DC components. Pin 4 (P2): Output terminal, directly connected to the first detector 113 to output the divided signal. Pin 5: Input terminal, receiving the input signal and serving as the signal input interface for the power divider. GND pin: Ground pin, connected to ground (GND) to further ensure circuit potential stability and improve anti-interference capability.

[0077] For example, the first detector 113 is model AD8361ART, including pins 1-6. Pin 1 (VRMS) is the RMS voltage output terminal, outputting the RMS voltage of the signal after detection. Pin 2 (COMM): common terminal, directly grounded in this circuit, providing a potential reference; Pin 3 (FLTR): filter connection terminal, connected to pin 1 through capacitor C12 to form a filter circuit, stabilizing the output signal; Pin 4 (PWDN): power-down control terminal, grounded to indicate normal operation (low level enable), connecting to a high level may enter a low-power mode; Pin 5 (RFIN): RF signal input terminal, receiving the external RF signal to be detected through capacitor C10, which acts as DC blocking and AC passing; Pin 6 (VPOS): positive power supply terminal, connected to a +5V power supply to power the detector, and filtered by capacitors C13 and C14 to remove power supply noise and ensure stable power supply.

[0078] The first detector 113 also includes corresponding peripheral circuits. The connection between the first detector 113 and the corresponding peripheral circuits includes: pin 6 (VPOS) is connected to +5V; capacitors C13 and C14 are connected in parallel between the power supply and ground to form a filter circuit to suppress power supply ripple and noise; the output signal of the first power divider 1126 is connected to pin 5 (RFIN) after passing through the circuit composed of R8, R12, and R13, and then through R11 and capacitor C10. Capacitor C10 blocks the DC component, allowing only AC RF signals to be input to the first detector 113; pin 1 (VRMS) is connected to pin 3 (FLTR) through capacitor C12 to form a filter network, smoothing the output signal and reducing high-frequency interference; pin 4 (PWDN) is grounded to put the detector in working condition; pin 2 (COMM) is directly grounded to provide a stable potential reference.

[0079] In one feasible implementation, the first operational amplifier unit 114 includes a first operational amplifier, a first resistor R6, a second resistor R10, a third resistor R7, a fourth resistor R5, a first capacitor C8, a second capacitor C9, a third capacitor C11, and a fifth resistor R9; wherein the first resistor R6, the second resistor R10, the third resistor R7, and the fourth resistor R5 are variable resistors.

[0080] The first input pin of the first operational amplifier is connected to the first power supply through the first resistor R6, and the first input pin of the first operational amplifier is grounded through the second resistor R10; the first inverting input pin of the first operational amplifier is connected to the first output pin of the first operational amplifier, and the first inverting input pin of the first operational amplifier is connected to the second inverting input pin of the first operational amplifier through the third resistor R7; the second inverting input pin of the first operational amplifier is connected to the second output pin of the first operational amplifier through the fourth resistor R5; the second input pin of the first operational amplifier is connected to the output terminal of the first detector, and the second output pin of the first operational amplifier is connected to the control terminal of the first voltage-controlled attenuator.

[0081] The first operational amplifier unit 114 also includes a first capacitor C8, a second capacitor C9, a third capacitor C11, and a fifth resistor R9: the power supply pin of the first operational amplifier is connected to a first power supply, and the power supply pin is grounded through the first capacitor C8 and the second capacitor C9 connected in parallel; the ground pin of the first operational amplifier is grounded; the second input pin of the first operational amplifier is connected to the output terminal of the first detector through the fifth resistor R9; the second output pin of the first operational amplifier is connected to the control terminal of the first voltage-controlled attenuator; and the second input pin of the first operational amplifier is grounded through the third capacitor C11.

[0082] In one example, the first operational amplifier is model AD8606ARZ, including pins 1 to 8. Pin 1 (OUT1) is the output of the first operational amplifier, outputting the signal processed by the first stage of operational amplification; pin 2 (IN1(-)) is the inverting input, used to receive the inverted input signal; pin 3 (IN1(+)) is the non-inverting input, grounded, and is one of the signal inputs of the operational amplifier, participating in differential signal processing; pin 4 (GND) is the negative power supply input, directly grounded to provide a low-potential reference; pin 5 (IN2(+)) is the... The non-inverting input of the two operational amplifiers is grounded through R9 and connected in parallel with C11; pin 6 (IN2(-)) is the inverting input of the second operational amplifier, which is connected to pin 1 (OUT1) through resistor R7 to form a negative feedback loop; pin 7 (OUT2) is the output of the second operational amplifier, which outputs the signal processed by the second stage of operational amplification and is connected to the control terminal of the first voltage-controlled attenuator 111; pin 8 (Vcc) is the positive power input, which is connected to an external +5V power supply to provide the operating voltage for the internal circuit of the operational amplifier, and capacitors C8 and C9 are connected in parallel for power supply filtering.

[0083] See Figure 3 , Figure 3 This is a schematic diagram of the second gain control loop provided in an embodiment of the present invention, as shown below. Figure 3 As shown,

[0084] The first gain control module 121 includes a second voltage-controlled attenuator 1211 and a first amplifier 1212; the second gain control module 122 includes a third voltage-controlled attenuator 1221 and a second amplifier 1222.

[0085] Correspondingly, the second output terminal of the RF processing module 112 is connected to the input terminal of the second voltage-controlled attenuator.

[0086] The output of the second voltage-controlled attenuator 1211 is connected to the input of the first amplifier 1212. The output of the first amplifier 1212 is connected to the input of the third voltage-controlled attenuator 1221. The output of the third voltage-controlled attenuator 1221 is connected to the input of the second amplifier 1222. The output of the second amplifier 1222 is connected to the input of the intermediate frequency processing module 123. The output of the second detector 124 is connected to the control terminals of the second and third voltage-controlled attenuators via the second operational amplifier unit 125.

[0087] For example, in this invention, the second gain control loop may include two or more gain control modules.

[0088] In one feasible implementation, the second voltage-controlled attenuator 1211 is model HGC2201LC4, including pins 1-16, wherein: pin 1 (GND): ground, providing a reference potential for the circuit; pin 2 (NC): unused, not connected to external circuits; pin 3 (RFout): RF signal output terminal, used to output the attenuated RF signal; pin 4 (NC): unused, not connected to external circuits; pins 5, 6, 7, and 8 (GND): all grounded, ensuring a common ground for the circuit and a stable operating potential; pin 9 (NC): unused, not connected to external circuits; pin 10 (R... Pin 11 (NC): RF signal input, receives the RF signal to be processed; Pin 12 (GND): Ground; Pin 13 (GND): Ground; Pin 14 (VC): Control voltage input, connected to the control voltage output of the second operational amplifier through resistor R21, used to adjust the attenuation; Pin 15 (VDD): Power input, connected to +5V power supply, and grounded through parallel capacitors C28 and C29, serving as a filter to stabilize the power supply voltage; Pin 16 (MODE): Mode pin, grounded, sets the operating mode of the voltage-controlled attenuator.

[0089] The voltage-controlled attenuator receives the RF signal through pin 10 (RFin), processes it internally, and outputs it from pin 3 (RFout). Pin 14 (VC) receives the control voltage to adjust the attenuation, pin 15 (VDD) provides power and filters the signal, and pin 16 (MODE) is grounded to determine the operating mode. All GND pins ensure that the circuit has a common ground.

[0090] The first amplifier 1212, model number ILA-0003A-CQ4, includes pins 1-24. See the fourth amplifier 1124 for details, which will not be repeated here. The first amplifier 1212 also includes corresponding peripheral circuitry, including capacitors C23, C15, and C16, inductor L6, and resistor R14. See [link to documentation] for details. Figure 3 .

[0091] The third voltage-controlled attenuator 1221 is model HGC2201LC4, including pins 1-16. The peripheral circuit corresponding to the third voltage-controlled attenuator 1221 includes capacitors C24, C26, and C27, as well as resistor R20. The connection of the third voltage-controlled attenuator 1221 and its corresponding peripheral circuit is the same as that of the second voltage-controlled attenuator 1211, and will not be described again.

[0092] The second amplifier 1222, model number ILA-0003A-CQ4, includes pins 1-24. The second amplifier 1222 also includes corresponding peripheral circuitry, including capacitors C25, C17, and C18, inductor L7, and resistor R15. (See attached diagram.) Figure 3For details, please refer to the fourth amplifier 1124, which will not be repeated here.

[0093] In one feasible implementation, the intermediate frequency processing module 123 includes a fifth amplifier 1231, a second filter 1232, and a second power divider 1233 connected in sequence; the output terminal of the second amplifier 1232 is connected to the input terminal of the fifth amplifier 1231; the first output terminal of the second power divider 1233 is connected to the input terminal of the second detector 124; and the second output terminal of the second power divider 1233 serves as the signal output terminal.

[0094] In one example, the fifth amplifier 1231 is model IHLN-009A-S89M, including pins 1-3. The fifth amplifier 1231 also includes corresponding peripheral circuitry, including capacitors C19, C20, and C21, see [link to documentation]. Figure 3 For details, please refer to the third amplifier 1121, which will not be repeated here.

[0095] In one feasible implementation, the second filter 1232 is model BLLBP429-60-01A, including pin 1 and pin 2. For details, please refer to the first filter 1125, which will not be described again.

[0096] See Figure 3 The second power divider 1233 includes pins 1-5, which are detailed in the first power divider 1126 and will not be repeated here. Among them, pin 3 (P1) of the second power divider 1233 serves as the signal output terminal, outputting the divided signal to the second detector 124 and the next stage circuit.

[0097] In one example, the peripheral circuit corresponding to the second power divider 1233 includes R16, R17, R18, R19, R22, and R23. See [link to connection details] for more information. Figure 3 .

[0098] In one feasible implementation, the second detector 124 is an AD8361ART, including pins 1-6. The second detector 124 also includes corresponding peripheral circuitry, including capacitors C32, C34, C35, and C36, and resistor R29. (See attached diagram.) Figure 3 For details, please refer to the first detector 113, which will not be described again.

[0099] In one example, the second operational amplifier unit 125 includes a second operational amplifier, a sixth resistor R24, a seventh resistor R28, an eighth resistor R26, and a ninth resistor R25; the sixth resistor R24, the seventh resistor R28, the eighth resistor R26, and the ninth resistor R25 are all variable resistors.

[0100] The first input pin of the second operational amplifier is connected to the second power supply through the sixth resistor R24, and the first input pin of the second operational amplifier is grounded through the seventh resistor R28; the first inverting input pin of the second operational amplifier is connected to the first output pin of the second operational amplifier; the first inverting input pin of the second operational amplifier is connected to the second inverting input pin of the second operational amplifier through the eighth resistor R26; the second inverting input pin of the second operational amplifier is connected to the second output pin of the second operational amplifier through the ninth resistor R25; the second input pin of the second operational amplifier is connected to the output terminal of the second detector 124, and the second output pin of the second operational amplifier is connected to the control terminal of the second voltage-controlled attenuator 1211 and the control terminal of the third voltage-controlled attenuator 1221.

[0101] In one feasible implementation, the second operational amplifier unit 125 further includes a fourth capacitor C30, a fifth capacitor C31, a sixth capacitor C33, and a tenth resistor R27; the power supply pin of the second operational amplifier is connected to a second power supply, and the power supply pin of the second operational amplifier is grounded through the fourth capacitor C30 and the fifth capacitor C31 connected in parallel; the ground pin of the second operational amplifier is grounded; the second input pin of the second operational amplifier is connected to the output terminal of the second detector 124 through the tenth resistor R27; the second output pin of the second operational amplifier is connected to the control terminal of the second voltage-controlled attenuator 1211 and the control terminal of the third voltage-controlled attenuator 1221; the second input pin of the second operational amplifier is grounded through the sixth capacitor (C33).

[0102] Specifically, the second operational amplifier is model AD8606ARZ, including pins 1 to 8. For details, please refer to the first operational amplifier, which will not be repeated here.

[0103] In one or more embodiments of this invention, the detector of the first gain control loop is located in the middle of the entire receiving link. The detected voltage output by the first detector is amplified by the first operational amplifier and filtered before being used as the control voltage to control the first voltage-controlled attenuator. The detector of the second gain control loop is located immediately adjacent to the output of the entire receiving link. The detected voltage output by the second detector is amplified by the second operational amplifier and filtered before being used as the control voltage to control the second and third voltage-controlled attenuators.

[0104] The entire receiving link has a gain of 90 dBc. When the input signal power is very low, for example, less than -100 dBm, neither the first nor the second gain control loop is activated. As the input signal increases, the detector voltage also increases. Because the detector in the second gain control loop is closer to the link output, its detection voltage will be higher than that of the first gain control loop, thus activating the second gain control loop first. When the input signal increases to a certain value, the detection voltage of the first gain control loop will reach the activation threshold, and the voltage-controlled attenuator in the first gain control loop will begin to attenuate. Because the voltage-controlled attenuator in the first gain control loop is located at the input, it also prevents amplifier saturation and large signal distortion when a large signal is input.

[0105] In one example, the control voltage V1 of the first gain control loop is:

[0106]

[0107] The control voltage V2 of the second gain control loop is:

[0108]

[0109] Among them, V 检1 It is the detection voltage of the first detector, V 检2 It is the detection voltage of the second detector. By combining the characteristics of the detector and the voltage-controlled attenuator with the above formula, a large dynamic automatic gain control (AGC) circuit can be realized.

[0110] In this invention, the design of the voltage-controlled attenuator in the second gain control loop being activated first ensures that the noise does not deteriorate; the first gain control loop is close to the input end and can attenuate when a large signal is input, avoiding saturation of the amplifier on the link and ensuring no distortion when a large signal is input; the detector position of the second gain control loop is set at the end of the link, and a positive AGC circuit is used, which has strong control capability and high control accuracy.

[0111] In one example, in one or more embodiments of the utility model, capacitors C1, C15, C17, and C19 are 0603 packaged capacitors with a capacitance of 100 picofarads (pF); capacitors C2, C8, C13, C16, C18, C26, C28, C30, and C35 are 0603 packaged capacitors with a capacitance of 1 microfarad (µF); capacitors C3 and C4 are 0603 packaged capacitors with a capacitance of 25 pF; capacitors C5, C10, C21, and C22... 2. C23, C24, C25, and C32 are 0603 packaged capacitors with a capacitance of 500pF; C9, C12, C14, C27, C29, C31, C34, and C36 are 0603 packaged capacitors with a capacitance of 1000pF; C11 and C33 are 0603 packaged capacitors with a capacitance of 10uF; C20 is a 0603 packaged capacitor with a capacitance of 2.2uF; Inductors L1, L3, and L4 are 0603 packaged capacitors. 3. Inductors with an inductance of 1 microhenry (µH); inductors L2, L6, and L7 are 0603 packaged inductors with an inductance of 220 nanohenry (nH); inductor L5 is a 0603 packaged inductor with an inductance of 270 nH; resistors R1, R14, and R15 are 0603 packaged resistors with a resistance of 10 ohms; resistors R2, R8, R16, and R19 are 0603 packaged resistors with a resistance of 12 ohms; resistors R3, R4, R12, and R1... 3. R17, R18, R22, and R23 are 0603 packaged resistors with a resistance of 430 ohms; R9, R27, R20, and R21 are 0603 packaged resistors with a resistance of 1 kΩ; R11 and R29 are 0603 packaged resistors with a resistance of 63.4 ohms; R5, R25, R6, R24, R7, R10, R26, and R28 are 0603 packaged resistors, and their resistance values ​​are calculated based on the detection voltage.

[0112] With the above settings, this invention can achieve a large dynamic range adjustment of the input power from -90dBm to 0dBm, and adjust the output signal power to 0±0.5dBm.

[0113] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be included within the protection scope of this utility model.

Claims

1. An automatic gain control circuit, characterized in that, The automatic gain control circuit includes a first gain control loop and a second gain control loop. The first gain control loop includes a first voltage-controlled attenuator, an RF processing module, a first detector, and a first operational amplifier unit; the second gain control loop includes a first gain control module, a second gain control module, an intermediate frequency processing module, a second detector, and a second operational amplifier unit. The input terminal of the first voltage-controlled attenuator serves as the signal input terminal, and the output terminal of the first voltage-controlled attenuator is connected to the input terminal of the radio frequency processing module. The first output terminal of the radio frequency processing module is connected to the input terminal of the first detector, and the output terminal of the first detector is connected to the control terminal of the first voltage-controlled attenuator via the first operational amplifier unit. The second output terminal of the radio frequency processing module is connected to the input terminal of the first gain control module; The first gain control module and the second gain control module are connected in series to the input terminal of the intermediate frequency processing module. The first output terminal of the intermediate frequency processing module is connected to the input terminal of the second detector. The output terminal of the second detector is connected to the control terminals of the first gain control module and the second gain control module via the second operational amplifier unit. The second output terminal of the intermediate frequency processing module serves as the signal output terminal, outputting a signal.

2. The automatic gain control circuit according to claim 1, characterized in that, The first gain control module includes a second voltage-controlled attenuator and a first amplifier; the second gain control module includes a third voltage-controlled attenuator and a second amplifier; The second output terminal of the radio frequency processing module is connected to the input terminal of the second voltage-controlled attenuator. The output of the second voltage-controlled attenuator is connected to the input of the first amplifier, the output of the first amplifier is connected to the input of the third voltage-controlled attenuator, the output of the third voltage-controlled attenuator is connected to the input of the second amplifier, and the output of the second amplifier is connected to the input of the intermediate frequency processing module. The output of the second detector is connected to the control terminals of the second voltage-controlled attenuator and the third voltage-controlled attenuator via the second operational amplifier unit.

3. The automatic gain control circuit according to claim 2, characterized in that, The radio frequency processing module includes a third amplifier, an attenuator, a mixer, a fourth amplifier, a first filter, and a first power divider connected in sequence. The output of the first voltage-controlled attenuator is connected to the input of the third amplifier; The first output terminal of the first power divider is connected to the input terminal of the first detector; The second output terminal of the first power divider is connected to the input terminal of the second voltage-controlled attenuator.

4. The automatic gain control circuit according to claim 2, characterized in that, The intermediate frequency processing module includes a fifth amplifier, a second filter, and a second power divider connected in sequence. The output of the second amplifier is connected to the input of the fifth amplifier; The first output terminal of the second power divider is connected to the input terminal of the second detector; The second output terminal of the second power divider serves as the signal output terminal.

5. The automatic gain control circuit according to any one of claims 1-4, characterized in that, The first operational amplifier unit includes a first operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor; the first resistor, the second resistor, the third resistor, and the fourth resistor are variable resistors. The first input pin of the first operational amplifier is connected to the first power supply through the first resistor, and the first input pin of the first operational amplifier is grounded through the second resistor. The first inverting input pin of the first operational amplifier is connected to the first output pin of the first operational amplifier, and the first inverting input pin of the first operational amplifier is connected to the second inverting input pin of the first operational amplifier through the third resistor; The second inverting input pin of the first operational amplifier is connected to the second output pin of the first operational amplifier through the fourth resistor; The second input pin of the first operational amplifier is connected to the output terminal of the first detector, and the second output pin of the first operational amplifier is connected to the control terminal of the first voltage-controlled attenuator.

6. The automatic gain control circuit according to claim 5, characterized in that, The first operational amplifier unit further includes a first capacitor, a second capacitor, a third capacitor, and a fifth resistor; The power supply pin of the first operational amplifier is connected to the first power supply, and the power supply pin is grounded through the first capacitor and the second capacitor connected in parallel; The ground pin of the first operational amplifier is grounded; The second input pin of the first operational amplifier is connected to the output terminal of the first detector through the fifth resistor; the second output pin of the first operational amplifier is connected to the control terminal of the first voltage-controlled attenuator. The second input pin of the first operational amplifier is grounded through the third capacitor.

7. The automatic gain control circuit according to any one of claims 2-4, characterized in that, The second operational amplifier unit includes a second operational amplifier, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor; the sixth resistor, the seventh resistor, the eighth resistor, and the ninth resistor are variable resistors. The first input pin of the second operational amplifier is connected to the second power supply through the sixth resistor, and the first input pin of the second operational amplifier is grounded through the seventh resistor; The first inverting input pin of the second operational amplifier is connected to the first output pin of the second operational amplifier. The first inverting input pin of the second operational amplifier is connected to the second inverting input pin of the second operational amplifier through the eighth resistor; The second inverting input pin of the second operational amplifier is connected to the second output pin of the second operational amplifier through the ninth resistor; The second input pin of the second operational amplifier is connected to the output of the second detector, and the second output pin of the second operational amplifier is connected to the control terminal of the second voltage-controlled attenuator and the control terminal of the third voltage-controlled attenuator.

8. The automatic gain control circuit according to claim 7, characterized in that, The second operational amplifier unit also includes a fourth capacitor, a fifth capacitor, a sixth capacitor, and a tenth resistor; The power supply pin of the second operational amplifier is connected to the second power supply, and the power supply pin of the second operational amplifier is grounded through the fourth capacitor and the fifth capacitor connected in parallel; The ground pin of the second operational amplifier is grounded; The second input pin of the second operational amplifier is connected to the output terminal of the second detector through the tenth resistor; the second output pin of the second operational amplifier is connected to the control terminal of the second voltage-controlled attenuator and the control terminal of the third voltage-controlled attenuator. The second input pin of the second operational amplifier is grounded through the sixth capacitor.

9. A microwave component, characterized in that, The microwave component includes the automatic gain control circuit as described in any one of claims 1-8.

10. A wireless communication device, characterized in that, The wireless communication device includes the microwave component as described in claim 9.

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