Current detection circuit and device and vehicle

Abstract

The utility model discloses a current detection circuit and device and a vehicle, and relates to the technical field of current detection, and the circuit comprises a control unit, the first end of the control unit is connected with the first end of a to-be-detected transistor, and the control unit is used for collecting the current mode of the to-be-detected transistor; the first end of the dormancy detection module is connected with the second end of the transistor to be detected, and the second end of the dormancy detection module is connected with the second end of the control unit; the first end of the work detection module is connected with the second end of the transistor to be detected, the second end of the work detection module is connected with the third end of the control unit, and the control unit is further used for controlling the sleep detection module to collect the first real-time current of the transistor to be detected when the current mode is the sleep mode; and when the first real-time current is greater than a preset current threshold value, the work detection module is controlled to carry out current detection on the transistor to be detected. According to the invention, the functionality of current detection is improved.

Description

Current detection circuits, devices and vehicles Technical Field

[0001] This application relates to the field of current detection technology, and in particular to a current detection circuit, device, and vehicle. Background Technology

[0002] With the increasing use of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), users have also placed higher demands on the current sensing capabilities of MOSFETs.

[0003] Traditional current sensing methods detect the current of a MOSFET using a current sensor in operating mode. However, this method has certain drawbacks. It cannot detect the current in the MOSFET's sleep mode (the current is too small to be detected by the current sensor in operating mode). In other words, this current sensing method is not very functional because it cannot detect the current in the MOSFET's sleep mode. Summary of the Invention

[0004] The main purpose of this application is to provide a current detection circuit, device, and vehicle, which aims to solve the technical problem of low functionality in current detection.

[0005] To achieve the above objectives, this application provides a current detection circuit, the current detection circuit comprising:

[0006] A control unit, the first terminal of which is connected to the first terminal of the transistor under test, is used to acquire the current mode of the transistor under test;

[0007] A sleep detection module, wherein a first terminal of the sleep detection module is connected to a second terminal of the transistor under test, and a second terminal of the sleep detection module is connected to a second terminal of the control unit;

[0008] The working detection module has a first terminal connected to the second terminal of the transistor under test and a second terminal connected to the third terminal of the control unit. The control unit is further configured to control the sleep detection module to collect the first real-time current of the transistor under test when the current mode of the transistor under test is sleep mode, and to control the working detection module to perform current detection on the transistor under test when the first real-time current is greater than a preset current threshold.

[0009] In one embodiment, the second terminal of the sleep detection module includes a first detection output terminal and a first detection control terminal, the second terminal of the working detection module includes a second detection output terminal and a second detection control terminal, and the control unit includes:

[0010] The control chip has a first terminal connected to the first terminal of the transistor under test, a second terminal connected to the first detection output terminal, a third terminal connected to the second detection output terminal, and a fourth terminal connected to both the first detection control terminal and the second detection control terminal.

[0011] In one embodiment, the control unit further includes a logic control chip, the input terminal of which is connected to the fourth terminal of the control chip, the first output terminal of which is connected to the first detection control terminal, and the second output terminal of which is connected to the second detection control terminal.

[0012] In one embodiment, the hibernation detection module includes:

[0013] A sleep current detection sensor is provided, wherein the input terminal of the sleep current detection sensor is connected to the second terminal of the transistor under test, the output terminal of the sleep current detection sensor is connected to the second terminal of the control chip, and the control terminal of the sleep current detection sensor is connected to the output terminal of the logic control chip.

[0014] In one embodiment, the working detection module includes:

[0015] The operating current detection sensor has its input terminal connected to the second terminal of the transistor under test, its output terminal connected to the third terminal of the control chip, and its control terminal connected to the output terminal of the logic control chip.

[0016] In one embodiment, the current detection circuit includes:

[0017] The mode selection module has its control terminal connected to the control chip in the control unit, its input terminal connected to the second terminal of the transistor under test, and its output terminal connected to the first terminal of the sleep detection module and the first terminal of the work detection module.

[0018] In one embodiment, the mode selection module includes:

[0019] A 2-to-1 multiplexer chip is provided, wherein the control terminal of the 2-to-1 multiplexer chip is connected to the control chip, the input terminal of the 2-to-1 multiplexer chip is connected to the second terminal of the transistor under test, the first output terminal of the 2-to-1 multiplexer chip is connected to the first terminal of the sleep detection module, and the second output terminal of the 2-to-1 multiplexer chip is connected to the first terminal of the working detection module.

[0020] In one embodiment, the hibernation detection module includes:

[0021] A first resistor, the first end of which is connected to a comparison current source, and the second end of which is connected to the output of the mode selection module;

[0022] The second resistor has its first end connected to the first end of the first resistor;

[0023] A third resistor, wherein the first end of the third resistor is connected to the second end of the first resistor;

[0024] The current comparator operational amplifier has its positive input terminal connected to the second terminal of the second resistor, its negative input terminal connected to the second terminal of the third resistor, its ground terminal grounded, and its power supply terminal connected to a power source.

[0025] A first capacitor, the first end of which is connected to the positive input terminal of the current comparator operational amplifier, and the second end of which is connected to the negative input terminal of the current comparator operational amplifier;

[0026] The second capacitor has its first terminal connected to the power supply and its second terminal grounded.

[0027] The fourth resistor has its first end connected to the negative input terminal of the current comparator operational amplifier, and its second end grounded.

[0028] The fifth resistor has its first end connected to the positive input terminal of the current comparator operational amplifier, and its second end connected to the output terminal of the current comparator operational amplifier.

[0029] The sixth resistor has its first end connected to the output terminal of the current comparator operational amplifier, and its second end connected to the second terminal of the control unit.

[0030] The third capacitor has its first terminal connected to the second terminal of the sixth resistor, and its second terminal is grounded.

[0031] A diode, wherein the cathode of the diode is connected to the second terminal of the sixth resistor, and the anode of the diode is grounded.

[0032] In addition, to achieve the above objectives, this application also provides a current detection device, which includes the current detection circuit described above.

[0033] In addition, to achieve the above objectives, this application also provides a vehicle that includes the aforementioned current detection device.

[0034] This application provides a current detection circuit, including a control unit, a first terminal of which is connected to a first terminal of a transistor under test (TUT), and the control unit is used to acquire the current mode of the TUT; a sleep detection module, a first terminal of which is connected to a second terminal of the TUT, and a second terminal of which is connected to a second terminal of the control unit; and a working detection module, a first terminal of which is connected to a second terminal of the TUT, and a second terminal of which is connected to a third terminal of the control unit. The control unit is further configured to, when the current mode of the TUT is sleep mode, control the sleep detection module to acquire a first real-time current of the TUT, and when the first real-time current exceeds a preset current threshold, control the working detection module to... The current detection circuit performs current detection on the transistor under test. This current detection circuit acquires the current mode of the transistor under test through the control unit. When the current mode of the transistor under test is sleep mode, the sleep detection module is controlled to acquire the first real-time current of the transistor under test, so as to realize the current detection of the transistor under test in sleep mode. At the same time, when the first real-time current is greater than the preset current threshold, the working detection module is controlled to detect the current of the transistor under test. This realizes the current detection and protection of the transistor under test in sleep mode, thereby avoiding the phenomenon that the current in sleep mode cannot be detected, that is, the current in sleep mode is too small to be detected by the current sensor in working mode (i.e., the working detection module cannot detect the small current changes in sleep mode). Attached Figure Description

[0035] Figure 1 is a schematic diagram of the framework of the first embodiment of the current detection circuit of this application;

[0036] Figure 2 is a schematic diagram of a mode switching of the transistor under test in the current detection circuit of this application;

[0037] Figure 3 is a circuit diagram of the first embodiment of the current detection circuit of this application;

[0038] Figure 4 is a schematic diagram of the module of the first embodiment of the current detection circuit of this application;

[0039] Figure 5 is a circuit diagram of a second embodiment of the current detection circuit of this application.

[0040] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0041] Explanation of icon numbers:

[0042] 200(Q), Transistor under test; 100, Current detection circuit; 10, Control unit; 20, Sleep detection module; 30, Working detection module; IN, Input signal; DEN, Enable signal; PWM, Width modulation signal; Vds, First voltage; Vds1, First voltage threshold; Vvs, Second voltage; Vvs1, Second voltage threshold; Ll1, Current threshold; Ll, Current; 11, Control chip; 12, Logic control chip; 21, Sleep current detection sensor; 31, Working current detection sensor; 40, Mode selection module; R1-R6, First resistor-Sixth resistor; U, Current comparator operational amplifier; C1-C3, First capacitor-Third capacitor; D, Diode; VS, Source voltage; I2t, Overcurrent capability port; OCT, Overcurrent threshold port; IS, Source current port; IDL, Input data port; OUT, Output port; G1, Comparator current source; P, Power supply. Detailed Implementation

[0043] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0044] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0045] The common current sensing method is to use a specific current sensor to sense the current of the MOSFET only in the operating mode. That is, the current sensor's detection result can be used to protect the MOSFET with an electronic fuse. Currently, MOSFETs have five modes: idle (low power or idle), i2t (current and time-based protection), CLS (Capacitive Load Switching), inactive (an intermediate mode between CLS and idle), and sleep mode. Referring to Figure 2, which is a schematic diagram of mode switching for the transistor under test in the current detection circuit of this application, the figure illustrates the switching between different modes. The main control is based on the high and low levels of the enable signal DEN and the input signal IN (where high level can be defined as 1 and low level as 0), as well as the input of PWM (Pulse Width Modulation). Alternatively, the judgment can be based on the relationship between the first voltage Vds and the set first voltage threshold Vds1, the relationship between the second voltage Vvs and the set second voltage threshold Vvs1, and the relationship between the current Ll and the threshold current Ll1. Here, Vds represents the voltage between the source and drain of the transistor under test 200, and Vvs represents the voltage between the source and drain of the transistor under test 200. It is worth noting that the entire switching control process also includes control conditions M1 and M2. The control condition for M1 can be that L1 is less than L11 and SI2t is less than the sum of the overcurrent deviation and the overcurrent hysteresis value. The control condition for M2 can be that SI2t is less than the sum of the overcurrent deviation and the overcurrent hysteresis value. The overcurrent deviation and overcurrent hysteresis value are known values, and SI2t is obtained by collecting parameters from the overcurrent capability port I2t. Therefore, switching between the five modes can be achieved through the above control. In idle, i2t, CLS, and inactive modes, the accuracy of current detection depends on the load and the current detection range. When the load and the chip's current carrying capacity are similar, the sampling accuracy is very high. In sleep mode, because the load consumes 0.XmA current in sleep mode, and consumes hundreds of mA after abnormal wake-up (i.e., the current detected by a specific current sensor in working mode has a step size of mA or higher), the original current accuracy error is too large to be accurately detected. Therefore, it cannot meet the abnormal sleep detection requirements of the controller after sleep mode.

[0046] Therefore, based on the shortcomings of the above current detection circuits, the current detection circuit of this application is proposed. The main solution of the embodiments of this application is: by acquiring the current mode of the transistor under test (TUT) through the control unit, when the current mode of the TUT is sleep mode, the sleep detection module is controlled to acquire the first real-time current of the TUT, thus realizing the current detection of the TUT in sleep mode. At the same time, when the first real-time current is greater than a preset current threshold, the working detection module is controlled to perform current detection on the TUT, so as to realize the current detection and protection of the TUT in sleep mode. This avoids the phenomenon that the current in the MOSFET sleep mode cannot be detected, that is, the current in the sleep mode is small and cannot be detected by the current sensor in the working mode (i.e., the working detection module cannot detect the small current change in the sleep mode). This current detection circuit realizes the current detection in sleep mode by acquiring the first real-time current of the TUT in sleep mode through the sleep detection module, thereby improving the functionality of current detection. When the first real-time current is greater than the preset current threshold, the working detection module is controlled to perform current detection on the TUT, which can ensure the protection of the TUT (i.e., avoid damage to the TUT due to excessive current in sleep mode).

[0047] Based on this, the present application provides a current detection circuit. Referring to Figure 1, Figure 1 is a schematic diagram of the framework of the first embodiment of the current detection circuit of the present application.

[0048] Referring to Figure 1, this application provides a current detection circuit 100, which includes:

[0049] Control unit 10, the first terminal of control unit 10 is connected to the first terminal of transistor under test 200, and control unit 10 is used to acquire the current mode of transistor under test 200;

[0050] The sleep detection module 20 has a first terminal connected to the second terminal of the transistor under test 200, and a second terminal connected to the second terminal of the control unit 10.

[0051] The first end of the working detection module 30 and the working detection module 330 are connected to the second end of the transistor under test 200, and the second end of the working detection module 30 is connected to the third end of the control unit 10. The control unit 10 is also used to control the sleep detection module 20 to collect the first real-time current of the transistor under test 200 when the current mode of the transistor under test is sleep mode, and to control the working detection module 30 to perform current detection on the transistor under test 200 when the first real-time current is greater than a preset current threshold.

[0052] In this embodiment, by adding a sleep detection module 20 in sleep mode to the current detection circuit 100, the current mode of the transistor under test 200 can be acquired based on the control unit 10. The current mode can be one of the above five modes. It can be judged directly based on the above signals, or directly connected to the control terminal of the transistor under test 200 (i.e., one of the first terminals of the transistor under test 200) or the corresponding transistor chip to directly acquire the signal. Of course, since it is only necessary to determine whether it is sleep mode or other modes, it is possible to directly determine whether the conditions for entering sleep mode are met, and thus determine whether it is sleep mode. For example, judging the M2 condition, or the intermediate mode diagnosis is that the input signal IN = 0, can directly determine whether it is sleep mode. When the system is in sleep mode, the sleep detection module 20 is controlled to collect the first real-time current of the transistor under test 200. This control can be achieved by powering the sleep detection module 20 or by connecting the sleep detection module 20 to the second terminal of the transistor under test 200 for current acquisition. The first real-time current refers to the current collected by the sleep detection module 20 in sleep mode. Because the sleep detection module 20 can be a static current sampling circuit, it performs small current detection with an innovative ±0.01mA detection accuracy, overcoming the limitation of not being able to collect current in sleep mode and thus expanding the functionality of the current detection circuit. The collected first real-time current is then compared with a preset current threshold. If the first real-time current is greater than the preset current threshold, the working detection module 30 is controlled to perform current detection on the transistor under test 200. The preset current threshold is the maximum current threshold set by the user in sleep mode (this threshold is adjustable). This threshold can be used to handle abnormal wake-up issues after vehicle sleep mode, ensuring safety in sleep mode. It is worth noting that when the first real-time current exceeds the preset current threshold, the control unit 10 will control the transistor under test 200 to enter a mode other than sleep mode, and the working detection module 30 will use the current detection module 30 to detect the current of the transistor under test 200 to ensure the accuracy of current acquisition and safety in sleep mode. The above current detection circuit can detect the current consumption of the controller after sleep mode, and can provide early alarm and fault handling when abnormalities are found, thereby expanding the functionality of the current detection circuit.

[0053] In this embodiment, a current detection circuit is provided, including a control unit, the first terminal of which is connected to the first terminal of the transistor under test (TUT), and the control unit is used to acquire the current mode of the TUT; a sleep detection module, the first terminal of which is connected to the second terminal of the TUT, and the second terminal of which is connected to the second terminal of the control unit; and a working detection module, the first terminal of which is connected to the second terminal of the TUT, and the second terminal of which is connected to the third terminal of the control unit. The control unit is further used to control the sleep detection module to acquire a first real-time current of the TUT when the current mode of the TUT is sleep mode, and to control the working detection module to acquire a first real-time current of the TUT when the first real-time current is greater than a preset current threshold. This circuit performs current detection on the transistor under test (TUT). The control unit acquires the current mode of the TUT. When the TUT is in sleep mode, the sleep detection module acquires the first real-time current of the TUT, enabling current detection in sleep mode. Simultaneously, when the first real-time current exceeds a preset current threshold, the operating detection module detects the current of the TUT. This achieves current detection and protection for the TUT in sleep mode, avoiding the inability to detect the current in sleep mode (i.e., the current is too small to be detected by the current sensor in operating mode). This current detection circuit improves the functionality of current detection by acquiring the first real-time current of the TUT in sleep mode through the sleep detection module. Furthermore, controlling the operating detection module to detect the current of the TUT when the first real-time current exceeds a preset current threshold ensures protection of the TUT (i.e., preventing damage from excessive current in sleep mode).

[0054] Furthermore, based on the first embodiment of this application described above, a second embodiment of the current detection circuit of this application is proposed. Referring to Figure 3, which is a circuit diagram of the first embodiment of the current detection circuit of this application, the second terminal of the sleep detection module 20 includes a first detection output terminal and a first detection control terminal, the second terminal of the working detection module 30 includes a second detection output terminal and a second detection control terminal, and the control unit 10 includes:

[0055] The control chip 11 has a first terminal connected to the first terminal of the transistor under test 200, a second terminal connected to the first detection output terminal, a third terminal connected to the second detection output terminal, and a fourth terminal connected to the first detection control terminal and the second detection control terminal.

[0056] In one embodiment, the control unit 10 further includes a logic control chip 12, the first output terminal of the logic control chip 12 being connected to the first detection control terminal, and the second output terminal of the logic control chip 12 being connected to the second detection control terminal.

[0057] In this embodiment, the control unit 10 includes a control chip 11 and a logic control chip 12. The control chip 11 can be a commonly used system-on-a-chip or microcontroller, and the logic control chip 12 can be a commonly used logic inverter. The control chip 11 can receive the detection results from the sleep detection module 20 and the detection results or current values ​​from the working detection module 30 through two ports, respectively, and then perform subsequent control. It is worth noting that, to reduce the internal control logic of the control chip 11, it can directly receive the detection results from the sleep detection module 20 and the working detection module 30. Taking the sleep detection module 20 as an example, if a high level is received from the output of the sleep detection module 20 (i.e., the output of the first detection output terminal), it is determined that the current exceeds the threshold in sleep mode, and then subsequent operations are performed, that is, waking up the transistor under test 200 to enter other modes and using the working detection module 30 for current detection. Meanwhile, to accurately use the sensor for current detection, that is, to ensure the lifespan of the sleep detection module 20 by not using it during normal operation, and to reduce the overall circuit loss by not using the working detection module 30 in sleep mode, the fourth terminal of the control chip 11 can be used for control. That is, the control logic of the fourth terminal of the control chip 11 controls the control chip 12 to select the sleep detection module 20 or the working detection module 30 to work. Its internal control logic can output a low level at the fourth terminal of the control chip 11, which wakes up the sleep detection module 20. The wake-up method can be power-on wake-up or connecting the sleep detection module 20 to the second terminal of the transistor under test 200 (such as the output terminal of the transistor under test 200). Thus, it is possible to select which detection module to use to ensure the high efficiency of the entire circuit. At the same time, it is possible to control the sleep detection module 20 to perform current detection in sleep mode, thereby improving the functionality of the current detection circuit.

[0058] In one embodiment, based on the first and / or second embodiments of this application described above, a third embodiment of the current detection circuit of this application is proposed. Referring to FIG4, FIG4 is a schematic diagram of the modules of the first embodiment of the current detection circuit of this application. The sleep detection module 20 includes:

[0059] The sleep current detection sensor 21 has its input terminal connected to the second terminal of the transistor under test 200, its output terminal connected to the second terminal of the control chip 11, and its control terminal connected to the output terminal of the logic control chip 12.

[0060] In one embodiment, the work detection module 30 includes:

[0061] The working current detection sensor 31 has its input terminal connected to the second terminal of the crystal 200 under test, its output terminal connected to the third terminal of the control chip 11, and its control terminal connected to the output terminal of the logic control chip 12.

[0062] In this embodiment, the sleep detection module 20 includes a sleep current detection sensor 21, which is used to detect the current of the transistor 200 under test in sleep mode. At this time, the selection requirement for the sleep current detection sensor 21 is high detection accuracy, such as ±0.01mA, so that the current in sleep mode can be accurately detected. The working detection module 30 includes a working current detection sensor 31, which is used to detect the current of the transistor 200 under test in normal working mode (i.e., other modes other than sleep mode). The detection accuracy of the sensor can be reduced. At this time, the current detection in sleep mode can be realized based on the high-precision sleep current detection sensor 21, thereby improving the functionality of the current detection circuit and ensuring the safety in sleep mode, avoiding overcurrent damage. Referring to Figure 4, a sleep current detection sensor 21 is added to the channel (composed of an integrated package component, that is, the device in the channel is packaged in a circuit board). When the transistor under test 200 switches to sleep mode, the circuit controls the switching from the working current detection sensor 31 to the sleep current detection sensor 21 through the logic control chip 12 to perform static current detection in sleep mode (the threshold of this detection current sensor is adjustable, such as directly changing the set threshold of the sleep current detection sensor 21). When an abnormal current is detected, this status signal is sent to the upstream control chip 11. The control chip 11 receives this instruction and wakes up to handle the abnormality. After the control chip 11 is woken up, the power supply chip switches to non-sleep mode (that is, other modes except sleep mode). The circuit controls the switching from the working current detection sensor 31 through the logic control chip 12 to continue to detect the current of the transistor under test 200. It is worth noting that other protection controls for the transistor under test 200 can also exist in the entire channel, such as overcurrent or short circuit protection. The functions and hardware composition of the entire transistor under test 200 can be as shown in Figure 4 (that is, a sleep current detection sensor 21 is added to the original functions and hardware composition of the transistor under test 200 to realize current detection in sleep mode, so as to improve the functionality of the current detection circuit). It will not be described in detail here.

[0063] Based on the first, second, and / or third embodiments of this application described above, a fourth embodiment of the current detection circuit of this application is proposed. Referring to Figure 5, which is a circuit diagram of the second embodiment of the current detection circuit of this application, the current detection circuit 100 includes:

[0064] The mode selection module 40 has its control terminal connected to the control chip 11 in the control unit 10, its input terminal connected to the second terminal of the transistor under test 200, and its output terminal connected to the first terminal of the sleep detection module 20 and the first terminal of the work detection module 30.

[0065] In one embodiment, the mode selection module 40 includes:

[0066] The 2-to-1 multiplexer chip has its control terminal connected to the control chip 11, its input terminal connected to the second terminal of the transistor under test 200, its first output terminal connected to the first terminal of the sleep detection module 20, and its second output terminal connected to the first terminal of the work detection module 30.

[0067] In this embodiment, the current detection circuit 100 includes a mode selection module 40. The mode selection module 40 can directly select the connection target of the transistor under test 200. That is, when it is determined to be in sleep mode, the second terminal of the transistor under test 200 can be connected to the sleep detection module 20; otherwise, it is disconnected from the sleep detection module 20 and connected to the working detection module 30. The mode selection module 40 can be a two-to-one chip, which enables the second terminal of the transistor under test 200 to be connected to either the sleep detection module 20 or the working detection module 30. The control basis of the two-to-one chip is the output of the control chip 11, and the output of the control chip 11 is related to the current mode of the transistor under test 200. This allows for the selection of the corresponding detection module for detection in different modes, thereby improving the functionality of the current detection circuit and the accuracy of current detection.

[0068] Furthermore, in one embodiment, the hibernation detection module 20 includes:

[0069] The first resistor R1 has its first end connected to the comparison current source G1 and its second end connected to the output of the mode selection module 40.

[0070] The second resistor R2 is connected to the first end of the first resistor R1.

[0071] The third resistor R3 has its first end connected to the second end of the first resistor R1.

[0072] The positive input terminal of the current comparator operational amplifier U is connected to the second terminal of the second resistor R2, the negative input terminal of the current comparator operational amplifier U is connected to the second terminal of the third resistor R3, the ground terminal of the current comparator operational amplifier U is grounded, and the power supply terminal of the current comparator operational amplifier U is connected to the power supply P.

[0073] The first capacitor C1 has its first terminal connected to the positive input terminal of the current comparator operational amplifier U, and its second terminal connected to the negative input terminal of the current comparator operational amplifier U.

[0074] The second capacitor C2 has its first terminal connected to the power supply P and its second terminal grounded.

[0075] The fourth resistor R4 has its first end connected to the negative input terminal of the current comparator operational amplifier U, and its second end grounded.

[0076] The fifth resistor R5 has its first end connected to the positive input terminal of the current comparator operational amplifier U, and its second end connected to the output terminal of the current comparator operational amplifier U.

[0077] The sixth resistor R6 has its first end connected to the output terminal of the current comparison operational amplifier U, and its second end connected to the second terminal of the control unit 10.

[0078] The third capacitor C3 has its first terminal connected to the second terminal of the sixth resistor R6, and its second terminal is grounded.

[0079] Diode D has its cathode connected to the second terminal of the sixth resistor R6, and its anode grounded.

[0080] In this embodiment, referring to Figure 5, the relevant circuitry can be arranged in the sleep detection module 20, eliminating the need for encapsulation in the channel. When the transistor under test 200 enters sleep mode, the control chip 11 controls the two-to-one multiplexer to connect the second terminal of the transistor under test 200 to the sleep detection module 20 for current detection of the downstream load. When the sleep detection module 20 detects an abnormality in the current, it triggers a GPIO (General Purpose Input / Output) output. The control chip 11 detects this abnormality, wakes up, performs abnormality handling, and uses the working detection module 30 for subsequent detection. This enables current detection in sleep mode, expanding the functionality of the current detection circuit without changing the original structure; that is, current detection in sleep mode can be achieved by directly externalizing the sleep detection module 20.

[0081] It is worth noting that the current source G1 can be selected according to the actual situation. The current comparison op-amp U needs to meet the high detection accuracy in order to realize the current detection in sleep mode. Of course, other current detection circuits or methods can also be used, which will not be described in detail here.

[0082] Based on the above embodiments of the current detection circuit, a current detection device is proposed, which includes the aforementioned current detection circuit.

[0083] In this embodiment, the above current detection device acquires the current mode of the transistor under test (TUT) through the control unit. When the TUT is in sleep mode, the sleep detection module is controlled to acquire the first real-time current of the TUT, thus realizing current detection of the TUT in sleep mode. Simultaneously, when the first real-time current exceeds a preset current threshold, the working detection module is controlled to detect the current of the TUT, achieving current detection and protection of the TUT in sleep mode. This avoids the phenomenon where the current in MOSFET sleep mode cannot be detected, i.e., the current is too small to be detected using the current sensor in working mode (i.e., the working detection module cannot detect minute current changes in sleep mode). This current detection circuit improves the functionality of current detection by acquiring the first real-time current of the TUT in sleep mode through the sleep detection module. Furthermore, controlling the working detection module to detect the current of the TUT when the first real-time current exceeds a preset current threshold ensures protection of the TUT (i.e., preventing damage to the TUT due to excessive current in sleep mode).

[0084] Based on the above embodiments of the current detection circuit, a vehicle is proposed, which includes the aforementioned current detection device.

[0085] In this embodiment, the vehicle uses a current detection device to collect the first real-time current of the transistor under test in sleep mode to detect the current in sleep mode, thereby improving the functionality of current detection. When the first real-time current is greater than a preset current threshold, the working detection module is controlled to detect the current of the transistor under test, which can ensure the protection of the transistor under test (i.e., avoid damage to the transistor under test caused by excessive current in sleep mode).

[0086] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A current detection circuit, characterized in that, The current detection circuit includes: a control unit, the first terminal of which is connected to the first terminal of the transistor under test (TUT), and the control unit is used to acquire the current mode of the TUT; a sleep detection module, the first terminal of which is connected to the second terminal of the TUT, and the second terminal of which is connected to the second terminal of the control unit; and a working detection module, the first terminal of which is connected to the second terminal of the TUT, and the second terminal of which is connected to the third terminal of the control unit. The control unit is further used to control the sleep detection module to acquire a first real-time current of the TUT when the current mode of the TUT is sleep mode, and to control the working detection module to perform current detection on the TUT when the first real-time current is greater than a preset current threshold.

2. The current detection circuit as described in claim 1, characterized in that, The second end of the sleep detection module includes a first detection output terminal and a first detection control terminal. The second end of the working detection module includes a second detection output terminal and a second detection control terminal. The control unit includes a control chip. The first end of the control chip is connected to the first end of the transistor under test. The second end of the control chip is connected to the first detection output terminal. The third end of the control chip is connected to the second detection output terminal. The fourth end of the control chip is connected to the first detection control terminal and the second detection control terminal.

3. The current detection circuit as described in claim 2, characterized in that, The control unit further includes a logic control chip, the input terminal of which is connected to the fourth terminal of the control chip, the first output terminal of which is connected to the first detection control terminal, and the second output terminal of which is connected to the second detection control terminal.

4. The current detection circuit as described in claim 3, characterized in that, The sleep detection module includes: a sleep current detection sensor, the input terminal of which is connected to the second terminal of the transistor under test, the output terminal of which is connected to the second terminal of the control chip, and the control terminal of which is connected to the output terminal of the logic control chip.

5. The current detection circuit as described in claim 3, characterized in that, The working detection module includes: a working current detection sensor, the input terminal of which is connected to the second terminal of the transistor under test, the output terminal of which is connected to the third terminal of the control chip, and the control terminal of which is connected to the output terminal of the logic control chip.

6. The current detection circuit as described in claim 1, characterized in that, The current detection circuit includes: a mode selection module, the control terminal of which is connected to the control chip in the control unit, the input terminal of which is connected to the second terminal of the transistor under test, and the output terminal of which is connected to the first terminal of the sleep detection module and the first terminal of the working detection module.

7. The current detection circuit as described in claim 6, characterized in that, The mode selection module includes: a 2-to-1 chip, the control terminal of the 2-to-1 chip is connected to the control chip, the input terminal of the 2-to-1 chip is connected to the second terminal of the transistor under test, the first output terminal of the 2-to-1 chip is connected to the first terminal of the sleep detection module, and the second output terminal of the 2-to-1 chip is connected to the first terminal of the working detection module.

8. The current detection circuit as described in claim 6, characterized in that, The sleep detection module includes: a first resistor, with a first end connected to a comparison current source and a second end connected to the output terminal of the mode selection module; a second resistor, with a first end connected to the first end of the first resistor; a third resistor, with a first end connected to the second end of the first resistor; a current comparator operational amplifier, with its positive input terminal connected to the second end of the second resistor and its negative input terminal connected to the second end of the third resistor, its ground terminal grounded, and its power supply terminal connected to a power source; and a first capacitor, with a first end connected to the positive input terminal of the current comparator operational amplifier and its second end connected to the negative input terminal of the current comparator operational amplifier. A second capacitor, with its first terminal connected to the power supply and its second terminal grounded; a fourth resistor, with its first terminal connected to the negative input terminal of the current comparator operational amplifier and its second terminal grounded; a fifth resistor, with its first terminal connected to the positive input terminal of the current comparator operational amplifier and its second terminal connected to the output terminal of the current comparator operational amplifier; a sixth resistor, with its first terminal connected to the output terminal of the current comparator operational amplifier and its second terminal connected to the second terminal of the control unit; a third capacitor, with its first terminal connected to the second terminal of the sixth resistor and its second terminal grounded; and a diode, with its cathode connected to the second terminal of the sixth resistor and its anode grounded.

9. A current detection device, characterized in that, The current detection device includes the current detection circuit according to any one of claims 1 to 8.

10. A vehicle, characterized in that, The vehicle includes the current detection device as described in claim 9.

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