Multi-AND-state control fault integrated detection circuit

Abstract

The utility model discloses a multi-AND-state control fault integrated detection circuit, and relates to the field of logic circuits and fault detection. The utility model aims to solve the problems of complex circuit structure, lack of joint detection capability and insufficient system robustness in a traditional multi-sensor independent detection mode. The circuit comprises a signal input module, a logic inverting module and a logic AND operation module, wherein the signal input module is used for distinguishing an A-type sensor input end and a B-type sensor input end; the A-type signal is converted into a high level through a phase inverter, and the B-type signal is directly input; all signals are accessed to the AND gate for logic AND operation, high level is output to indicate that all sensors are normal, and low level indicates that at least one sensor fails. According to the utility model, multi-sensor joint detection is realized through a three-stage modular structure, high-frequency interference is suppressed by adopting the filter resistor, and the device has the characteristics of few used components, simple structure and accurate detection, is suitable for centralized fault detection of a multi-sensor system, and can improve the stability and anti-interference capability of the system.

Description

Technical Field

[0001] This utility model relates to the fields of logic circuits, multi-AND control, and fault detection. Background Technology

[0002] In the field of fault detection for multi-sensor systems, existing technologies typically employ a single-sensor independent detection mode: each sensor is configured with an independent detection circuit (such as a NOT gate circuit or a direct sampling unit of an MCU), and fault identification is achieved by judging the level state of the output signal of a single sensor (such as abnormal high or low levels).

[0003] The core objective of existing technologies is to achieve fault monitoring of individual sensors. These technologies rely on a one-to-one connection between the sensor and the detection unit. When the sensor output signal exceeds a preset threshold, a fault alarm is triggered. However, this approach has significant shortcomings:

[0004] 1. Complex circuit structure: Each sensor needs to be designed with a separate detection circuit, resulting in a large number of components and complicated wiring, especially when there are many sensors, the system integration is low;

[0005] 2. Lack of joint detection capability: It can only independently determine the fault of a single sensor and cannot perform joint logic analysis on the collaborative working status of multiple sensors. When it is necessary to verify the global state such as "all sensors are normal" or "at least one sensor is abnormal", an additional complex logic combination circuit is required.

[0006] 3. Insufficient system robustness: In independent detection mode, failure of any detection unit may lead to overall monitoring failure, and the high circuit redundancy increases maintenance costs.

[0007] Therefore, in order to meet the need for efficient fault detection in multi-sensor systems, there is an urgent need for an integrated solution that can simplify the circuit structure and realize joint judgment of the status of multiple sensors. Utility Model Content

[0008] The purpose of this invention is to provide a fault integrated detection circuit for multi-mode control, which is used for efficient fault detection in multi-sensor systems.

[0009] To achieve the above objectives, the fault integrated detection circuit for multi-AND state control of this utility model includes a signal input module, a logic inverting module, and a logic AND operation module; the signal input module includes several input terminals, classifying sensors into type A sensors and type B sensors;

[0010] Class A sensors output a low level under normal conditions and continuously output a high level under fault conditions;

[0011] Class B sensors output a high level under normal conditions and continuously output a low level under fault conditions;

[0012] The input terminal includes several Class A sensor input terminals, each of which is used to receive the output signal of a Class A sensor.

[0013] The logic inverting module includes several inverters, and the input terminal of each inverter is electrically connected to the input terminal of the Class A sensor in a one-to-one correspondence, which is used to convert the sensor output signal into a logic inverted signal;

[0014] The logic AND operation module includes an AND gate, the input of which is electrically connected to the output of all inverters, and is used to perform a logic AND operation on the logic inverted signals output by all inverters, and output the fault detection result through the output of the AND gate.

[0015] The input terminal includes several Class B sensor input terminals, each of which is used to receive the output signal of a Class B sensor; the output signal of the Class B sensor is connected to the input terminal of the AND gate.

[0016] The inverter is a CMOS inverter, each inverter includes an NMOS transistor and a PMOS transistor. The gate of the NMOS transistor is electrically connected to the corresponding input terminal, and its drain is connected to the drain of the PMOS transistor to serve as the output terminal of the inverter. The gate of the PMOS transistor is electrically connected to the corresponding input terminal, and its source is connected to the power supply voltage. The source of the NMOS transistor is grounded.

[0017] The AND gate is a TTL AND gate, with the number of its input terminals equal to the number of inverters, and each input terminal is directly connected to the output terminal of the corresponding inverter via a wire.

[0018] A filter resistor is connected in series between the input terminal of the signal input module and the output terminal of the sensor. The resistance of the filter resistor is 1kΩ~10kΩ.

[0019] This utility model has the following advantages:

[0020] This invention achieves multi-sensor joint detection through a three-level modular structure (input-inverter-AND operation), solving the problem that traditional single detection circuits cannot handle multiple fault scenarios, and simplifies the circuit structure through hardware logic integration. By combining multiple inverters and AND gates, this invention achieves real-time monitoring and fault detection of multiple Class A sensors. It features a simple structure, accurate detection, and is suitable for centralized fault detection in multi-sensor systems.

[0021] The input terminal of a Class B sensor is directly connected to the input terminal of an AND gate, while the input terminal of a Class A sensor is connected to the input terminal of an AND gate via an inverter. This converts the normal signals of both types of sensors into a unified high level. If the AND gate receives a low level, it means that at least one sensor is faulty. Therefore, this structure unifies the detection of Class A and Class B sensors and is suitable for detection scenarios with a large number of sensors and where both Class A and Class B sensors are present, achieving unified and efficient sensor fault detection.

[0022] A CMOS inverter is used to achieve low-power, high-noise-margin signal inversion, ensuring stable and reliable inversion function. TTL AND gates offer fast response characteristics, and direct wire connections reduce signal delay, ensuring real-time operation of multi-signal synchronous calculations. High-frequency interference is suppressed through filter resistors, improving the stability of the input signal and avoiding false detections caused by noise. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of this utility model.

[0024] Component names and reference numerals

[0025] 1. Class A sensor input terminal 1

[0026] Installation location: Signal input module.

[0027] Structural relationship: Each Class A sensor input terminal 1 is electrically connected to the output terminal of a Class A sensor, and then connected to the logic inverting module after being connected in series with the filter resistor 5.

[0028] Working principle and technical function: Receives the output signal of Class A sensor (low level in normal state, high level in fault state), suppresses high-frequency interference by filter resistor 5, and then sends it to inverter 3 for logic conversion to realize the preprocessing of Class A sensor signal.

[0029] 2. Type B sensor input terminal 2

[0030] Installation location: Signal input module.

[0031] Structural relationship: Each Class B sensor input terminal 2 is electrically connected to the output terminal of a Class B sensor, and connected to the input terminal of AND gate 4 of the logic AND operation module.

[0032] Working principle and technical function: Receives the output signal of Class B sensor (high level in normal state, low level in fault state), transmits it directly to AND gate 4 without inversion, and participates in the joint fault judgment of multiple sensors.

[0033] The number of input terminals 1 for Class A sensors and input terminals 2 for Class B sensors depends on the actual number of Class A / Class B sensors in the device / system under test. Whether a sensor is classified as Class A or Class B is determined by the characteristics of its output level.

[0034] 3. Inverter 3

[0035] Installation location: Logic inverting module.

[0036] Structural relationship: The input terminal is electrically connected to the input terminal 1 of the Class A sensor in a one-to-one correspondence, and the output terminal is directly connected to the input terminal of AND gate 4 of the logic AND operation module; the CMOS inverter is composed of NMOS transistors and PMOS transistors.

[0037] Working principle and technical function: It inverts the low-level (normal) signal input from Class A sensors and converts it to a high level; it inverts the high-level signal during a fault to a low level, unifying the normal signal reference (both are high level) for Class A and Class B sensors, and providing consistent input conditions for subsequent logic and operation modules, i.e., AND gate 4.

[0038] 4. AND gate 4

[0039] Installation location: AND operation module.

[0040] Structural relationship: The number of input terminals is equal to the number of all sensors being tested (including Class A and Class B sensors), and they are connected to the output terminals of all inverters 3 and the input terminal 2 of Class B sensors, respectively. The output terminals output the fault detection results.

[0041] Working principle and technical function: Performs a logical AND operation on all input signals (Class A inverted signals and Class B original signals). When all sensors are normal, the inputs are all high level and the output is high level; when any sensor malfunctions (Class A inverted signal is low level or Class B signal directly outputs low level), the output is low level, realizing multi-sensor joint fault detection.

[0042] 5. Filter resistor 5

[0043] Installation location: between the input terminals of the signal input module (input terminals 1 and 2 for Class A and Class B sensors) and the sensor output terminals.

[0044] Structural relationship: Connected in series between the sensor output terminal and the circuit input terminal, with a resistance range of 1kΩ~10kΩ.

[0045] Working principle and technical function: Suppress high-frequency interference in the sensor output signal, improve the stability of the input signal, avoid false detection caused by noise, and ensure the accuracy of fault diagnosis. Detailed Implementation

[0046] like Figure 1As shown, the fault integrated detection circuit of the multi-AND control of this utility model includes a signal input module, a logic inverting module, and a logic AND operation module; the signal input module includes several input terminals, classifying the sensors into type A sensors and type B sensors; type A sensors output a low level under normal conditions and continuously output a high level under fault conditions; type B sensors output a high level under normal conditions and continuously output a low level under fault conditions.

[0047] The input terminal includes several Class A sensor input terminals 1, each Class A sensor input terminal 1 is used to receive the output signal of a Class A sensor;

[0048] The logic inverting module includes several inverters 3 (NOT gates) connected in parallel. The input terminal of each inverter 3 is electrically connected to the input terminal 1 of the Class A sensor in a one-to-one correspondence, and is used to convert the sensor output signal into a logic inverted signal.

[0049] The logic AND operation module includes an AND gate 4. The input terminal of the AND gate 4 is electrically connected to the output terminal of all inverters 3, and is used to perform a logic AND operation on the logic inverted signals output by all inverters 3, and output the fault detection result through the output terminal of the AND gate 4.

[0050] This invention achieves multi-sensor joint detection through a three-level modular structure (input-inverting-AND operation), solving the problem that traditional single detection circuits cannot handle multiple fault scenarios, and simplifies the circuit structure through hardware logic integration. By combining multiple inverters 3 and AND gates 4, this invention realizes real-time monitoring and fault detection of multiple Class A sensors. It features a simple structure, accurate detection, and is suitable for centralized fault detection in multi-sensor systems.

[0051] The circuit in this invention performs logical inversion on the output signals of multiple Class A sensors, and then performs a logical AND operation on all the inverted signals to achieve joint detection of the status of multiple Class A sensors. Specifically, when all Class A sensors are in a low-level state, the output of inverter 3 is high, and the output of the logical AND gate 4 is high, indicating that all sensors are working normally. If any Class A sensor malfunctions and causes an abnormal output (e.g., remains high for a long time), the corresponding output of inverter 3 is low, and the output of the logical AND gate 4 is low, indicating that at least one sensor is faulty.

[0052] The input terminal also includes several Class B sensor input terminals 2, each Class B sensor input terminal 2 is used to receive the output signal of a Class B sensor; the output signal of the Class B sensor is connected to the input terminal of AND gate 4.

[0053] The input terminal 2 of the Class B sensor is directly connected to the input terminal of AND gate 4, and the input terminal 1 of the Class A sensor is connected to the input terminal of AND gate 4 through inverter 3. This converts the normal signals of both types of sensors into a high level. As long as AND gate 4 receives a low level, it means that at least one sensor is faulty. Therefore, this structure unifies the detection of Class A and Class B sensors and is suitable for detection scenarios with a large number of sensors and both Class A and Class B sensors, achieving unified and efficient sensor fault detection.

[0054] The inverter 3 is a CMOS inverter 3. Each inverter 3 includes an NMOS transistor and a PMOS transistor. The gate of the NMOS transistor is electrically connected to the corresponding input terminal, and its drain is connected to the drain of the PMOS transistor, serving as the output terminal of the inverter 3. The gate of the PMOS transistor is electrically connected to the corresponding input terminal, and its source is connected to the power supply voltage. The source of the NMOS transistor is grounded. The CMOS inverter 3 achieves low-power, high-noise-margin signal inversion, ensuring stable and reliable inversion function. The CMOS inverter 3 is a conventional technology, and its specific structure is not shown in the figure.

[0055] The AND gate 4 is a TTL AND gate, with the same number of inputs as the inverters 3, and each input is directly connected to the output of the corresponding inverter 3 via a wire. The TTL AND gate 4 has fast response characteristics, and the direct wire connection reduces signal delay, ensuring the real-time performance of multi-signal synchronous operation.

[0056] A filter resistor 5 is connected in series between the input terminal of the signal input module (including the input terminals 2 of Class A and Class B sensors) and the sensor output terminal. The resistance of the filter resistor 5 is 1kΩ~10kΩ. The filter resistor 5 suppresses high-frequency interference, improves the stability of the input signal, and avoids false detections caused by noise.

[0057] In this invention, "multi-AND state" means that multiple input signals are uniformly connected to AND gate 4, and any sensor failure will cause AND gate 4 to output a fault signal.

[0058] This invention achieves integrated fault detection using a three-level modular structure. The working process is as follows:

[0059] I. Circuit Structure and Signal Preprocessing

[0060] 1. Signal Input Module

[0061] Distinguishing between Class A and Class B sensor input terminals 2: Class A sensors normally output a low level (output a high level when in fault condition), while Class B sensors normally output a high level (output a low level when in fault condition). The specific number of Class A and Class B sensors is determined by the actual situation of the object being detected.

[0062] Type A signals are input after high-frequency interference is suppressed by a filter resistor 5 (1kΩ~10kΩ), while Type B signals are directly connected to subsequent circuits.

[0063] 2. Logic Inversion Module

[0064] The signal from a Class A sensor is logically inverted by a CMOS inverter 3 (composed of an NMOS transistor and a PMOS transistor): a normal low level is converted to a high level, and a fault high level is converted to a low level.

[0065] Class B sensor signals do not require inversion and are directly transmitted to the logic AND operation module.

[0066] II. Logical Operations and Fault Diagnosis

[0067] The logic and operation module uses TTL AND gate 4 to implement joint detection:

[0068] Normal state: All Class A inverted signals are high level, all Class B signals are high level → AND gate 4 outputs a high level, indicating that the system is fault-free.

[0069] Fault status: Any Class A sensor failure (outputs low level after inversion) or any Class B sensor failure (outputs low level directly) → AND gate 4 outputs a low level, indicating that there is a sensor failure, triggering a fault alarm, requiring manual intervention and maintenance work, such as replacing the faulty sensor.

[0070] This invention integrates hardware logic using "3 inverters + 4 AND gates" to replace traditional multi-sensor independent detection circuits, reducing the number of components and wiring complexity, and improving system integration.

[0071] This invention supports mixed access of Class A and Class B sensors, uses a unified high level as the normal signal reference, and enables real-time joint judgment under multiple fault scenarios.

[0072] The above process avoids the problem of "single detection unit failure leading to overall failure" in traditional independent detection modes. It achieves global status monitoring through logical AND operations, improving the system's anti-interference capability and fault identification reliability. This technology is suitable for centralized fault detection in multi-sensor systems, and has significant application value, especially in industrial control, automation equipment, and other scenarios with high requirements for circuit stability.

[0073] The above embodiments are only used to illustrate and not limit the technical solutions of this utility model. Although the utility model has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the utility model without departing from the spirit and scope of the utility model. Any modifications or partial substitutions should be covered within the scope of the claims of this utility model.

Claims

1. A fault integrated detection circuit for multi-mode control, characterized in that: It includes a signal input module, a logic inverting module, and a logic AND operation module; the signal input module contains several input terminals, classifying the sensor into type A and type B sensors. Class A sensors output a low level under normal conditions and continuously output a high level under fault conditions; Class B sensors output a high level under normal conditions and continuously output a low level under fault conditions; The input terminal includes several Class A sensor input terminals, each of which is used to receive the output signal of a Class A sensor. The logic inverting module includes several inverters, and the input terminal of each inverter is electrically connected to the input terminal of the Class A sensor in a one-to-one correspondence, which is used to convert the sensor output signal into a logic inverted signal; The logic AND operation module includes an AND gate, the input of which is electrically connected to the output of all inverters, and is used to perform a logic AND operation on the logic inverted signals output by all inverters, and output the fault detection result through the output of the AND gate.

2. The fault integrated detection circuit for multi-AND control according to claim 1, characterized in that: The input terminal includes several Class B sensor input terminals, each of which is used to receive the output signal of a Class B sensor; the output signal of the Class B sensor is connected to the input terminal of the AND gate.

3. The fault integrated detection circuit for multi-AND control according to claim 1, characterized in that: The inverter is a CMOS inverter, each inverter includes an NMOS transistor and a PMOS transistor. The gate of the NMOS transistor is electrically connected to the corresponding input terminal, and its drain is connected to the drain of the PMOS transistor to serve as the output terminal of the inverter. The gate of the PMOS transistor is electrically connected to the corresponding input terminal, and its source is connected to the power supply voltage. The source of the NMOS transistor is grounded.

4. The fault integrated detection circuit for multi-AND control according to claim 1, characterized in that: The AND gate is a TTL AND gate, with the number of its input terminals equal to the number of inverters, and each input terminal is directly connected to the output terminal of the corresponding inverter via a wire.

5. The fault integrated detection circuit for multi-AND control according to claim 1, characterized in that: A filter resistor is connected in series between the input terminal of the signal input module and the output terminal of the sensor. The resistance of the filter resistor is 1kΩ~10kΩ.

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