Array substrate, display panel and display device
By introducing auxiliary patterns into the array substrate, the short circuit problem between the data signal line and the first conductive layer is solved, thereby reducing the risk of short circuit and improving stability, while reducing material consumption and alignment accuracy requirements.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHONGQING BOE OPTOELECTRONICS
- Filing Date
- 2025-04-30
- Publication Date
- 2026-05-08
AI Technical Summary
In existing technologies, short circuits are prone to occur between data signal lines and the first conductive layer, leading to short circuit defects. Existing solutions, such as optimizing the production environment and aging tests, cannot completely solve this problem.
An auxiliary pattern is introduced into the array substrate. The semiconductor pattern and the auxiliary pattern are spaced apart. The auxiliary pattern covers the overlapping area between the data signal line and the first conductive layer, which increases the spacing and reduces the influence of impurity particles, thereby reducing the risk of short circuit.
This effectively reduces the risk of short circuits between data signal lines and the first conductive layer, improves the reliability and stability of the array substrate, reduces material consumption, and lowers the alignment accuracy requirements during the fabrication process.
Smart Images
Figure CN224216972U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology
[0002] With the continuous development of display technology, display devices have been widely used. Common display devices include liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs). Among them, liquid crystal displays have attracted much attention due to their small size, low power consumption, no radiation, and high display resolution. Utility Model Content
[0003] The purpose of this disclosure is to provide an array substrate, a display panel, and a display device to reduce the risk of short circuits between data signal lines and a first conductive layer.
[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:
[0005] On one hand, an array substrate is provided. The array substrate includes a substrate and a first conductive layer, a first insulating layer, a semiconductor layer, and a second conductive layer stacked along a direction away from the substrate. The semiconductor layer includes a semiconductor pattern and a plurality of auxiliary patterns, the semiconductor pattern being spaced apart from at least one of the auxiliary patterns, and the semiconductor pattern comprising an active layer of a transistor. The second conductive layer includes data signal lines, the orthographic projection of the data signal lines onto the substrate having N overlapping first regions with the orthographic projection of the sidewalls of the first conductive layer onto the substrate. The orthographic projections of the plurality of auxiliary patterns onto the substrate cover M of the first regions, 2 ≤ M ≤ N, where M and N are positive integers.
[0006] In the aforementioned display panel, the thickness of the portion of the first insulating layer covering the sidewall of the first conductive layer is relatively small. When the data signal line transmits a voltage signal, the risk of the data signal line breaking through the first insulating layer at the sidewall of the first conductive layer is greater. The semiconductor pattern and at least one auxiliary pattern are spaced apart. On the one hand, the auxiliary pattern is more likely to be exposed to light, so even if the auxiliary pattern undergoes some defect changes under light, it will not affect the stability of the transistor's switching (on-state voltage). On the other hand, it also helps to reduce the total area of the auxiliary pattern and the semiconductor pattern, thereby reducing the material consumption of the semiconductor layer. The first region is the overlapping portion of the sidewall of the first conductive layer and the orthographic projection of the data signal line on the substrate. Multiple auxiliary patterns cover at least two of the first regions. In this way, the auxiliary patterns can increase the spacing between the data signal line and the sidewall of the first conductive layer, thereby increasing the distance of electron movement between the data signal line and the first conductive layer. Even if there are impurity particles in the first insulating layer, the auxiliary pattern covering the sidewall of the first insulating layer remains an insulating layer, thus effectively reducing the risk of short circuits between the data signal line and the first conductive layer, i.e., reducing the risk of short circuits in the array substrate.
[0007] In some embodiments, the first conductive layer includes a plurality of gate lines extending along a first direction and spaced apart along a second direction, the first direction intersecting the second direction. The data signal line includes a first body portion extending along the second direction and a source portion located on one side of the first body portion, at least a portion of the orthographic projection of the source portion onto the substrate being within the range of the orthographic projection of the gate lines onto the substrate. In the plurality of first regions, the region where the orthographic projections of the sidewalls of the first body portion and the gate lines onto the substrate overlap is a first sub-region. The plurality of auxiliary patterns include a first auxiliary pattern, the first auxiliary pattern and the semiconductor pattern being arranged along the first direction, and the orthographic projection of the first auxiliary pattern onto the substrate covering the first sub-region.
[0008] In some embodiments, the orthographic projection of one of the first auxiliary patterns onto the substrate covers one of the first sub-regions, and there is a gap between two adjacent first auxiliary patterns.
[0009] In some embodiments, the orthographic projection of one of the first auxiliary patterns on the substrate covers two first sub-regions whose orthographic projections on the substrate coincide with those of the first main body portion and the sidewall of the same gate line.
[0010] In some embodiments, the orthographic projection of the source portion onto the substrate is located within the range of the orthographic projection of the gate line onto the substrate.
[0011] In some embodiments, the orthographic projection of one end of the source portion onto the substrate is located outside the orthographic projection of the gate line onto the substrate and is connected to the first main body portion. In the plurality of first regions, the region where the orthographic projections of the sidewalls of the source portion and the gate line onto the substrate overlap is a second sub-region. The plurality of auxiliary patterns include a second auxiliary pattern, the orthographic projection of which covers the second sub-region.
[0012] In some embodiments, the second auxiliary pattern and the semiconductor pattern are connected as a single structure.
[0013] In some embodiments, the second auxiliary pattern and the first auxiliary pattern closest to the second auxiliary pattern are connected to form an integral structure.
[0014] In some embodiments, the portion of the orthographic projection of the gate line on the substrate that overlaps with the orthographic projection of the data signal line on the substrate has a dimension of 3.5 μm to 7 μm along the second direction.
[0015] In some embodiments, the first conductive layer includes a plurality of gate lines extending along a first direction and spaced apart along a second direction, the first direction intersecting the second direction. A data signal line extends along the second direction, and the portion where the orthographic projection of the data signal line on the substrate overlaps with the orthographic projection of the gate line on the substrate forms a source portion. In the plurality of first regions, the region where the orthographic projections of the sidewalls of the data signal line and the gate line on the substrate overlap is a third sub-region. The plurality of auxiliary patterns include a third auxiliary pattern, which is arranged along the second direction with the semiconductor pattern, and the orthographic projection of the third auxiliary pattern on the substrate covers the third sub-region.
[0016] In some embodiments, the semiconductor pattern is spaced apart from at least one of the third auxiliary patterns.
[0017] In some embodiments, the semiconductor pattern is connected to at least one of the third auxiliary patterns to form an integral structure.
[0018] In some embodiments, the array substrate further includes a first electrode and a second electrode. The first electrode is disposed on the side of the second conductive layer away from the substrate. The second electrode is disposed on the side of the first electrode away from the substrate. The second conductive layer further includes a drain portion electrically connected to the semiconductor pattern and the first electrode, respectively. The first conductive layer also includes multiple first voltage signal lines electrically connected to the second electrode. In the plurality of first regions, the region where the orthographic projections of the sidewalls of the data signal lines and the first voltage signal lines on the substrate overlap is a fourth sub-region. The plurality of auxiliary patterns includes a fourth auxiliary pattern, the orthographic projection of which covers the fourth sub-region on the substrate.
[0019] In some embodiments, one of the fourth auxiliary patterns covers two fourth sub-regions whose sidewalls of the data signal line and the same first voltage signal line coincide on the orthographic projection of the data signal line onto the substrate.
[0020] In some embodiments, the fourth auxiliary pattern is spaced apart from the adjacent auxiliary patterns and from the semiconductor pattern.
[0021] In some embodiments, the fourth auxiliary pattern is connected to the nearest auxiliary pattern to the fourth auxiliary pattern to form an integral structure.
[0022] In some embodiments, the interval between the boundary of the orthographic projection of the auxiliary pattern on the substrate and the boundary of the first region covered by the auxiliary pattern is 1 μm to 5 μm.
[0023] In some embodiments, at least two boundaries of the orthographic projection of the auxiliary pattern onto the substrate are not equidistant from the boundaries of the first region covered by the auxiliary pattern.
[0024] In some embodiments, the shape of the orthographic projection of at least one of the auxiliary patterns on the substrate is the same as the shape of the orthographic projection of the target segment of the data signal line on the substrate; the orthographic projection of the target segment on the substrate is located within the range of the orthographic projection of the auxiliary pattern on the substrate.
[0025] In some embodiments, the second conductive layer further includes a drain portion electrically connected to the semiconductor pattern. The region where the orthographic projection of the drain portion onto the substrate overlaps with the orthographic projection of the sidewall of the first conductive layer onto the substrate constitutes a second region. The orthographic projection of the semiconductor pattern onto the substrate covers this second region.
[0026] On the other hand, a display panel is provided comprising a color filter substrate, a liquid crystal layer, and an array substrate as described in any of the above embodiments. The color filter substrate is disposed opposite to the array substrate; the liquid crystal layer is disposed between the array substrate and the color filter substrate.
[0027] In another aspect, a display device is provided. The display device includes the aforementioned display panel.
[0028] The above-described display panel and display device have the same structure and beneficial technical effects as the array substrate provided in some of the above embodiments, and will not be described again here. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.
[0030] Figure 1 This is a plan view of a display device according to some embodiments;
[0031] Figure 2 This is a structural diagram of a display device according to some embodiments;
[0032] Figure 3 This is a planar structural diagram of an array substrate according to some embodiments;
[0033] Figure 4 For along Figure 3 A sectional view with section line A1-A1;
[0034] Figure 5 This is a schematic diagram of a structure of an array substrate including a first auxiliary pattern according to some embodiments;
[0035] Figure 6 For along Figure 5 A sectional view along section line A2-A2;
[0036] Figure 7 For along Figure 5 A magnified view of part B1;
[0037] Figure 8 This is a schematic diagram of another structure of an array substrate including a first auxiliary pattern according to some embodiments;
[0038] Figure 9This is a structural schematic diagram of a first auxiliary pattern and a second auxiliary pattern according to some embodiments;
[0039] Figure 10 For along Figure 9 A magnified view of part B2;
[0040] Figure 11 This is a schematic diagram of another structure of the first auxiliary pattern and the second auxiliary pattern according to some embodiments;
[0041] Figure 12 This is yet another structural schematic diagram of the first auxiliary pattern and the second auxiliary pattern according to some embodiments;
[0042] Figure 13 This is yet another structural schematic diagram of the first auxiliary pattern and the second auxiliary pattern according to some embodiments;
[0043] Figure 14 This is a schematic diagram of a structure of an array substrate including a third auxiliary pattern according to some embodiments;
[0044] Figure 15 For along Figure 14 A magnified view of part B3;
[0045] Figure 16 This is a schematic diagram of another structure of an array substrate including a third auxiliary pattern according to some embodiments;
[0046] Figure 17 This is a schematic diagram of yet another structure of an array substrate including a third auxiliary pattern according to some embodiments;
[0047] Figure 18 This is a schematic diagram of a structure of an array substrate including a fourth auxiliary pattern according to some embodiments;
[0048] Figure 19 For along Figure 18 A magnified view of part B4;
[0049] Figure 20 This is a schematic diagram of another structure of an array substrate including a fourth auxiliary pattern according to some embodiments;
[0050] Figure 21 This is a structural diagram showing a semiconductor pattern covering a second region according to some embodiments. Detailed Implementation
[0051] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.
[0052] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.
[0053] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.
[0054] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.
[0055] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.
[0056] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.
[0057] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.
[0058] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.
[0059] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).
[0060] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.
[0061] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.
[0062] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.
[0063] See Figure 1 The present disclosure provides a display device, wherein the display device 1000 is a product having an image display function. Exemplarily, the display device 1000 may be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.
[0064] For example, the display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, personal digital assistant (PDA), mobile phone, watch, clock, calculator, GPS receiver / navigator, camera, display of camera view (e.g., display of a rearview camera in a vehicle), wearable device, augmented reality (AR) device, virtual reality (VR) device, mixed reality (MR) device, in-vehicle display, flying display, etc.
[0065] In some embodiments, the display device described above may be a liquid crystal display (LCD). See also Figure 2 When the display device is a liquid crystal display (LCD), the display device 1000 may include a display panel 1100 and a backlight module 1200, with the display panel 1100 disposed on the light-emitting side of the backlight module 1200. The backlight module 1200 may be a direct-lit backlight module or an edge-lit backlight module, etc., and the backlight module 1200 is used to provide a light source for the display panel 1100. The display panel 1100 includes multiple sub-pixels, and the display panel 1100 can adjust the amount of light passing through each sub-pixel, thereby enabling the multiple sub-pixels to display the same or different gray levels to achieve the purpose of image display.
[0066] Continue reading Figure 2When the display panel 1100 is a liquid crystal display panel, it may include an array substrate 100 and a color filter substrate 200 disposed opposite to each other, and a liquid crystal layer 300 disposed between the array substrate 100 and the color filter substrate 200. The color filter substrate 200 can filter the light passing through it. One sub-pixel can emit light of one color (such as red, green, or blue), and multiple sub-pixels can emit light of the same or different colors, thereby enabling the display panel 1100 to achieve color display. Of course, the structure of the display panel 1100 is not limited to this. The display panel 1100 may also include other structures, as long as the same technical concept is adopted. For example, the display panel 1100 may also include a first alignment film (not shown in the figure) disposed on the side of the array substrate 100 near the liquid crystal layer 300, and a second alignment film (not shown in the figure) disposed on the side of the color filter substrate 200 near the liquid crystal layer 300, etc.
[0067] In some embodiments, see Figure 3 and Figure 4 The array substrate 100 may include a substrate 10 and a direction away from the substrate 10 ( Figure 4 The array substrate 100 comprises a first conductive layer 20, a first insulating layer 30, a semiconductor layer 40, and a second conductive layer 50 stacked from bottom to top. The array substrate 100 may also include a thin film transistor (TFT).
[0068] The substrate 10 can be a transparent substrate, such as a glass substrate. This allows light emitted from the backlight module to pass through the substrate 10, which helps improve the transmittance of the array substrate 100. The first insulating layer 30 can be a gate insulating layer. Furthermore, the first insulating layer 30 can be a single-layer structure (e.g., a single-layer silicon oxide), a double-layer structure (e.g., a stacked structure formed by silicon nitride and silicon oxide), or a three-layer structure (e.g., a stacked structure formed by silicon nitride, silicon oxynitride, and silicon oxide). The embodiments disclosed herein will not be listed individually for each of these types of structures.
[0069] Semiconductor layer 40 may include semiconductor pattern 41, which includes the active layer of transistor T. Transistor T may also include a gate located in the first conductive layer 20, and a source and drain located in the second conductive layer 50. That is, the gate of transistor T is located on the side of the active layer closer to the substrate 10, and transistor T is a bottom-gate transistor.
[0070] The material of semiconductor layer 40 may include metal oxide materials and / or metal oxide nitride materials. Metal oxide materials include, but are not limited to: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxides (In-free OS), rare earth-doped oxides (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In₂O₃:Sn, In₂O₃:Mo, Cd₂SnO₄, ZnO:Al, TiO₂:Nb, and Cd-Sn-O. Metal oxide nitride materials include, but are not limited to: zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. The semiconductor layer 40 can be made of amorphous, partially crystalline, single-crystal, or polycrystalline materials. In addition, the semiconductor layer 40 can be a single-layer film structure or a multi-layer film structure.
[0071] The second conductive layer 50 includes a plurality of data signal lines 51, which extend generally along the second direction Y and are spaced apart along the first direction X. The orthographic projection of the data signal lines 51 on the substrate 10 at least partially overlaps with the orthographic projection of the first conductive layer 20 on the substrate 10.
[0072] The first conductive layer 20 and the second conductive layer 50 may include metallic materials. The metallic materials may include a single-layer metallic structure formed from a single metallic material, such as titanium, aluminum, copper, molybdenum, niobium, nickel, and their alloys. Alternatively, the metallic materials may include a multi-layered metallic stacked structure, which may include titanium-aluminum-titanium (Ti / Al / Ti) stacked structures, molybdenum-aluminum (Mo / Al) stacked structures, molybdenum-aluminum-molybdenum (Mo / Al / Mo) stacked structures, molybdenum-niobium-titanium (MoNb / Ti) stacked structures, molybdenum-niobium-titanium-copper (MoNb / Ti / Cu) stacked structures, molybdenum-niobium-copper (MoNb / Cu) stacked structures, molybdenum-niobium-titanium-copper (MTD / Cu) stacked structures, and molybdenum-niobium-copper... - One or a combination of the following structures: MoNb / Cu / MTD stacked structure, MoNb-Cu-MoNb-MoNd stacked structure, MoTi / Cu stacked structure, MoTi-Cu-MoNb stacked structure, MoTi / Cu / MTD stacked structure, MoTi / Cu / MoTi stacked structure, MoTi-Cu-MoNd stacked structure, MoNb-MoNd stacked structure, and AlNb-MoNd stacked structure.
[0073] The inventors discovered that short circuits, specifically gate-drain short-circuit issues (DGS issues), are prone to occur in the area where the projections of the data signal lines and the first conductive layer overlap. The main reasons for DGS issues in the array substrate are as follows: During the fabrication of the first insulating layer 30, foreign objects, such as particles, from the cavity environment can fall into the first insulating layer. Since the subsequently deposited thin films (such as the semiconductor layer and the second conductive layer) cannot completely encapsulate these foreign objects, the film quality of the first insulating layer around the foreign object becomes porous, easily forming holes. When the display panel is lit, an alternating electric field exists between the data signal lines and the first conductive layer. The metal electrodes near the foreign object are affected by this alternating electric field and diffuse along the foreign object and surrounding transport film to form conductive channels, thus causing a short circuit between the data signal lines and the first conductive layer. Furthermore, the inventors also found that DGS issues often occur at locations where the data signal lines climb the first conductive layer.
[0074] In the array substrates provided by related technologies, in order to solve the DGS problem, the production environment and production conditions of the gate insulating layer GI can be optimized. At the same time, rework (Sorting) can be carried out through aging tests in the module stage, that is, defective products are screened out, thereby reducing the occurrence rate of DGS. However, this still cannot completely solve the DGS problem.
[0075] To solve the above technical problems, please refer to Figure 5 and Figure 6 The array substrate 100 provided in the embodiments of this disclosure has N overlapping first regions 60 where the orthographic projection of the data signal line 51 on the substrate 10 and the orthographic projection of the sidewall 21 of the first conductive layer 20 on the substrate 10 are respectively. The first conductive layer 20 is a film layer of a certain thickness, and its sidewall 21 refers to the portion of the surface of the first conductive layer 20 that connects the surface near the substrate 11 and the surface away from the substrate 11. The angle between the sidewall 21 of the first conductive layer 20 and the substrate 10 is greater than 0° and less than 90°, that is, the sidewall 21 of the first conductive layer 20 is an inclined slope. The region where the orthographic projection of the sidewall 21 of the first conductive layer 20 on the substrate 10 is located is: the boundary of the orthographic projection of the first conductive layer 20 on the substrate 10 and a portion of the region adjacent to this boundary.
[0076] like Figure 6As shown, when preparing the first insulating layer 30, the thickness of the material deposited on the sidewall 21 is less than the thickness of the material deposited in other areas. In other words, the thickness of the portion of the first insulating layer 30 covering the sidewall 21 of the first conductive layer 20 is smaller. Therefore, when the data signal line 51 transmits a voltage signal, the risk of the data signal line 51 breaking down the first insulating layer 30 at the sidewall 21 of the first conductive layer 20 is greater. The semiconductor layer 40 also includes multiple auxiliary patterns 42, with the semiconductor pattern 41 and at least one auxiliary pattern 42 spaced apart. On the one hand, the auxiliary pattern 42 is more likely to be exposed to light, so even if the auxiliary pattern 42 undergoes some defect changes under light, it will not affect the stability of the switching (on-state voltage) of the transistor T. On the other hand, it also helps to reduce the total area of the auxiliary pattern 42 and the semiconductor pattern 41, thereby reducing the material consumption of the semiconductor layer 40. The first region 60 is the overlapping portion of the orthographic projections of the sidewall 21 of the first conductive layer 20 and the data signal line 51 onto the substrate 10. The orthographic projections of the multiple auxiliary patterns 42 onto the substrate 10 cover M first regions 60. Where 2≤M≤N, M and N are positive integers, meaning that multiple auxiliary patterns 42 cover at least two first regions 60. In this way, the auxiliary patterns 42 can increase the spacing between the data signal line 51 and the sidewall 21 of the first conductive layer 20, thereby increasing the distance of electron movement between the data signal line 51 and the first conductive layer 20. Even if there are impurity particles in the first insulating layer 30, the auxiliary patterns 42 covering the sidewall of the first insulating layer 30 are still insulating layers, thereby effectively reducing the risk of short circuit between the data signal line 51 and the first conductive layer 20, that is, reducing the risk of DGS on the array substrate.
[0077] In some embodiments, the interval between the boundary of the orthographic projection of the auxiliary pattern 42 on the substrate 10 and the boundary of the first region 60 covered by the auxiliary pattern 42 can be 0.1 μm to 10 μm. This is beneficial to increase the area covered by the auxiliary pattern 42, so that the portion of the data signal line 51 that overlaps with the sidewall 21 of the gate line 22 on the substrate 10 can be completely disposed on the auxiliary pattern 42, further reducing the risk of short circuit between the data signal line 51 and the sidewall 21 of the gate line 22, and also helping to reduce the alignment accuracy requirements between the auxiliary pattern 42 and the data signal line 51 during the array substrate fabrication process. For example, the interval between the boundary of the orthographic projection of the auxiliary pattern 42 on the substrate 10 and the boundary of the first region 60 covered by the auxiliary pattern 42 can be 0.1μm to 1μm, 1μm to 5μm, or 5μm to 10μm. For example, the above interval can be 0.1μm, 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 5μm, 8μm, or 10μm, etc. The embodiments of this disclosure will not be listed one by one.
[0078] In some embodiments, at least two boundaries of the orthographic projection of the auxiliary pattern 42 onto the substrate 10 are not equidistant from the boundaries of the first region 60 covered by the auxiliary pattern 42. This allows for flexible adjustment of the position and boundaries of the auxiliary pattern 42 based on the structure near the first region 60, thereby enhancing the arrangement flexibility of the auxiliary pattern 42.
[0079] For example, the position of the boundary of the auxiliary pattern 42 near the semiconductor pattern 41 can be flexibly adjusted according to the interval between the first region 60 and the semiconductor pattern 41. For example, if the interval between the first region 60 and the semiconductor pattern 41 is small, the interval between the boundary of the auxiliary pattern 42 near the semiconductor pattern 41 and the first region 60 can be appropriately reduced.
[0080] In some embodiments, the shape of the orthographic projection of at least one auxiliary pattern 42 onto the substrate 10 is the same as the shape of the orthographic projection of the target segment of the data signal line 51 onto the substrate 10; the orthographic projection of the target segment onto the substrate 10 is located within the range of the orthographic projection of the auxiliary pattern 42 onto the substrate 10, that is, the portion of the auxiliary pattern 42 and the data signal line 51 located on the auxiliary pattern 42 is a contour-mimicking structure. This ensures that the edge of the data signal line 51 is completely within the boundary of the auxiliary pattern 42, and greatly reduces the area of the auxiliary pattern 42, thereby reducing the material consumption of the semiconductor layer 40.
[0081] In some other embodiments, the interval between the boundary of the orthographic projection of the auxiliary pattern 42 on the substrate 10 and the boundary of the first region 60 covered by the auxiliary pattern 42 can be equal everywhere, that is, the interval between each side boundary of the auxiliary pattern 42 and the boundary of the first region 60 is equal.
[0082] Continue reading Figure 5 and Figure 6 In some embodiments, the first conductive layer 20 includes a plurality of gate lines 22, which extend along a first direction X and are spaced apart along a second direction Y, wherein the first direction X and the second direction Y intersect. Exemplarily, the gate lines 22 may include a second body portion 221 and a gate portion 222, the gate portion 222 extending along the first direction X and protruding along the second direction Y from one side boundary of the second body portion 221, and being integrally disposed with the body portion 221.
[0083] The extension direction of the data signal line 51 intersects the extension direction of the gate line 22, and the orthographic projections of the data signal line 51 and the gate line 22 on the substrate 10 at least partially overlap. The data signal line 51 may include a first body portion 511 extending along the second direction Y, and a source portion 512 located on one side of the first body portion 511. At least a portion of the orthographic projection of the source portion 512 on the substrate 10 is located within the range of the orthographic projection of the gate line 22 on the substrate 10. The orthographic projection of the first body portion 511 on the substrate 10 overlaps with the orthographic projection of the sidewall 21 of the gate line 22 (e.g., the second body portion 221) on the substrate 10. For example, among the plurality of first regions 60, the region where the orthographic projections of the first body portion 511 and the sidewall 21 of the gate line 22 (the second body portion 221) on the substrate 10 overlap is a first sub-region 61, and the first body portion 511 and the orthographic projection of each gate line 22 on the substrate 10 form two first sub-regions 61. The source portion 512 refers to the portion of the data signal line 51 used to form the source of the transistor T.
[0084] like Figure 5 As shown, the portion of the orthographic projection of the gate line 22 on the substrate 10 that overlaps with the orthographic projection of the data signal line 51 on the substrate 10 has a dimension D1 of 3.5 μm to 7 μm along the second direction Y. Exemplarily, when the gate line 22 includes a second body portion 221 and a gate portion 222, the orthographic projection of the data signal line 51 on the substrate 10 partially coincides with the orthographic projection of the second body portion 221 on the substrate 10, but does not coincide with the orthographic projection of the gate portion 222 on the substrate 10. In this case, the aforementioned dimension D1 can be considered as the dimension of the surface of the second body portion 221 near the substrate 10 along the second direction Y, i.e., the maximum linewidth of the second body portion 221. For example, the aforementioned dimension D1 can be 3.5 μm, 4 μm, 5 μm, 6 μm, 6.5 μm, or 7 μm, etc., and the embodiments of this disclosure will not be listed one by one.
[0085] The plurality of auxiliary patterns 42 include a first auxiliary pattern 421, which is arranged along the first direction X with the semiconductor pattern 41, and the orthographic projection of the first auxiliary pattern 421 on the substrate 10 covers the first sub-region 61. The first auxiliary pattern 421 can increase the spacing between the data signal line 51 and the sidewall 21 of the gate line 22, thereby reducing the risk of short circuit between the data signal line 51 and the sidewall 21 of the gate line 22.
[0086] In some embodiments, see Figure 7The distance D2 between the boundary of the orthographic projection of the first auxiliary pattern 421 on the substrate 10 and the boundary of the first sub-region 61 covered by the first auxiliary pattern 421 is 1μm to 5μm. This helps to increase the area covered by the first auxiliary pattern 421, so that the portion of the data signal line 51 located within the first sub-region 61 can be completely disposed on the first auxiliary pattern 421, further reducing the risk of short circuit between the data signal line 51 and the gate line 22. Exemplarily, the distance D2 between the boundary of the orthographic projection of the first auxiliary pattern 421 on the substrate 10 and the boundary of the first sub-region 61 can be 1μm, 2μm, 2.5μm, 3μm, 3.5μm, or 5μm, etc., and the embodiments of this disclosure will not be listed one by one.
[0087] For example, such as Figure 7 As shown, the first sub-region 61 is rectangular, and the orthographic projection of the first auxiliary pattern 421 onto the substrate 10 is also rectangular. The orthographic projection of the first auxiliary pattern 421 onto the substrate 10 has four opposing boundaries with the first sub-region 61. The intervals between the four boundaries of the orthographic projection of the first auxiliary pattern 421 onto the substrate 10 and the first sub-region 61 are D21, D22, D23, and D24, respectively, and each of these intervals is between 1 μm and 5 μm. At least two of the intervals D21, D22, D23, and D24 may have different values. This allows for flexible adjustment of the position and boundaries of the first auxiliary pattern 421 based on the structure near the first sub-region 61, thereby improving the arrangement flexibility of the first auxiliary pattern 421.
[0088] For example, such as Figure 7 As shown, the shape of the orthographic projection of the first auxiliary pattern 421 onto the substrate 10 is the same as or approximately the same as the shape of the orthographic projection of the portion of the data signal line 51 located on the first auxiliary pattern 421 onto the substrate 10.
[0089] like Figure 5 As shown, in some embodiments, the orthographic projection of a first auxiliary pattern 421 on the substrate 10 covers a first sub-region 61, and there is a gap between two adjacent first auxiliary patterns 421. In this way, the total area of the first auxiliary pattern 421 can be greatly reduced, thereby reducing the material consumption of the semiconductor layer 40.
[0090] For example, when the dimension D1 of the orthographic projection of the gate line 22 onto the substrate 10 along the second direction Y is large, and the spacing D2 between the boundary of the first auxiliary pattern 421 and the boundary of the first sub-region 61 is small, the first auxiliary pattern 421 can be adopted as follows: Figure 5 Configure it as shown.
[0091] See Figure 8In some embodiments, the orthographic projection of a first auxiliary pattern 421 on the substrate 10 covers two first sub-regions 61 on the substrate 10 that overlap with the orthographic projections of the first main body portion 511 and the sidewall 21 of the same gate line 22. In this way, when the interval between the two first sub-regions 61 is small, the fabrication difficulty of the first auxiliary pattern 421 can be reduced.
[0092] For example, when the dimension D1 of the orthographic projection of the gate line 22 onto the substrate 10 along the second direction Y is small, and the spacing D2 between the boundary of the first auxiliary pattern 421 and the boundary of the first sub-region 61 is large, the first auxiliary pattern 421 can be adopted as follows: Figure 8 Configure it as shown.
[0093] like Figure 5 As shown, in some embodiments, the orthogonal projection of the source portion 512 on the substrate 10 is located within the range of the orthogonal projection of the gate line 22 on the substrate 10. At this time, the orthogonal projection of the source portion 512 on the substrate 10 does not coincide with the orthogonal projection of the sidewall 21 of the gate line 22 on the substrate 10.
[0094] like Figures 5-8 As shown, the first auxiliary pattern 421 can be spaced apart from the semiconductor pattern 41.
[0095] like Figure 9 As shown, in some embodiments, one end of the source portion 512 ( Figure 9 The orthographic projection of the right end of the source electrode portion 512 on the substrate 10 is located outside the orthographic projection of the gate line 22 on the substrate 10 and is connected to the first main body portion 511. The orthographic projection of the source electrode portion 512 on the substrate 10 coincides with the orthographic projection of the sidewall 21 of the gate line 22 on the substrate 10.
[0096] Among the multiple first regions 60, the region where the orthographic projections of the sidewalls 21 of the source portion 512 and the gate line 22 (e.g., the gate portion 222) on the substrate 10 overlap is the second sub-region 62. The multiple auxiliary patterns 42 include a second auxiliary pattern 422, the orthographic projection of which covers the second sub-region 62 on the substrate 10. The second auxiliary pattern 422 can increase the spacing between the sidewalls 21 of the source portion 512 and the gate line 22 (gate portion 222), thereby reducing the risk of a short circuit between the source portion 512 and the sidewalls 21 of the gate line 22.
[0097] In some embodiments, see Figure 10The distance D3 between the boundary of the orthographic projection of the second auxiliary pattern 422 on the substrate 10 and the boundary of the second sub-region 62 covered by the second auxiliary pattern 422 is 1μm to 5μm. This is beneficial for increasing the area covered by the second auxiliary pattern 422, so that the portion of the source portion 512 located within the second sub-region 62 can be completely disposed on the second auxiliary pattern 422, further reducing the risk of short circuit between the source portion 512 and the gate line 22. Exemplarily, the distance D3 between the boundary of the orthographic projection of the second auxiliary pattern 422 on the substrate 10 and the boundary of the second sub-region 62 can be 1μm, 2μm, 2.5μm, 3μm, 3.5μm, or 5μm, etc., and will not be listed one by one in the embodiments of this disclosure.
[0098] For example, such as Figure 10 As shown, the second sub-region 62 is rectangular, and the orthographic projection of the second auxiliary pattern 422 onto the substrate 10 is also rectangular. The orthographic projection of the second auxiliary pattern 422 onto the substrate 10 has four opposing boundaries with the first sub-region 61. The intervals between the four boundaries of the orthographic projection of the second auxiliary pattern 422 onto the substrate 10 and the second sub-region 62 are D31, D32, D33, and D34, respectively, and each of these intervals is between 1 μm and 5 μm. At least two of the intervals D31, D32, D33, and D34 may have different values. This allows for flexible adjustment of the position and boundaries of the second auxiliary pattern 422 based on the structure near the second sub-region 62, thereby improving the flexibility of the auxiliary pattern 42's arrangement.
[0099] For example, such as Figure 10 As shown, the shape of the orthographic projection of the second auxiliary pattern 422 onto the substrate 10 is the same as or approximately the same as the shape of the orthographic projection of the portion of the source portion 512 located on the second auxiliary pattern 422 onto the substrate 10. For example, the shape of the orthographic projection of the second auxiliary pattern 422 onto the substrate 10 is rectangular, and the shape of the orthographic projection of the portion of the source portion 512 located on the first auxiliary pattern 421 onto the substrate 10 is also rectangular.
[0100] In some embodiments, such as Figure 9 As shown, the second auxiliary pattern 422 is spaced apart from both the first auxiliary pattern 421 and the semiconductor pattern 41. For example, when the spacing between the first sub-region 61 and the second sub-region 62 is large, and the spacing between the first auxiliary pattern 421 and the first sub-region 61 is small, the second auxiliary pattern 422 is spaced apart from the first auxiliary pattern 421; when the spacing between the second sub-region 62 and the semiconductor pattern 41 is large, and the spacing between the second auxiliary pattern 422 and the second sub-region 62 is small, the second auxiliary pattern 422 is spaced apart from the semiconductor pattern 41.
[0101] like Figure 11 As shown, in some embodiments, the second auxiliary pattern 422 and the semiconductor pattern 41 are connected as a single structure. This reduces the graphic complexity of the second auxiliary pattern 422 and the semiconductor pattern 41, thereby reducing the fabrication difficulty of the second auxiliary pattern 422 and the semiconductor pattern 41. For example, when the spacing between the second sub-region 62 and the semiconductor pattern 41 is small, and the spacing between the second auxiliary pattern 422 and the second sub-region 62 is large, the second auxiliary pattern 422 and the semiconductor pattern 41 can be connected as a single structure.
[0102] like Figure 12 As shown, in some embodiments, the second auxiliary pattern 422 and the first auxiliary pattern 421 closest to the second auxiliary pattern 422 are connected to form a single structure. For example, when the interval between the second sub-region 62 and the first sub-region 61 is small, the second auxiliary pattern 422 and the first auxiliary pattern 421 can be connected to form a single structure.
[0103] like Figure 13 As shown, in some embodiments, the second auxiliary pattern 422 is connected to the semiconductor pattern 41 and the first auxiliary pattern 421 closest to the second auxiliary pattern 422 to form an integral structure.
[0104] In some embodiments, see Figure 14 The first conductive layer 20 includes multiple gate lines 22, which extend along a first direction X and are spaced apart along a second direction Y. A data signal line 51 extends along the second direction Y. The portion where the orthographic projection of the data signal line 51 onto the substrate 10 overlaps with the orthographic projection of the gate lines 22 onto the substrate 10 forms a source portion 512. In other words, the data signal line 51 is a straight line and does not have any portion protruding along the first direction X.
[0105] Among the multiple first regions 60, the region where the orthographic projections of the sidewalls 21 of the data signal line 51 and the gate line 22 (gate portion 222) on the substrate 10 overlap is a third sub-region 63. Specifically, the orthographic projections of the data signal line 51 and each gate line 22 on the substrate 10 form two third sub-regions 63. The multiple auxiliary patterns 42 include a third auxiliary pattern 423, which is arranged along the second direction Y with the semiconductor pattern 41, and the orthographic projection of the third auxiliary pattern 423 on the substrate 10 covers the third sub-region 63. The third auxiliary pattern 423 can increase the spacing between the sidewalls 21 of the data signal line 51 and the gate line 22, thereby reducing the risk of short circuits between the data signal line 51 and the sidewalls 21 of the gate line 22.
[0106] In some embodiments, see Figure 15The distance D4 between the boundary of the orthographic projection of the third auxiliary pattern 423 on the substrate 10 and the boundary of the third sub-region 63 covered by the third auxiliary pattern 423 is 1μm to 5μm. This is beneficial for increasing the area covered by the third auxiliary pattern 423, so that the portion of the data signal line 51 located within the third sub-region 63 can be completely disposed on the third auxiliary pattern 423, reducing the risk of short circuit between the data signal line 51 and the gate line 22. Exemplarily, the distance D4 between the boundary of the orthographic projection of the third auxiliary pattern 423 on the substrate 10 and the boundary of the third sub-region 63 can be 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 4.5μm, or 5μm, etc., and will not be listed one by one in the embodiments of this disclosure.
[0107] For example, such as Figure 15 As shown, the third sub-region 63 is rectangular, and the orthographic projection of the third auxiliary pattern 423 onto the substrate 10 is also rectangular. There are four opposing boundaries between the orthographic projection of the third auxiliary pattern 423 onto the substrate 10 and the third sub-region 63. The intervals between the four boundaries of the orthographic projection of the third auxiliary pattern 423 onto the substrate 10 and the third sub-region 63 are D41, D42, D43, and D44, respectively. Each of these intervals, D41, D42, D43, and D44, is between 1 μm and 5 μm. At least two of the intervals D41, D42, D43, and D44 may have different values. This allows for flexible adjustment of the position and boundaries of the third auxiliary pattern 423 based on the structure near the third sub-region 63, thereby improving the arrangement flexibility of the third auxiliary pattern 423.
[0108] For example, such as Figure 15 As shown, the shape of the orthographic projection of the third auxiliary pattern 423 on the substrate 10 is the same as or approximately the same as the shape of the orthographic projection of the portion of the data signal line 51 located on the third auxiliary pattern 423 on the substrate 10.
[0109] like Figure 14 and Figure 16 As shown, in some embodiments, the semiconductor pattern 41 and at least one third auxiliary pattern 423 are spaced apart. The spacing between the third sub-region 63 and the semiconductor pattern 41 can be flexibly adjusted to determine whether the third auxiliary pattern 423 covering the third sub-region 63 and the semiconductor pattern 41 are connected as a single structure. For example, as... Figure 14 As shown, the semiconductor pattern 41 can be spaced apart from the two third auxiliary patterns 423. Alternatively, as... Figure 16 As shown, the semiconductor pattern 41 can be spaced apart from one of the third auxiliary patterns 423 and connected to the other third auxiliary pattern 423 to form an integral structure.
[0110] like Figure 16 and Figure 17As shown, the semiconductor pattern 41 and at least one third auxiliary pattern 423 are connected as a single structure. This reduces the fabrication difficulty of the semiconductor pattern 41 and the third auxiliary pattern 423 when the spacing between the third sub-region 63 and the semiconductor pattern 41 is small. For example, as... Figure 16 As shown, the conductor pattern 41 can be spaced apart from one of the third auxiliary patterns 423 and connected to the other third auxiliary pattern 423 to form an integral structure. Alternatively, as... Figure 17 As shown, the semiconductor pattern 41 can be connected to the two third auxiliary patterns 423 to form an integral structure.
[0111] In some embodiments, such as Figures 14-17 As shown, the shape of the orthographic projection of the third auxiliary pattern 423 onto the substrate 10 is the same as or approximately the same as the shape of the orthographic projection of the portion of the data signal line 51 located on the third auxiliary pattern 423 onto the substrate 10. This ensures that the edge of the data signal line 51 is completely within the boundary of the third auxiliary pattern 423, and greatly reduces the area of the auxiliary pattern 42, thereby reducing the material consumption of the semiconductor layer 40.
[0112] In some embodiments, see Figure 3 and Figure 4 The array substrate 100 may further include a first electrode 31 and a second electrode 32. The first electrode 31 may be a pixel electrode, and the second electrode may be a common electrode. The first electrode 31 is disposed on the side of the second conductive layer 50 away from the substrate 10. The second conductive layer 50 also includes a drain portion 52 and a source portion 512 electrically connected to the semiconductor pattern 41 and the first electrode 31, respectively. The second electrode 32 is disposed on the side of the first electrode 31 away from the substrate 10. The first conductive layer 20 also includes a plurality of first voltage signal lines 23, which may be, for example, common voltage signal lines, and are electrically connected to the second electrode 32. That is, the array substrate 100 includes a common voltage signal line disposed on the same layer as the gate line 22. The common voltage signal line is used to be electrically connected to the second electrode in the display area, so as to be disposed in parallel with the second electrode, thereby reducing the resistance and voltage drop of the second electrode.
[0113] For example, such as Figure 3 and Figure 4 As shown, the array substrate 100 may further include a second insulating layer 33 located between the second conductive layer 50 and the first electrode 31, and a third insulating layer 34 located between the first electrode 31 and the second electrode 32. Furthermore, the array substrate 100 may also include a transition electrode 35 made of the same material as the first electrode 31 and disposed in the same layer, through which the first voltage signal line 23 is electrically connected to the second electrode 32.
[0114] See Figure 18 and Figure 19 The extension direction of the first voltage signal line 23 is the same as the extension direction of the gate line 22. The orthographic projection of the data signal line 51 on the substrate 10 also partially coincides with the orthographic projection of the first voltage signal line 23 on the substrate 10. At this time, among the plurality of first regions 60, the region where the orthographic projections of the sidewalls 21 of the data signal line 51 and the first voltage signal line 23 on the substrate 10 overlap is the fourth sub-region 64. The data signal line 51 and the orthographic projection of each first voltage signal line 23 on the substrate 10 form two fourth sub-regions 64.
[0115] The plurality of auxiliary patterns 42 include a fourth auxiliary pattern 424, the orthographic projection of which covers the fourth sub-region 64 on the substrate 10. The fourth auxiliary pattern 424 can increase the spacing between the data signal line 51 and the sidewall 21 of the first voltage signal line 23, thereby reducing the risk of a short circuit between the data signal line 51 and the sidewall 21 of the first voltage signal line 23.
[0116] like Figure 18 and Figure 19 As shown, in some embodiments, a fourth auxiliary pattern 424 covers two fourth sub-regions 64 whose sidewalls 21 of the data signal line 51 and the same first voltage signal line 23 coincide on the substrate 10. When the spacing between the two fourth sub-regions 64 is small, the fabrication difficulty of the fourth auxiliary pattern 424 can be reduced.
[0117] Of course, in some other embodiments, when the interval between two adjacent fourth sub-regions 64 is large, a fourth auxiliary pattern 424 may be provided to cover one fourth sub-region 64. Below, embodiments of this disclosure will be described exemplarily using the example of one fourth auxiliary pattern 424 covering two fourth sub-regions 64.
[0118] In some embodiments, see Figure 19 The minimum interval D5 between the boundary of the orthographic projection of the fourth auxiliary pattern 424 on the substrate 10 and the boundary of the fourth sub-region 64 covered by the first auxiliary pattern 421 is 1μm to 5μm. This helps to increase the area covered by the fourth auxiliary pattern 424, so that the portion of the data signal line 51 that overlaps with the projection of the first voltage signal line 23 can be completely disposed on the fourth auxiliary pattern 424, further reducing the risk of short circuit between the data signal line 51 and the first voltage signal line 23. Exemplarily, the interval D5 between the boundary of the orthographic projection of the fourth auxiliary pattern 424 on the substrate 10 and the boundary of the fourth sub-region 64 can be 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 4μm, or 5μm, etc., and will not be listed one by one in the embodiments of this disclosure.
[0119] For example, such as Figure 19As shown, the line connecting the outer contours of the two fourth sub-regions 64 can be a rectangle, and the shape of the orthographic projection of the fourth auxiliary pattern 424 on the substrate 10 is a rectangle.
[0120] The orthographic projection of the fourth auxiliary pattern 424 onto the substrate 10 has four opposing boundaries with the two fourth sub-regions 64. The intervals between the four boundaries of the orthographic projection of the fourth auxiliary pattern 424 onto the substrate 10 and the fourth sub-regions 64 are D51, D52, D53, and D54, respectively, and each of the four intervals D51, D52, D53, and D54 is 1μm to 5μm. At least two of the four intervals D51, D52, D53, and D54 may have different values. This allows for flexible adjustment of the position and boundaries of the fourth auxiliary pattern 424 based on the structure near the fourth sub-regions 64, thereby improving the arrangement flexibility of the fourth auxiliary pattern 424.
[0121] like Figure 18 As shown, in some embodiments, the fourth auxiliary pattern 424 is spaced apart from the adjacent auxiliary pattern 42 and from the semiconductor pattern 41. This significantly reduces the total area of the semiconductor layer 40, thereby reducing the material consumption of the semiconductor layer 40.
[0122] like Figure 20 As shown, in some embodiments, the fourth auxiliary pattern 424 is connected to the nearest auxiliary pattern 42 (such as the third auxiliary pattern 423) to form a single structure. Alternatively, as... Figure 21 As shown, the fourth auxiliary pattern 424 is connected to the semiconductor pattern 41 as a single structure. In this way, when the fourth sub-region 64 is close to the adjacent first region 60 or close to the semiconductor pattern 41, the fabrication difficulty of the fourth auxiliary pattern 424 can be reduced.
[0123] See Figure 21 In some embodiments, the second conductive layer 50 further includes a drain portion 52, which is electrically connected to the semiconductor pattern 41. The region where the orthographic projection of the drain portion 52 on the substrate 10 overlaps with the orthographic projection of the sidewall 21 of the first conductive layer 30 (gate 22) on the substrate 10 is a second region 36. The orthographic projection of the semiconductor pattern 41 on the substrate 10 covers the second region 36. The semiconductor pattern 41 can increase the spacing between the drain portion 52 and the first conductive layer 20, thereby increasing the distance for electron movement between the drain portion 52 and the first conductive layer 20. Even if impurity particles are present in the first insulating layer 30, the semiconductor pattern 41 covering the sidewall of the first insulating layer 30 can be configured as an insulating layer, which can effectively reduce the risk of short circuit between the drain portion 52 and the first conductive layer 20, i.e., reduce the incidence of DGS on the array substrate.
[0124] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. An array substrate, characterized in that, include: A substrate and a first conductive layer, a first insulating layer, a semiconductor layer, and a second conductive layer stacked in a direction away from the substrate; wherein... The semiconductor layer includes a semiconductor pattern and a plurality of auxiliary patterns, the semiconductor pattern being spaced apart from at least one of the auxiliary patterns, and the semiconductor pattern containing an active layer of a transistor; the second conductive layer includes a data signal line, the orthographic projection of the data signal line on the substrate having N overlapping first regions with the orthographic projection of the sidewall of the first conductive layer on the substrate, and the orthographic projection of the plurality of auxiliary patterns on the substrate covering M of the first regions, 2≤M≤N, where M and N are positive integers.
2. The array substrate according to claim 1, characterized in that, The first conductive layer includes a plurality of gate lines, which extend along a first direction and are spaced apart along a second direction, wherein the first direction intersects the second direction; The data signal line includes a first body portion extending along the second direction and a source portion located on one side of the first body portion, wherein at least a portion of the orthographic projection of the source portion onto the substrate is located within the range of the orthographic projection of the gate line onto the substrate. Among the plurality of first regions, the region in which the orthographic projections of the first main body and the sidewalls of the gate line on the substrate overlap with each other is the first sub-region; The plurality of auxiliary patterns includes a first auxiliary pattern, which is arranged along the first direction with the semiconductor pattern, and the orthographic projection of the first auxiliary pattern on the substrate covers the first sub-region.
3. The array substrate according to claim 2, characterized in that, An orthographic projection of one of the first auxiliary patterns onto the substrate covers one of the first sub-regions, and there is a gap between two adjacent first auxiliary patterns.
4. The array substrate according to claim 2, characterized in that, The orthographic projection of the first auxiliary pattern on the substrate covers the two first sub-regions whose orthographic projections on the substrate coincide with those of the first main body portion and the sidewall of the same gate line.
5. The array substrate according to any one of claims 2 to 4, characterized in that, The orthographic projection of the source electrode onto the substrate is located within the range of the orthographic projection of the gate line onto the substrate.
6. The array substrate according to any one of claims 2 to 4, characterized in that, The orthographic projection of one end of the source portion onto the substrate is located outside the orthographic projection of the gate line onto the substrate, and is connected to the first main body portion; Among the plurality of first regions, the region in which the orthographic projections of the source portion and the sidewalls of the gate line on the substrate overlap is the second sub-region; The plurality of auxiliary patterns includes a second auxiliary pattern, the orthographic projection of which covers the second sub-region on the substrate.
7. The array substrate according to claim 6, characterized in that, The second auxiliary pattern is connected to the semiconductor pattern to form an integral structure.
8. The array substrate according to claim 6, characterized in that, The second auxiliary pattern is connected to the first auxiliary pattern closest to the second auxiliary pattern to form an integral structure.
9. The array substrate according to any one of claims 2 to 4, characterized in that, The portion of the orthographic projection of the gate line on the substrate that overlaps with the orthographic projection of the data signal line on the substrate has a dimension of 3.5 μm to 7 μm along the second direction.
10. The array substrate according to claim 1, characterized in that, The first conductive layer includes a plurality of gate lines, which extend along a first direction and are spaced apart along a second direction, wherein the first direction intersects the second direction; The data signal line extends along the second direction, and the portion of the orthographic projection of the data signal line on the substrate that overlaps with the orthographic projection of the gate line on the substrate forms a source portion; Among the plurality of first regions, the region in which the orthographic projections of the sidewalls of the data signal line and the gate line on the substrate overlap is the third sub-region; The plurality of auxiliary patterns includes a third auxiliary pattern, which is arranged along the second direction with the semiconductor pattern, and the orthographic projection of the third auxiliary pattern on the substrate covers the third sub-region.
11. The array substrate according to claim 10, characterized in that, The semiconductor pattern is spaced apart from at least one of the third auxiliary patterns.
12. The array substrate according to claim 10, characterized in that, The semiconductor pattern is connected to at least one of the third auxiliary patterns to form an integral structure.
13. The array substrate according to claim 1, characterized in that, The array substrate further includes: The first electrode is disposed on the side of the second conductive layer away from the substrate; The second electrode is disposed on the side of the first electrode away from the substrate; The second conductive layer further includes a drain portion, which is electrically connected to the semiconductor pattern and the first electrode respectively. The first conductive layer also includes a plurality of first voltage signal lines, which are electrically connected to the second electrode. Among the plurality of first regions, the region in which the orthographic projections of the sidewalls of the data signal line and the first voltage signal line on the substrate overlap is the fourth sub-region; The plurality of auxiliary patterns includes a fourth auxiliary pattern, the orthographic projection of which covers the fourth sub-region on the substrate.
14. The array substrate according to claim 13, characterized in that, One of the fourth auxiliary patterns covers two fourth sub-regions whose sidewalls on the same first voltage signal line and the same data signal line coincide on the orthographic projection of the data signal line onto the substrate.
15. The array substrate according to claim 13 or 14, characterized in that, The fourth auxiliary pattern is spaced apart from the adjacent auxiliary patterns and from the semiconductor pattern.
16. The array substrate according to claim 13 or 14, characterized in that, The fourth auxiliary pattern is connected to the auxiliary pattern closest to the fourth auxiliary pattern to form an integral structure.
17. The array substrate according to claim 1, characterized in that, The interval between the boundary of the orthographic projection of the auxiliary pattern on the substrate and the boundary of the first region covered by the auxiliary pattern is 1 μm to 5 μm.
18. The array substrate according to claim 17, characterized in that, The intervals between at least two boundaries of the orthographic projection of the auxiliary pattern onto the substrate and the boundaries of the first region covered by the auxiliary pattern are not equal.
19. The array substrate according to claim 1, characterized in that, The shape of at least one of the auxiliary patterns projected onto the substrate is the same as the shape of the target segment of the data signal line projected onto the substrate; the projected shape of the target segment onto the substrate is located within the range of the projected shape of the auxiliary pattern onto the substrate.
20. The array substrate according to claim 1, characterized in that, The second conductive layer further includes a drain portion, which is electrically connected to the semiconductor pattern; The region where the orthographic projection of the drain portion on the substrate overlaps with the orthographic projection of the sidewall of the first conductive layer on the substrate is the second region. The orthogonal projection of the semiconductor pattern onto the substrate covers the second region.
21. A display panel, characterized in that, include: The array substrate as described in any one of claims 1 to 20; A color filter substrate is disposed opposite to the array substrate; A liquid crystal layer is disposed between the array substrate and the color filter substrate.
22. A display device, characterized in that, Includes the display panel as described in claim 21.