Memristor with micro-nano interlocking interface
By employing a micro-nano structure of a semiconductor active layer and a charge compensation dielectric layer in a memristor to form a physical interlock, a planar ion migration mechanism is achieved, solving the problems of random resistance control and structural stability in memristors, improving flexibility and durability, and making it suitable for wearable devices and flexible displays.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SUZHOU UNIV
- Filing Date
- 2026-04-08
- Publication Date
- 2026-05-08
AI Technical Summary
Existing memristors rely on conductive filament mechanisms, resulting in strong randomness in resistance adjustment, poor structural stability, and insufficient flexibility, which limits their application in wearable devices and flexible displays.
A micro-nano structure is used to form a physical interlock at the junction of the semiconductor active layer and the charge compensation dielectric layer, realizing a planar ion migration mechanism to replace point-like conductive filaments and enhance mechanical flexibility and bending resistance.
It achieves high linearity and continuous control of resistance, improves electrical and cyclic stability, enhances the flexibility and resilience of memristors, and solves the problems of randomness and structural instability of conductive filaments.
Smart Images
Figure CN224218783U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor memristor technology, and in particular to a memristor with a micro-nano interlocking interface. Background Technology
[0002] With the rapid development of neuromorphic computing and brain-inspired intelligent hardware, developing hardware foundational units capable of simulating the plasticity and memory functions of biological synapses has become a core industry demand. Memristors, as stimulus-dependent circuit elements with a two-terminal structure, are considered key physical components for constructing artificial neural networks due to their highly analogous electrical characteristics to biological synapses. In particular, memristors based on polymer materials, while possessing good biocompatibility, hold promise for achieving continuous resistance control through interfacial ion doping effects, providing an important direction for the physical realization of flexible brain-inspired chips.
[0003] However, existing memristor technology faces a major problem in practical applications: memristors mostly employ a metal-functional layer-metal sandwich structure, and their working principle primarily relies on a conductive filament mechanism. When the top electrode uses an active metal such as silver or aluminum, an electric field causes metal ions to deposit and form a metal filament running through the upper and lower electrodes within the dielectric layer. This working mechanism has inherent drawbacks:
[0004] First, from a physical perspective, the formation and breakage of conductive filaments within the dielectric layer are highly random. Because the deposition sites and growth paths of metal ions cannot be precisely controlled, the resistance state of the memristor exhibits nonlinear, step-like jumps, resulting in severe current discretization. This randomness makes it difficult to achieve precise, continuous resistance adjustment of the memristor, failing to meet the core requirements of neuromorphic computing for polymorphic storage and linear updates of synaptic weights.
[0005] Secondly, because the growth location of the filament is not fixed, the formation and melting of the conductive filament occur at different locations in the dielectric layer during each cycle. This uncontrollable physical process leads to cumulative physical damage to the dielectric layer. As the number of cycles increases, irreversible structural damage gradually forms inside the dielectric layer, thereby reducing the reproducibility and lifespan of the memristor.
[0006] More importantly, metal filaments are inherently brittle physical connections, and their mechanical properties are fundamentally incompatible with flexible substrates. When memristors are applied to wearable devices or flexible displays and subjected to bending stress, the filaments penetrating the dielectric layer are highly susceptible to physical breakage, leading to memristor failure. This defect fundamentally limits the application prospects of memristors in emerging fields such as wearable devices and flexible displays. Utility Model Content
[0007] Therefore, the purpose of this invention is to overcome the defects of memristors, which rely on conductive filament mechanisms, resulting in strong randomness in resistance control, poor structural stability, and insufficient flexibility. The invention provides a memristor with a micro / nano interlocking interface. Through the micro / nano structure at the junction of the semiconductor active layer and the charge compensation dielectric layer, a physical interlock is formed, enabling a planar ion migration mechanism to replace point-like conductive filaments. This improves the linearity of resistance control and electrical stability, while simultaneously enhancing the mechanical flexibility and bending resistance of the memristor through the stress dispersion effect of the interlocking interface.
[0008] To solve the above-mentioned technical problems, this utility model provides a memristor with a micro-nano interlocking interface, comprising:
[0009] Substrate layer;
[0010] A bottom electrode layer is disposed on the upper surface of the substrate layer;
[0011] A charge-compensating dielectric layer is disposed on the upper surface of the bottom electrode layer;
[0012] A semiconductor active layer is disposed on the upper surface of the charge compensation dielectric layer; the junction surface between the semiconductor active layer and the charge compensation dielectric layer is provided with a micro / nano structure, and the semiconductor active layer and the charge compensation dielectric layer are physically interlocked through the micro / nano structure;
[0013] A top electrode layer is disposed on the upper surface of the semiconductor active layer.
[0014] Preferably, the micro / nano structure has a sawtooth texture, which includes alternating first teeth and first recesses formed on the surface of the charge compensation dielectric layer; and alternating second teeth and second recesses formed on the surface of the semiconductor active layer; the first teeth are embedded in the second recesses, and the second teeth are embedded in the first recesses.
[0015] Preferably, the first tooth and / or the second tooth are triangular teeth; the first recess is adapted to the contour of the second tooth; and the second recess is adapted to the contour of the first tooth.
[0016] Preferably, the triangular tooth has an inclined sidewall, and the angle between the sidewall and the horizontal upper surface of the charge compensation dielectric layer is 30° to 60°.
[0017] Preferably, the thickness of the charge compensation dielectric layer is 30nm~200nm.
[0018] Preferably, the ratio of the thickness of the charge compensation dielectric layer to the thickness of the semiconductor active layer is 1:1 to 5:1.
[0019] Preferably, the cross-sectional shape of the micro / nano structure is wavy or trapezoidal wavy, when longitudinally cut along the thickness direction of the memristor.
[0020] Preferably, the top electrode layer comprises a plurality of interconnected grid cells, with stress relief gaps between adjacent grid cells.
[0021] Preferably, the grid cells are hexagonal or honeycomb-shaped.
[0022] Preferably, the thickness of the top electrode layer is 30nm~200nm.
[0023] Compared with the prior art, the above-mentioned technical solution of this utility model has the following beneficial effects:
[0024] The memristor with micro-nano interlocking interface described in this invention forms a physical interlock through the micro-nano structure at the junction of the semiconductor active layer and the charge compensation dielectric layer. This enables a planar ion migration mechanism to replace point-like conductive filaments, thereby improving the linearity of resistance control and electrical stability. At the same time, the stress dispersion effect of the interlocking interface enhances the mechanical flexibility and bending resistance of the memristor.
[0025] Specifically, firstly, by replacing point-like conductive filaments with planar ion migration mechanisms, high linearity and continuous control of resistance values are achieved, overcoming the problem of current discretization in memristors and enabling memristors to more accurately simulate the polymorphic plasticity behavior of biological synapses. Secondly, the micro-nano physical interlocking interface, by constraining ion migration paths and stabilizing the interface structure, maintains the consistency and repeatability of electrical behavior in multiple cycles, effectively improving the cycle stability and lifespan of memristors. Thirdly, the stress dispersion mechanism and mechanical reinforcement effect of the interlocking structure give memristors excellent flexibility and resilience, fundamentally solving the defect of metal filaments being prone to breakage when bent, and providing a feasible solution for the application of memristors in emerging fields such as wearable devices and flexible neuromorphic chips. Attached Figure Description
[0026] To make the content of this utility model easier to understand, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings.
[0027] Figure 1 This is a schematic diagram of the structure of a memristor with a micro-nano interlock interface in a preferred embodiment of the present invention;
[0028] Figure 2 for Figure 1 A partially enlarged schematic diagram of part A of the memristor shown;
[0029] Figure 3 for Figure 1 A three-dimensional schematic diagram of the top electrode layer of the memristor shown;
[0030] Figure 4 for Figure 3 A top view of the top electrode layer shown;
[0031] Figure 5 This is a current-voltage hysteresis loop diagram of a preferred embodiment of the memristor of this utility model;
[0032] Figure 6 The current response curve of the memristor simulating the excitation and inhibition behavior of biological synapses is shown in the preferred embodiment of this utility model.
[0033] Explanation of reference numerals in the accompanying drawings: 2-substrate layer; 4-bottom electrode layer; 6-charge compensation dielectric layer; 8-semiconductor active layer; 10-top electrode layer; 7-micro / nano structure; 71-first tooth; 72-first recess; 73-second tooth; 74-second recess; 12-grid unit; 14-stress relief gap. Detailed Implementation
[0034] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments are not intended to limit the present invention.
[0035] The purpose of this utility model embodiment is to overcome the defects of memristors, which rely on the conductive filament mechanism, resulting in strong randomness in resistance adjustment, poor structural stability, and insufficient flexibility and tolerance, and to provide a memristor with a micro-nano interlocking interface.
[0036] The following combination Figure 1 The technical solution of this utility model will be described in detail with reference to specific embodiments:
[0037] A memristor with a micro / nano interlocking interface is disclosed. The memristor adopts a vertically stacked structure, comprising, from bottom to top, a substrate layer 2 supporting the entire memristor configuration, a bottom electrode layer 4 deposited on the surface of the substrate layer 2, a charge compensation dielectric layer 6 covering the bottom electrode layer 4, a semiconductor active layer 8 in close contact with the charge compensation dielectric layer 6 and forming a physical heterogeneous interface, and a top electrode layer 10 at the top. The junction surface between the semiconductor active layer 8 and the charge compensation dielectric layer 6 is provided with a micro / nano structure 7, and the semiconductor active layer 8 and the charge compensation dielectric layer 6 are physically interlocked through the micro / nano structure 7.
[0038] Specifically, the substrate layer 2 is made of a flexible material, either polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), which has good flexibility and transparency and can provide stable mechanical support for the upper structure.
[0039] The bottom electrode layer 4 is selected from gold or platinum metal thin films with a thickness of 30nm~200nm. This thickness avoids discontinuities in extremely thin regions, ensuring carrier injection. Furthermore, the excellent film quality at this thickness allows for a nanoscale flat interface, thereby optimizing the uniformity of the electric field distribution at the electrode / functional layer interface and improving the consistency of the memristor's resistive switching cycle. The bottom electrode layer 4 is deposited on the surface of the substrate layer 2 using a magnetron sputtering process. During deposition, the sputtering power and deposition rate are controlled to ensure the density and uniformity of the film.
[0040] The charge-compensating dielectric layer 6 is selected from polyurethane urea (PUU) or polyvinyl alcohol (PVA) films; this material has good ion-accommodating space and charge-compensating ability, and can work synergistically with the upper semiconductor active layer 8 to achieve a planar ion migration mechanism. Its thickness is 30nm~200nm, and this thickness range is designed to ensure the voltage division effect of the dielectric layer and prevent electrical breakdown of the memristor.
[0041] The semiconductor active layer 8 is a semiconductor thin film structure with ion transport channels. The thickness ratio of the charge compensation dielectric layer 6 to the semiconductor active layer 8 is 1:1 to 5:1. The thickness ratio is used to consider: first, the ratio optimizes the electric field distribution between the two layers, ensuring that the active layer achieves effective resistive switching behavior at a lower driving voltage; second, through precise control of the thickness ratio, the charge compensation rate can be matched with the carrier transport characteristics in the active layer, thereby improving the linearity and multi-state control capability of the resistive switching process.
[0042] The top electrode layer 10 is selected from gold or platinum metal thin films with a thickness of 30nm to 200nm. By avoiding discontinuities in extremely thin regions, carrier injection is ensured. Secondly, the excellent film quality at this thickness enables the achievement of a nanoscale flat interface, thereby optimizing the uniformity of the electric field distribution at the electrode / functional layer interface and improving the consistency of the memristor's resistive switching cycle. The top electrode layer 10 is deposited on the surface of the semiconductor active layer 8 through a thermal evaporation process. During the deposition process, the evaporation rate and deposition temperature are controlled to avoid thermal damage to the underlying organic semiconductor material.
[0043] In this embodiment of the invention, the core feature of the charge compensation dielectric layer 6 lies in the presence of micro / nano structures on its upper surface. Specifically, in this embodiment, periodically arranged micro / nano structures 7 are formed on the surface of the PUU film using a nanoimprinting process, as shown in the figure. Figure 2As shown, the micro / nano structure 7 includes alternating first teeth 71 and first recesses 72, arranged in a periodic array along the surface of the charge compensation dielectric layer 6. The first teeth 71 are triangular teeth with inclined sidewalls, the angle between the sidewalls and the horizontal upper surface of the charge compensation dielectric layer 6 being approximately 30° to 60°, preferably 45°. The period of the micro / nano structure is approximately 300 nm, which is the distance between the vertices of two adjacent first teeth 71; the height of the first teeth is approximately 100 nm, which is the vertical distance from the lowest point of the first recess 72 to the vertices of the first teeth 71. The selection of the above size range is based on the following considerations: this scale can produce a significant mechanical anchoring effect without affecting the film formation continuity of the upper active layer due to excessive structure size, and it can match the thickness of the subsequent semiconductor active layer to ensure a uniform distribution of the interfacial electric field.
[0044] The semiconductor active layer 8 is deposited on the surface of the charge compensation dielectric layer 6 with a micro / nano structure via spin coating. During spin coating, the solution spreads uniformly under centrifugal force and fully fills the recessed areas of the micro / nano structure on the surface of the charge compensation dielectric layer 6. As the solvent evaporates, the material forms a film on the surface of the micro / nano structure, creating a complementary structure that matches the surface texture of the charge compensation dielectric layer 6. Specifically, the lower surface of the semiconductor active layer 8 forms alternating second teeth 73 and second recesses 74, where the second teeth 73 are embedded in the first recesses 72 of the charge compensation dielectric layer 6, and the second recesses 74 are embedded in the first teeth 71 of the charge compensation dielectric layer 6. Thus, a three-dimensional interlocking physical interface is formed between the semiconductor active layer 8 and the charge compensation dielectric layer 6, and the two layers are tightly mechanically bonded through the micro / nano structure 7.
[0045] The memristor with a micro-nano interlocked interface fabricated in this embodiment operates on the following core mechanism: When an electric field is applied between the top electrode layer 10 and the bottom electrode layer 4, doped ions in the semiconductor active layer 8 migrate under the drive of the electric field, either entering the charge compensation dielectric layer 6 or returning from the charge compensation dielectric layer 6 to the semiconductor active layer 8. Because of the three-dimensional interlocked micro-nano interface between the semiconductor active layer 8 and the charge compensation dielectric layer 6, the ion migration behavior is no longer a local, random point-like process, but rather a planar migration along the entire interlocked interface. This planar migration mechanism allows ions to be uniformly distributed and redistributed throughout the interface region, thereby achieving continuous and linear control of the memristor's resistance. Simultaneously, the micro-nano interlocked interface tightly bonds the two layers together through a physical anchoring effect, maintaining the stability and repeatability of the ion migration path during multiple cycles, avoiding electrical performance fluctuations and cumulative physical damage caused by the random growth of filaments in filament-type memristors. When a memristor is subjected to bending stress, the micro-nano interlocking interface effectively locks the interlayer displacement by dispersing the lateral shear stress to the inclined sidewalls of the microstructure, preventing physical peeling between heterogeneous layers and ensuring the structural integrity and functional stability of the memristor under dynamic deformation.
[0046] From the perspective of its working mechanism, this invention abandons the approach of relying on metal ion deposition to form point-like conductive filaments, and instead adopts a stacked heterostructure of a charge-compensating dielectric layer and a semiconductor active layer. When an electric field is applied, ions migrate in a planar manner between the two layers rather than forming localized point-like filaments. This planar migration mechanism allows ions to be uniformly distributed and redistributed throughout the entire interface region, eliminating the irregularity and randomness of conductive filament formation from a physical perspective. Since the ion migration path is no longer limited to a randomly formed filament channel, but rather spreads throughout the entire interlocked interface, the resistance change exhibits continuous and linear characteristics, fundamentally solving the problem of current discretization in traditional memristors.
[0047] From the perspective of structural stability, the micro-nano interlocking interface physically fixes and constrains the ion migration path. Specifically, the complementary structure formed by the micro-nano texture on the dielectric layer surface and the conformal filling of the active layer material constitutes a mortise and tenon-like physical anchoring mechanism. This structure exerts a dual constraint on ion migration behavior: on the one hand, the interlocking interface provides a stable and repeatable ion migration path, ensuring consistent ion redistribution behavior in each cycle and avoiding electrical performance fluctuations caused by the random growth of traditional filaments; on the other hand, the existence of the interlocking structure confines ion migration to the spatial range defined by the micro-nano texture. Even after multiple cycles, ion migration continues along the same interface path, preventing cumulative physical damage to the dielectric and active layers, thereby significantly improving the reproducibility and lifespan of the memristor.
[0048] To verify the technical effectiveness of this invention, the memristor prepared according to the specific embodiments was subjected to electrical performance and mechanical stability tests.
[0049] In electrical performance testing, refer to Figure 5 As shown, a voltage signal was applied to the memristor, linearly scanning from +20V to -20V and back to +20V, and the current-voltage hysteresis loop of the memristor was measured. The test results show that the current window of the memristor exhibits high symmetry, and the resistance change is continuous and smooth, without the step jump phenomenon commonly seen in filament-type memristors. This indicates that the planar ion migration mechanism of this invention effectively overcomes the randomness problem of conductive filaments and achieves high linearity continuous control of the resistance value.
[0050] Reference Figure 6 As shown, continuous excitation and inhibition pulses were applied to the memristor, and the current response was monitored under a fixed read voltage. The results showed that the conductance of the memristor exhibited continuous, linearly adjustable symmetrical behavior, demonstrating its potential in simulating biological synaptic plasticity. After 350 cycles, its linearity of regulation did not show significant decay, demonstrating good reproducibility and stability.
[0051] In mechanical stability testing, memristors were attached to bending fixtures with different radii of curvature for dynamic bending tests. Test results showed that when the bending radius was as small as 5 mm, the electrical performance of the memristor remained stable, with no significant performance degradation or failure observed. Interface morphology observation of the bent memristors revealed that the micro-nano interlocking interface remained intact, with no signs of delamination or slippage between the two material layers. This verifies that the micro-nano structure effectively disperses bending stress through a physical anchoring effect, preventing interlayer displacement and delamination, and endowing the memristor with excellent flexibility and resilience.
[0052] From the perspective of flexibility tolerance, the micro-nano interlocking interface achieves the dual functions of stress dispersion and mechanical reinforcement at the mechanical level. When a memristor is applied to flexible electronic devices and subjected to bending stress, the transverse shear stress between the layers acts on the inclined sidewalls of the micro-nano structure. Through the physical anchoring effect, the concentrated stress is dispersed to all stress-bearing surfaces of the entire interlocking interface, effectively locking the relative displacement between the two layers of materials. Unlike filament-type memristors where the brittle metal filaments directly bear all the bending stress, this invention disperses the mechanical stress to the entire interface region through the micro-nano structure, enabling the memristor to maintain structural and functional integrity under large-amplitude or high-frequency bending. More importantly, the three-dimensional interlocking structure formed by the interlocking interface is itself a mechanical reinforcement structure, which physically combines the two functional materials into a whole, fundamentally eliminating the risk of interlayer delamination.
[0053] In another embodiment, the cross-sectional shape of the micro / nano structure is wavy when longitudinally cut along the thickness direction of the memristor. Specifically, this embodiment uses nanoimprint lithography to form a periodically arranged wavy texture on the surface of the PUU film. This wavy texture consists of alternating, smoothly undulating peaks and troughs, arranged in a periodic array along the surface of the charge compensation dielectric layer 6. The period of the micro / nano structure is approximately 350 nm, and the distance between two adjacent peaks is the period; the vertical distance between a peak and a trough is approximately 80 nm. Compared to the sharp serrated edges of a zigzag texture, the wavy texture has a smooth contour change, a larger radius of curvature, and no sharp turning points.
[0054] The lower surface of the semiconductor active layer 8 forms an undulating profile that matches the wave-like texture of the charge compensation dielectric layer 6. The trough regions of the semiconductor active layer 8 are embedded in the peak regions of the charge compensation dielectric layer 6, and the peak regions of the semiconductor active layer 8 cover the trough regions of the charge compensation dielectric layer 6. Thus, a three-dimensional interlocking physical interface is formed between the semiconductor active layer 8 and the charge compensation dielectric layer 6, and the two layers of materials achieve a tight mechanical bond through the wave-like micro / nano structure.
[0055] The fabrication process of the wavy micro / nano structure is as follows: First, a nanoimprint mold with a wavy, concave-convex pattern is prepared. The pattern of this mold is complementary to the surface texture of the desired charge compensation dielectric layer 6. A PUU precursor solution is coated onto the surface of the bottom electrode layer 4. The mold is then imprinted onto the PUU layer surface at an appropriate temperature, allowing the PUU material to fill the recessed areas of the mold. After UV curing or thermal curing to cross-link the PUU, the mold is removed, resulting in a wavy micro / nano structure on the surface of the PUU dielectric layer that is complementary to the mold pattern. By adjusting the pattern parameters of the mold and the imprinting process conditions, the period, amplitude, and overall morphology of the wavy texture can be precisely controlled.
[0056] In another embodiment, the cross-sectional shape of the micro / nano structure is trapezoidal wave-like when longitudinally cut along the thickness direction of the memristor. The trapezoidal wave-like texture consists of alternating plateau regions and transition regions: each periodic unit includes a horizontal upper plateau, a sloping sidewall transition section, and a horizontal lower plateau, connected by sloping sidewalls to form a trapezoidal wave-like undulating profile. The period of the micro / nano structure is approximately 400 nm, and the distance between the center points of two adjacent upper plateaus is this period; the vertical distance between the upper and lower plateaus is approximately 100 nm; the angle between the sloping sidewalls and the horizontal plane is approximately 50°. The lower surface of the semiconductor active layer 8 has an undulating profile matching the trapezoidal wave-like texture of the charge compensation dielectric layer 6, and the two layers form close contact in both the horizontal plateau region and the sloping sidewall region.
[0057] The fabrication process of trapezoidal wavy micro / nano structures is similar to that of wave-like structures, except that a nanoimprint mold with a trapezoidal wavy pattern is used. By adjusting the width of the platform, the tilt angle of the sidewalls, and the height of the steps in the mold pattern, the geometric parameters of the trapezoidal wavy texture can be precisely controlled.
[0058] In the aforementioned embodiments, the top electrode layer 10 uses a continuous and dense metal thin film. Although this can achieve good conductivity, it has the following problems in flexible electronics applications: First, metal materials are inherently brittle. When the substrate layer 2 is bent, the continuous and dense metal thin film will generate large tensile stress, which can easily lead to cracking or breakage of the film, causing the electrode conductivity path to be interrupted. Second, after the electrode breaks, the memristor fails as a whole, and the fractured area may produce sharp edges, causing secondary mechanical damage to the underlying functional layer. Third, the strain capability of the continuous thin film electrode is limited, making it difficult to adapt to the requirements of high-frequency and large-amplitude dynamic bending, which limits the reliability of memristors in wearable devices, flexible displays and other fields.
[0059] To address this problem, the present invention further provides a memristor that, while maintaining good conductivity, improves the mechanical flexibility and bending resistance of the top electrode layer 10. The following is a detailed description... Figure 3 and Figure 4 The solution of this embodiment will be described in detail.
[0060] The top electrode layer 10 comprises multiple interconnected grid units 12, with stress relief gaps 14 between adjacent grid units. Specifically, in one embodiment, the top electrode layer 10 adopts a hexagonal grid structure, i.e., the grid units are hexagonal in shape; multiple hexagonal grid units are interconnected by metal segments to form an overall grid-like electrode; stress relief gaps 14 are provided between adjacent hexagonal grid units, which are blank areas between grid units where no metal material is deposited.
[0061] The fabrication process of the hexagonal grid electrode in this embodiment is as follows: First, a layer of photoresist is spin-coated onto the surface of the semiconductor active layer 8. Then, a photomask with a hexagonal grid pattern is exposed to ultraviolet light, and after development, a photoresist opening region complementary to the desired electrode pattern is formed. Next, a gold film is deposited under the action of a gold target through an electron beam evaporation process; the gold material is deposited in the photoresist opening region to form the metal portion of the hexagonal grid unit. Finally, the residual photoresist is removed by a lift-off process to obtain the hexagonal grid-shaped top electrode layer. In this fabrication process, by adjusting the pattern parameters of the photomask, the size of the hexagonal grid unit, the width of the metal segment, and the width of the stress relief gap 14 between adjacent units can be precisely controlled.
[0062] The design principle of the hexagonal grid electrode is based on the stress relief mechanism of geometric redundancy. When the flexible substrate containing the memristor bends, the tensile or compressive strain generated in the substrate is transferred to the top electrode layer 10. For continuous and dense metal films, this strain cannot be effectively released and will directly accumulate into tensile stress inside the film. When the stress exceeds the yield strength of the metal material, the film cracks. However, the hexagonal grid electrode has the following structural characteristics: First, there are preset stress relief gaps 14 between the grid units 12. These gaps are blank areas and do not bear stress. Second, the hexagonal grid units are connected only by metal segments, and the connection areas have a certain deformation capacity. Third, the hexagonal structure itself has good geometric stability and can absorb strain through the slight tilting or displacement of the units when under stress. When bending stress is applied to the grid electrode, the stress relief gaps 14 provide displacement space for the grid units 12. Adjacent units can move or tilt relative to each other, releasing the tensile stress originally concentrated inside the continuous film into the stress relief gaps 14, thereby avoiding excessive stress on the metal material itself and effectively preventing the electrode from cracking and breaking.
[0063] In another embodiment, the top electrode layer 10 adopts a honeycomb structure. It should be noted that while honeycomb structures and hexagonal grid structures are geometrically similar, honeycomb structures typically refer to a regular, densely packed arrangement of hexagons, with adjacent hexagons sharing edges, forming a periodic array similar to a natural honeycomb. In this embodiment, the honeycomb grid cells are also interconnected by metal segments, and stress relief gaps 14 are also provided between adjacent cells, but the way these gaps are set is slightly different from that of the hexagonal grid.
[0064] Specifically, in the honeycomb grid electrode of this embodiment, each hexagonal honeycomb cell is surrounded by a metal frame. Adjacent honeycomb cells are electrically connected by sharing a portion of the frame, while stress relief gaps are reserved in the central region of each honeycomb cell or between the frames. This design maintains the honeycomb dense structure while imparting strain capability to the electrode layer through the presence of gaps. The fabrication process of the honeycomb grid electrode is the same as that of the hexagonal structure, except that a photolithographic mask with a honeycomb pattern is used.
[0065] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the protection scope of this invention.
Claims
1. A memristor with a micro / nano interlock interface, characterized in that, include: Substrate layer; A bottom electrode layer is disposed on the upper surface of the substrate layer; A charge-compensating dielectric layer is disposed on the upper surface of the bottom electrode layer; A semiconductor active layer is disposed on the upper surface of the charge compensation dielectric layer; the junction surface between the semiconductor active layer and the charge compensation dielectric layer is provided with a micro / nano structure, and the semiconductor active layer and the charge compensation dielectric layer are physically interlocked through the micro / nano structure; A top electrode layer is disposed on the upper surface of the semiconductor active layer.
2. The memristor with a micro / nano interlocking interface according to claim 1, characterized in that, The micro / nano structure has a sawtooth texture, which includes alternating first teeth and first recesses formed on the surface of the charge compensation dielectric layer; and alternating second teeth and second recesses formed on the surface of the semiconductor active layer; the first teeth are embedded in the second recesses, and the second teeth are embedded in the first recesses.
3. The memristor with a micro / nano interlocking interface according to claim 2, characterized in that, The first tooth and / or the second tooth are triangular teeth; the first recess is adapted to the contour of the second tooth; the second recess is adapted to the contour of the first tooth.
4. The memristor with a micro / nano interlocking interface according to claim 3, characterized in that, The triangular tooth has an inclined sidewall, and the angle between the sidewall and the horizontal upper surface of the charge compensation dielectric layer is 30° to 60°.
5. The memristor with a micro / nano interlocking interface according to claim 1, characterized in that, The thickness of the charge compensation dielectric layer is 30nm~200nm.
6. The memristor with a micro / nano interlocking interface according to claim 1 or 5, characterized in that, The ratio of the thickness of the charge compensation dielectric layer to the thickness of the semiconductor active layer is 1:1 to 5:
1.
7. The memristor with a micro / nano interlocking interface according to claim 1, characterized in that, When longitudinally cut along the thickness direction of the memristor, the cross-sectional shape of the micro / nano structure is wavy or trapezoidal.
8. The memristor with a micro / nano interlocking interface according to claim 1, characterized in that, The top electrode layer comprises multiple interconnected grid cells, with stress relief gaps between adjacent grid cells.
9. The memristor with a micro / nano interlocking interface according to claim 8, characterized in that, The grid cells are hexagonal or honeycomb-shaped.
10. The memristor with a micro / nano interlocking interface according to claim 1 or 8, characterized in that, The thickness of the top electrode layer is 30nm~200nm.