Display panel and display device

Abstract

The utility model relates to the field of display, and discloses a display panel and a display device.The display panel comprises a substrate and a plurality of sub-pixel units arranged on the substrate, each sub-pixel unit comprises a shared electrode wire, a flat layer and a pixel electrode, the shared electrode wire is arranged on one side of the substrate, the flat layer is arranged on the side, away from the substrate, of the shared electrode wire, and the pixel electrode is arranged on the flat layer. A first via hole is formed in the flat layer, the pixel electrode is arranged on the side, away from the substrate, of the flat layer, part of the pixel electrode is located in the first via hole, and the shared electrode wire and the pixel electrode are overlapped in the setting area of the first via hole. According to the technical scheme, the pixel electrode and the shared electrode wire are electrically connected in a mode of fusing the flat layer at the position of the first via hole when the position is reserved at the flat layer of the display panel and the display abnormity of dark spots of the display panel is caused when the pixel electrode is in the open circuit state; therefore, the signal can be transmitted to the pixel electrode by the shared electrode wire, so that the dark spot repairing effect of the pixel electrode is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] The display panel may have a disconnected pixel electrode, resulting in a dark spot. In order to repair the dark spot, the related art adopts a wiring method to connect the disconnected pixel electrode between the pixel electrodes to repair the dark spot.

[0003] However, the wiring method for repairing the dark spot may make the display panel dark. CONTENT OF THE INVENTION

[0004] Embodiments of the present application provide a display panel, which repairs the dark spot of the display panel while ensuring the overall brightness of the display panel, so as to at least partially solve the above technical problems.

[0005] In order to achieve the above purpose, according to a first aspect of the present application, a display panel is provided, comprising: a substrate and a plurality of sub-pixel units arranged on the substrate, each of the sub-pixel units comprising:

[0006] a shared electrode line arranged on one side of the substrate;

[0007] a planar layer arranged on a side of the shared electrode line away from the substrate, the planar layer being provided with a first via hole; and

[0008] a pixel electrode arranged on a side of the planar layer away from the substrate, part of the pixel electrode being located in the first via hole.

[0009] In the setting area of the first via hole, the shared electrode line and the pixel electrode overlap.

[0010] Optionally, the pixel electrode comprises a first main electrode, and the first main electrode is arranged in parallel with the extension direction of the shared electrode line.

[0011] The first via hole and the first main electrode have an overlapping part on the planar layer.

[0012] Optionally, the pixel electrode further comprises a second main electrode arranged in cross with the first main electrode.

[0013] The first via hole is located in the intersection area of the first main electrode and the second main electrode.

[0014] Optionally, the sub-pixel unit further comprises:

[0015] a common electrode line between the substrate and the shared electrode line, the common electrode line and the shared electrode line have a parallel extension direction and have an overlapping portion with the shared electrode line;

[0016] wherein the common electrode line is disconnected in a region corresponding to the first via.

[0017] Optionally, the first via is non-overlapped with the common electrode line in the orthographic projection of the substrate.

[0018] Optionally, the line width of the common electrode line is greater than the line width of the first stem electrode, and the line width of the first stem electrode is greater than the line width of the shared electrode line.

[0019] Optionally, the depth of the first via is less than or equal to the thickness of the planar layer.

[0020] Optionally, each of the sub-pixel units further comprises:

[0021] a first insulating layer between the planar layer and the shared electrode line;

[0022] wherein a second via is formed on the first insulating layer, the second via and the first via are in communication, and the pixel electrode is electrically connected with the shared electrode line through the first via and the second via.

[0023] Optionally, the sub-pixel unit comprises a first display area, a second display area, and a transistor arrangement area between the first display area and the second display area, and the area of the first display area is less than the area of the second display area.

[0024] wherein the first via is located in the second display area.

[0025] According to a second aspect of the present application, a display device is provided, comprising the display panel as described above.

[0026] The display panel provided by the embodiments of the present application can repair dark spots without reducing the overall brightness of the display panel.

[0027] In the display panel provided by the embodiment of the present application, the display panel comprises a substrate and a plurality of sub-pixel units arranged on the substrate. Each sub-pixel unit comprises a shared electrode line, a planar layer and a pixel electrode. The shared electrode line is arranged on one side of the substrate. The planar layer is arranged on the side of the shared electrode line away from the substrate. A first via hole is formed in the planar layer. The pixel electrode is arranged on the side of the planar layer away from the substrate, and part of the pixel electrode is located in the first via hole. In the setting area of the first via hole, the shared electrode line and the pixel electrode overlap. According to the above technical solution, part of the pixel electrode is located in the first via hole of the planar layer, so as to reduce the vertical distance between part of the pixel electrode and the shared electrode line. In this way, a reserved position is provided in the planar layer of the display panel. When the pixel electrode is in an open circuit state and causes display abnormality of the display panel in the form of dark spots, the pixel electrode and the shared electrode line are electrically connected by fusing the planar layer at the position of the first via hole. In this way, the shared electrode line can transmit signals to the pixel electrode, so as to repair the dark spots of the pixel electrode, and avoid the situation that the display panel as a whole becomes dark due to the repair of the disconnected pixel electrode by wiring.

[0028] Other features and advantages of the present application will be described in detail in the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0030] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0031] Figure 1 is a schematic diagram of the overall structure of the display panel provided in the exemplary embodiment of the present application;

[0032] Figure 2 is an enlarged schematic diagram of B in Figure 1

[0033] Figure 3 is another schematic diagram of the first via hole in the exemplary embodiment of the present application;

[0034] Figure 4 is a schematic diagram of the structure of the shared electrode line, the common electrode line and the first via hole provided in the exemplary embodiment of the present application;

[0035] Figure 5 ​is another structure schematic view of the shared electrode line and the common electrode line and the first via provided in the exemplary embodiments of the present application;

[0036] Figure 6 is a cross-sectional structure schematic view of D-D along Figure 4

[0037] Figure 7 is a structure schematic view of the pixel electrode and the shared electrode line and the common electrode line provided in the exemplary embodiments of the present application;

[0038] Figure 8 is a cross-sectional structure schematic view of the shared electrode line and the common electrode line and the first via and the second via provided in the exemplary embodiments of the present application;

[0039] Figure 9 is a cross-sectional structure schematic view of another structure of the pixel electrode and the shared electrode line and the common electrode line provided in the exemplary embodiments of the present application;

[0040] Figure 10 is a cross-sectional structure schematic view of C-C provided in the exemplary embodiments of the present application. Figure 2

[0041] BRIEF DESCRIPTION OF THE DRAWINGS

[0042] 10, display panel;

[0043] 100, substrate; 200, sub-pixel unit; 200a, first via; 200b, second via;

[0044] 210, shared electrode line; 220, planar layer; 230, pixel electrode;

[0045] 231, first main trunk electrode; 232, second main trunk electrode;

[0046] 240, common electrode line; 241, first sub-common electrode line; 242, second sub-common electrode line;

[0047] 250, first insulating layer; 260, second insulating layer;

[0048] A1, first display area; A2, second display area; A3, transistor arrangement area. DETAILED DESCRIPTION

[0049] ​​With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort are within the protection scope of the present application.

[0050] The pixel electrode of the display panel may be disconnected, resulting in a dark spot. In order to repair the dark spot, the disconnected pixel electrode is connected by wiring between the pixel electrodes in the related art, so as to repair the dark spot.

[0051] The disconnected pixel electrode of the thin film transistor in the related art, that is, ITO2, causes the pixel to be unable to be normally charged after being disconnected, and further causes the display panel to be abnormal, for example, a long line connection between adjacent display areas can be used to re-input voltage to the disconnected pixel electrode, but this method will cause the voltage of the display area borrowed by the voltage to be reduced, and further cause the brightness of the display area borrowed by the voltage to be darkened.

[0052] According to a first aspect of the present application, referring to Figures 1 to 7 , a display panel 10 is provided, comprising: a substrate 100 and a plurality of sub-pixel units 200 arranged on the substrate 100, each sub-pixel unit 200 comprising: a shared electrode line 210, a planar layer 220 and a pixel electrode 230.

[0053] Referring to Figure 7 , the shared electrode line 210 in the embodiments of the present application is arranged on one side of the substrate 100, the planar layer 220 is arranged on the side of the shared electrode line 210 away from the substrate 100, and the pixel electrode 230 is arranged on the side of the planar layer 220 away from the substrate 100. A first via hole 200a is formed on the planar layer 220, and part of the pixel electrode 230 is located in the first via hole 200a.

[0054] In the setting area of the first via hole 200a, the shared electrode line 210 and the pixel electrode 230 overlap.

[0055] In this embodiment, through the above technical solution, some pixel electrodes 230 are located within the first via 200a of the planarization layer 220, which can reduce the vertical spacing between some pixel electrodes 230 and the shared electrode line 210. This allows the reserved position of the planarization layer 220 of the display panel 10 to be electrically connected to the shared electrode line 210 by melting the planarization layer 220 at the reserved position of the first via 200a when the pixel electrode is in an open circuit state, causing a display abnormality of dark spots on the display panel. This allows the shared electrode line 210 to transmit signals to the pixel electrode 230, thereby achieving the effect of repairing dark spots on the pixel electrode 230 and avoiding the situation where the entire display panel 10 becomes dark due to the repair of the disconnected pixel electrode 230 by wiring.

[0056] It should be noted that the overlap of the shared electrode line 210 and the pixel electrode 230 within the setting area of ​​the first via 200a means that at the position where the shared electrode line 210 and the pixel electrode 230 overlap, the first via 200a is provided on the shared electrode line 210, and a portion of the pixel electrode 230 is located within the first via 200a, which can reduce the spacing between this portion of the pixel electrode 230 and the shared electrode line 210.

[0057] In the embodiments of this application, when the pixel electrode 230 is in an open circuit state, the first via 200a corresponding to the planarization layer 220 can be fused to allow the pixel electrode 230 to be electrically connected to the shared electrode line 210, thereby achieving the effect that the shared electrode line 210 can provide a compensation signal to the pixel electrode 230, so that the pixel electrode 230 can be adjusted from an open circuit state to a pass-through state.

[0058] For example, the first via 200a can be a through hole formed in the planarization layer 220. That is, along the thickness direction of the planarization layer 220, at the overlapping position of the pixel electrode 230 and the shared electrode line 210, a first via 200a is formed on the planarization layer 220 corresponding to the thickness of the planarization layer 220. In this case, the distance between the pixel electrode 230 and the shared electrode line 210 can be reduced, and the obstruction caused by the thickness during the melting process can be reduced.

[0059] It should be noted that the reference Figure 7 Reducing the spacing between the pixel electrode 230 and the shared electrode line 210 means that the spacing between the part of the pixel electrode 230 not within the first via 200a and the shared electrode line 210 is J1, while the spacing between the other part of the pixel electrode 230 within the first via 200a and the shared electrode line 210 is J2. In this case, J1 is greater than J2. This makes it easier to operate during the process of forming an electrical connection between the pixel electrode 230 and the shared electrode line 210, and the obstruction provided by the thickness of the planarization layer 220 is reduced.

[0060] In this embodiment, the thickness direction refers to the direction in which the planarization layer 220 is disposed toward the substrate 100.

[0061] In some other embodiments, reference is made to... Figure 6 and Figure 8 The first via 200a can also be a countersunk hole provided in the planarization layer 220, that is, the first via 200a does not penetrate the planarization layer 220 along the thickness direction of the planarization layer 220.

[0062] The inner wall surface of the first via 200a in this embodiment can be constructed as a slope angle. The slope angle of the inner wall surface of the first via 200a in this embodiment ranges from 0° to 60° to avoid discontinuous deposition of the pixel electrode 230 in the via. For example, it can be 10°, 15°, 20°, 25°, or 30°. The specific value is set according to the actual situation.

[0063] It should also be noted that the cross-section of the first via 200a can be constructed as a trapezoid, and along the thickness direction of the flat layer 220 from top to bottom, the size of the lower base of the trapezoidal cross-section is smaller than the size of the upper base of the trapezoidal cross-section.

[0064] The pixel electrode 230 in this embodiment is made of indium tin oxide.

[0065] In some embodiments, reference Figures 1 to 6 The pixel electrode 230 includes a first main electrode 231, which is arranged parallel to the extension direction of the shared electrode line 210.

[0066] The first via 200a and the first main electrode 231 have an overlapping portion on the planarization layer 220.

[0067] By setting the first main electrode 231 and the shared electrode line 210 in parallel directions, and by having the first via 200a and the first main electrode 231 have overlapping projections on the planarization layer 220, the display panel 10 can be displayed more uniformly. After forming the first via 200a on the planarization layer 220, the portion of the first main electrode 231 corresponding to the first via 200a can be placed in the first via 200a. Then, through a fusing operation, the first main electrode 231 and the shared electrode line 210 are brought into contact, so that the shared electrode line 210 can transmit signals to the first main electrode 231.

[0068] In some embodiments, the pixel electrode 230 further includes a second main electrode 232 that is disposed intersecting the first main electrode 231, wherein the first via 200a is located in the intersection area of ​​the first main electrode 231 and the second main electrode 232.

[0069] In this embodiment, the structure of the main electrode in the intersection area of ​​the first main electrode 231 and the second main electrode 232 is more stable. Therefore, by opening the first via 200a in this area, the stability of the connection and the stability of the signal transmission can be guaranteed.

[0070] In some embodiments, the sub-pixel unit 200 further includes a common electrode line 240.

[0071] In this embodiment, the common electrode line 240 is located between the substrate 100 and the shared electrode line 210, with the extension directions of the common electrode line 240 and the shared electrode line 210 being parallel and having an overlapping portion with the shared electrode line 210. The common electrode line 240 is disconnected in the region corresponding to the first via 200a.

[0072] In this embodiment, by disconnecting the area on the common electrode line 240 corresponding to the first via 200a, it is possible to avoid the heat generated during the melting of the planarization layer 220 at the first via 200a, which could also damage the common electrode line 240 and cause abnormal display of the display panel 10.

[0073] For example, the common electrode line 240 includes a first sub-common electrode line 241 and a second sub-common electrode line 242. The first sub-common electrode line 241 and the second sub-common electrode line 242 are spaced apart, and the spaced apart in this embodiment corresponds to the position of the first via 200a, thereby disconnecting the common electrode line 240 from the area corresponding to the first via 200a.

[0074] In some embodiments, the orthographic projection of the first via 200a onto the substrate 100 does not overlap with the orthographic projection of the common electrode line 240 onto the substrate 100.

[0075] In this embodiment, by ensuring that the orthographic projection of the first via 200a on the substrate 100 does not overlap with the orthographic projection of the common electrode line 240 on the substrate 100, it is further guaranteed that the heat generated during melting will not damage the common electrode line 240.

[0076] In some other embodiments, reference is made to... Figure 6 Alternatively, the orthographic projection of the first via 200a on the substrate 100 can be partially overlapped with the orthographic projection of the common electrode line 240 on the substrate 100. That is, the orthographic projection of a portion of the edge of the first via 200a on the substrate 100 can overlap with the orthographic projection of the common electrode line 240 on the substrate 100. In this way, a certain stress dispersion can be achieved, ensuring the structural stability of the display panel 10.

[0077] In some embodiments, the linewidth of the common electrode line 240 is greater than the linewidth of the first main electrode 231, and the linewidth of the first main electrode 231 is greater than the linewidth of the shared electrode line 210. In this way, the narrow linewidth of the collinear electrode line can maintain the effect of high light transmittance.

[0078] refer to Figure 3 In this embodiment of the application, the line width of the common electrode line 240 is defined as W1, the line width of the first main electrode 231 is defined as W2, and the line width of the shared electrode line 210 is defined as W3. Then W1 is greater than W2, and W2 is greater than W3.

[0079] In some embodiments, the depth of the first via 200a is less than or equal to the thickness of the planarization layer 220.

[0080] In this embodiment of the application, the depth of the first via 200a is defined as H1, and the thickness of the planarization layer 220 is defined as H2, then H1 is less than or equal to H2.

[0081] For example, refer to Figure 8 and Figure 9 In the embodiment of this application, when the first via 200a is constructed as a through hole in the planarization layer 220, the depth H1 of the first via 200a is equal to the thickness H2 of the planarization layer 220.

[0082] refer to Figure 6 In this embodiment of the application, the first via 200a can also be a countersunk hole provided in the planarization layer 220. That is, when the first via 200a does not penetrate the planarization layer 220 along the thickness direction of the planarization layer 220, the depth H1 of the first via 200a is less than the thickness H2 of the planarization layer 220.

[0083] In some embodiments, each sub-pixel unit 200 further includes a first insulating layer 250.

[0084] refer to Figure 10 In this embodiment of the application, the first insulating layer 250 is disposed between the planarization layer 220 and the shared electrode line 210. A second via 200b is formed on the first insulating layer 250. The second via 200b and the first via 200a are connected. The pixel electrode 230 passes through the first via 200a and the second via 200b and is electrically connected to the shared electrode line 210.

[0085] In this embodiment, by opening a second via 200b on the first insulating layer 250, and having the second via 200b connected to the first via 200a, the pixel electrode 230 can pass through the first via 200a and the second via 200b to be electrically connected to the shared electrode line 210, and a certain insulation effect is achieved between the planarization layer 220 and the shared electrode line 210.

[0086] For example, refer to Figure 8 The first via 200a can be constructed as a through hole on the planarization layer 220, and the second via 200b can be constructed as a countersunk hole on the first insulating layer 250. When the pixel electrode 230 is disconnected, the position of the countersunk hole in the first insulating layer 250 is melted, thereby achieving the effect of electrically connecting the pixel electrode 230 with the shared electrode line 210.

[0087] It should be noted that the inner wall surface of the second via 200b can also be constructed as a slope angle, and the slope angle of the inner wall surface of the second via 200b is set to be the same as the slope angle of the inner wall surface of the first via 200a. This ensures that the inner wall surfaces of the first via 200a and the second via 200b can form a continuous slope, which enables better electrical connection between the pixel electrode 230 and the shared electrode line 210, and reduces the molding difficulty.

[0088] In some embodiments, the sub-pixel unit 200 includes a first display area A1, a second display area A2, and a transistor setting area A3 located between the first display area A1 and the second display area A2. The area of ​​the first display area A1 is smaller than the area of ​​the second display area A2, wherein the first via 200a is located within the second display area A2.

[0089] In this embodiment of the application, by placing the first via 200a within the second display area A2, the occupation of the effective display area can be reduced.

[0090] In some embodiments, each sub-pixel unit 200 further includes a second insulating layer 260.

[0091] In this embodiment, the second insulating layer 260 is located between the shared electrode line 210 and the common electrode line 240, which can prevent short circuits between the shared electrode line 210 and the common electrode line 240, thereby improving the display reliability of the display panel 10.

[0092] The first insulating layer 250 and the second insulating layer 260 in the embodiments of this application can be made of silicon nitride or silicon dioxide.

[0093] According to a second aspect of this application, a display device is provided, including a display panel 10 as described above.

[0094] The display device in this application embodiment includes the display panel 10 as described above, and therefore possesses all the beneficial effects of the aforementioned display panel 10, which will not be repeated here. In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0095] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0096] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0097] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The substrate includes a substrate and a plurality of sub-pixel units disposed on the substrate, each of the sub-pixel units comprising: A shared electrode line is disposed on one side of the substrate; A planarization layer is disposed on the side of the shared electrode line away from the substrate, and a first via is formed on the planarization layer; and A pixel electrode is disposed on the side of the planarization layer away from the substrate, and a portion of the pixel electrode is located within the first via. Within the area where the first via is located, the shared electrode line and the pixel electrode overlap.

2. The display panel according to claim 1, characterized in that, The pixel electrode includes a first main electrode, which is arranged parallel to the extension direction of the shared electrode line. The first via and the orthographic projection of the first main electrode on the planar layer overlap.

3. The display panel according to claim 2, characterized in that, The pixel electrode also includes a second main electrode that is intersected with the first main electrode; The first via is located in the intersection area of ​​the first main electrode and the second main electrode.

4. The display panel according to claim 2, characterized in that, The sub-pixel unit further includes: A common electrode line is located between the substrate and the shared electrode line, the common electrode line and the shared electrode line extend in parallel directions and have an overlapping portion; The common electrode line is disconnected in the region corresponding to the first via.

5. The display panel according to claim 4, characterized in that, The orthographic projection of the first via on the substrate does not overlap with the orthographic projection of the common electrode line on the substrate.

6. The display panel according to claim 4, characterized in that, The linewidth of the common electrode line is greater than the linewidth of the first main electrode, and the linewidth of the first main electrode is greater than the linewidth of the shared electrode line.

7. The display panel according to any one of claims 1 to 6, characterized in that, The depth of the first via is less than or equal to the thickness of the planarization layer.

8. The display panel according to any one of claims 1 to 6, characterized in that, Each of the sub-pixel units further includes: A first insulating layer is disposed between the planarization layer and the shared electrode line; The first insulating layer has a second via, which is connected to the first via. The pixel electrode passes through the first via and the second via and is electrically connected to the shared electrode line.

9. The display panel according to any one of claims 1 to 6, characterized in that, The sub-pixel unit includes a first display area, a second display area, and a transistor setting area located between the first display area and the second display area, wherein the area of ​​the first display area is smaller than the area of ​​the second display area; The first via is located within the second display area.

10. A display device, characterized in that, Includes a display panel as described in any one of claims 1 to 9.

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