Integrated plug box and resonance elimination monitoring system

Abstract

The utility model relates to the technical field of harmonic detection, in particular to an integrated plug box and a harmonic elimination monitoring system. The side wall of the accommodating frame is fixedly provided with a connecting assembly; the connecting assembly comprises a voltage and current acquisition port, an input port and an output port. The voltage acquisition loop comprises a clamping protection module and a signal conditioning module and is used for monitoring and inputting real-time voltage; the current acquisition loop comprises a signal conditioning module, a current transformer is connected to one end of the signal conditioning module, and real-time current is monitored and recorded; the input end of the digital-to-analog conversion module is connected to the signal conditioning module, and the output end pin of the digital-to-analog conversion module is connected to the CPU. According to the scheme, allogeneic hanging rail type side wall installation and modular design connection are adopted, the size is reduced by 40%, dense installation is supported, and MTBF is larger than 100,000 hours; the precision is higher, the voltage / current measurement precision reaches 0.5%, the phase error is smaller than or equal to 1 degree, the temperature drift is smaller than 1% of a full scale, long-term monitoring and transient fault capture can be both considered, and accurate analysis after the detection process is finished is supported.

Description

Technical Field

[0001] This utility model relates to the field of harmonic detection technology, and in particular to an integrated junction box and harmonic suppression monitoring system. Background Technology

[0002] In power systems, voltage and current can be decomposed into fundamental and harmonic waves in frequency domain analysis. Fundamental voltage and fundamental current are the basis for the normal operation of power systems, while harmonics are caused by nonlinear loads, transformers, generators and other power components in the circuit. Harmonic voltage and harmonic current will increase the loss of power equipment, causing problems such as overheating, vibration and noise, and will interfere with the communication quality between equipment and undermine the stability of the power system.

[0003] Harmonic suppression online monitoring and analysis devices are important secondary equipment in smart grids. They monitor and analyze harmonic voltages and currents in the power grid online, providing sufficient data support for locating and eliminating harmonic faults. However, traditional devices have large sampling accuracy and measurement errors, resulting in inaccurate harmonic data and difficulty in accurately identifying fault types. Most devices only support short-term waveform recording and storage, affecting fault tracing and analysis. Some devices have poor compatibility, making it difficult to integrate with other smart devices (such as smart waveform recorders), and lack remote access capabilities, resulting in low operation and maintenance efficiency.

[0004] Therefore, there is a need for an integrated plug-in box and harmonic suppression monitoring system that provides a highly reliable harmonic monitoring and fault location solution for smart grids, with high acquisition accuracy, more intelligent storage and analysis, and real-time feedback of harmonic monitoring results to meet the needs of the current environment. Utility Model Content

[0005] The purpose of this section is to outline some aspects of the embodiments of this utility model and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section, as well as in the abstract and title of this application, to avoid obscuring the purpose of this section, the abstract and the title of this utility model. Such simplifications or omissions shall not be used to limit the scope of this utility model.

[0006] Given that some existing devices have poor compatibility, are difficult to integrate with other smart devices (such as smart waveform recorders), have low efficiency, and poor versatility.

[0007] Therefore, the technical problem to be solved by this utility model is to design an integrated plug-in box that is highly compatible, can be effectively integrated and connected with other smart devices, and has high monitoring efficiency to meet the needs of the current environment.

[0008] To solve the above-mentioned technical problems, this utility model provides the following technical solution: an integrated plug-in box, comprising,

[0009] A receiving frame, wherein connecting components are fixedly installed on the sidewalls of the receiving frame;

[0010] The connection components include voltage and current acquisition ports, input ports, and output ports.

[0011] As an improvement to this utility model

[0012] A power plug port is fixedly provided on one side of the opening port;

[0013] One end of the housing frame is equipped with a quick-connect guide rail.

[0014] Given that existing technologies suffer from problems such as large sampling accuracy and measurement errors in traditional devices, inaccurate harmonic data, difficulty in accurately identifying fault types, and the fact that most devices only support short-term waveform recording and storage, which affects fault tracing and analysis.

[0015] To solve the above-mentioned technical problems, this utility model provides the following technical solution: an integrated plug-in box and harmonic suppression monitoring system, comprising,

[0016] The voltage acquisition circuit includes a clamping protection module and a signal conditioning module. The voltage acquisition circuit monitors and records the real-time voltage.

[0017] The current acquisition circuit includes a signal conditioning module, and a current transformer is connected to one end of the signal conditioning module to monitor and record the real-time current.

[0018] The input terminal of the digital-to-analog converter module is connected to the output terminal of the signal conditioning module, and the output pin of the digital-to-analog converter module is connected to the CPU.

[0019] As an improvement to this utility model

[0020] The voltage acquisition circuit is connected to a proportionally matched resistor assembly for positive and negative polarity connection.

[0021] The clamping protection module consists of Zener diodes connected in parallel with the proportional resistor assembly.

[0022] As an improvement to this utility model

[0023] The signal conditioning module input is connected to the clamping protection module;

[0024] The output of the signal conditioning module is connected to the operational amplifier power supply module through a CLCΠ-type filter circuit.

[0025] As an improvement to this utility model

[0026] The signal conditioning module includes an operational amplifier unit;

[0027] The clamping protection module is connected to input ports 5 and 6 of the operational amplifier unit at both ends.

[0028] As an improvement to this utility model

[0029] The No. 5 input port of the operational amplifier unit is connected to a CLCΠ-type filter circuit;

[0030] The No. 7 output of the operational amplifier unit is connected to the DB pin in the digital-to-analog converter module via the output pin.

[0031] As an improvement to this utility model

[0032] The current transformer's No. 3 port is grounded, and No. 1 and No. 2 ports are connected to the circuit under test.

[0033] The current transformer's ports 4 and 6 are connected to the signal conditioning module.

[0034] As an improvement to this utility model

[0035] An independent proportional resistor is additionally set in the signal conditioning module, and filter capacitors are connected in parallel on both sides of the independent proportional resistor;

[0036] A low-pass filter is formed by connecting a filter capacitor and an independently proportional resistor.

[0037] As an improvement to this utility model

[0038] The digital-to-analog conversion module 5 uses pins 9-15 and 24 and 25 to connect to pins E19-G22 in the CPU via the FPGA to achieve data transmission and analysis.

[0039] The beneficial effects of this utility model are as follows: it adopts a non-linear mounting rail sidewall installation and modular design connection, which reduces the volume by 40% and supports dense installation, with an MTBF of >100,000 hours; it has higher accuracy, with voltage / current measurement accuracy of 0.5%, phase error ≤1°, temperature drift <1% of full scale, and can take into account both long-term monitoring and transient fault capture, and supports accurate analysis after the detection process is completed. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Among them:

[0041] Figure 1 This is a diagram illustrating the deployment environment of this utility model.

[0042] Figure 2 This is a schematic diagram of the integrated plug-in box in this utility model.

[0043] Figure 3 This is the voltage acquisition circuit diagram of the harmonic elimination monitoring system in this utility model.

[0044] Figure 4 This is a schematic diagram of the internal circuit of the operational amplifier power supply module in the harmonic suppression monitoring system of this utility model.

[0045] Figure 5 This is the current acquisition circuit diagram of the harmonic elimination monitoring system in this utility model.

[0046] Figure 6 This is a schematic diagram of the internal principle of the analog-to-digital conversion module of the harmonic elimination monitoring system in this utility model.

[0047] Figure 7 This is a partial schematic diagram of the CPU corresponding to the harmonic elimination monitoring system in this utility model.

[0048] Figure 8 This is a schematic diagram of the harmonic elimination monitoring system in this utility model. Detailed Implementation

[0049] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.

[0050] Example 1

[0051] Reference Figures 1-2 This embodiment provides an integrated plug-in box.

[0052] The housing frame 1 can be made of 1.5mm thick galvanized steel sheet, bent into shape, forming a rectangular cavity with dimensions of 180mm×120mm×80mm. The overall structure meets the IP54 protection rating. Strip-shaped heat dissipation holes can be opened on the side wall of the housing frame 1, and aluminum heat dissipation fins can be added to the top of the housing frame 1 to enhance the heat dissipation effect.

[0053] The internal frame of the housing frame 1 can be configured as a two-layer structure, facilitating the layered installation of the CPU main control board and the acquisition board. All components of the connecting assembly 2 are located on the side walls of the housing frame 1, connecting the internal CPU main control board and the acquisition board for data transmission and connection control. The voltage and current acquisition port 21 can use Phoenix terminals and features four voltage acquisition channels and one current acquisition channel. The current acquisition supports the use of a matching 5A / 1A jumper.

[0054] The input port 22 is equipped with 4 optocoupler isolated inputs, with the optional model TLP281-4, supporting DC 24V / 110V configuration. Each optocoupler isolated input can be connected in series with a 1kΩ current-limiting resistor. The output port 23 is equipped with 2 relay outputs, and the relay coil drive circuit includes a freewheeling diode.

[0055] The power connector 231 can be located on one side of the output port 23, and adopts a 3-pole pluggable terminal. The quick-connect rail 11 is set as a 35mm DIN rail clip, which makes it easier for the entire housing frame 1 to be placed in the position to be tested.

[0056] Example 2

[0057] Reference Figures 1-7 This embodiment is based on the previous embodiment, and differs from the previous embodiment in that:

[0058] This technical solution can monitor three-phase voltage, open delta voltage, and primary neutral point current of voltage transformers in real time, and record steady-state and transient voltage and current waveforms. It also enables online monitoring and analysis of line harmonic voltages and currents.

[0059] The operation of voltage acquisition circuit 3 is mainly completed by the clamping protection module 31, signal conditioning module 32, and supporting filter structure and digital-to-analog conversion module 5 working together. The clamping protection module 31 is mainly composed of Zener diodes, which are connected in parallel between the proportional matching resistor assembly 33. This part of the circuit clamps the signal input to the subsequent stage within a certain range to prevent the input voltage from being too large and causing damage to the subsequent stage circuit.

[0060] In the positive and negative terminal access areas of voltage acquisition circuit 3, multiple proportional matching resistors are set to form a proportional matching resistor assembly 33. The resistance accuracy is ±1% and the temperature drift is ±25ppm. In addition, this scheme uses input resistors with larger resistance values ​​as much as possible while ensuring the correct attenuation ratio. This can effectively improve the measurement accuracy, reduce energy loss, and improve signal transmission efficiency.

[0061] The current acquisition circuit 4 also includes a signal conditioning module 32. However, unlike the voltage acquisition scheme, the current acquisition scheme uses a high-precision current transformer 41 in front of the signal conditioning module 32 to convert the current signal in the line into a voltage signal. The ratio difference of the current transformer 41 does not exceed 3 / 1000 and the phase difference does not exceed 15 minutes, which ensures the accuracy of the current signal acquisition. The current acquisition circuit 4 monitors and records the real-time current.

[0062] The digital-to-analog converter module 5 uses the integrated analog-to-digital converter chip AD7606, offering 16-bit resolution, high-precision conversion, and a maximum sampling rate of 200kSPS, suitable for high-speed signal acquisition. It features built-in overvoltage protection circuitry, allowing the input to withstand overvoltages up to ±16.5V, and integrates an anti-aliasing filter and input buffer. The digital-to-analog converter module 5 transmits the converted digital signal to the CPU for analysis via a high-speed serial bus.

[0063] The operational amplifier unit 321 included in the signal conditioning module 32 adopts a current-type negative feedback operational amplifier, which has advantages such as high bandwidth, high speed response, low distortion, wide dynamic range, high stability and flexible design compared with traditional voltage-type negative feedback operational amplifiers. DC negative feedback is introduced into the corresponding installed operational circuit to stabilize the static operating point by stabilizing the DC operating state of the amplifier, thereby stabilizing the AC operating state.

[0064] The input terminal of the signal conditioning module 32 is connected to the clamping protection module 31, and the output terminal of the signal conditioning module 32 is connected to the operational amplifier power supply module 34 through a CLCΠ-type filter circuit. The operational amplifier power supply module 34 mainly includes a CLCΠ-type filter circuit, which can effectively isolate the analog power supply for the operational amplifier from other digital power supplies in the board. Because the operational amplifier unit 321 in this solution has a high power supply voltage rejection ratio, it can suppress high-frequency noise in the circuit and prevent power supply ripple, noise, and other factors from affecting the signal.

[0065] In voltage acquisition circuit 3, the two ends of clamp protection module 31 are connected to input ports 5 and 6 of operational amplifier unit 321, respectively. Input port 5 of operational amplifier unit 321 is connected to CLCΠ type filter circuit, and output terminal 7 is connected to DB pin in digital-to-analog converter module 5 through output pin. Output terminal 7 finally realizes data amplification and transmission to CPU for monitoring and analysis.

[0066] Port 3 of the current transformer 41 is grounded, and ports 1 and 2 are connected to the circuit under test. Ports 4 and 6 of the current transformer 41 are connected to the signal conditioning module 32 for corresponding signal conversion. The signal conditioning module 32 includes an independent proportional resistor 322, which is connected in parallel with a filter capacitor 35. Through this parallel connection, the filter capacitor 35 forms a low-pass filter with the independent proportional resistor 322, reducing the gain of high-frequency signals in the signal circuit while retaining effective low-frequency signals.

[0067] The digital-to-analog converter module 5 has different functional areas. It provides analog input functionality for pins V1 to V8 and their corresponding GND pins. Pins 6, 7, 8, 23, 34, and 42 are used for configuration. When REF SELECT is high, the AD7606 uses an internal reference source; otherwise, it uses an external reference source. When PAR / SER / BYTE_SEL is low, the AD7606 uses a 16-bit parallel interface for communication. If PAR / SER / BUTE_SEL is high, it uses the SPI serial interface for data transmission. If both PAR / SER / BUTE_SEL and DB15 / BYTE_SEL are high, it uses a byte-parallel interface. When the STBY pin is high, the AD7606 operates in normal mode; when STBY is low, the AD7606 operates in power-saving mode.

[0068] The digital-to-analog converter module 5 uses pins 1, 37, 38, 48, 36, 39, 44, and 45 for power input. The module connects to pins E19 to G22 within the CPU via pins 9-15 and 24 and 25 through the FPGA for data transmission and analysis.

[0069] Example 3

[0070] Reference Figures 1-8 This embodiment is based on the previous embodiment, and differs from the previous embodiment in that:

[0071] The CPU analyzes and processes the collected data, and in real time transfers the monitoring data received from the FPGA into a COMTEADE waveform file. Based on the calculation results, it judges and analyzes disturbances. As the control core of the entire device, the CPU can be externally expanded with debugging serial ports and communication network ports. It can also be internally connected with SPI-Flash, DDR cache, RTC real-time chip, temperature monitoring chip, voltage monitoring chip and SATA storage to expand additional functions and achieve more comprehensive functional coverage.

[0072] The CPLD strictly controls the power-on and operating sequence of the entire system to ensure its stability and reliability. The FPGA, acting as a high-speed data acquisition controller, adds an absolute timestamp to each frame of data and converts it into the required monitoring data message format. Simultaneously, it performs real-time calculations based on start-up criteria. Once the criteria are met, it enters data recording mode and saves the data at a high sampling rate. This solution employs a ZYNQ+FPGA high-speed storage scheme, with internal data exchange via a high-speed AXI bus.

[0073] In terms of software, this solution allows reading and writing SATA hard drives through a file system interface. In terms of hardware, it uses an FPGA to acquire 5 analog signals in real time, with a steady-state sampling rate of 1K (transient sampling rate of 4K) and a data bit width of 16bit. The data acquired by the FPGA in real time is cached in the DDR cache queue on the PS side via the AXI bus, and then the PS operation writes the data in the cache queue to the SATA hard drive.

[0074] When waveform disturbances trigger transient recording, the sampling rate is increased (4kHz). Data recording uses an AB segment method, where segment A contains data before the start of a large waveform disturbance, and segment B contains data in the initial stage after the large system disturbance. Both time segments are configurable, and all recorded data can be exported for analysis, facilitating the analysis and handling of harmonic faults in power systems. This invention also supports the IEC61850 communication protocol, constructs a device CID model, and transmits data including ledger data, remote signaling data, and telemetry data. It can be used as a harmonic acquisition unit to send data to intelligent waveform recorders and other systems, enabling centralized management of monitoring data.

[0075] The above description describes some of the functions of this utility model. In field implementation, this harmonic elimination online monitoring and analysis device can be configured according to the needs of the substation to realize the monitoring of harmonic current and harmonic voltage in the substation, thereby improving the power quality and operational safety of the power system.

[0076] It should be noted that the above embodiments are only used to illustrate the technical solution of this utility model and are not intended to limit it. Although this utility model has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solution of this utility model without departing from the spirit and scope of the technical solution of this utility model, and all such modifications or substitutions should be covered within the scope of the claims of this utility model.

Claims

1. An integrated plug-in box, characterized in that: include, A receiving frame (1) is provided, and a connecting assembly (2) is fixedly installed on the side wall of the receiving frame (1); The connection component (2) includes a voltage and current acquisition port (21), an input port (22), and an output port (23).

2. The integrated plug-in box according to claim 1, characterized in that: A power plug-in port (231) is fixedly provided on one side of the opening port (23); One end of the housing frame (1) is provided with a quick-connect guide rail (11).

3. A harmonic suppression monitoring system, characterized in that: Including the integrated plug-in box as described in claim 2, and, The voltage acquisition circuit (3) includes a clamping protection module (31) and a signal conditioning module (32). The voltage acquisition circuit (3) monitors and records the real-time voltage. The current acquisition circuit (4) includes a signal conditioning module (32), and a current transformer (41) is connected to one end of the signal conditioning module (32) to monitor and record the real-time current. The input terminal of the digital-to-analog converter module (5) is connected to the output terminal of the signal conditioning module (32), and the output pin of the digital-to-analog converter module (5) is connected to the CPU through the FPGA.

4. The harmonic suppression monitoring system according to claim 3, characterized in that: Voltage acquisition circuit (3) positive and negative terminals are connected to set proportional resistor assembly (33); The clamping protection module (31) is composed of Zener diodes and is connected in parallel between the proportional matching resistor assembly (33).

5. The harmonic suppression monitoring system according to claim 3, characterized in that: The input terminal of the signal conditioning module (32) is connected to the clamping protection module (31); The output of the signal conditioning module (32) is connected to the operational amplifier power supply module (34) through a CLCΠ-type filter circuit.

6. The harmonic suppression monitoring system according to claim 3 or 4, characterized in that: The signal conditioning module (32) includes an operational amplifier unit (321); The clamping protection module (31) is connected to input ports 5 and 6 of the operational amplifier unit (321) at both ends.

7. The harmonic suppression monitoring system according to claim 6, characterized in that: Input port 5 of the operational amplifier unit (321) is connected to a CLCΠ-type filter circuit; The No. 7 output terminal of the operational amplifier unit (321) is connected to the DB pin inside the digital-to-analog converter module (5) through the output pin.

8. The harmonic suppression monitoring system according to claim 7, characterized in that: The 3rd port of the current transformer (41) is grounded, and the 1st and 2nd ports are connected to the circuit under test; The current transformer (41) has its ports 4 and 6 connected to the signal conditioning module (32).

9. The harmonic suppression monitoring system according to claim 8, characterized in that: An independent proportional resistor (322) is additionally provided in the signal conditioning module (32), and a filter capacitor (35) is connected in parallel on both sides of the independent proportional resistor (322); The filter capacitor (35) and the independently proportional resistor (322) are connected to form a low-pass filter.

10. The harmonic suppression monitoring system according to claim 9, characterized in that: The digital-to-analog conversion module (5) uses pins 9-15 and 24 and 25 to connect to pins E19-G22 in the CPU via the FPGA to achieve data transmission and analysis.

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