Data acquisition network transmission system based on FPGA detector

Abstract

The utility model discloses a data acquisition network transmission system based on an FPGA (Field Programmable Gate Array) detector, which comprises a signal receiving and preprocessing module, a signal routing and switching module, a signal conditioning and amplifying module, an analog-to-digital conversion module, a core processing and control module, a data transmission module and a PC (Personal Computer) control and display module, the signal receiving and preprocessing module, the signal routing and switching module, the signal conditioning and amplifying module and the analog-to-digital conversion module are electrically connected in sequence, and the core processing and control module, the data transmission module and the PC control and display module are electrically connected in sequence. And the signal routing and switching module and the analog-to-digital conversion module are electrically connected with the core processing and control module respectively. According to the utility model, the core processing and control module is used as a data processing core, so that high-speed data acquisition is realized, the real-time requirement is met, the processing capability is improved, the complex signal processing requirement is met, the flexible configuration of the system structure is realized, and the system is suitable for different application scenes.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit technology, and in particular to a data acquisition network transmission system based on an FPGA detector. Background Technology

[0002] A data acquisition network transmission system is a network system used to collect data. Due to the limitations of the acquisition environment, in most fields it is necessary to transmit the collected data through the data acquisition network transmission system to the main control center for display and control, and then monitor the changes in the measured environment through the data acquisition network transmission system.

[0003] Existing data acquisition network transmission systems typically consist of multiple independent hardware modules that use CPUs or DSPs for data processing. Their processing speed is limited and cannot meet the needs of high-speed data acquisition. As for digital signal processing methods, such as Fast Fourier Transform (FFT), the computational load is huge when processing complex signals, and the processing capacity is insufficient, failing to meet the requirements of real-time performance and accuracy. Furthermore, their multiple independent component structures are fixed and difficult to adjust according to actual needs, making it difficult to meet the needs of different application scenarios and resulting in high costs.

[0004] Therefore, there is an urgent need for a data acquisition network transmission system based on FPGA detectors, which can utilize the high-speed parallel processing capabilities, customized digital signal processing algorithms, programmability, and integrability of FPGAs. Utility Model Content

[0005] In view of the above problems, this utility model is proposed to provide a data acquisition network transmission system based on an FPGA detector that overcomes or at least partially solves the above problems.

[0006] This utility model provides a data acquisition network transmission system based on an FPGA detector. The data acquisition network transmission system based on an FPGA detector includes: a signal receiving and preprocessing module, a signal routing and switching module, a signal conditioning and amplification module, an analog-to-digital conversion module, a core processing and control module, a data transmission module, and a PC control and display module. The signal receiving and preprocessing module, the signal routing and switching module, the signal conditioning and amplification module, and the analog-to-digital conversion module are electrically connected in sequence. The core processing and control module, the data transmission module, and the PC control and display module are electrically connected in sequence. The signal routing and switching module and the analog-to-digital conversion module are respectively electrically connected to the core processing and control module.

[0007] Optionally, the signal receiving and preprocessing module includes an antenna, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C99, a first inductor L1, and a second inductor L2; one end of the antenna and one end of the first capacitor C1 are respectively connected to one end of the first inductor L1, the other end of the first inductor L1 and one end of the second capacitor C2 are respectively connected to one end of the second inductor L2, the other end of the second inductor L2 and one end of the third capacitor C3 are respectively connected to one end of the fourth capacitor C99, the other end of the fourth capacitor C99 is connected to the signal routing and switching module, and the other ends of the antenna, the first capacitor C1, the second capacitor C2, and the third capacitor C3 are grounded.

[0008] Optionally, the signal routing and switching module includes a multiplexing chip U25, a fifth capacitor C101, a first resistor R108, a second resistor R111, and a third resistor R112; the multiplexing chip U25 is a 74CBTLV3253 and includes 16 pins; wherein, one end of the first resistor R108 and pin 7 of the multiplexing chip U25 are respectively connected to the fourth capacitor C99 of the signal receiving and preprocessing module; the other end of the first resistor R108, one end of the fifth capacitor C101, and one end of the second resistor R111 are... One end of the third resistor R112 is connected to ground, the other end of the fifth capacitor C101 and the other end of the second resistor R111 are grounded; pin 16 of the multiplexing chip U25 and the other end of the third resistor R112 are respectively connected to the 3.3V power supply; pins 2 and 14 of the multiplexing chip U25 are respectively connected to the core processing and control module; pins 3, 4, 5 and 6 of the multiplexing chip U25 are respectively connected to the signal conditioning and amplification module; pins 1, 8 and 15 of the multiplexing chip U25 are grounded.

[0009] Optionally, the signal conditioning and amplification module includes two parallel amplification units, a first amplification unit and a second amplification unit.

[0010] Optionally, the first amplification unit includes a first operational amplifier U1A, a sixth capacitor C4, a seventh capacitor C95, a fourth resistor R102, a fifth resistor R103, and a sixth resistor R107; the product model of the first operational amplifier U1A is MCP6022; one end of the sixth capacitor C4 is connected to pin 5 of the multiplexing chip U25, and the other end of the sixth capacitor C4 is connected to one end of the fourth resistor R102; the other end of the fourth resistor R102, one end of the seventh capacitor C95, and one end of the sixth resistor R107 are respectively connected to... Pins 6 and 7 of the first operational amplifier U1A are respectively connected to the other end of the seventh capacitor C95, the other end of the sixth resistor R107, the analog-to-digital conversion module, and the core processing and control module; one end of the fifth resistor R103 is connected to pin 3 of the multiplexing chip U25, the other end of the fifth resistor R103 is connected to pin 5 of the first operational amplifier U1A, pin 8 of the first operational amplifier U1A is connected to the VCC power supply terminal, and pin 4 of the first operational amplifier U1A is grounded.

[0011] Optionally, the second amplification unit includes a second operational amplifier U2B, an eighth capacitor C5, a ninth capacitor C94, a seventh resistor R104, an eighth resistor R105, and a ninth resistor R106; the product model of the second operational amplifier U2B is MCP6022; one end of the eighth capacitor C5 is connected to pin 6 of the multiplexing chip U25, and the other end of the eighth capacitor C5 is connected to one end of the seventh resistor R104; the other end of the seventh resistor R104, one end of the ninth capacitor C94, and one end of the ninth resistor R106 are respectively connected to... Pin 2 and pin 1 of the second operational amplifier U2B are respectively connected to the other end of the ninth capacitor C94, the other end of the ninth resistor R106, the analog-to-digital conversion module, and the core processing and control module; one end of the eighth resistor R105 is connected to pin 4 of the multiplexing chip U25, the other end of the eighth resistor R105 is connected to pin 3 of the second operational amplifier U2B, pin 8 of the second operational amplifier U2B is connected to the VCC power supply terminal, and pin 4 of the second operational amplifier U2B is grounded.

[0012] Optionally, the analog-to-digital conversion module includes an analog-to-digital conversion chip U24, the product model of which is PCM1808, which includes 14 sets of pins. Among them, pin 14 of the analog-to-digital conversion chip U24 is connected to pin 7 of the multiplexing chip U1A, pin 13 of the analog-to-digital conversion chip U24 is connected to pin 1 of the multiplexing chip U2B, pin 3 of the analog-to-digital conversion chip U24 is connected to a 5V power supply terminal, pin 4 of the analog-to-digital conversion chip U24 is connected to a 3.3V power supply terminal, pins 6, 7, 8, 9, 10 and 11 of the analog-to-digital conversion chip U24 are connected to the core processing and control module, and pins 1, 2, 5 and 12 of the analog-to-digital conversion chip U24 are grounded.

[0013] Optionally, the core processing and control module is an FPGA with product model Lattice LFE3-70EA. The FPGA's GPIO1 pin is connected to pin 2 of the multiplexing chip U25, the FPGA's GPIO2 pin is connected to pin 14 of the multiplexing chip U25, the FPGA's GPIO3 pin is connected to pin 6 of the analog-to-digital converter chip U24, the FPGA's GPIO4 pin is connected to pin 7 of the analog-to-digital converter chip U24, the FPGA's GPIO5 pin is connected to pin 8 of the analog-to-digital converter chip U24, the FPGA's GPIO7 pin is connected to pin 9 of the analog-to-digital converter chip U24, the FPGA's GPIO6 pin is connected to pin 10 of the analog-to-digital converter chip U24, the FPGA's GPIO8 pin is connected to pin 11 of the analog-to-digital converter chip U24, the FPGA's GPIO9 pin is connected to pin 7 of the first operational amplifier U1A, and the FPGA's GPIO10 pin is connected to pin 1 of the first operational amplifier U2B.

[0014] Optionally, the data transmission module is a Gigabit Ethernet chip with product model number 88E1119R.

[0015] Optionally, the signal receiving and preprocessing module, signal routing and switching module, signal conditioning and amplification module, analog-to-digital conversion module, core processing and control module, and data transmission module are integrated into one unit.

[0016] The technical solution provided in this embodiment of the utility model has at least the following technical effects or advantages:

[0017] The data acquisition network transmission system based on an FPGA detector described in this embodiment utilizes a core processing and control module as the data processing core. Based on the high-speed parallel processing capability of the FPGA, it achieves high-speed data acquisition to meet real-time requirements. Customized digital signal processing algorithms are implemented through the FPGA, improving processing capabilities and meeting complex signal processing needs. The programmable nature of the FPGA enables flexible configuration of the system structure to adapt to different application scenarios. At the same time, by integrating multiple functional modules into the FPGA chip, the system structure is simplified.

[0018] The above description is merely an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this utility model more obvious and understandable, specific embodiments of this utility model are given below. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the data acquisition network transmission system based on the FPGA detector described in this utility model;

[0021] Figure 2 The diagram shows a reference circuit diagram of the signal receiving and preprocessing module.

[0022] Figure 3 The diagram shown is a reference circuit diagram of the signal routing and switching module;

[0023] Figure 4 The diagram shown is a reference circuit diagram of the first amplification unit;

[0024] Figure 5 The diagram shown is a reference circuit diagram of the second amplification unit;

[0025] Figure 6 The diagram shown is a circuit reference diagram of the analog-to-digital converter module.

[0026] Explanation of reference numerals in the attached figures:

[0027] 1. Signal receiving and preprocessing module; 2. Signal routing and switching module; 3. Signal conditioning and amplification module; 4. Analog-to-digital conversion module; 5. Core processing and control module; 6. Data transmission module; 7. PC control and display module. Detailed Implementation

[0028] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings.

[0029] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. The accompanying drawings show preferred embodiments of the present invention. The present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present invention more thorough and complete.

[0030] Unless otherwise specified, all raw materials, instruments and equipment used in this invention can be purchased from the market or prepared by existing methods.

[0031] Figure 1 This is a schematic diagram of a data acquisition network transmission system based on an FPGA detector provided in an embodiment of this utility model. (See attached diagram.) Figure 1 As shown, the data acquisition network transmission system based on the FPGA detector includes a signal receiving and preprocessing module, a signal routing and switching module, a signal conditioning and amplification module, an analog-to-digital conversion module, a core processing and control module, a data transmission module, and a PC control and display module. The signal receiving and preprocessing module, the signal routing and switching module, the signal conditioning and amplification module, and the analog-to-digital conversion module are electrically connected in sequence. The core processing and control module, the data transmission module, and the PC control and display module are electrically connected in sequence. The signal routing and switching module and the analog-to-digital conversion module are electrically connected to the core processing and control module.

[0032] In this embodiment of the invention, the signal receiving and preprocessing module, the signal routing and switching module, the signal conditioning and amplification module, the analog-to-digital conversion module, the core processing and control module, and the data transmission module can be integrated into one unit.

[0033] Combination Figure 2The diagram shows a reference circuit diagram of a signal receiving and preprocessing module. This module includes an antenna, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C99, a first inductor L1, and a second inductor L2. One end of the antenna and one end of the first capacitor C1 are connected to one end of the first inductor L1. The other end of the first inductor L1 and one end of the second capacitor C2 are connected to one end of the second inductor L2. The other end of the second inductor L2 and one end of the third capacitor C3 are connected to one end of the fourth capacitor C99. The other end of the fourth capacitor C99 is connected to the signal routing and switching module. The other ends of the antenna, the first capacitor C1, the second capacitor C2, and the third capacitor C3 are grounded. The high-frequency signal (such as a 30MHz radio frequency signal) received by the antenna is first fed into an LCπ filter. LCπ filters are typically used in the output section of a DC power supply to smooth the rectified voltage. The LCπ filter contains two capacitors and one inductor, namely a first capacitor C1, a second capacitor C2, and a first inductor L1. The inductor is located between the two capacitors and can effectively filter out ripple voltage in the power supply and improve the quality of the output voltage. The inductor helps to prevent high-frequency components from passing through. The first capacitor C1 and the second capacitor C2 filter out high-frequency noise on the input and output sides, respectively. The filtered signal enters pin 7 of the 74CBTLV3253 chip of the signal routing and switching module.

[0034] Combination Figure 3The diagram shows a reference circuit diagram of the signal routing and switching module. The module includes a multiplexing chip U25, a fifth capacitor C101, a first resistor R108, a second resistor R111, and a third resistor R112. The multiplexing chip U25, model number 74CBTLV3253, has 16 pins and provides dual-channel 1-of-4 high-speed multiplexing / demultiplexing functionality, supports bidirectional signal transmission, and features low on-resistance (5Ω) and rail-to-rail switching capability. One end of the first resistor R108 and pin 7 of the multiplexing chip U25 are connected to the fourth capacitor C99 of the signal receiving and preprocessing module. The other end of the first resistor R108, one end of the fifth capacitor C101, and one end of the second resistor R111 are connected to... One end of the third resistor R112, the other end of the fifth capacitor C101, and the other end of the second resistor R111 are grounded; pin 16 of the multiplexing chip U25 and the other end of the third resistor R112 are respectively connected to a 3.3V power supply; pins 2 and 14 of the multiplexing chip U25 are respectively connected to the core processing and control module; pins 3, 4, 5, and 6 of the multiplexing chip U25 are respectively connected to the signal conditioning and amplification module; pins 1, 8, and 15 of the multiplexing chip U25 are grounded; the multiplexing chip U25 transmits the IQ signals input from the signal receiving and preprocessing module in parallel to the signal conditioning and amplification module, and dynamically switches the signal transmission channels according to the control signals of the core processing and control module.

[0035] The signal conditioning and amplification module includes two parallel amplification units: a first amplification unit and a second amplification unit.

[0036] Combination Figure 4The diagram shows a reference circuit diagram of the first amplification unit. The first amplification unit includes a first operational amplifier U1A, a sixth capacitor C4, a seventh capacitor C95, a fourth resistor R102, a fifth resistor R103, and a sixth resistor R107. The product model of the first operational amplifier U1A is MCP6022. One end of the sixth capacitor C4 is connected to pin 5 of the multiplexing chip U25, and the other end of the sixth capacitor C4 is connected to one end of the fourth resistor R102. The other end of the fourth resistor R102, one end of the seventh capacitor C95, and the sixth resistor R107 are connected together. One end of pin 7 is connected to pin 6 of the first operational amplifier U1A. Pin 7 of the first operational amplifier U1A is connected to the other end of the seventh capacitor C95, the other end of the sixth resistor R107, the analog-to-digital conversion module, and the core processing and control module. One end of the fifth resistor R103 is connected to pin 3 of the multiplexing chip U25. The other end of the fifth resistor R103 is connected to pin 5 of the first operational amplifier U1A. Pin 8 of the first operational amplifier U1A is connected to the VCC power supply terminal. Pin 4 of the first operational amplifier U1A is grounded.

[0037] Combination Figure 5 The diagram shows a reference circuit diagram of the second amplification unit. The second amplification unit includes a second operational amplifier U2B, an eighth capacitor C5, a ninth capacitor C94, a seventh resistor R104, an eighth resistor R105, and a ninth resistor R106. The product model of the second operational amplifier U2B is MCP6022. One end of the eighth capacitor C5 is connected to pin 6 of the multiplexing chip U25, and the other end of the eighth capacitor C5 is connected to one end of the seventh resistor R104. The other end of the seventh resistor R104, one end of the ninth capacitor C94, and the ninth resistor R106 are connected to each other. One end of 6 is connected to pin 2 of the second operational amplifier U2B, and pin 1 of the second operational amplifier U2B is connected to the other end of the ninth capacitor C94, the other end of the ninth resistor R106, the analog-to-digital conversion module, and the core processing and control module. One end of the eighth resistor R105 is connected to pin 4 of the multiplexing chip U25, and the other end of the eighth resistor R105 is connected to pin 3 of the second operational amplifier U2B. Pin 8 of the second operational amplifier U2B is connected to the VCC power supply terminal, and pin 4 of the second operational amplifier U2B is grounded.

[0038] In this embodiment of the invention, the first operational amplifier U1A and the second operational amplifier U2B are configured in differential mode (VIN-connected to 1B4 = GND), with a gain set to 20 times (RF = 19kΩ, RG = 1kΩ), amplifying the 0.2V RF signal to 4V (under 5V power supply). A 100nF ceramic capacitor and a 10μF electrolytic capacitor are connected in parallel on the VDD pin to filter out high-frequency and low-frequency power supply noise. A 50Ω resistor is connected in series on the input pin to match the antenna impedance (50Ω) and reduce reflection. The amplified 4V signal is connected to the differential input terminal of the PCM1808 ADC of the analog-to-digital converter module, and then transmitted through I... 2 The data is transmitted via the C(SCL and SDA) interface to the core processing and control module (FPGA) for digital demodulation.

[0039] Under the signal control of the signal routing and switching module, the signal conditioning and amplification module routes the RF (radio frequency) signal of the antenna signal to the first amplification unit or the second amplification unit, and after amplification by the first amplification unit and the second amplification unit, routes it to the analog-to-digital conversion module.

[0040] Combination Figure 6 The diagram shown is a circuit reference schematic of an analog-to-digital conversion module. The module includes an analog-to-digital conversion chip U24, model number PCM1808, which has 14 pins. Pin 14 of the U24 is connected to pin 7 of the multiplexing chip U1A, pin 13 is connected to pin 1 of the multiplexing chip U2B, pin 3 is connected to a 5V power supply, pin 4 is connected to a 3.3V power supply, pins 6, 7, 8, 9, 10, and 11 are connected to the core processing and control module, and pins 1, 2, 5, and 12 are grounded.

[0041] The analog-to-digital converter chip U24 synchronizes its internal operations via a master clock signal (MCLK) (e.g., input via computer code). This master clock signal can be provided by the core processing and control module or an external clock source, which needs to be connected to the core processing and control module for synchronization control. Simultaneously, the analog-to-digital converter chip U24 also has a bit clock (BCK) and a frame synchronization signal (LRCK), which also need to be connected to the core processing and control module. The core processing and control module uses these signals to accurately read the data output by the analog-to-digital converter chip U24.

[0042] The core processing and control module is an FPGA (Field-Programmable Gate Array) with product model Lattice LFE3-70EA. This FPGA generates orthogonal oscillation signals using DDS technology to achieve a frequency resolution of ±80kHz, decodes IQ signals, and executes algorithms such as filtering, noise reduction, and oversampling (10x). It also configures multiplexer channels, ADC parameters, Ethernet transmission strategies, and implements data buffering via the AXI bus and DDR3 controller. Specifically, pin GPIO1 of the FPGA is connected to pin 2 of the multiplexing chip U25, pin GPIO2 of the FPGA is connected to pin 14 of the multiplexing chip U25, and pin GPIO3 of the FPGA is connected to the analog-to-digital converter chip U25. Pin 6 of 4, pin GPIO4 of the FPGA is connected to pin 7 of the analog-to-digital converter chip U24, pin GPIO5 of the FPGA is connected to pin 8 of the analog-to-digital converter chip U24, pin GPIO7 of the FPGA is connected to pin 9 of the analog-to-digital converter chip U24, pin GPIO6 of the FPGA is connected to pin 10 of the analog-to-digital converter chip U24, pin GPIO8 of the FPGA is connected to pin 11 of the analog-to-digital converter chip U24, pin GPIO9 of the FPGA is connected to pin 7 of the first operational amplifier U1A, and pin GPIO10 of the FPGA is connected to pin 1 of the first operational amplifier U2B.

[0043] In this embodiment of the utility model, the FPGA serves as the core control unit, responsible for configuring the status of specific peripheral interfaces. The analog-to-digital converter chip U24 outputs data from its pins 13 and 14, which is then transmitted to the FPGA's pins GPIO9 and GPIO10 after analog-to-digital conversion.

[0044] The analysis data code for the FPGA is shown below for reference:

[0045]

[0046]

[0047]

[0048] After the data transmission physical layer protocol IP core converts the data to 8b / 10b code, it transmits the eight-channel data to the data transmission protocol IP core for parsing. The AXI_stream data stream is then transmitted to the analog-to-digital conversion module. The processed raw data is converted into bus data by the FDMA controller and then sent to the DDR3 memory for storage by the DDR3 controller. When the PC control and display module requests to read data, it reads the data from the DDR3 memory (the aforementioned FDMA controller, DDR3 controller, and DDR3 memory are not shown).

[0049] The FPGA initializes and configures the analog-to-digital converter chip U24. Before data acquisition begins, the FPGA needs to perform I / O operations. 2 The C interface (not shown in the figure) is used to initialize and configure the analog-to-digital converter chip U24. The specific steps are as follows:

[0050] Reset operation: The FPGA sends a reset signal to the RESET pin of the analog-to-digital converter chip U24 to reset the chip to its initial state.

[0051] I 2 C communication: FPGA communicates via I 2 The C bus communicates with the analog-to-digital converter chip U24 and writes configuration parameters into its internal registers.

[0052] Common configuration parameters include: sampling rate: different sampling rates can be set; gain setting: adjust the gain of the input signal.

[0053] The FPGA provides the master clock (MCLK) to the analog-to-digital converter chip U24, ensuring the proper operation of the PCM1808. The analog-to-digital converter chip U24 generates a bit clock (BCK) and a frame synchronization signal (LRCK) based on the master clock, and these signals are also fed back to the FPGA. The FPGA uses these signals to synchronize the data reception process, ensuring accurate reading of data at each sampling point.

[0054] The analog-to-digital converter (ADC) chip U24 receives analog signal input via its analog input pins (VINL and VINR, corresponding to the left and right channels, respectively). The ADC chip U24 samples and quantizes the input analog audio signal, converting it into a digital signal. The conversion process is based on the sampling rate and other parameters configured by the FPGA. The ADC chip U24 then sends the converted digital audio data to the FPGA via its data output pin (DOUT). The data is transmitted according to the timing of the bit clock (BCK) and frame synchronization signal (LRCK), and the FPGA accurately receives and parses the data based on the timing of these signals.

[0055] After receiving the digital signal output from the analog-to-digital converter chip U24, the FPGA stores it in its internal registers or memory. The FPGA can perform various processing operations on the received data, such as filtering, noise reduction, and audio encoding. The specific processing method depends on the application requirements. The processed data can then be further transmitted to other devices, such as being sent to a PC control and display module for storage and analysis via an Ethernet interface, or being output to a speaker for playback via an audio interface.

[0056] The FPGA's driver code for the analog-to-digital conversion module is shown below for reference:

[0057]

[0058]

[0059]

[0060] In this embodiment of the utility model, the data transmission module is a gigabit Ethernet chip with product model number 88E1119R, which can support the GMII / MII interface (through which it can be connected to the MAC / Switch port of the FPGA) to realize gigabit data transmission. It is used to encapsulate the data processed by the FPGA into Ethernet frames and transmit them to the PC control and display module.

[0061] In this embodiment of the invention, the PC control and display module is used for network communication with the FPGA, receiving data sent by the FPGA for real-time image display and data acquisition and storage.

[0062] Compared with the prior art, the data acquisition network transmission system based on FPGA detector described in this embodiment of the invention has the following advantages:

[0063] 1. Utilizing the core processing and control module as the data processing core, and leveraging the high-speed parallel processing capabilities of FPGA, high-speed data acquisition is achieved to meet real-time requirements. Customized digital signal processing algorithms are implemented through FPGA, enhancing processing capabilities and meeting complex signal processing needs. Furthermore, the programmable nature of FPGA enables flexible configuration of the system structure to adapt to different application scenarios. At the same time, the system structure is simplified by integrating multiple functional modules.

[0064] 2. In the signal receiving and preprocessing module, the saturation problem of the high-frequency operational amplifier was solved by adding two coupling capacitors. The capacitors filter out the DC component in the input signal, thus ensuring that the operational amplifier only processes AC signals and avoiding saturation caused by DC offset. This improvement not only eliminated the saturation problem but also improved the overall performance of the system.

[0065] 3. Due to the improved frequency accuracy and oversampling capability, the MCP6022 can be used as the amplification unit, which has the advantage of low cost while ensuring that the overall performance meets the requirements.

[0066] 4. The I (same direction) and Q (quadrature) signals generated by the two amplification units of the signal conditioning and amplification module contain the information required for complete demodulation. By analyzing the I and Q signals, the amplitude, phase, and frequency characteristics of the signal can be obtained, and the high-low relationship between the signal frequency and the local oscillator frequency can be determined. By increasing the oversampling rate of the I and Q signals to ten times the original, the ability to suppress aliasing signals is improved. In the signal receiving and preprocessing module, the frequency is fine-tuned through software control using an ultra-high resolution NCO and mixer. This allows for precise frequency control through software means even under hardware limitations, ensuring the receiver's superior performance throughout the entire operating bandwidth.

[0067] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0068] Similarly, it should be understood that, in order to simplify this disclosure and aid in understanding one or more of the various aspects of the invention, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this method of disclosure should not be construed as reflecting an intention that the claimed invention requires more features than expressly recited in each claim. Rather, as reflected in the claims, the inventive aspect lies in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the invention.

[0069] It should be noted that the above embodiments are illustrative of the present invention and not restrictive of the present invention, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims.

Claims

1. A data acquisition network transmission system based on an FPGA detector, characterized in that, The data acquisition network transmission system based on the FPGA detector includes: a signal receiving and preprocessing module, a signal routing and switching module, a signal conditioning and amplification module, an analog-to-digital conversion module, a core processing and control module, a data transmission module, and a PC control and display module. The signal receiving and preprocessing module, the signal routing and switching module, the signal conditioning and amplification module, and the analog-to-digital conversion module are electrically connected in sequence. The core processing and control module, the data transmission module, and the PC control and display module are electrically connected in sequence. The signal routing and switching module and the analog-to-digital conversion module are electrically connected to the core processing and control module.

2. The data acquisition network transmission system based on an FPGA detector according to claim 1, characterized in that: The signal receiving and preprocessing module includes an antenna, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C99, a first inductor L1, and a second inductor L2. One end of the antenna and one end of the first capacitor C1 are respectively connected to one end of the first inductor L1. The other end of the first inductor L1 and one end of the second capacitor C2 are respectively connected to one end of the second inductor L2. The other end of the second inductor L2 and one end of the third capacitor C3 are respectively connected to one end of the fourth capacitor C99. The other end of the fourth capacitor C99 is connected to the signal routing and switching module. The other ends of the antenna, the first capacitor C1, the second capacitor C2, and the third capacitor C3 are grounded.

3. The data acquisition network transmission system based on an FPGA detector according to claim 1, characterized in that: The signal routing and switching module includes a multiplexing chip U25, a fifth capacitor C101, a first resistor R108, a second resistor R111, and a third resistor R112. The multiplexing chip U25 is a 74CBTLV3253 and includes 16 pins. One end of the first resistor R108 and pin 7 of the multiplexing chip U25 are connected to the fourth capacitor C99 of the signal receiving and preprocessing module. The other end of the first resistor R108, one end of the fifth capacitor C101, and one end of the second resistor R111 are connected to... One end of the third resistor R112, the other end of the fifth capacitor C101, and the other end of the second resistor R111 are grounded; pin 16 of the multiplexing chip U25 and the other end of the third resistor R112 are respectively connected to the 3.3V power supply; pins 2 and 14 of the multiplexing chip U25 are respectively connected to the core processing and control module; pins 3, 4, 5, and 6 of the multiplexing chip U25 are respectively connected to the signal conditioning and amplification module; pins 1, 8, and 15 of the multiplexing chip U25 are grounded.

4. The data acquisition network transmission system based on an FPGA detector according to claim 3, characterized in that: The signal conditioning and amplification module includes two parallel amplification units: a first amplification unit and a second amplification unit.

5. The data acquisition network transmission system based on an FPGA detector according to claim 4, characterized in that: The first amplification unit includes a first operational amplifier U1A, a sixth capacitor C4, a seventh capacitor C95, a fourth resistor R102, a fifth resistor R103, and a sixth resistor R107; the product model of the first operational amplifier U1A is MCP6022; one end of the sixth capacitor C4 is connected to pin 5 of the multiplexing chip U25, and the other end of the sixth capacitor C4 is connected to one end of the fourth resistor R102; the other end of the fourth resistor R102, one end of the seventh capacitor C95, and one end of the sixth resistor R107 are respectively connected to pin 6 of the first operational amplifier U1A; pin 7 of the first operational amplifier U1A is respectively connected to the other end of the seventh capacitor C95, the other end of the sixth resistor R107, the analog-to-digital conversion module, and the core processing and control module; one end of the fifth resistor R103 is connected to pin 3 of the multiplexing chip U25, and the other end of the fifth resistor R103 is connected to pin 5 of the first operational amplifier U1A; pin 8 of the first operational amplifier U1A is connected to the VCC power supply terminal, and pin 4 of the first operational amplifier U1A is grounded.

6. The data acquisition network transmission system based on an FPGA detector according to claim 5, characterized in that: The second amplification unit includes a second operational amplifier U2B, an eighth capacitor C5, a ninth capacitor C94, a seventh resistor R104, an eighth resistor R105, and a ninth resistor R106; the product model of the second operational amplifier U2B is MCP6022; one end of the eighth capacitor C5 is connected to pin 6 of the multiplexing chip U25, and the other end of the eighth capacitor C5 is connected to one end of the seventh resistor R104; the other end of the seventh resistor R104, one end of the ninth capacitor C94, and one end of the ninth resistor R106 are respectively connected to pin 2 of the second operational amplifier U2B; pin 1 of the second operational amplifier U2B is respectively connected to the other end of the ninth capacitor C94, the other end of the ninth resistor R106, the analog-to-digital conversion module, and the core processing and control module; one end of the eighth resistor R105 is connected to pin 4 of the multiplexing chip U25, and the other end of the eighth resistor R105 is connected to pin 3 of the second operational amplifier U2B; pin 8 of the second operational amplifier U2B is connected to the VCC power supply terminal, and pin 4 of the second operational amplifier U2B is grounded.

7. The data acquisition network transmission system based on an FPGA detector according to claim 6, characterized in that: The analog-to-digital conversion module includes an analog-to-digital conversion chip U24, model number PCM1808, which has 14 pins. Pin 14 of the analog-to-digital conversion chip U24 is connected to pin 7 of the multiplexing chip U1A, pin 13 of the analog-to-digital conversion chip U24 is connected to pin 1 of the multiplexing chip U2B, pin 3 of the analog-to-digital conversion chip U24 is connected to a 5V power supply, pin 4 of the analog-to-digital conversion chip U24 is connected to a 3.3V power supply, pins 6, 7, 8, 9, 10, and 11 of the analog-to-digital conversion chip U24 are connected to the core processing and control module, and pins 1, 2, 5, and 12 of the analog-to-digital conversion chip U24 are grounded.

8. The data acquisition network transmission system based on an FPGA detector according to claim 7, characterized in that: The core processing and control module is an FPGA with product model Lattice LFE3-70EA. GPIO1 of the FPGA is connected to pin 2 of the multiplexing chip U25; GPIO2 of the FPGA is connected to pin 14 of the multiplexing chip U25; GPIO3 of the FPGA is connected to pin 6 of the analog-to-digital converter chip U24; GPIO4 of the FPGA is connected to pin 7 of the analog-to-digital converter chip U24; GPIO5 of the FPGA is connected to pin 8 of the analog-to-digital converter chip U24; GPIO7 of the FPGA is connected to pin 9 of the analog-to-digital converter chip U24; GPIO6 of the FPGA is connected to pin 10 of the analog-to-digital converter chip U24; GPIO8 of the FPGA is connected to pin 11 of the analog-to-digital converter chip U24; GPIO9 of the FPGA is connected to pin 7 of the first operational amplifier U1A; and GPIO10 of the FPGA is connected to pin 1 of the first operational amplifier U2B.

9. The data acquisition network transmission system based on an FPGA detector according to claim 1, characterized in that: The data transmission module is a gigabit Ethernet chip with product model number 88E1119R.

10. The data acquisition network transmission system based on an FPGA detector according to claim 1, characterized in that: The signal receiving and preprocessing module, signal routing and switching module, signal conditioning and amplification module, analog-to-digital conversion module, core processing and control module, and data transmission module are integrated into one unit.

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