Duty ratio detection device, duty ratio calibration device and electronic equipment

Abstract

The utility model discloses a duty ratio detection device, a duty ratio calibration device and electronic equipment, and the device comprises a first filtering unit which carries out the high-frequency filtering of an input signal, and outputs a first signal; the first signal processing unit is provided with a first input end for inputting a first signal, a second input end for inputting a reference signal and an output end for outputting a second signal; an integrating circuit that accumulates a difference between the first signal and the reference signal; the second filtering unit is used for performing high-frequency filtering on the signal output by the integrating circuit; the first signal processing unit comprises a control module and a first operational amplifier, the control module controls a first signal input by the first input end to be alternately input into the positive pole input end and the negative pole input end of the first operational amplifier, and a reference signal input by the second input end is input into the other input end of the first operational amplifier; and the first operational amplifier is controlled to output corresponding output signals to the output end of the first signal processing unit based on signals input by the positive pole input end and the negative pole input end of the first operational amplifier.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a duty cycle detection device, a duty cycle calibration device, and an electronic device. Background Technology

[0002] In modern electronic systems, the stability of high-precision clock signals is a key factor in ensuring data transmission reliability and system performance. Especially in high-speed digital circuits, communication equipment, and low-power electronic devices, the duty cycle of the clock signal (i.e., the ratio of high level to period) must be strictly close to 50% to minimize timing skew, reduce bit error rate, and improve signal integrity. To adapt to different signal transmission conditions and operating environments, and to ensure accurate data reception and parsing during transmission, duty cycle calibration is performed to adjust and optimize the signal's duty cycle, bringing it as close to 50% as possible. This reduces timing skew and bit error rate during data transmission, improving data transmission stability and reliability. Therefore, how to perform high-precision duty cycle detection to improve duty cycle calibration accuracy has become a research direction for researchers in this field. Utility Model Content

[0003] In view of the above problems, this application provides a duty cycle detection device, a duty cycle calibration device, and an electronic device. The specific solution is as follows:

[0004] A duty cycle detection device, comprising:

[0005] The first filtering unit is used to perform high-frequency filtering on the input signal and output the first signal;

[0006] A first signal processing unit has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives the first signal, the second input terminal receives a reference signal, and the output terminal outputs a second signal, the second signal representing the comparison result between the first signal and the reference signal;

[0007] An integrating circuit, comprising a first resistor and a first capacitor, wherein the first resistor is located between the output terminal of the first filter unit and the first input terminal of the first signal processing unit, a first terminal of the first capacitor is electrically connected to the end of the first resistor away from the first filter unit, and a second terminal of the first capacitor is electrically connected to the output terminal of the first signal processing unit, thereby accumulating the difference between the first signal and the reference signal;

[0008] The second filtering unit is electrically connected to the second terminal of the first capacitor and is used to perform high-frequency filtering on the signal output by the integrator circuit.

[0009] The first signal processing unit includes a control module and a first operational amplifier. The control module controls the first signal input from the first input terminal to be alternately input to the positive and negative input terminals of the first operational amplifier, and the reference signal input from the second input terminal to the other input terminal of the first operational amplifier. The control module also controls the first operational amplifier to output a corresponding output signal to the output terminal of the first signal processing unit based on the signal input from its positive and negative input terminals.

[0010] Optionally, the control module includes a first control circuit and a second control circuit, wherein,

[0011] The first control circuit controls the first signal input at the first input terminal to be alternately input to the positive input terminal and the negative input terminal of the first operational amplifier, and the reference signal input at the second input terminal is input to the other input terminal of the first operational amplifier;

[0012] The second control circuit controls the first operational amplifier to output a corresponding output signal to the output terminal of the first signal processing unit based on the signal input at its positive input terminal and the signal input at its negative input terminal.

[0013] Optionally, the first control circuit includes a first control path, a second control path, a third control path, and a fourth control path, and the second control circuit includes a fifth control path and a sixth control path; wherein,

[0014] The first control path controls the state of the path between the first input terminal of the first signal processing unit and the negative input terminal of the first operational amplifier, and the second control path controls the state of the path between the first input terminal of the first signal processing unit and the positive input terminal of the first operational amplifier.

[0015] The third control path controls the state of the path between the second input terminal of the first signal processing unit and the negative input terminal of the first operational amplifier, and the fourth control path controls the state of the path between the second input terminal of the first signal processing unit and the positive input terminal of the first operational amplifier.

[0016] The fifth control path controls the path state between the first output terminal of the first operational amplifier and the output terminal of the first signal processing unit.

[0017] The sixth control path controls the path state between the second output terminal of the first operational amplifier and the output terminal of the first signal processing unit.

[0018] Optionally, the first signal processing unit further includes:

[0019] The second operational amplifier has its input terminal connected to the output terminal of the second control circuit and its output terminal connected to the output terminal of the first signal processing unit.

[0020] Optionally, the first signal processing unit is a chopper operational amplifier.

[0021] Optional, also includes:

[0022] The second signal processing unit is configured to output a high-level signal when the output signal of the integrator circuit is greater than a first threshold voltage, and to output a low-level signal when the output signal of the integrator circuit is lower than a second threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage.

[0023] Optionally, the second signal processing unit includes a Schmitt trigger.

[0024] Optionally, a reference voltage unit is also included, which is connected to the second input terminal of the first signal processing unit and is used to generate the reference signal.

[0025] A duty cycle calibration device includes a duty cycle adjustment device, a duty cycle detection device, and a control device, wherein the control device generates a control command for the duty cycle adjustment device based on the adjustment signal output by the duty cycle detection device, so that the duty cycle adjustment device adjusts the duty cycle of the clock signal input to its input terminal.

[0026] The duty cycle detection device generates the adjustment signal based on the signal output by the duty cycle adjustment device and the reference signal. The duty cycle detection device includes:

[0027] The first filtering unit is used to perform high-frequency filtering on the input signal and output the first signal;

[0028] A first signal processing unit has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives the first signal, the second input terminal receives a reference signal, and the output terminal outputs a second signal, the second signal representing the comparison result between the first signal and the reference signal;

[0029] An integrating circuit is provided, comprising a first resistor and a first capacitor. The first resistor is located between the output terminal of the first filter unit and the first input terminal of the first signal processing unit. A first terminal of the first capacitor is electrically connected to the end of the first resistor away from the first filter unit, and a second terminal of the first capacitor is electrically connected to the output terminal of the first signal processing unit, thereby accumulating the difference between the first signal and the reference signal.

[0030] The second filtering unit is electrically connected to the second terminal of the first capacitor and is used to perform high-frequency filtering on the signal output by the integrator circuit.

[0031] The first signal processing unit includes a control module and a first operational amplifier. The control module controls the first signal input from the first input terminal to be alternately input to the positive and negative input terminals of the first operational amplifier, and the reference signal input from the second input terminal to the other input terminal of the first operational amplifier. The control module also controls the first operational amplifier to output a corresponding output signal to the output terminal of the first signal processing unit based on the signal input from its positive and negative input terminals.

[0032] An electronic device includes a duty cycle calibration device, which includes a duty cycle adjustment device, a duty cycle detection device, and a control device. The control device generates a control command for the duty cycle adjustment device based on the adjustment signal output by the duty cycle detection device, so that the duty cycle adjustment device adjusts the duty cycle of a clock signal input to its input terminal.

[0033] The duty cycle detection device generates the adjustment signal based on the signal output by the duty cycle adjustment device and the reference signal. The duty cycle detection device includes:

[0034] The first filtering unit is used to perform high-frequency filtering on the input signal and output the first signal;

[0035] A first signal processing unit has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives the first signal, the second input terminal receives a reference signal, and the output terminal outputs a second signal, the second signal representing the comparison result between the first signal and the reference signal;

[0036] An integrating circuit is provided, comprising a first resistor and a first capacitor. The first resistor is located between the output terminal of the first filter unit and the first input terminal of the first signal processing unit. A first terminal of the first capacitor is electrically connected to the end of the first resistor away from the first filter unit, and a second terminal of the first capacitor is electrically connected to the output terminal of the first signal processing unit, thereby accumulating the difference between the first signal and the reference signal.

[0037] The second filtering unit is electrically connected to the second terminal of the first capacitor and is used to perform high-frequency filtering on the signal output by the integrator circuit.

[0038] The first signal processing unit includes a control module and a first operational amplifier. The control module controls the first signal input from the first input terminal to be alternately input to the positive and negative input terminals of the first operational amplifier, and the reference signal input from the second input terminal to the other input terminal of the first operational amplifier. The control module also controls the first operational amplifier to output a corresponding output signal to the output terminal of the first signal processing unit based on the signal input from its positive and negative input terminals. Attached Figure Description

[0039] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0040] Figure 1 This application provides a schematic diagram of the structure of a duty cycle detection device;

[0041] Figure 2 A schematic diagram of another duty cycle detection device provided in this application;

[0042] Figure 3 To simulate the duty cycle device provided in the embodiments of this application, schematic diagrams of the duty cycle detection results after adding 10mV offset, the duty cycle detection results without adding 10mV offset, and the output results of the integrator circuit are shown.

[0043] Figure 4 for Figure 3 A magnified view of the area within the dashed box;

[0044] Figure 5 A schematic diagram of another duty cycle detection device provided in this application;

[0045] Figure 6 A schematic diagram of another duty cycle detection device provided in this application;

[0046] Figure 7 A schematic diagram of a duty cycle calibration device provided in this application;

[0047] Figure 8 A schematic diagram of another duty cycle calibration device provided in this application;

[0048] Figure 9 for Figure 8 The diagram shows the timing signals during the operation of the duty cycle calibration device. Detailed Implementation

[0049] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0050] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0051] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0052] As described in the background section, how to perform high-precision duty cycle detection to improve the calibration accuracy of the duty cycle has become a research direction for those in this field.

[0053] In view of this, embodiments of this application provide a duty cycle detection device, such as... Figure 1 As shown, the device includes:

[0054] The first filtering unit 10 is used to perform high-frequency filtering on the input signal and output a first signal. Optionally, in one embodiment of this application, the first filtering unit 10 is a low-pass filter.

[0055] A first signal processing unit 20 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives the first signal, the second input terminal receives the reference signal VREF, and the output terminal outputs the second signal, which represents the comparison result between the first signal and the reference signal VREF.

[0056] An integrating circuit 30 includes a first resistor R1 and a first capacitor C1. The first resistor R1 is located between the output terminal of the first filter unit 10 and the first input terminal of the first signal processing unit 20. The first terminal of the first capacitor C1 is unidirectionally connected to the end of the first resistor R1 away from the first filter unit 10. The second terminal of the first capacitor C1 is electrically connected to the output terminal of the first signal processing unit 20. The circuit accumulates the difference between the first signal and the reference signal VREF.

[0057] The second filtering unit 40 is electrically connected to the second terminal of the first capacitor C1 and is used to perform high-frequency filtering on the signal output by the integrator circuit 30.

[0058] Optionally, in one embodiment of this application, the input signal is a clock signal to be detected, and the reference signal is a reference voltage of 1 / 2 of the supply voltage. In this embodiment, the working process of the duty cycle detection device includes: the clock signal to be detected is input to the first filtering unit, and high-frequency components are filtered out by the first filtering unit to obtain a first signal; then the first signal and the reference signal are compared by the first signal processing unit to obtain the comparison result of the first signal and the reference signal, and the comparison result of the first signal and the reference signal is accumulated by the integration circuit.

[0059] It should be noted that the difference between the first signal and the reference signal is accumulated using an integrating circuit. Even small deviations between the first signal and the reference signal are continuously accumulated. Specifically, as the accumulation time of the comparison result between the first signal and the reference signal by the integrating circuit increases, when the duty cycle of the clock signal to be detected is greater than 50%, the output signal of the integrating circuit gradually approaches a high level; when the duty cycle of the clock signal to be detected is less than 50%, the output signal of the integrating circuit gradually approaches a low level. Therefore, the duty cycle detection device provided in this embodiment has extremely high detection accuracy, ensuring that the maximum deviation between the duty cycle detection result and the true value does not exceed ±0.1%.

[0060] Therefore, the duty cycle detection device provided in this application embodiment can detect the duty cycle of the clock signal to be detected, and the detection accuracy is high.

[0061] It should be noted that in practical applications, the asymmetry between the positive and negative input terminals of the first operational amplifier can affect the detection of the duty cycle, thus impacting the accuracy of duty cycle detection. The causes of this asymmetry include the offset voltage of the first operational amplifier and device noise. The first operational amplifier is typically constructed from multiple transistors. The offset voltage arises from manufacturing deviations in the input differential pair transistors, leading to a mismatch between the threshold voltage, dimensions, and other parameters of the input differential pair and the target threshold voltage and dimensions, resulting in a static offset voltage at the first operational amplifier input. Device noise includes 1 / f noise (flicker noise), which primarily originates from the random capture and release of channel carriers in the transistors of the first operational amplifier. This noise is significant in the low-frequency range (e.g., Hz~kHz) and can affect the low-frequency accuracy of the integrating circuit.

[0062] Therefore, in this embodiment, the first signal processing unit includes a control module and a first operational amplifier. The control module controls the first signal input from the first input terminal to be alternately input to the positive and negative input terminals of the first operational amplifier, and the reference signal input from the second input terminal is input to the other input terminal of the first operational amplifier. The control module also controls the first operational amplifier to output a corresponding output signal to the output terminal of the first signal processing unit based on the signal input from its positive and negative input terminals. This is to modulate the frequency of the offset voltage and device noise in the first operational amplifier to a high-frequency region, and then filter them out using a second filtering unit to eliminate the influence of the offset voltage and device noise of the first operational amplifier on the duty cycle detection result.

[0063] Furthermore, as the operating time of the duty cycle detection device increases or the ambient temperature changes, the offset voltage and / or device noise in the first operational amplifier may also change. In this embodiment, the control module controls the first signal input from the first input terminal to alternately input to the positive and negative input terminals of the first operational amplifier, and the reference signal input from the second input terminal to the other input terminal of the first operational amplifier. The control module also controls the first operational amplifier to output a corresponding output signal to the output terminal of the first signal processing unit based on the signal input from its positive and negative input terminals. This eliminates the influence of the offset voltage and device noise of the first operational amplifier on the duty cycle detection result, ensuring that the detection accuracy of the duty cycle detection device is not affected by changes in the magnitude of the offset voltage and / or device noise in the first operational amplifier.

[0064] Optionally, in one embodiment of this application, the operation of the duty cycle detection device includes alternating first and second time periods; continuing as... Figure 1 As shown:

[0065] During the first time period, the control module 21 controls the first signal input at the first input terminal a to be input to the positive input terminal c of the first operational amplifier, and the reference signal VREF input at the second input terminal b to be input to the negative input terminal d of the first operational amplifier. It also controls the first output terminal e of the first operational amplifier to output the comparison result of the first signal and the reference signal VREF. That is, at this time, the signal output by the output terminal g of the first signal processing unit 20 is the signal output by the first output terminal e of the first operational amplifier 22.

[0066] During the second time period, the control module 21 controls the first signal input at the first input terminal a to be input to the negative input terminal d of the first operational amplifier, and the reference signal VREF input at the second input terminal b to be input to the positive input terminal c of the first operational amplifier. It also controls the second output terminal f of the first operational amplifier to output the comparison result of the first signal and the reference signal VREF. That is, at this time, the signal output by the output terminal g of the first signal processing unit 20 is the signal output by the second output terminal f of the first operational amplifier 22.

[0067] Specifically, in one embodiment of this application, the following continues... Figure 1 As shown, the control module 21 includes a first control circuit 211 and a second control circuit 212. The first control circuit 211 controls the first signal input at the first input terminal a to be alternately input to the positive and negative input terminals of the first operational amplifier 22, and the reference signal VREF input at the second input terminal b to the other input terminal of the first operational amplifier 22. The second control circuit 212 controls the first operational amplifier 22 to output the response based on the signal input at its positive and negative input terminals and send the response to the output terminal of the first signal processing unit 20, so as to control the input and output of the first operational amplifier respectively through different control circuits.

[0068] like Figure 2 As shown, assuming the first signal is V1, the reference signal VREF is V2, the positive input terminal of the first operational amplifier 22 is c, the negative input terminal is d, and the voltage deviation introduced by the offset voltage and device noise is Vx, which is equivalently applied to the positive input terminal c of the first operational amplifier 22. It should be noted that V1, V2, and Vx are all low-frequency signals. In this embodiment, when the duty cycle detection device is working, the first signal V1 and the reference signal V2 are alternately input to the positive input terminal c and the negative input terminal d of the first operational amplifier 22 under the control of the first control circuit 211. During this process, the frequencies of the first signal V1 and the reference signal V2 are modulated by the first control circuit to switch the input frequency and enter the high-frequency region.

[0069] The first signal V1 and the reference signal V2 are input to the first operational amplifier 22. After being output from the first or second output terminal of the first operational amplifier 22, they are controlled by the second control circuit 212 to switch the output frequency for secondary modulation before being output by the first signal processing unit 20, thereby being demodulated and restoring their original low-frequency range (i.e., the frequency before being input into the first control circuit).

[0070] The voltage deviation Vx introduced by the offset voltage and device noise is only modulated once by the second control circuit when it is output to the output terminal of the first signal processing unit 20. Therefore, it remains in the high frequency region.

[0071] After the signal output from the common terminal of the first signal processing unit and the integrator circuit passes through the second filtering unit, the high-frequency signal is filtered out and the low-frequency signal passes through. Therefore, the duty cycle detection device provided in this application embodiment can eliminate the influence of the offset voltage and device noise of the first operational amplifier on the duty cycle detection result, and does not affect the detection of the duty cycle, further ensuring the detection accuracy of the duty cycle detection device.

[0072] Additionally, it should be noted that during the operation of the duty cycle detection device, in the first half of a cycle, such as the first time period, (V1+Vx-V2) / R1 will charge and discharge the first capacitor C1. In the second half of a cycle, such as the second time period, (V1-Vx-V2) / R1 will charge and discharge the first capacitor C1. Within a complete cycle (i.e., the first time period + the second time period), the charging and discharging of Vx on the first capacitor C1 will cancel each other out, so that the output signal at the output terminal of the integrator circuit only reflects the cumulative change of V1-V2 over time.

[0073] like Figure 3 and Figure 4 As shown, Figure 3 The red waveform in the middle represents the duty cycle detection result after artificially adding a 10mV offset during simulation of the duty cycle device provided in this embodiment. The yellow waveform represents the duty cycle detection result without adding a 10mV offset during simulation of the duty cycle device provided in this embodiment. The blue-green waveform represents the output result of the integrator circuit. Figure 4 for Figure 3 A magnified view of the area within the dashed box, from... Figure 3 and Figure 4 It can be seen that when using the duty cycle detection device provided in this application embodiment to detect the duty cycle, the output result of the integration circuit is almost the same regardless of whether there is an offset.

[0074] Therefore, in the duty cycle detection device provided in this application embodiment, the control module controls the first signal input from the first input terminal to be alternately input to the positive and negative input terminals of the first operational amplifier, and the reference signal input from the second input terminal to be input to the other input terminal of the first operational amplifier. This allows the voltage offset (i.e., voltage deviation) Vx in the clock signal to be detected caused by mismatch between different devices and 1 / f noise to be alternately superimposed on the first and second output terminals of the first operational amplifier. Thus, within a period consisting of a first time period and a second time period, +Vx can be superimposed on the output of the first signal processing unit in the first time period, and -Vx can be superimposed on the output of the first signal processing unit in the second time period. Consequently, within a period consisting of a first time period and a second time period, the accumulated difference between +Vx and -Vx in the integrating circuit cancels each other out, thereby eliminating the influence of voltage offset caused by mismatch between different devices and 1 / f noise on the detection result of the clock signal to be detected, and further improving the detection accuracy of the duty cycle detection device.

[0075] Optionally, in one embodiment of this application, the -3dB bandwidth of the first filtering unit is less than 1 / 2 of the chopping frequency to avoid signal aliasing between the first signal output by the first filtering unit and the chopping signal. The chopping frequency is the frequency at which the control module alternately inputs the first signal input from the first input terminal to the positive and negative input terminals of the first operational amplifier. The chopping signal is the control signal by which the control module controls the first signal input from the first input terminal to alternately input to the positive and negative input terminals of the first operational amplifier.

[0076] Optionally, in one embodiment of this application, the chopping frequency f(chop) is greater than twice the corner frequency f(1 / f corner) of the 1 / f noise, i.e., f(chop) > 2 × f(1 / f corner), so that the control module can completely modulate the low-frequency 1 / f noise signal into the high-frequency region; similarly, the chopping frequency f(chop) is greater than twice the frequency f(offset) of the offset voltage, i.e., f(chop) > 2 × f(offset), so that the control module can completely modulate the low-frequency offset voltage signal into the high-frequency region. However, this application does not limit this, and it depends on the specific circumstances.

[0077] Based on any of the above embodiments, in one embodiment of this application, the first control circuit includes a first control path, a second control path, a third control path, and a fourth control path; wherein...

[0078] Wherein, the first control path controls the state of the path between the first input terminal of the first signal processing unit and the negative input terminal of the first operational amplifier, and the second control path controls the state of the path between the first input terminal of the first signal processing unit and the positive input terminal of the first operational amplifier.

[0079] The third control path controls the state of the path between the second input terminal of the first signal processing unit and the negative input terminal of the first operational amplifier, and the fourth control path controls the state of the path between the second input terminal of the first signal processing unit and the positive input terminal of the first operational amplifier.

[0080] Therefore, this application embodiment achieves the first signal input from the first input terminal being alternately input to the positive and negative input terminals of the first operational amplifier by controlling different signal paths to be in a conducting state, and the reference signal input from the second input terminal being input to the other input terminal of the first operational amplifier. However, this application does not limit this, and it depends on the specific situation.

[0081] Based on any of the above embodiments, in one embodiment of this application, the second control circuit includes a fifth control path and a sixth control path; wherein, the fifth control path controls the path state between the first output terminal of the first operational amplifier and the output terminal of the first signal processing unit; and the sixth control path controls the path state between the second output terminal of the first operational amplifier and the output terminal of the first signal processing unit.

[0082] Therefore, this application embodiment controls the first operational amplifier to output corresponding output signals to the output terminal of the first signal processing unit by controlling different signal paths to be in the conducting state. However, this application does not limit this and it depends on the specific situation.

[0083] Based on any of the above embodiments, in one embodiment of this application, such as Figure 5 As shown, the first signal processing unit 20 further includes a second operational amplifier 23. The input terminal of the second operational amplifier 23 is connected to the output terminal of the second control circuit 212, and the output terminal is connected to the output terminal of the first signal processing unit 20. The second operational amplifier 23 amplifies the output result of the first operational amplifier 22, accelerates the accumulation process of the integral circuit, and thus accelerates the judgment process of the duty cycle detection device.

[0084] Optionally, in one embodiment of this application, the first signal processing unit includes a chopper operational amplifier to compare the first signal and the reference signal and eliminate deviations caused by mismatch noise and 1 / f noise. However, this application does not limit this and the specific implementation depends on the circumstances.

[0085] Based on any of the above embodiments, in one embodiment of this application, the following continues... Figure 5 As shown, the duty cycle detection device further includes:

[0086] The second signal processing unit 50 is configured to output a high-level signal when the output signal of the integrating circuit 30 is greater than a first threshold voltage, and to output a low-level signal when the output signal of the integrating circuit 30 is lower than a second threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage. In this embodiment, when the output signal of the integrating circuit 30 reaches the first threshold voltage, the duty cycle detection device outputs a high level without requiring the output signal of the integrating circuit to reach 1; similarly, when the output signal of the integrating circuit 30 is lower than the second threshold voltage, the duty cycle detection device outputs a low level without requiring the output signal of the integrating circuit to reach 0. This rapidly raises or lowers the output signal of the integrating circuit, thereby accelerating the detection process of the duty cycle detection device and improving its detection sensitivity.

[0087] Optionally, in one embodiment of this application, the second signal processing unit is a Schmitt trigger, but this application does not limit it and it depends on the specific circumstances.

[0088] Based on any of the above embodiments, in one embodiment of this application, such as Figure 5 and Figure 6 As shown, the duty cycle detection device further includes a reference voltage unit 60, which is connected to the second input terminal b of the first signal processing unit 20 and is used to generate the reference signal VREF.

[0089] Optionally, in one embodiment of this application, the reference voltage unit includes a reference voltage composed of a resistor divider and a low-pass filter, with an output voltage value of 1 / 2 of the supply voltage.

[0090] Specifically, in one embodiment of this application, the reference voltage unit 60 includes: a second resistor R2 and a third resistor R3 connected in series between the power supply terminal VDD and the ground terminal GND; a fourth resistor R4 whose first end is connected to the common terminal of the second resistor R2 and the third resistor R3, and whose second end is connected to the second input terminal of the first signal processing unit 20; and a second capacitor C2 connected between the fourth resistor R4 and the ground terminal GND. The power supply terminal VDD is the input supply voltage, and the second resistor R2 and the third resistor R3 are equal, so that the reference voltage unit outputs a reference voltage of 1 / 2 of the supply voltage. However, this application does not limit this, and the specific implementation depends on the circumstances.

[0091] Accordingly, embodiments of this application also provide a duty cycle calibration device and an electronic device including the duty cycle calibration device, such as... Figure 7 As shown, the duty cycle calibration device includes: a duty cycle adjustment device 100, a duty cycle detection device 200, and a control device 300. The control device 300 generates a control command for the duty cycle adjustment device 100 based on the adjustment signal output by the duty cycle detection device 200, so that the duty cycle adjustment device 100 adjusts the duty cycle of the clock signal input to its input terminal.

[0092] The duty cycle detection device 200 generates the adjustment signal based on the signal output by the duty cycle adjustment device 100 and the reference signal, and continues as follows. Figure 1 As shown, the duty cycle detection device includes:

[0093] The first filtering unit 10 is used to perform high-frequency filtering on the input signal and output a first signal. Optionally, in one embodiment of this application, the first filtering unit 10 is a low-pass filter.

[0094] A first signal processing unit 20 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives the first signal, the second input terminal receives the reference signal VREF, and the output terminal outputs the second signal, which represents the comparison result between the first signal and the reference signal VREF.

[0095] An integrating circuit 30 includes a first resistor R1 and a first capacitor C1. The first resistor R1 is located between the output terminal of the first filter unit 10 and the first input terminal of the first signal processing unit 20. The first terminal of the first capacitor C1 is unidirectionally connected to the end of the first resistor R1 away from the first filter unit 10. The second terminal of the first capacitor C1 is electrically connected to the output terminal of the first signal processing unit 20. The circuit accumulates the difference between the first signal and the reference signal VREF.

[0096] The second filtering unit 40 is electrically connected to the second terminal of the first capacitor C1 and is used to perform high-frequency filtering on the signal output by the integrator circuit 30.

[0097] The first signal processing unit includes a control module and a first operational amplifier. The control module controls the first signal input from the first input terminal to be alternately input to the positive and negative input terminals of the first operational amplifier. The reference signal input from the second input terminal is input to the other input terminal of the first operational amplifier. The control module also controls the first operational amplifier to output a corresponding output signal based on the signal input from its positive and negative input terminals to the output terminal of the first signal processing unit. This modulates the frequency of the offset voltage and device noise in the first operational amplifier to a high-frequency region, which is then filtered out by a second filtering unit to eliminate the influence of the offset voltage and device noise of the first operational amplifier on the duty cycle detection result.

[0098] Furthermore, as the operating time of the duty cycle detection device increases or the ambient temperature changes, the offset voltage and / or device noise in the first operational amplifier may also change. In this embodiment, the control module controls the first signal input from the first input terminal to alternately input to the positive and negative input terminals of the first operational amplifier, and the reference signal input from the second input terminal to the other input terminal of the first operational amplifier. The control module also controls the first operational amplifier to output a corresponding output signal to the output terminal of the first signal processing unit based on the signal input from its positive and negative input terminals. This eliminates the influence of the offset voltage and device noise of the first operational amplifier on the duty cycle detection result, ensuring that the detection accuracy of the duty cycle detection device is not affected by changes in the magnitude of the offset voltage and / or device noise in the first operational amplifier.

[0099] Since the duty cycle detection device has been described in the above embodiments, it will not be repeated here.

[0100] Optionally, in one embodiment of this application, the control device is a state machine, such as a finite state machine (FSM), but this application does not limit it and the specific choice depends on the circumstances.

[0101] The working process of the duty cycle calibration device is described below with reference to a distance embodiment.

[0102] like Figure 8As shown, in this embodiment, the control device is a finite state machine (FSM), the duty cycle adjustment device has an external duty cycle adjuster, the integration circuit is an integrator, the first filtering unit is a low-pass filter (LPF1), the first signal processing unit is a chopper operational amplifier, the second filtering unit is a low-pass filter (LPF2), and the second signal processing unit is a Schmitt trigger. In this embodiment, the operation process of the duty cycle calibration device includes:

[0103] The clock signal to be calibrated is input to the duty cycle regulator, and the waveform of the clock signal to be calibrated is as follows: Figure 9 As shown in CLK;

[0104] The duty cycle adjuster increases or decreases the duty cycle of the input clock signal to be calibrated according to FSM (Finite State Machine) instructions. The adjusted clock signal is then output to the low-pass filter LPF1 in the duty cycle detection device for filtering to obtain the DC component of the calibrated clock signal CLK, which is then output. Figure 9 The waveform corresponding to LPF1 out in the data;

[0105] The output signal and reference signal of the low-pass filter LPF1 are input to the first and second input terminals of the chopper operational amplifier. During this period, under the control of the first control circuit in the chopper operational amplifier, the output signal and reference signal of the low-pass filter LPF1 are periodically and alternately input to the positive and negative input terminals of the first operational amplifier, resulting in the output signal of the first output terminal and the output signal of the second output terminal of the first operational amplifier. The waveform of the output signal at the first output terminal e of the first operational amplifier is as follows: Figure 9 The waveform corresponding to 'e out' in the figure, and the output signal of the second output terminal are as follows: Figure 9 The waveform corresponding to f out in the example is the chopping signal. Figure 9 The CHOP CLK waveform in the image shows that its frequency follows the clock frequency of the chopper signal.

[0106] The output signals from the first and second output terminals of the first operational amplifier are alternately output to the output terminal of the chopper operational amplifier under the control of the second control circuit in the chopper operational amplifier, resulting in the waveform at the output terminal of the chopper operational amplifier as shown below. Figure 9 The waveform corresponding to Vout is shown below;

[0107] The integrator accumulates the signal output from the chopper operational amplifier to obtain the input signal of the low-pass filter LPF2. This input signal is then fed into the low-pass filter LPF2, where it filters out high-frequency signals (i.e., high-frequency signals). Figure 9 The output is the sawtooth waveform (as shown in the image), where the input waveform of the low-pass filter LPF2 is as follows: Figure 9The waveform corresponding to LPF2 in is shown in the figure. The output waveform of the low-pass filter LPF2 is as follows. Figure 9 The waveform corresponding to LPF2 iout is shown in the figure;

[0108] The output signal of the low-pass filter LPF2 is input to the Schmitt trigger. When the output signal of the low-pass filter LPF2 is greater than the first threshold voltage, the Schmitt trigger outputs 1 to the finite state machine; when the output signal of the low-pass filter LPF2 is less than the second threshold voltage, the Schmitt trigger outputs 0 to the finite state machine. The output signal of the Schmitt trigger can be as follows: Figure 9 As shown in Schmitt's diagram, the vertical curve represents the second threshold voltage;

[0109] The finite state machine generates control commands for the duty cycle regulator based on the output signal of the Schmitt trigger, so that the duty cycle regulator adjusts the duty cycle of the clock signal input to its input terminal. This process is repeated until a clock signal with a duty cycle as close as 50% is obtained.

[0110] In summary, the duty cycle detection device, duty cycle calibration device, and electronic device provided in this application embodiment can detect the duty cycle of the clock signal to be detected, and the detection accuracy is high, and it is not affected by the offset voltage and 1 / f noise in the first signal processing unit.

[0111] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other.

[0112] It should be noted that, in the description of this application, the accompanying drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in an article or device comprising the aforementioned element.

[0113] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A duty cycle detection apparatus, characterized by comprising: include: The first filtering unit is used to perform high-frequency filtering on the input signal and output the first signal; A first signal processing unit has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives the first signal, the second input terminal receives a reference signal, and the output terminal outputs a second signal, the second signal representing the comparison result between the first signal and the reference signal; An integrating circuit, comprising a first resistor and a first capacitor, wherein the first resistor is located between the output terminal of the first filter unit and the first input terminal of the first signal processing unit, a first terminal of the first capacitor is electrically connected to the end of the first resistor away from the first filter unit, and a second terminal of the first capacitor is electrically connected to the output terminal of the first signal processing unit, thereby accumulating the difference between the first signal and the reference signal; The second filtering unit is electrically connected to the second terminal of the first capacitor and is used to perform high-frequency filtering on the signal output by the integrator circuit. The first signal processing unit includes a control module and a first operational amplifier. The control module controls the first signal input from the first input terminal to be alternately input to the positive and negative input terminals of the first operational amplifier, and the reference signal input from the second input terminal to the other input terminal of the first operational amplifier. The control module also controls the first operational amplifier to output a corresponding output signal to the output terminal of the first signal processing unit based on the signal input from its positive and negative input terminals.

2. The duty cycle detection device according to claim 1, characterized in that, The control module includes a first control circuit and a second control circuit, wherein... The first control circuit controls the first signal input at the first input terminal to be alternately input to the positive input terminal and the negative input terminal of the first operational amplifier, and the reference signal input at the second input terminal is input to the other input terminal of the first operational amplifier; The second control circuit controls the first operational amplifier to output a corresponding output signal to the output terminal of the first signal processing unit based on the signal input at its positive input terminal and the signal input at its negative input terminal.

3. The duty cycle detection device according to claim 2, characterized in that, The first control circuit includes a first control path, a second control path, a third control path, and a fourth control path; the second control circuit includes a fifth control path and a sixth control path; wherein, The first control path controls the state of the path between the first input terminal of the first signal processing unit and the negative input terminal of the first operational amplifier, and the second control path controls the state of the path between the first input terminal of the first signal processing unit and the positive input terminal of the first operational amplifier. The third control path controls the state of the path between the second input terminal of the first signal processing unit and the negative input terminal of the first operational amplifier, and the fourth control path controls the state of the path between the second input terminal of the first signal processing unit and the positive input terminal of the first operational amplifier. The fifth control path controls the path state between the first output terminal of the first operational amplifier and the output terminal of the first signal processing unit. The sixth control path controls the path state between the second output terminal of the first operational amplifier and the output terminal of the first signal processing unit.

4. The duty cycle detection device according to claim 2, characterized in that, The first signal processing unit further includes: The second operational amplifier has its input terminal connected to the output terminal of the second control circuit and its output terminal connected to the output terminal of the first signal processing unit.

5. The duty cycle detection device according to claim 1, characterized in that, The first signal processing unit is a chopper operational amplifier.

6. The duty cycle detection device according to claim 1, characterized in that, Also includes: The second signal processing unit is configured to output a high-level signal when the output signal of the integrator circuit is greater than a first threshold voltage, and to output a low-level signal when the output signal of the integrator circuit is lower than a second threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage.

7. The duty cycle detection device according to claim 6, characterized in that, The second signal processing unit includes a Schmitt trigger.

8. The duty cycle detection device according to claim 1, characterized in that, It also includes a reference voltage unit, which is connected to the second input terminal of the first signal processing unit and is used to generate the reference signal.

9. A duty cycle calibration device, characterized in that, It includes a duty cycle adjustment device, a duty cycle detection device, and a control device, wherein the control device generates a control command for the duty cycle adjustment device based on the adjustment signal output by the duty cycle detection device, so that the duty cycle adjustment device adjusts the duty cycle of the clock signal input to its input terminal. The duty cycle detection device generates the adjustment signal based on the signal output by the duty cycle adjustment device and the reference signal. The duty cycle detection device includes: The first filtering unit is used to perform high-frequency filtering on the input signal and output the first signal; A first signal processing unit has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives the first signal, the second input terminal receives a reference signal, and the output terminal outputs a second signal, the second signal representing the comparison result between the first signal and the reference signal; An integrating circuit includes a first resistor and a first capacitor. The first resistor is located between the output terminal of the first filter unit and the first input terminal of the first signal processing unit. A first terminal of the first capacitor is electrically connected to the end of the first resistor away from the first filter unit, and a second terminal of the first capacitor is electrically connected to the output terminal of the first signal processing unit to accumulate the difference between the first signal and the reference signal. The second filtering unit is electrically connected to the second terminal of the first capacitor and is used to perform high-frequency filtering on the signal output by the integrator circuit. The first signal processing unit includes a control module and a first operational amplifier. The control module controls the first signal input from the first input terminal to be alternately input to the positive and negative input terminals of the first operational amplifier, and the reference signal input from the second input terminal to the other input terminal of the first operational amplifier. The control module also controls the first operational amplifier to output a corresponding output signal to the output terminal of the first signal processing unit based on the signal input from its positive and negative input terminals.

10. An electronic device, characterized in that, The device includes a duty cycle calibration device, which comprises a duty cycle adjustment device, a duty cycle detection device, and a control device. The control device generates a control command for the duty cycle adjustment device based on the adjustment signal output by the duty cycle detection device, so that the duty cycle adjustment device adjusts the duty cycle of the clock signal input to its input terminal. The duty cycle detection device generates the adjustment signal based on the signal output by the duty cycle adjustment device and the reference signal. The duty cycle detection device includes: The first filtering unit is used to perform high-frequency filtering on the input signal and output the first signal; A first signal processing unit has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives the first signal, the second input terminal receives a reference signal, and the output terminal outputs a second signal, the second signal representing the comparison result between the first signal and the reference signal; An integrating circuit includes a first resistor and a first capacitor. The first resistor is located between the output terminal of the first filter unit and the first input terminal of the first signal processing unit. A first terminal of the first capacitor is electrically connected to the end of the first resistor away from the first filter unit, and a second terminal of the first capacitor is electrically connected to the output terminal of the first signal processing unit to accumulate the difference between the first signal and the reference signal. The second filtering unit is electrically connected to the second terminal of the first capacitor and is used to perform high-frequency filtering on the signal output by the integrator circuit. The first signal processing unit includes a control module and a first operational amplifier. The control module controls the first signal input from the first input terminal to be alternately input to the positive and negative input terminals of the first operational amplifier, and the reference signal input from the second input terminal to the other input terminal of the first operational amplifier. The control module also controls the first operational amplifier to output a corresponding output signal to the output terminal of the first signal processing unit based on the signal input from its positive and negative input terminals.

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