10g clock data recovery unit

Abstract

This utility model discloses a 10G clock data recovery instrument, encompassing front-end signal conditioning, clock extraction, data recovery, control and monitoring, and power management modules. The front-end signal conditioning module receives high-speed data signals and performs preprocessing such as amplification and filtering to remove noise, enhance signal strength, and improve signal quality, laying the foundation for subsequent clock extraction and data recovery and reducing bit errors and data loss caused by poor signal strength. The clock extraction unit filters the phase difference signal to accurately extract the clock signal synchronized with the data signal, providing a stable time reference for data recovery. The data recovery module samples and recovers data based on this clock signal, accurately restoring the original data, ensuring the accuracy and integrity of data during high-speed transmission, and effectively improving the reliability of data transmission.

Description

Technical Field

[0001] This utility model belongs to the field of communication testing technology, specifically a 10G clock data recovery instrument. Background Technology

[0002] With the rapid development of high-speed data communication technology, data transmission rates are constantly increasing. In 10G and higher speed data transmission systems, such as 10G Ethernet and 10G fiber optic communication, signal integrity and accurate clock data recovery become extremely critical. Furthermore, with increasing system integration, the requirements for miniaturization, low power consumption, and compatibility with other components in clock data recovery devices are also growing.

[0003] Existing technologies are susceptible to interference from factors such as noise, dispersion, and jitter during transmission, leading to a decline in signal quality. Moreover, traditional methods may have shortcomings in terms of clock extraction accuracy, data recovery accuracy, and adaptability to different code patterns and signal characteristics. Utility Model Content

[0004] The purpose of this invention is to provide a 10G clock data recovery instrument to address the shortcomings of existing methods in the background art in terms of clock extraction accuracy, data recovery accuracy, and adaptability to different code patterns and signal characteristics.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows:

[0006] A 10G clock data recovery device includes a front-end signal conditioning module, a clock extraction unit, a data recovery module, a control and monitoring module, and a power management module;

[0007] The front-end signal conditioning module receives high-speed data signals, amplifies and filters them to improve signal quality and make them suitable for subsequent processing. After signal conditioning, it transmits the signal to the clock extraction unit. The clock extraction unit filters the phase difference signal and transmits the filtered signal to the data recovery module. The data recovery module samples and recovers the data.

[0008] The control and monitoring module is used to monitor and control the working status of the entire clock data recovery instrument; the power management module is used to provide a stable and appropriate power supply for each module.

[0009] According to the above technical solution, the front-end signal conditioning module includes chip U707-1, capacitor C858, capacitor C859, capacitor C860, capacitor C861, capacitor C862, ferrite bead FB11, and ferrite bead FB12.

[0010] Pins 1, 4, 7, 10, 19, 21, 24, 27, 30, 41, 42, 43, and 44 of chip U707-1 are all grounded;

[0011] Pin 18 of chip U707-1 is connected to one end of capacitor C858. The other end of capacitor C858 is connected to one end of capacitor C859 and capacitor C860 respectively. The other end of capacitor C860 is connected to the other end of capacitor C859, pin 40 and pin 31 of chip 707-1, and one end of ferrite bead FB11 respectively.

[0012] Pin 20 of chip 707-1 is connected to pin 11 of chip 707-1, capacitor C861, capacitor C862 and one end of ferrite bead FB12; the other ends of capacitors C861 and C862 are connected to pins 52 to 45 and 53 of chip U707-1.

[0013] According to the above technical solution, pin 18 of chip U707-1 is connected to capacitor C858 and power supply; capacitors C858, C859 and C860 are all grounded.

[0014] According to the above technical solution, both magnetic beads FB11 and FB12 are also connected to a power source.

[0015] According to the above technical solution, the clock extraction unit includes chip U707-3, resistors R882, R881, R880, R879, R878, and R877; pin 16 of chip U707-3 is connected to one end of resistor R882, pin 17 of chip U707-3 is connected to one end of resistor R881, pin 25 of chip U707-3 is connected to one end of resistor R880, and pin U707... Pin 32 of chip U707-3 is connected to one end of resistor R879; pin 33 of chip U707-3 is connected to one end of resistor R878; pin 37 of chip U707-3 is connected to one end of resistor R877; the other ends of resistors R882, R881, R880, R879, R878, and R877 are all grounded; pins 12 and 15 of chip U707-3 are connected to the control and monitoring modules respectively.

[0016] According to the above technical solution, the data recovery module includes chip U707-2, connectors J16, J17, J18, J19, J30, J31, J32, J33, capacitors C867, C868, C869, C870, C871, C872, C873, and C874.

[0017] Pin 3 of chip U707-2 is connected to one end of capacitor C871, and the other end of capacitor C871 is connected to one end of connector J16, with the other end of connector J16 grounded; pin 2 of chip U707-2 is connected to one end of capacitor C872, and the other end of capacitor C872 is connected to one end of connector J17, with the other end of connector J17 grounded; pin 8 of chip U707-2 is connected to one end of capacitor C873, and the other end of capacitor C873 is connected to one end of connector J19, with the other end of connector J19 grounded; pin 9 of chip U707-2 is connected to one end of capacitor C874, and the other end of capacitor C874 is connected to one end of connector J18, with the other end of connector J18 grounded.

[0018] Pin 28 of chip U707-2 is connected to one end of capacitor C870, and the other end of capacitor C870 is connected to one end of connector J30, which is grounded. Pin 29 of chip U707-2 is connected to one end of capacitor C869, and the other end of capacitor C869 is connected to one end of connector J31, which is grounded. Pin 23 of chip U707-2 is connected to one end of capacitor C868, and the other end of capacitor C868 is connected to one end of connector J32, which is grounded. Pin 22 of chip U707-2 is connected to one end of capacitor C867, and the other end of capacitor C867 is connected to one end of connector J33, which is grounded.

[0019] According to the above technical solution, the control and monitoring module includes chip U12, capacitor C6, resistor R12, resistor R883, resistor R884, resistor R885 and connector J10.

[0020] Pins 2, 4, 5, and 8 of chip U12 are connected to the power management module; pin 3 of chip U2 is connected to one end of capacitor C6, the other end of capacitor C6 is connected to one end of resistor R885 and pin 6 of chip U12, and the other end of resistor R885 is connected to the power supply.

[0021] Pin 9 of chip U12 is connected to pin 7 of connector J10 and one end of resistor R12, with the other end of resistor R12 connected to the power supply; pin 10 of chip U12 is connected to pin 4 of connector J10; pin 14 of chip U12 is connected to one end of resistor R883, with the other end of resistor R883 connected to pin 16 of chip U12; pin 15 of chip U12 is connected to one end of resistor R884, with the other end of resistor R884 connected to pin 17 of chip U12.

[0022] Pin 1 of connector J10 is connected to the power supply; pins 3 and 9 of connector J10 are grounded; pin 2 of connector J10 is grounded.

[0023] According to the above technical solution, pin 14 of chip U12 is connected to pin 12 of chip U707-3, and pin 15 of chip U12 is connected to pin 15 of chip U707-3.

[0024] According to the above technical solution, the USB interface module includes connector J7, connector J14, resistor R886, diode D2, and resistor R9; pin 1 of connector J7 is connected to pin 8 of chip U12; pin 2 of connector J7 is connected to pin 5 of chip U12; pin 3 of connector J7 is connected to pin 4 of chip U12; pin 4 of connector J7 is connected to one end of resistor R886, and the other end of resistor R886 is connected to pins 5 and 6 of connector J7 respectively.

[0025] Pin 4 of connector J7 and resistor R886 are both grounded; pins 5 and 6 of connector J7 and resistor R886 are also grounded.

[0026] Pin 1 of connector J14 is connected to pin 8 of chip U12; pin 2 of connector J14 is connected to pin 5 of chip U12; pin 3 of connector J14 is connected to pin 4 of chip U12; pin 4 of connector J14 is grounded.

[0027] One end of diode D2 is connected to the power supply, and the other end of diode D2 is connected to one end of resistor R9. The other end of resistor R9 is connected to pin 2 of chip U12.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] In this invention, the front-end signal conditioning module performs preprocessing such as amplification and filtering on the high-speed data signal, effectively removing noise interference, enhancing signal strength, and significantly improving signal quality. The preprocessed signal is more suitable for subsequent module processing, laying a solid foundation for accurate clock extraction and data recovery, and helping to reduce bit errors and data loss caused by poor signal quality. The clock extraction unit filters the phase difference signal, accurately extracting a clock signal synchronized with the data signal, providing a stable time reference for data recovery. The data recovery module samples and recovers the data based on this clock signal, accurately restoring the original data, ensuring the accuracy and integrity of data during high-speed transmission, and improving the reliability of data transmission. Attached Figure Description

[0030] Figure 1 This is a circuit diagram of the front-end signal conditioning module of this utility model;

[0031] Figure 2This is a circuit diagram of the clock extraction unit of this utility model;

[0032] Figure 3 This is a circuit diagram of the data recovery module of this utility model;

[0033] Figure 4 This is the circuit diagram of the control and monitoring module of this utility model;

[0034] Figure 5 This is the circuit diagram of the power management module of this utility model. Detailed Implementation

[0035] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0036] Example 1

[0037] A 10G clock data recovery device, specifically relating to a 10G clock data recovery circuit; including a front-end signal conditioning module, a clock extraction unit, a data recovery module, a control and monitoring module, and a power management module;

[0038] The front-end signal conditioning module receives high-speed data signals, amplifies and filters them to improve signal quality and make them suitable for subsequent processing. After signal conditioning, it transmits the signal to the clock extraction unit. The clock extraction unit filters the phase difference signal and transmits the filtered signal to the data recovery module. The data recovery module samples and recovers the data.

[0039] The control and monitoring module is used to monitor and control the working status of the entire clock data recovery instrument; the power management module is used to provide a stable and appropriate power supply for each module.

[0040] In this invention, the front-end signal conditioning module performs preprocessing such as amplification and filtering on the high-speed data signal, effectively removing noise interference, enhancing signal strength, and significantly improving signal quality. The preprocessed signal is more suitable for subsequent module processing, laying a solid foundation for accurate clock extraction and data recovery, and helping to reduce bit errors and data loss caused by poor signal quality. The clock extraction unit filters the phase difference signal, accurately extracting a clock signal synchronized with the data signal, providing a stable time reference for data recovery. The data recovery module samples and recovers the data based on this clock signal, accurately restoring the original data, ensuring the accuracy and integrity of data during high-speed transmission, and improving the reliability of data transmission.

[0041] Example 2

[0042] This embodiment is a further refinement of Embodiment 1.

[0043] like Figure 1 As shown, the front-end signal conditioning module includes chip U707-1, capacitors C858, C859, C860, C861, C862, ferrite bead FB11, and ferrite bead FB12.

[0044] Pins 1, 4, 7, 10, 19, 21, 24, 27, 30, 41, 42, 43, and 44 of chip U707-1 are all grounded;

[0045] Pin 18 of chip U707-1 is connected to one end of capacitor C858. The other end of capacitor C858 is connected to one end of capacitor C859 and capacitor C860 respectively. The other end of capacitor C860 is connected to the other end of capacitor C859, pin 40 and pin 31 of chip 707-1, and one end of ferrite bead FB11 respectively.

[0046] Pin 20 of chip 707-1 is connected to pin 11 of chip 707-1, capacitor C861, capacitor C862 and one end of ferrite bead FB12; the other ends of capacitors C861 and C862 are connected to pins 52 to 45 and 53 of chip U707-1.

[0047] Pin 18 of chip U707-1 and capacitor C858 are also connected to the power supply; capacitors C858, C859 and C860 are all grounded.

[0048] Both FB11 and FB12 magnetic beads are also connected to a power source.

[0049] like Figure 2As shown, the clock extraction unit includes chip U707-3, resistors R882, R881, R880, R879, R878, and R877. Pin 16 of chip U707-3 is connected to one end of resistor R882, pin 17 of chip U707-3 is connected to one end of resistor R881, pin 25 of chip U707-3 is connected to one end of resistor R880, pin 32 of chip U707-3 is connected to one end of resistor R879, pin 33 of chip U707-3 is connected to one end of resistor R878, and pin 37 of chip U707-3 is connected to one end of resistor R877. Resistors R882, R881, R880, R879, R878, and R877 are all grounded. Pins 12 and 15 of chip U707-3 are connected to the control and monitoring module, respectively.

[0050] like Figure 3 As shown, the data recovery module includes chip U707-2, connectors J16, J17, J18, J19, J30, J31, J32, J33, capacitors C867, C868, C869, C870, C871, C872, C873, and C874;

[0051] Pin 3 of chip U707-2 is connected to one end of capacitor C871, and the other end of capacitor C871 is connected to one end of connector J16, with the other end of connector J16 grounded; pin 2 of chip U707-2 is connected to one end of capacitor C872, and the other end of capacitor C872 is connected to one end of connector J17, with the other end of connector J17 grounded; pin 8 of chip U707-2 is connected to one end of capacitor C873, and the other end of capacitor C873 is connected to one end of connector J19, with the other end of connector J19 grounded; pin 9 of chip U707-2 is connected to one end of capacitor C874, and the other end of capacitor C874 is connected to one end of connector J18, with the other end of connector J18 grounded.

[0052] Pin 28 of chip U707-2 is connected to one end of capacitor C870, and the other end of capacitor C870 is connected to one end of connector J30, which is grounded. Pin 29 of chip U707-2 is connected to one end of capacitor C869, and the other end of capacitor C869 is connected to one end of connector J31, which is grounded. Pin 23 of chip U707-2 is connected to one end of capacitor C868, and the other end of capacitor C868 is connected to one end of connector J32, which is grounded. Pin 22 of chip U707-2 is connected to one end of capacitor C867, and the other end of capacitor C867 is connected to one end of connector J33, which is grounded.

[0053] like Figure 4 As shown, the control and monitoring module includes chip U12, capacitor C6, resistor R12, resistor R883, resistor R884, resistor R885 and connector J10;

[0054] Pins 2, 4, 5, and 8 of chip U12 are connected to the power management module; pin 3 of chip U2 is connected to one end of capacitor C6, the other end of capacitor C6 is connected to one end of resistor R885 and pin 6 of chip U12, and the other end of resistor R885 is connected to the power supply.

[0055] Pin 9 of chip U12 is connected to pin 7 of connector J10 and one end of resistor R12, with the other end of resistor R12 connected to the power supply; pin 10 of chip U12 is connected to pin 4 of connector J10; pin 14 of chip U12 is connected to one end of resistor R883, with the other end of resistor R883 connected to pin 16 of chip U12; pin 15 of chip U12 is connected to one end of resistor R884, with the other end of resistor R884 connected to pin 17 of chip U12.

[0056] Pin 1 of connector J10 is connected to the power supply; pins 3 and 9 of connector J10 are grounded; pin 2 of connector J10 is grounded.

[0057] Pin 14 of chip U12 is connected to pin 12 of chip U707-3, and pin 15 of chip U12 is connected to pin 15 of chip U707-3.

[0058] like Figure 5As shown, the USB interface module includes connector J7, connector J14, resistor R886, diode D2, and resistor R9; pin 1 of connector J7 is connected to pin 8 of chip U12; pin 2 of connector J7 is connected to pin 5 of chip U12; pin 3 of connector J7 is connected to pin 4 of chip U12; pin 4 of connector J7 is connected to one end of resistor R886, and the other end of resistor R886 is connected to pins 5 and 6 of connector J7 respectively.

[0059] Pin 4 of connector J7 and resistor R886 are both grounded; pins 5 and 6 of connector J7 and resistor R886 are also grounded.

[0060] Pin 1 of connector J14 is connected to pin 8 of chip U12; pin 2 of connector J14 is connected to pin 5 of chip U12; pin 3 of connector J14 is connected to pin 4 of chip U12; pin 4 of connector J14 is grounded.

[0061] One end of diode D2 is connected to the power supply, and the other end of diode D2 is connected to one end of resistor R9. The other end of resistor R9 is connected to pin 2 of chip U12.

[0062] Furthermore, all components involved in this utility model are existing technologies. For example, chip U707-1 uses a MASC-37028 chip; chip U12 uses a C8051 F342 chip.

[0063] The working principle of this utility model is as follows: Chip U707-1 and its surrounding capacitors and ferrite beads constitute a front-end signal conditioning module. Multiple pins of chip U707-1 are grounded, and pin 18 is connected to capacitor C858 and the power supply. Through filtering operations performed by capacitors C858, C859, and C860, high-frequency noise in the power signal is filtered out, providing a stable power supply to the chip. Simultaneously, ferrite beads FB11 and FB12 are also connected to the power supply to suppress high-frequency interference on the power line. This module receives high-speed data signals, uses chip U707-1 to amplify and filter the signals, improving signal quality to meet the requirements of subsequent processing, and then transmits the processed signal to the clock extraction unit.

[0064] The U707-3 chip, along with multiple resistors, forms a clock extraction unit. Pins 16, 17, 25, 32, 33, and 37 of the U707-3 chip are connected to resistors R882, R881, R880, R879, R878, and R877, respectively. The other ends of these resistors are grounded, allowing for voltage division or current limiting of the input signal. Pins 12 and 15 of the U707-3 chip are connected to the control and monitoring module, receiving control signals or feedback status information. The clock extraction unit filters the signal from the front-end signal conditioning module, extracts the clock signal, and transmits it to the data recovery module, providing a clock reference for data recovery.

[0065] The U707-2 chip, along with multiple connectors and capacitors, forms a data recovery module. Multiple pins of the U707-2 chip are connected to capacitors and connectors, such as pin 3 connecting capacitor C871 and connector J16, and pin 2 connecting capacitor C872 and connector J17. This circuit, composed of capacitors and connectors, is used for sample-and-hold or filtering of the data signal. Synchronized with the clock signal provided by the clock extraction unit, the data recovery module samples and recovers the signal after front-end processing and clock extraction, restoring it to the original data signal.

[0066] Chip U12 and related resistors, capacitors, and connectors constitute the control and monitoring module. Pins 2, 4, 5, and 8 of chip U12 are connected to the power management module to obtain power. Chip U12 connects to capacitor C6 and resistor R885 via pin 3 to perform power filtering and voltage division. Pin 9 connects to connector J10 and resistor R12, and pin 10 connects to pin 4 of connector J10 for communication with external devices or receiving control commands. Pin 14 connects to pin 12 of chip U707-3, and pin 15 connects to pin 15 of chip U707-3 to control and monitor the clock extraction unit. The control and monitoring module is responsible for monitoring and controlling the overall operation of the clock data recovery instrument, including setting operating parameters, monitoring module status, and handling abnormal situations.

[0067] A stable and suitable power supply is provided to each module to ensure its normal operation. In the control and monitoring module, multiple pins of chip U12 are connected to the power management module, indicating that the power management module provides power to the control and monitoring module, and also provides the necessary power to other modules such as the front-end signal conditioning module, clock extraction unit, and data recovery module, ensuring the stable operation of the entire system.

[0068] The external device communication circuit consists of connectors J7 and J14, resistor R886, diode D2, and resistor R9. Multiple pins of connectors J7 and J14 are connected to different pins of chip U12 to enable data transmission or communication with external devices. Resistor R886 is used for current limiting or voltage division, and the circuit composed of diode D2 and resistor R9 controls the on / off function of indicator lights on chip U12. The USB interface module provides a data transmission channel between the clock data recovery instrument and external devices, facilitating user operations such as device configuration, data reading, and system upgrades.

[0069] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0070] Finally, it should be noted that the above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A 10G clock data recovery device, characterized by: It includes a front-end signal conditioning module, a clock extraction unit, a data recovery module, a control and monitoring module, and a power management module; The front-end signal conditioning module receives high-speed data signals, amplifies and filters them to improve signal quality for subsequent processing, and then transmits the signal to the clock extraction unit after signal conditioning. The clock extraction unit filters the phase difference signal and transmits the filtered signal to the data recovery module. The data recovery module samples and recovers the data. The control and monitoring module is used to monitor and control the working status of the entire clock data recovery unit; the power management module is used to provide a stable power supply to each module. The front-end signal conditioning module includes: chip U707-1, capacitors C858, C859, C860, C861, C862, ferrite bead FB11, and ferrite bead FB12. Pins 1, 4, 7, 10, 19, 21, 24, 27, 30, 41, 42, 43, and 44 of chip U707-1 are all connected to ground; Pins 20 and 11 of chip U707-1 are connected and connected to system ground via capacitors C861 and C862 in parallel. At the same time, it is connected to the external power supply via ferrite bead FB12. The clock extraction unit includes: chip U707-3, resistors R877, R878, R879, R880, R881, and R882; Pins 16, 17, 25, 32, 33, and 37 of chip U707-3 are pulled down to system ground through resistors R882, R881, R880, R879, R878, and R877, respectively, to set the bandwidth parameters of the clock extraction loop; pins 12 and 15 of chip U707-3 are connected to the control and monitoring module. The data recovery module includes: chip U707-2, connectors J16, J17, J18, J19, J30, J31, J32, J33, capacitors C867, C868, C869, C870, C871, C872, C873, and C874; Pins 3, 2, 8, 9, 28, 29, 23, and 22 of chip U707-2 are connected to one end of data output connectors J16, J17, J19, J18, J30, J31, J32, and J33 via first capacitors C871, C872, C873, C874, C870, C869, C868, and C867, respectively. The other end of the data output connectors is connected to system ground.

2. The 10G clock data recovery device according to claim 1, characterized in that: Pin 18 of chip U707-1 is connected to one end of capacitor C858. The other end of capacitor C858 is connected to one end of capacitor C859 and capacitor C860 respectively. The other end of capacitor C860 is connected to the other end of capacitor C859, pin 40 and pin 31 of chip 707-1, and one end of ferrite bead FB11 respectively.

3. A 10G clock data recovery device according to claim 2, wherein: Pin 18 of chip U707-1 is connected to capacitor C858 and the power supply; capacitors C858, C859 and C860 are all grounded.

4. A 10G clock data recovery device according to claim 3, wherein: Both FB11 and FB12 magnetic beads are also connected to a power source.

5. A 10G clock data recovery device according to claim 1, wherein: The control and monitoring module includes chip U12, capacitor C6, resistor R12, resistor R883, resistor R884, resistor R885, and connector J10; Pins 2, 4, 5, and 8 of chip U12 are connected to the power management module; pin 3 of chip U2 is connected to one end of capacitor C6, the other end of capacitor C6 is connected to one end of resistor R885 and pin 6 of chip U12, and the other end of resistor R885 is connected to the power supply. Pin 9 of chip U12 is connected to pin 7 of connector J10 and one end of resistor R12, with the other end of resistor R12 connected to the power supply; pin 10 of chip U12 is connected to pin 4 of connector J10; pin 14 of chip U12 is connected to one end of resistor R883, with the other end of resistor R883 connected to pin 16 of chip U12; pin 15 of chip U12 is connected to one end of resistor R884, with the other end of resistor R884 connected to pin 17 of chip U12. Pin 1 of connector J10 is connected to the power supply; pins 3 and 9 of connector J10 are grounded; pin 2 of connector J10 is grounded.

6. A 10G clock data recovery device according to claim 5, wherein: Pin 14 of chip U12 is connected to pin 12 of chip U707-3, and pin 15 of chip U12 is connected to pin 15 of chip U707-3.

7. A 10G clock data recovery device according to claim 6, wherein: The USB interface module includes connector J7, connector J14, resistor R886, diode D2, and resistor R9; pin 1 of connector J7 is connected to pin 8 of chip U12; pin 2 of connector J7 is connected to pin 5 of chip U12; pin 3 of connector J7 is connected to pin 4 of chip U12; pin 4 of connector J7 is connected to one end of resistor R886, and the other end of resistor R886 is connected to pins 5 and 6 of connector J7 respectively. Pin 4 of connector J7 and resistor R886 are both grounded; pins 5 and 6 of connector J7 and resistor R886 are also grounded. Pin 1 of connector J14 is connected to pin 8 of chip U12; pin 2 of connector J14 is connected to pin 5 of chip U12; pin 3 of connector J14 is connected to pin 4 of chip U12; pin 4 of connector J14 is grounded. One end of diode D2 is connected to the power supply, and the other end of diode D2 is connected to one end of resistor R9. The other end of resistor R9 is connected to pin 2 of chip U12.

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