Storage circuits, in-memory computing devices, in-memory computing systems and electronic devices

Abstract

Storage circuits, in-memory computing devices, in-memory computing systems, and electronic devices are disclosed, designing for use in the semiconductor technology field. The storage circuit, used in an in-memory computing system, includes a storage cell array. The storage cell array includes a first storage region and a second storage region. The first storage region is used to store weight data and to perform calculations based on the weight data and input data. The second storage region is used to store non-weight data. The number of storage cell arrays in the storage circuit can be reduced, thereby reducing the number of peripheral circuits, and consequently reducing the hardware overhead of the storage circuit and the in-memory computing device and system using it.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to memory circuits, in-memory computing devices, in-memory computing systems, and electronic devices. Background Technology

[0002] In traditional computing paradigms, such as the von Neumann architecture, storage and computation are physically separated. When processing data using this paradigm, data is frequently transferred between storage devices and computing devices, resulting in data transmission latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the volume of data processing is growing rapidly, and the demand for data transmission is also increasing rapidly. The resulting transmission latency and energy consumption are becoming increasingly prominent, restricting the development of data processing capabilities and making traditional computing paradigms unable to meet the demands of processing power.

[0003] In-memory computing (IMC) architecture physically integrates storage and computation, enabling computation through storage devices or storing data within computing devices. This reduces data transfer requirements, lowers latency and energy consumption, and significantly improves data processing efficiency. However, IMC architecture still faces challenges; for example, the efficiency of storage space utilization in IMC architecture still needs improvement. Utility Model Content

[0004] This application provides a storage circuit, a storage computing device, a storage computing system, and an electronic device.

[0005] In a first aspect, a storage circuit is provided for a storage computing system. The storage circuit includes a storage cell array, which includes a first storage area and a second storage area. The first storage area is used to store weight data and to perform calculations based on the weight data and input data. The second storage area is used to store non-weight data.

[0006] A storage cell array includes both areas for storing weighted data and areas for storing non-weighted data. This reduces the number of storage cell arrays, thereby reducing the number of peripheral circuits and ultimately reducing the hardware overhead of the in-memory computing system.

[0007] Optionally, the non-weight data includes management data of the in-memory computing system. The management data includes one or more of the following: status data for managing the status of the storage circuit; startup parameters for controlling the startup of the in-memory computing system; configuration parameters for configuring the in-memory computing system; address parameters for managing the address of the storage circuit; and computing parameters for controlling the programming or reading of weight data or the calculation of the in-memory computing system.

[0008] Optionally, the first storage region includes a first storage cell, and the second storage region includes a second storage cell. The first storage cell includes a first input terminal and a first output terminal; the second storage cell includes a second input terminal and a second output terminal; the first output terminal and the second output terminal are connected to the same output line, and the first input terminal and the second output terminal are connected to different input lines.

[0009] Optionally, when reading the calculation result of the storage cell group where the first storage cell is located through the same output line, the second storage cell in the second storage area is turned off.

[0010] Optionally, the first and second storage units are programmed synchronously via different input lines.

[0011] Optionally, the first storage area includes a third storage cell, the second storage area includes a fourth storage cell, the third storage cell includes a third input terminal and a third output terminal; the fourth storage cell includes a fourth input terminal and a fourth output terminal; the third input terminal and the fourth input terminal are connected to the same input line, and the third output terminal and the fourth output terminal are connected to different output lines.

[0012] Optionally, the third and fourth memory cells are programmed synchronously via the same input line.

[0013] Optionally, the first storage area includes a first sub-region and a second sub-region. The first sub-region and the second storage area share an output line, while the output lines of the second sub-region and the second storage area are independent. When reading the calculation result of the storage cell group in the second sub-region, the storage cells in the first sub-region and the second storage area are turned off.

[0014] Optionally, the first storage region is located in the first region of the storage circuit at a first time and in the second region of the storage circuit at a second time, and the first region and the second region are different.

[0015] Optionally, the second storage region is located in the third region of the storage circuit at the third time and in the fourth region of the storage circuit at the fourth time, and the third region and the fourth region are different.

[0016] In a second aspect, a storage computing device is provided, including any of the storage circuits in the first aspect; an input circuit connected to the storage circuit and shared by a first storage area and a second storage area; and an output circuit connected to the storage circuit and shared by the first storage area and the second storage area.

[0017] Optionally, the channel activated by the input circuit is determined based on the operating state of the memory system and the locations of the first and second storage areas.

[0018] Thirdly, a storage computing system is provided, including any of the storage computing devices described in the second aspect; and a control device for controlling the operating state of the storage computing device.

[0019] Fourthly, an electronic device is provided, including any of the memory computing systems described in the third aspect. Attached Figure Description

[0020] Figure 1 A schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown.

[0021] Figure 2 A schematic diagram of another in-memory computing system according to an exemplary embodiment of this application is shown.

[0022] Figure 3 A schematic diagram of a memory computing device according to an exemplary embodiment of this application is shown.

[0023] Figure 4 A schematic diagram of another memory computing device according to an exemplary embodiment of this application is shown.

[0024] Figure 5 A schematic diagram of another memory computing device according to an exemplary embodiment of this application is shown.

[0025] Figure 6 A schematic diagram of another memory computing device according to an exemplary embodiment of this application is shown.

[0026] Figure 7 A schematic diagram of another memory computing device according to an exemplary embodiment of this application is shown.

[0027] Figure 8 A schematic diagram of another memory computing device according to an exemplary embodiment of this application is shown.

[0028] Figure 9 A schematic diagram of another memory computing device according to an exemplary embodiment of this application is shown.

[0029] Figure 10 A schematic diagram of a control device according to an exemplary embodiment of this application is shown.

[0030] Figure 11 A schematic diagram of another in-memory computing system according to an exemplary embodiment of this application is shown.

[0031] Figure 12 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown. Detailed Implementation

[0032] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0033] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0034] The business scenarios described in the embodiments of this application are for illustrative purposes only and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0035] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other components, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components.

[0036] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0037] In in-memory computing technology, storage and computation (or operation) are physically integrated. This physical integration includes, for example, integrating storage and computation components close together through processes such as packaging; integrating processing circuits with processing capabilities within the memory to achieve integrated processing functions within the memory; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. According to some embodiments, an in-memory computing system may include a storage circuit and a processing circuit (or control circuit); the storage circuit is used to store data; the processing circuit (or control circuit) is used to control the operation of the storage circuit, such as controlling the writing, reading, computation, or sensing of computation results. For example, the processing circuit can call up data stored in the storage circuit and perform computation based on the called data; or the processing circuit can control the computation of the storage circuit; or the processing circuit can be used to read or sense the computation results of the storage circuit and process the computation results. This application does not limit the type of memory, which may include, but is not limited to, non-volatile memory (NVM) or volatile memory (VM). Volatile memory may include, but is not limited to, static random access memory (SRAM); non-volatile memory may include, but is not limited to, flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric memory (FeRAM), or phase change memory (PCM).

[0038] For ease of understanding, Figure 1 A schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown. This in-memory computing system is described as an example of implementing in-memory computation using memory as a carrier.

[0039] like Figure 1As shown, the in-memory computing system 100 may include a storage circuit (or in-memory computing circuit) 110 and a control circuit 120. The storage circuit 110 can be used to store weight data (also called weights); the control circuit 120 can be used to control the operating state of the storage circuit 110. The operating states of the storage circuit 110 include, for example, a programming state and a calculation state. In the programming state, weight data is written into the storage circuit 110. In the calculation state, the storage circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit 110 can store multiple weight data, which can be equivalent to at least one vector (or matrix). The storage circuit 110 can store weight data in units of storage cells, which can also be called storage units or storage structures. For example, the storage circuit 110 includes a storage cell array, which includes multiple storage cells arranged in an array.

[0040] Storage cells can utilize the conduction capabilities of semiconductor devices, such as electrical conductance or transconductance, to store weight data. For example, a storage cell can include a resistive storage device or a transistor storage device. For instance, weight data can be stored by controlling the conductance of a resistive storage device, or by controlling the transconductance of a transistor storage device. Alternatively, a storage cell can also utilize a capacitor to store weight data.

[0041] The storage circuit 110 can perform calculations in groups. For example, a storage cell array includes at least one storage cell group, and each storage cell group includes multiple storage cells that can store multiple weight data. These multiple weight data can be equivalent to a first data vector (or a first data matrix). In programming mode, the weight data is written into the storage cells, which is equivalent to writing the first data vector (or the first data matrix) into the storage cell group in the storage cell array. In calculation mode, the storage circuit 110 receives an input signal, and the conduction capability of the storage cells can change the input signal to obtain an output signal. Accumulating the output signals in the storage cell group can achieve an equivalent multiplication operation. The storage cell array includes one-dimensional arrays, two-dimensional arrays, or three-dimensional arrays, etc., and the storage cell group includes multiple storage cells located in the same row or column, or multiple storage cells located in multiple rows or columns, etc. These multiple storage cells can output their output signals collinearly.

[0042] In some possible embodiments, the in-memory computing system 100 may further include an input circuit 130 and an output circuit 140. The control circuit 120 may, based on the input data D1, control the input circuit 130 to provide at least one input signal Sin to the storage circuit 110; the storage circuit 110 may convert the received input signal Sin into an output signal Sout based on weight data; the control circuit 120 may control the output circuit 140 to convert the output signal Sout into output data D2 for output. The at least one input signal may be equivalent to a second data vector (or a second data matrix), and the output data D2 may be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0043] As an example, Figure 2 A schematic diagram of another in-memory computing system according to an exemplary embodiment of this application is shown.

[0044] like Figure 2 As shown, the in-memory computing system 200 includes one or more memory cell arrays 210. The memory cell array 210 includes multiple memory cells S. ij ,in, , Where m is the number of rows in the storage cell array, and n is the number of columns in the storage cell array. Storage cell S ij It can store weight data W ij When the memory cell array 210 is in the programming state, memory cell S ij The conduction capability can be controlled based on weight data to achieve a target state, thereby achieving the storage of weight data. When the storage cell array 210 is in the calculation state, it can be controlled through storage cell S. ij The input terminal IN is directed to the storage unit S ij Provide an input signal, such as an input voltage V i Storage unit S ij The output terminal OUT outputs its output signal, such as the output current. Multiple memory cells (e.g., S...) 1j -S mj The output terminals of the memory can be collinear. According to Kirchhoff's laws, the output signals of multiple memory cells are accumulated to obtain the output signal I. j Satisfy the following formula:

[0045] .

[0046] In some possible embodiments, the input data includes digital input signals, such as the input signal V of the storage cell array 210. iThe input signal may include an analog signal. Input circuitry 230 may include, for example, a digital-to-analog converter (DAC) to convert the digital signal into an analog signal for supply to memory cell array 210. In some possible embodiments, the input signal to memory cell array 210 may include a digital signal, represented by waveform characteristics such as pulse width, amplitude, or area. Input circuitry 230 may adjust the waveform of the signal based on the input data to obtain the input signal, which is then provided to memory cell array 210.

[0047] In some possible embodiments, the input circuit includes an interface circuit that can convert the signal format of the digital signal into an input signal Sin that can be received and recognized by the storage circuit. Alternatively, the interface circuit can be a storage protocol interface that converts the digital signal into an input signal Sin with the signal format defined by the storage protocol. For example, the interface circuit can be a Negative-AND flash (NAND flash) interface that can convert received data or instructions according to the Open NAND Flash Interface (ONFI) protocol. For example, the control circuit can control the interface circuit to convert the digital signal into an input signal Sin with the format specified by the ONFI protocol, thereby enabling the storage circuit to receive and recognize the input signal Sin.

[0048] In some possible embodiments, the output circuit 240 may include at least one conversion circuit for converting the output signal of the memory cell array 210 and outputting it to a subsequent circuit. This conversion may include one or more signal type conversions, signal magnitude conversions, such as current-to-voltage conversion, analog-to-digital conversion, amplification, etc. For example, the output circuit 240 may include a first conversion circuit 241 for performing a first conversion on the output signal of the memory cell array 210. For instance, if the output signal of the memory cell array 210 includes a current signal, the first conversion circuit 241 can convert the current signal into a voltage signal. Alternatively, the output circuit 240 may include a second conversion circuit 242 for performing a second conversion on the output signal of the memory cell array 210. The second conversion may be implemented, for example, through a sampling circuit. Optionally, the signal converted by the first conversion circuit 241 may be further provided to the second conversion circuit 242 for a second conversion. For example, the first conversion circuit 241 may include a transimpedance amplifier (TIA) to convert a current signal into a voltage signal; the second conversion circuit 242 may include an analog-to-digital converter (ADC) to convert the analog signal into a digital signal for subsequent circuitry. Alternatively, the output circuit may include a sense amplifier (SA) that can sense, amplify, or process the signal obtained from the memory cell array 210 or the first conversion circuit 241. Furthermore, in Figure 2 In the example, the in-memory computing system 200 may further include a control circuit 220, which can be used to control the memory cells S in the memory cell array 210. ij The running state, such as the programming state and computation state mentioned above.

[0049] Figure 2 This is merely an example illustrating a connection method of storage cells in a storage cell array 210, except... Figure 2Besides the connection method shown, other connection methods can also be used. For example, the input terminals of the memory cells can be connected collinearly by columns, and the output terminals of the memory cells can be connected collinearly by rows. Furthermore, the input terminals of the memory cells can include the gate of a transistor memory device, or the input terminals of the memory cells can include the source or drain of a transistor memory device; this application does not limit this. This application also does not limit the type of memory cell; for example, the memory cell includes a floating gate transistor (FGT), a memristor, a magnetic tunnel junction (MTJ), or a phase-change structure. Furthermore, the memory cell can include multiple transistors; for example, the memory cell can include a first transistor and a second transistor, where the gate of one transistor is connected to the source or drain of the other transistor, and the charge stored at the gate can be used to characterize weight data. Optionally, the gate can also be connected to a capacitor to increase the stability and duration of the stored charge.

[0050] Non-in-memory computing systems (such as CPUs (central processing units), MCUs (microcontroller units), and GPUs (graphics processing units)) include computing circuits and storage circuits, which differ in structure. For example, a CPU's computing circuits use CMOS (complementary metal-oxide-semiconductor) logic arrays, while its storage circuits use SRAM, DRAM, etc. Therefore, computing circuits and storage circuits each have separate physical locations and peripheral circuits.

[0051] In-memory computing systems can include storage devices that store weight data used for calculations. In-memory computing systems can utilize these storage devices for computation. In addition to weight data, the electronic devices housing in-memory computing systems often also store non-weight data. Due to their different applications, these electronic devices often require additional storage for this non-weight data, increasing the hardware cost of the electronic devices.

[0052] In view of this, this application provides a storage circuit, a storage computing device, a storage computing system, and an electronic device that stores weighted data and non-weighted data in the same storage cell array, so that the storage cell array can both store non-weighted data and perform storage computing, thereby improving the hardware utilization of the storage circuit, enhancing the flexibility of the storage circuit's usage, and enabling the storage circuit to be applicable to a variety of application scenarios.

[0053] According to embodiments of this application, the storage circuit for an in-memory computing system may include a storage cell array, which may include a first storage area and a second storage area. The first storage area is used to store weight data, and the second storage area is used to store non-weight data. The first storage area can be used for calculations based on the weight data and input data. The calculation method can be referred to... Figure 1 and Figure 2 The specific implementation examples are not described in detail here.

[0054] In the storage circuit provided in this application embodiment, the storage cell array includes both a region for storing weight data and a region for storing non-weight data. This allows the storage cell array to store non-weight data and perform in-memory processing, thereby improving the storage space utilization rate of the storage circuit, enhancing the flexibility of its usage, and making it suitable for various application scenarios. This, in turn, helps reduce the hardware cost of the electronic device in which the storage circuit is located. Furthermore, this application embodiment adopts a storage method that partitions weight data and non-weight data on the same array, which is beneficial for partitioning and managing different data. Moreover, this application embodiment can apply existing peripheral circuits of the in-memory computing system to the storage of non-weight data. Compared to an in-memory computing system that only stores weight data, this application embodiment does not introduce additional peripheral circuits, thus balancing the hardware overhead of the in-memory computing system.

[0055] According to some embodiments, non-weight data may include management data of the in-memory computing system. For example, management data can be used to manage the operation of the in-memory computing system. In this implementation, management data and weight data used to manage the in-memory computing system are stored in the same storage array within the in-memory computing system. This allows operations on the in-memory computing system to be centralized within the system, reducing the frequency of accessing other storage systems during invocations. For example, during this period, it is unnecessary to access other storage systems to obtain management data. Therefore, this implementation simplifies the operational control of the in-memory computing system and reduces its dependence on other hardware (such as other storage systems).

[0056] In this embodiment, the management data can have various possible types. For example, management data may include one or more of the following: status data, startup parameters, configuration parameters, address parameters, and storage parameters.

[0057] In some embodiments, state data is used to manage the state of the memory circuit. For example, state data may include the damaged state of a memory cell or set of memory cells in the memory circuit. As another example, state data may include the erased state of a memory cell or set of memory cells. Yet another example, state data may include both the erased and damaged states of a memory cell or set of memory cells. Exemplarily, a set of memory cells may be a block, a plane, or other types of memory cell collections; this embodiment of the application does not limit this.

[0058] In some embodiments, startup parameters can be used to control the startup of the in-memory computing system.

[0059] In some embodiments, configuration parameters can be used to configure the in-memory computing system. For example, configuration information can be used to adjust the circuitry or modules of the in-memory computing system. Address parameters can be used to manage the addresses of the storage circuitry. For example, address parameters may include address translation tables for storage pages, management tables for storage banks, etc.

[0060] In some embodiments, stored-value parameters can be used to control the programming or reading of weight data or the calculation of the stored-value system. For example, stored-value parameters may include address translation tables, management tables, etc., that are read and calculated.

[0061] According to some embodiments, management data can be stored in multiple storage areas. Management data can be stored in two or more different storage areas of the storage cell array. For example, two storage areas within these multiple storage areas can store the same management data. One or more of status data, startup parameters, configuration parameters, address parameters, and computational parameters can be stored in multiple storage areas. Thus, if the management data in one storage area is corrupted, the management data in other storage areas can still be read correctly, thereby ensuring the reliability of the management data. For example, two storage areas within these multiple storage areas can store different management data. This allows for more flexible configuration of the storage areas used to store management data. For instance, the storage area storing management data can flexibly change at least one of its location and size depending on the amount of management data and the layout of the weight data on the storage cell array.

[0062] According to some embodiments, weighted data and unweighted data can be stored in multiple storage cell arrays, and different storage cell arrays can be written to or read from in parallel. For example, weighted data and unweighted data can have the same or different degrees of parallelism. The degree of parallelism for weighted data includes the number of storage cell arrays storing weighted data, and the degree of parallelism for unweighted data includes the number of storage cell arrays storing unweighted data.

[0063] In some embodiments, the parallelism of using weighted data and unweighted data can be the same. This simplifies the management of both weighted and unweighted data.

[0064] In some implementations, the parallelism used for weight data can be greater than that used for non-weight data. This improves the efficiency of reading or calculating weight data when using large-scale models in in-memory computing systems. Meanwhile, smaller-scale non-weight data can be used with less parallelism, thus reducing storage resource consumption.

[0065] Figure 3 A schematic diagram of a memory computing device according to an exemplary embodiment of this application is shown.

[0066] like Figure 3 As shown, the in-memory computing device 300 may include a storage circuit. The storage circuit may include a storage cell array 300, which includes a first storage area 311 and a second storage area 312. The first storage area 311 is used to store weight data, and the second storage area 312 is used to store non-weight data. The storage cell array 310 may include a storage cell array, which may include the first storage area 311 and the second storage area 312. The storage cell array may include storage cells arranged in an array along a first direction and a second direction. Figure 3 In this context, the first direction may include the row direction of the storage cell array, and the second direction may include the column direction of the storage cell array; alternatively, the first direction may include the column direction of the storage cell array, and the second direction may include the row direction of the storage cell array. In the following description, the case where the first direction includes the row direction and the second direction includes the column direction will be used.

[0067] According to some embodiments, the in-memory computing device 300 may further include an input circuit 320 connected to the storage cell array 310. The first storage area 311 and the second storage area 312 may share the output circuit 330. This allows the storage cell array 310 to both store non-weighted data and perform in-memory processing, thereby improving the storage space utilization of the storage circuit, enhancing the flexibility of its usage, and enabling it to be applicable to various application scenarios, thus reducing the hardware cost of the electronic device containing the storage circuit. Furthermore, the embodiments of this application employ a partitioned storage method for weighted data and non-weighted data on the same array, which facilitates partitioned management of different data. In addition, the regions storing weighted data and non-weighted data share the output circuit in the embodiments of this application, thus balancing the hardware overhead of the in-memory computing device 300.

[0068] According to some embodiments, the in-memory computing device 300 may further include an input circuit 320 connected to the memory cell array 310. The first storage region 311 and the second storage region 312 may share the input circuit 320. In this way, the region storing weight data and the region storing non-weight data in the storage circuit share the input circuit, which can take into account the hardware overhead of the in-memory computing device 300.

[0069] During calculation, the input circuit 320 can provide an input signal to the memory cell array 310, for example, to the first memory region 311. The memory cell array 310 can then output an output signal calculated from the input signal and the stored weight data, as can be seen from [reference needed]. Figure 1 and Figure 2 Description of input circuits 130 and 230. During reading, input circuit 320 can provide an input signal to the memory cell array 310 to read data stored in the memory cell array 310, for example, reading weight data stored in the first memory area 311 or non-weight data stored in the second memory area 312. During programming, input circuit 320 can provide write data to the memory cell array 310, for example, providing write data of weight data to the first memory area 311 or write data of non-weight data to the second memory area 312.

[0070] The input circuit 320 may include multiple input channels arranged along the second direction. The input channels of the input circuit 320 can provide input signals or write data to the memory cells connected to them in the first direction through input lines extending along the first direction.

[0071] Output circuit 330 can convert the output signal of memory cell array 310 or its included memory cell array and output it to subsequent circuits, as shown in the following example. Figure 1 and Figure 2 Description of output circuits 140 and 240. During calculation, the output signal of the memory cell array 310 or the memory cell array may include the result signal calculated based on the weight data; during reading, the output signal of the memory cell array 310 or the memory cell array may include the read signal of the weight data or non-weight data; during programming, the output signal of the memory cell array 310 or the memory cell array may include the read signal of the written weight data or non-weight data, which can be used to verify whether the programming is successful.

[0072] The output circuit 330 may include multiple output channels arranged along the first direction. The output channels of the output circuit 330 can output the output signals of the memory cells or memory cell groups connected to them in the second direction through output lines extending along the second direction.

[0073] According to some embodiments, the first storage region 311 and the second storage region 312 may be located in two adjacent regions of the storage cell array 310 in a second direction. (Refer to...) Figure 3 The second storage region 312 may be located between the first storage region 311 and the output circuit 330. The first storage region 311 may be farther away from the output circuit 330 than the second storage region 312. However, the embodiments are not limited to this; the first storage region 311 may be located between the second storage region 312 and the output circuit 330. The first storage region 311 may be closer to the output circuit 330 than the second storage region 312.

[0074] According to some embodiments, the first storage region 311 and the second storage region 312 may have the same size in a first direction and the same or different sizes in a second direction. Figure 4 For example:

[0075] Figure 4 A schematic diagram of another memory computing device according to an exemplary embodiment of this application is shown.

[0076] like Figure 4 As shown, the in-memory computing device 400 may include a storage circuit. The storage circuit includes a storage cell array 410, such as... Figure 4 As shown, the memory cell array 410 may include a first storage area 411 and a second storage area 412. The first storage area 411 is used to store weight data, and the second storage area 412 is used to store non-weight data. The memory cell array 410 may include a memory cell array, which may include the first storage area 411 and the second storage area 412. The in-memory computing device 400 may also include an input circuit 420 or an output circuit 430. A description of the in-memory computing device 400 can be found in [reference needed]. Figure 3 The corresponding description of the in-memory computing device 300. The difference between the in-memory computing device 400 and the in-memory computing device 300 includes: the regions of the first storage area 411 and the second storage area 411 in the storage cell array 410.

[0077] Compared to the first storage region 311, the first storage region 411 can be located in a smaller area within the storage circuit. For example, refer to... Figure 3 and Figure 4 The first storage region 411 may be smaller than the first storage region 311 in the second direction. Compared to the second storage region 312, the second storage region 412 may occupy a larger area in the storage circuit. For example, referring to… Figure 3 and Figure 4The second storage region 412 can be larger than the second storage region 312 in the second direction. The first storage region 411 can have fewer input channels connected to the corresponding input circuitry than the first storage region 311. The second storage region 412 can have more input channels connected to the corresponding input circuitry than the second storage region 312.

[0078] However, the embodiments are not limited to this. Compared to the first storage region 311, the first storage region 411 may be located in a larger area of ​​the storage circuit. For example, the first storage region 411 may be larger than the first storage region 311 in the second direction. Compared to the second storage region 312, the second storage region 412 may be located in a smaller area of ​​the storage circuit. For example, the second storage region 412 may be smaller than the second storage region 312 in the second direction. The first storage region 411 may correspond to more input channels connected to the input circuit than the first storage region 311. The second storage region 412 may correspond to fewer input channels connected to the input circuit than the second storage region 312.

[0079] According to some embodiments, the first storage region and the second storage region may have the same or different sizes in the first direction, and the same or different sizes in the second direction. Figure 5 For example:

[0080] Figure 5 A schematic diagram of another memory computing device according to an exemplary embodiment of this application is shown.

[0081] like Figure 5 As shown, the in-memory computing device 500 may include a storage circuit. The storage circuit includes a storage cell array 510, such as... Figure 5 As shown, the storage cell array 510 may include a first storage area 511 and a second storage area 512. The first storage area 511 is used to store weight data, and the second storage area 512 is used to store non-weight data. The storage cell array 510 may include a storage cell array, which may include the first storage area 511 and the second storage area 512. The in-memory computing device 500 may also include an input circuit 520 or an output circuit 530. A description of the in-memory computing device 500 can be found in [reference needed]. Figure 3 The corresponding description of the in-memory computing device 300. The difference between the in-memory computing device 500 and the in-memory computing device 300 includes: the areas of the first storage region 511 and the second storage region 511 in the storage cell array 510.

[0082] Compared to the second storage region 312, the second storage region 512 can be located in a smaller area of ​​the storage circuit. For example, refer to... Figure 3 and Figure 5The second storage region 512 may be smaller than the second storage region 312 in the first direction. Compared to the first storage region 311, the first storage region 511 may be located in a larger area of ​​the storage circuit. For example, refer to... Figure 3 and Figure 5 The first storage region 511 may also include a region adjacent to the second storage region 512 in the first direction. The second storage region 512 may have fewer input channels and output channels than the second storage region 312.

[0083] According to some embodiments, the sizes of the first storage region and the second storage region are variable in the first and second directions. For example, when the weighted data increases and the non-weighted data decreases, the size of the first storage region in the first and / or second directions can be increased accordingly, while the size of the second storage region in the first and / or second directions can be decreased.

[0084] According to some embodiments, the storage circuit may also include a third storage area, which may be used for storing weight data or for purposes other than non-weight data, such as being used as a dummy storage area.

[0085] According to some embodiments, the size of the second storage area is fixed, and the size of the second storage area is not less than the known amount of non-weighted data. For example, the second storage area can be used to store specific types of non-weighted data, such as the management data of the aforementioned storage system. The amount of such data is known, therefore the required storage area size of the second storage area is fixed. In the embodiments of this application, the size of the second storage area is fixed, and the size of the first storage area can be adapted to the size of the second storage area, which is beneficial to improving the storage reliability of the storage circuit for non-weighted data.

[0086] For example, the second storage region may include a subarray of the storage cell array, and the first storage region may include the remaining array of the storage cell array. Alternatively, the first and third storage regions may include the remaining array of the storage cell array. For instance, the storage cell array of the storage circuit may include m rows and n columns of storage cells, and the first subarray may include storage cells in rows a1 to a2 and columns b1 to b2 of m rows and n columns, where m, n, a1, a2, b1, and b2 are all positive integers, 1 ≤ a1 ≤ a2 ≤ m, 1 ≤ b1 ≤ b2 ≤ n, and the values ​​of a1, a2, b1, and b2 are such that the storage cell array includes the remaining array. For example, 1 < a1 < a2 = m, 1 = b1 < b2 ≤ n.

[0087] For example, the second storage region may be a non-contiguous region on the storage cell array. For instance, the second storage region may include multiple subarrays of the storage cell array. The first storage region may include the remaining array of the storage cell array. Alternatively, the first and third storage regions may include the remaining array of the storage cell array.

[0088] According to some embodiments, the first storage region is located in the first region of the storage circuit at a first time and in the second region of the storage circuit at a second time, and the first region and the second region are different. The first region and the second region may partially overlap or be completely separated; this application embodiment does not impose any limitations on this. In this way, the area of ​​the first storage region can dynamically change based on the storage requirements of the weight data, thereby flexibly meeting the storage requirements of the in-memory computing system for the weight data.

[0089] For example, the first storage area is located at the first time. Figure 4 The region of the first storage area 411 of the storage cell array 410 in the second time is located in Figure 3 The region of the first storage area 311 of the storage cell array 310 in the memory. For example, the first storage area is located in the first time... Figure 5 The region of the first storage area 511 of the storage cell array 510 in the second time is located in Figure 4 The area of ​​the first storage region 411 of the storage cell array 410 in the memory.

[0090] According to some embodiments, the second storage region is located in the third region of the storage circuit at a third time and in the fourth region of the storage circuit at a fourth time, and the third and fourth regions are different. The third and fourth regions may partially overlap or be completely separated; this embodiment does not impose any limitations on this. Thus, the area of ​​the second storage region can dynamically change based on the storage requirements of non-weighted data, thereby flexibly meeting the storage needs of the in-memory computing system for non-weighted data.

[0091] For example, the second storage area is located at the third time. Figure 4 The region of the second storage area 412 of the storage cell array 410 in the fourth time is located in Figure 5 The region of the second storage region 512 in the storage cell array 510. For example, the second storage region is located at a third time... Figure 3 The region of the second storage area 312 of the storage cell array 310 in the fourth time is located in Figure 5 The area of ​​the second storage region 512 of the storage cell array 510 in the memory.

[0092] According to some embodiments, the first storage region and the second storage region are located in the fifth and sixth regions of the storage circuit at the fifth time, respectively, and in the seventh and eighth regions of the storage circuit at the sixth time, respectively. The fifth and seventh regions are different, and the sixth and eighth regions are different.

[0093] According to some embodiments, the sizes of the first and second storage areas can be dynamically adjusted based on the storage requirements of weighted and unweighted data. The area division of the storage cell array can be adjusted row by row; for example, one or more rows of storage cells included in the first storage area can be adjusted to be included in the second storage area. For instance, the first storage area can be adjusted from storage area 311 to storage area 411, and the second storage area can be adjusted from storage area 312 to storage area 412.

[0094] According to some embodiments, the region division of the storage cell array can be adjusted in conjunction with columns. For example, one or more rows of storage cells included in the second storage region can be adjusted to be included in the first storage region. For example, the first storage region is adjusted from the region of storage region 311 to the region of storage region 511, and the second storage region is adjusted from the region of storage region 312 to the region of storage region 512.

[0095] According to some embodiments, the input channels activated by the input circuit can be determined based on the operating state of the in-memory computing system and the locations of the first and second storage regions. In this way, the input channels activated by the input circuit can be selected according to the operating state. On the one hand, this reduces the number of channels that need to be activated when not all input channels need to be activated, thus lowering power consumption; on the other hand, it avoids interference from input channels that do not need to be activated.

[0096] According to some embodiments, the channel activated by the output circuit can be determined based on the operating state of the in-memory computing system and the locations of the first and second storage regions. In this way, the output channel activated by the output circuit can be selected according to the operating state, reducing the number of output channels that need to be activated when not all output channels need to be activated, thus lowering power consumption. Furthermore, it can prevent unnecessary output channels from interfering with the operation.

[0097] According to some embodiments, when the in-memory computing system is in a programming state, the input channels of the input circuits connected to the first and second storage areas can both be activated. This allows for simultaneous programming of both the first and second storage areas, which improves the overall writing efficiency of weighted and unweighted data.

[0098] According to some embodiments, when the in-memory computing system is in a programming state, the input channels of the input circuits connected to the first and second storage areas can be started in a time-sharing manner. At a first time, the input channel corresponding to the first storage area can be started, and at a second time, which does not overlap with the first time, the input channel corresponding to the second storage area can be started. In some cases, the value ranges of weighted data and unweighted data differ significantly, and the write time difference exceeds a threshold time. Therefore, writing to the first and second storage areas can be done in a time-sharing manner, thereby avoiding the situation where slower-writing data drags down the write efficiency of faster-writing data when writing simultaneously.

[0099] Figure 6 A schematic diagram of another memory computing device according to an exemplary embodiment of this application is shown.

[0100] like Figure 6 As shown, the in-memory computing device 600 may include a storage circuit 610 and an input circuit 620. The storage circuit 610 may include a first storage area 611 and a second storage area 612. The first storage area 611 is used to store weight data, and the second storage area 612 is used to store non-weight data. The storage circuit 610 may include a storage cell array, which may include the first storage area 611 and the second storage area 612. The input circuit 620 may include N input channels 621 and M input channels 622, where M and N are both integers greater than or equal to 1. The N input channels 621 correspond to the first storage area 611, and the M input channels 622 correspond to the second storage area 612. The in-memory computing device 600 may also include an output circuit 630. The output circuit 630 may include output channels, which are connected to the first storage area 611 and the second storage area 612 respectively.

[0101] According to some embodiments, input channels 621 and 622 can be activated when the in-memory computing system is in a programming state. According to some embodiments, input channels 621 and 622 can be activated in a time-sharing manner when the in-memory computing system is in a programming state.

[0102] According to some embodiments, refer to Figure 6 When the in-memory computing system is in computational state, input channel 621 is activated, and the storage cells in the first storage area 611 can participate in the computation. Additionally, the output channel of output circuit 630 can be activated.

[0103] According to some embodiments, refer to Figure 6 When the memory computing system is in read mode, input channel 621 or 622 is activated, and the memory cells in the first memory area 611 or the second memory area 612 can be read. Additionally, the output channel of output circuit 630 can be activated.

[0104] Figure 7 A schematic diagram of another memory computing device according to an exemplary embodiment of this application is shown.

[0105] like Figure 7 As shown, the in-memory computing device 700 may include a storage circuit 710 and an input circuit 720. The storage circuit 710 may include a first storage region 711 and a second storage region 712. The first storage region 711 is used to store weight data, and the second storage region 712 is used to store non-weight data. The storage circuit 710 may include a storage cell array, which may include the first storage region 711 and the second storage region 712. The first storage region 711 may include a first sub-region 7111, a second sub-region 7112, and a third sub-region 7113. The first sub-region 7111 may be aligned with the second storage region 712 in a second direction, and the third sub-region 7113 may be aligned with the second storage region 712 in a first direction. The second sub-region 7112 may be aligned with the first sub-region 7111 in the first direction and with the third sub-region 7113 in the second direction. The input circuit 720 may include N input channels 721 and M input channels 722, where M and N are both integers greater than or equal to 1. N input channels 721 can be connected to the first storage area 711, and M input channels 722 can be connected to the first storage area 711 and the second storage area 712. N input channels 721 can also be connected to the first sub-region 7111 and the second sub-region 7112. M input channels 722 can be connected to the second storage area 712 and the third sub-region 7113. The memory computing device 700 may further include an output circuit 730. The output circuit 730 may include E output channels 731 and F output channels 732, where E and F are integers greater than or equal to 1. E output channels 731 can be connected to the first storage area 711 and the second storage area 712, and F output channels 722 can be connected to the first storage area 711. E output channels 731 can be connected to the first sub-region 7111 and the second storage area 712. F output channels 732 can be connected to the second sub-region 7112 and the third sub-region 7113.

[0106] When the in-memory computing system is in the programming state, input channels 721 and 722 can be started. According to some embodiments, when the in-memory computing system is in the programming state, input channels 721 and 722 can be started in a time-sharing manner. During time-sharing startup, at least one of the first sub-region 7111 and the second sub-region 7112, as well as at least one of the second storage region 712 and the third sub-region 7113, can be written to in a time-sharing manner. For example, during time-sharing startup, the first sub-region 7111 and the second storage region 712 can be written to in a time-sharing manner.

[0107] According to some embodiments, when the in-memory computing system is in a computing state, the first input channel of the input circuit is activated, and the first input channel is connected to the memory cell in the first storage area that participates in the computing. In this way, the input channel activated by the input circuit can be selected according to the computing state. On the one hand, it can reduce the number of input channels that need to be activated when it is not necessary to activate all input channels, thereby reducing power consumption; on the other hand, it can avoid interference from input channels that do not need to be activated.

[0108] According to some embodiments, refer to Figure 7 When the in-memory computing system is in computation state, at least one of input channels 721 and 722 can be activated, and the storage units of at least one of the first sub-regions 7111, the second sub-region 7112, and the third sub-region 7113 can participate in the computation. For example, when the in-memory computing system is in computation state, input channel 721 can be activated, and the storage units of at least one of the first sub-regions 7111 and the second sub-region 7112 can participate in the computation. When the storage units of the first sub-region 7111 participate in the computation, output channel 731 is activated. When the storage units of the second sub-region 7112 participate in the computation, output channel 732 is activated. When the storage units of both the first sub-region 7111 and the second sub-region 7112 participate in the computation, both output channels 731 and 732 are activated. As another example, when the in-memory computing system is in computation state, input channel 722 can be activated, the storage units of the third sub-region 7113 can participate in the computation, and output channel 732 can be activated. For example, when the in-memory computing system is in the computing state, input channels 721 and 722 can both be started, the storage units of the second sub-region 7112 and the third sub-region 7113 can both participate in the computing, and output channel 732 can be started.

[0109] According to some embodiments, when the in-memory computing system is in read mode, the second input channel of the input circuit is activated. The second input channel corresponds to the memory cell to be read in the first or second memory area. In this way, the input channel activated by the input circuit can be selected according to the read state, reducing the number of input channels activated when not all input channels need to be activated, thus lowering power consumption.

[0110] According to some embodiments, refer to Figure 7 When the in-memory computing system is in read mode, for example, input channel 722 is activated, and the memory cells in the second memory area 712 can be read; additionally, output channel 731 can be activated. As another example, input channel 722 is activated, and the memory cells in the third sub-area 712 can be read; additionally, output channel 732 can be activated. As yet another example, input channel 721 is activated, and the memory cells in the first sub-area 7111 and the second sub-area 7112 can be read; output channels 731 and 732 can be activated to achieve the read operation.

[0111] According to some embodiments, the output terminal of the first storage cell in the first storage region and the output terminal of the second storage cell in the second storage region can be connected to the same output line, while the input terminal of the first storage cell in the first storage region and the input terminal of the second storage cell in the second storage region can be connected to different input lines. In this way, the storage cells in the first and second storage regions can share the output line, achieving the storage of both weighted and unweighted data while also considering the hardware overhead of the in-memory computing system.

[0112] In addition, the storage cells of the first and second storage areas share the same output line, and thus can share the same peripheral circuits, such as the output circuit. In this way, there is no need to increase the hardware overhead of the in-memory computing system on the peripheral circuits.

[0113] Figure 8 A schematic diagram of another memory computing device according to an exemplary embodiment of this application is shown.

[0114] The in-memory computing device 800 may include storage circuitry. The storage circuitry may include a storage cell array 810. The storage cell array 810 may include a first storage region 811 and a second storage region 812. The storage cell array 810 may include a plurality of storage cells S. ij ,in, , Storage unit S ij It includes an input terminal IN and an output terminal OUT. When the first direction includes the row direction and the second direction includes the column direction, m is the number of rows in the storage cell array and n is the number of columns in the storage cell array. When the first direction includes the column direction and the second direction includes the row direction, m is the number of columns in the storage cell array and n is the number of rows in the storage cell array. The first storage cell can be a storage cell in the first storage area 811, and the second storage cell can be a storage cell in the second storage area 812.

[0115] As mentioned above, the output circuit may include multiple output channels. For example, an output channel may include a sub-output circuit, which can be connected to the output line of the storage circuit and can read the signal on the output line. Figure 8 For example, the memory computing device 800 may also include an output circuit 830. The output circuit 830 may include a sub-output circuit 831. The first memory unit and the second memory unit may share the same sub-output circuit 831; for example, memory unit S... 11 and storage unit S m1 via the same output line L o Output signal. For example, such as... Figure 8 As shown, output line L o Connected to sub-output circuit 831, storage unit S 11 and storage unit S mThey can share the same sub-output circuit 831.

[0116] Reference Figure 8 The number of sub-output circuits 831 can be the same as the number of output lines; however, the embodiments are not limited to this. Multiple output lines can share a single sub-output circuit 831 via a multiplexing circuit, such as a multiplexer. Since the hardware overhead of the output circuit is greater than that of the multiplexing circuit, reducing the number of sub-output circuits through multiplexing circuits can reduce the number of output circuits, thereby reducing the hardware overhead of the in-memory computing system.

[0117] According to some embodiments, the first storage region 811 and the second storage region 812 can be programmed in the same programming process. This improves the programming efficiency of the storage circuit.

[0118] During programming, the memory cell array can be synchronously programmed in either a first direction or a second direction. When the memory cell array is synchronously programmed in the first direction, memory cells connected to the same input line in the first direction can be programmed synchronously. Memory cells can receive different programming signals via different programming lines (not shown). In this way, after each programming step, the programmed data can be read out through different output lines, allowing for earlier verification of the programming status and adjustment of programming parameters as needed based on the programming results.

[0119] When the memory cell array is synchronously programmed in the second direction, memory cells connected to the same output line in the second direction can be programmed synchronously. Memory cells can receive different programming signals via different input lines. For example, the first and second memory cells can be synchronously programmed via different input lines. This allows for direct programming using the input lines, reducing wiring complexity.

[0120] According to some embodiments, refer to Figure 8 The first storage area 811 may include storage units from row 1 to row 0. The second storage area 812 may include storage units from row 0+1 to row m. The first storage unit and the second storage unit may include any two storage units sharing a common output line in the first storage area 811 and the second storage area 812.

[0121] According to some embodiments, when reading the calculation result of the first storage unit group through the output line connected to the output terminal of the storage unit within the first storage unit group, the second storage unit in the second storage area is turned off. Thus, by turning off the storage unit storing non-weighted data connected to the output line for reading the calculation result, the influence of non-weighted data on the calculation result can be avoided. For example... Figure 8 In the storage unit S 11 When performing calculations, the storage unit S can be turned off.（o+1）1 To storage unit S m1 This is to avoid affecting the calculation results.

[0122] Reference Figure 8 The first storage area 812 includes a group of storage cells, which includes multiple storage cells. The output terminals OUT of the multiple storage cells in the storage cell group are connected to the same output line L. o The input terminal IN is connected to different input lines L. i The group of storage cells containing the first storage cell can be referred to as the first storage cell group.

[0123] According to some embodiments, the input line connected to the second storage unit can input a shutdown signal to the second storage unit or not input any signal to the second storage unit, thereby shutting down the second storage unit.

[0124] As mentioned above, the input circuit can include multiple input / output channels. For example, an input channel can include a sub-input circuit, which can be connected to the input lines of the storage circuit and can input signals to the storage circuit via the input lines. Figure 8 For example, the input circuit 820 includes sub-input circuits 821, and the number of sub-input circuits 821 can be the same as the number of input lines L. i The number is the same, however the embodiments are not limited to this, multiple input lines L i A sub-input circuit 821 can be shared via a multiplexing circuit, for example, via a multiplexer. In this way, since the hardware overhead of the input circuit is greater than that of the multiplexing circuit, the number of sub-input circuits can be reduced by using multiplexing circuits, thereby reducing the number of input circuits and thus reducing the hardware overhead of the in-memory computing system.

[0125] According to some embodiments, the sub-input circuit 821 connected to the second storage unit can input a shutdown signal to the second storage unit or not input any signal to the second storage unit, thereby shutting down the second storage unit.

[0126] According to some embodiments, the input terminal of the third storage cell in the first storage region and the input terminal of the fourth storage cell in the second storage region can be connected to the same input line, and the output terminal of the third storage cell and the output terminal of the fourth storage cell can be connected to different output lines. In this way, the storage cells in the first storage region and the second storage region can share the input line, reducing the hardware overhead of the storage circuit, thereby reducing the hardware overhead of the in-memory computing system.

[0127] In addition, the storage cells of the first and second storage areas share the input line, and thus can share the peripheral circuits, such as the input circuit. In this way, while realizing the storage of weighted data and non-weighted data, the hardware overhead of the storage system is also taken into account.

[0128] Figure 9 A schematic diagram of another memory computing device according to an exemplary embodiment of this application is shown.

[0129] The in-memory computing device 900 may include a storage circuit 910. The storage circuit may include a storage cell array 910. The storage cell array 910 may include a first storage region 911 and a second storage region 912. A third storage cell may be a storage cell in the first storage region 911, and a fourth storage cell may be a storage cell in the second storage region 912. A description of the storage cell array can be found in [reference needed]. Figure 8 Related descriptions.

[0130] The memory storage device 900 may further include an input circuit 920. The input circuit 920 may include a sub-input circuit 921. The third memory cell and the fourth memory cell may share the same sub-input circuit 921, for example, via the same input line L. i They share the same sub-input circuit 921. Additionally, the memory device 900 may also include an output circuit 930. The output circuit 930 may include a sub-output circuit 931.

[0131] According to some embodiments, the third and fourth memory units can be programmed synchronously via the same input line. This allows the programmed data to be read out via different output lines after each programming step, enabling earlier verification of the programming status and adjustment of programming parameters as needed. For example... Figure 9 In the process of storing unit S m1 and S mn When performing calculations, the data can be programmed synchronously through the input line that is connected to both, and the programmed data can be read out through the output lines that are connected to each separately.

[0132] According to some embodiments, refer to Figure 9 The second storage area 912 may include storage cells from row (0+1) to row (m) and column (1) to column (p). , The first storage region 911 may include the remaining storage cells of the storage cell array. The first storage cell and the second storage cell may include any two storage cells sharing a common output line in the first storage region 911 and the second storage region 912. The third storage cell and the fourth storage cell may include any two storage cells sharing a common input line in the first storage region 911 and the second storage region 912.

[0133] According to some embodiments, refer to Figure 9The first storage area 911 includes a first sub-region 9111 and a second sub-region 9112. The first sub-region 9111 and the second storage area 912 share an output line, while the output lines of the second sub-region 9112 and the second storage area 912 are independent. When reading the calculation result of the storage cell group in the second sub-region 9112, the storage cells in the first sub-region 9111 and the second storage area 912 are turned off. In this way, the storage cells in the sub-region storing weight data unrelated to the calculation and the storage area storing non-weight data can be turned off, and the calculation can be performed using the sub-region of the storage area storing weight data, achieving flexible utilization of the storage circuit.

[0134] According to some embodiments, the second sub-region of the first storage region 911 may include a portion of region 9112.

[0135] This application also provides a control device, which can be found in the embodiments of this application. Figure 10 . Figure 10 A schematic diagram of a control device according to an exemplary embodiment of this application is shown. Figure 10 As shown, the control device 1000 includes at least one processing circuit 1010 and an interface circuit 1020. The interface circuit 1020 is used for signal connection with a memory computing device or storage circuit, and the at least one processing circuit 1010 is used for controlling the operating state of the memory computing device or storage circuit. For example, the control device can control a first storage area and a second storage area.

[0136] This application also provides an in-memory computing system, which can be found in the embodiments described above. Figure 11 . Figure 11 A schematic diagram of another in-memory computing system according to an exemplary embodiment of this application is shown. For example... Figure 11 As shown, the in-memory computing system 1100 includes an in-memory computing device 1110 and a control device 1120, the control device 1120 being used to control the operating state of the in-memory computing device. For example, the control device can control a first storage area and a second storage area.

[0137] This application also provides an electronic device, which can be found in [reference 1]. Figure 12 . Figure 12 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown. Figure 12As shown, the electronic device 1200 may include any of the above-mentioned in-memory computing systems 1210 for processing data from the electronic device. The electronic device may also include an input / output device 1220 for receiving user input or outputting processing results. This application does not limit the input and output types; for example, input may include voice input, text input, image input, or video input. Output may include text output, voice output, image output, or video output. The electronic device may also include a processor 1230, which can process data provided to the in-memory computing system 1210 or process the output data of the in-memory computing system 1210. The output of the input / output device 1220 may be based on the output of the processor 1230 or the output of the in-memory computing system 1210.

[0138] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.

[0139] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. A storage circuit, characterized in that, For a storage computing system, the storage circuit includes a storage cell array, the storage cell array includes a first storage area and a second storage area, the first storage area is used to store weight data, the first storage area is used to perform calculations based on the weight data and input data, and the second storage area is used to store non-weight data.

2. The storage circuit according to claim 1, characterized in that, The non-weighted data includes the management data of the in-memory computing system, and the management data includes one or more of the following: Status data is used to manage the status of the storage circuit; Startup parameters are used to control the startup of the in-memory computing system; Configuration parameters are used to configure the in-memory computing system; Address parameters are used to manage the addresses of the storage circuits; Storage parameters are used to control the programming or reading of the weight data or the calculation of the storage system.

3. The storage circuit according to claim 1, characterized in that, The first storage area includes a first storage unit, and the second storage area includes a second storage unit. The first storage unit includes a first input terminal and a first output terminal; The second storage unit includes a second input terminal and a second output terminal; The first output terminal and the second output terminal are connected to the same output line. The first input terminal and the second output terminal are connected to different input lines.

4. The storage circuit according to claim 3, characterized in that, When reading the calculation result of the storage cell group where the first storage cell is located through the same output line, the second storage cell in the second storage area is turned off.

5. The storage circuit according to claim 3 or 4, characterized in that, The first storage unit and the second storage unit are programmed synchronously via the different input lines.

6. The storage circuit according to any one of claims 1 to 4, characterized in that, The first storage area includes a third storage unit, and the second storage area includes a fourth storage unit. The third storage unit includes a third input terminal and a third output terminal; The fourth storage unit includes a fourth input terminal and a fourth output terminal; The third input terminal and the fourth input terminal are connected to the same input line. The third output terminal and the fourth output terminal are connected to different output lines.

7. The storage circuit according to claim 6, characterized in that, The third and fourth storage units are programmed synchronously via the same input line.

8. The storage circuit according to claim 1 or 2, characterized in that, The first storage area includes a first sub-region and a second sub-region. The first sub-region and the second storage area share an output line, while the output lines of the second sub-region and the second storage area are independent. When reading the calculation result of the storage cell group in the second sub-region, the storage cells in the first sub-region and the second storage area are turned off.

9. The storage circuit according to any one of claims 1 to 4, characterized in that, The first storage region is located in the first region of the storage circuit at a first time, and in the second region of the storage circuit at a second time. The first region and the second region are different.

10. The storage circuit according to any one of claims 1 to 4, characterized in that, The second storage region is located in the third region of the storage circuit at a third time and in the fourth region of the storage circuit at a fourth time, wherein the third region and the fourth region are different.

11. A storage computing device, characterized in that, include: The storage circuit as described in any one of claims 1 to 10; An input circuit is connected to the storage circuit and is shared by the first storage area and the second storage area; The output circuit is connected to the storage circuit and is shared by the first storage area and the second storage area.

12. The storage computing device according to claim 11, characterized in that, The channel activated by the input circuit is determined based on the operating state of the in-memory computing system and the positions of the first and second storage areas.

13. An in-memory computing system, characterized in that, include: The memory computing device as described in claim 11 or 12; Control device, used to control the working status of the in-memory computing device.

14. An electronic device, characterized in that, Including the in-memory computing system as described in claim 13.

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