Image sensor

Abstract

This application discloses an image sensor, including a pixel array and a control module. The pixel array includes multiple pixel rows, each containing pixel circuitry. The control module includes an inter-frame switching control circuit. The inter-frame switching control circuit determines, based on exposure information from a first exposure frame and exposure information from a second exposure frame, that there is an overlap between the first and second exposure frames. When this overlap is determined, the control module performs quantization control corresponding to the first exposure frame in each pixel row. Furthermore, during the execution of exposure control corresponding to the second exposure frame in each pixel row, the transmission transistors in the pixel circuitry of that pixel row remain off. Thus, this application enables the image sensor to avoid logic problems during multi-frame quantization, thereby allowing the image sensor to better complete quantization and obtain better images.

Description

Technical Field

[0001] This application relates to the field of image sensor technology, and in particular to an image sensor. Background Technology

[0002] Image sensors are widely used in various electronic devices to capture and identify images of people or scenes, such as video surveillance systems, smartphones, digital cameras, medical devices, drones, AI, and facial recognition. In particular, the rapid development of CMOS (Complementary Metal-Oxide-Semiconductor) image sensor technology has led to higher demands on the output image quality of image sensors. An image sensor is a semiconductor-based sensor that generates electrical signals in response to light. As a crucial component of digital cameras, it converts incident light signals into electrical charges, then into voltage or current signals, and finally outputs the converted electrical signals. An image sensor contains a photosensitive pixel array, which collects light signal information from the image array and converts it into electrical signal data for use by the terminal.

[0003] Image sensors may acquire multiple frames consecutively, potentially resulting in overlapping processing times for two frames (or the first exposure frame and the second exposure frame). This can lead to logic problems when the control module manages the pixel array for quantization corresponding to the first exposure frame and the second exposure frame. For example, two pixel rows might be exposed simultaneously, or the transmission transistor might malfunction during the exposure of the second exposure frame, negatively impacting both the exposure and quantization. Therefore, avoiding these logic problems when the image sensor performs separate quantization of two frames in situations with overlapping processing times is a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0004] The purpose of this application is to provide an image sensor that, when acquiring multiple frames and having overlapping processing times for two frames, avoids logic problems when performing separate quantization of the two frames, thereby enabling the image sensor to better complete quantization and obtain better images.

[0005] To achieve the above objectives:

[0006] This application provides an image sensor, including a pixel array and a control module. The pixel array includes multiple pixel rows including pixel circuits. The control module includes an inter-frame switching control circuit. The inter-frame switching control circuit determines the inter-frame state based on the exposure information of a first exposure frame and the exposure information of a second exposure frame. When the inter-frame state is determined to be an overlap between the first exposure frame and the second exposure frame, the control module is used to complete the quantization control corresponding to the first exposure frame in the pixel row, and during the process of performing the exposure control corresponding to the second exposure frame in the pixel row, the transmission transistor in the pixel circuit of the pixel row is kept off.

[0007] Through the above-described technical solution of this application, when the inter-frame switching control circuit in the control module of the image sensor determines that there is an overlap between the first exposure frame and the second exposure frame, the control module can be used to complete the quantization control corresponding to the first exposure frame in the pixel row. Furthermore, during the process of performing exposure control corresponding to the second exposure frame in the pixel row, the transmission transistor in the pixel circuit of the pixel row is kept off to prevent the aforementioned transmission transistor from being abnormally turned on during the exposure control of the second exposure frame, thereby ensuring that the pixel row can complete the exposure and quantization corresponding to the second exposure frame as designed. Thus, the technical solution of this application enables the image sensor to avoid logic problems when performing separate quantization of two frames in situations where the processing time of two frames overlaps after acquiring multiple frames, thereby allowing the image sensor to better complete quantization and obtain better images. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0009] Figure 1 This is a schematic diagram of the main structural framework of the image sensor provided in the first embodiment of this application.

[0010] Figure 2 This is a schematic diagram of the frame structure of the pixel column in the pixel array of the image sensor provided in the second embodiment of this application.

[0011] Figure 3 This is a schematic diagram of the inter-frame switching control circuit of the example in this application.

[0012] Figure 4 This is a first structural schematic diagram of the signal generation circuit of the example in this application.

[0013] Figure 5 This is a schematic diagram of the second structure of the signal generation circuit in this application.

[0014] Figure 6 This is a circuit diagram of a pixel column in the pixel array of an image sensor, as exemplified in this application.

[0015] Figure 7 This is a waveform diagram of a key node controlling the entry into the charge clearing stage in some implementations of the examples in this application.

[0016] Figure 8 This is a waveform diagram of a key node in the image sensor control entering the charge clearing stage, as provided in the example of this application.

[0017] Figure 9 These are waveform diagrams of key nodes in the implementation of inter-frame control by the control module.

[0018] Figure 10 This is a waveform diagram of a key node in the control module of this application example for inter-frame control.

[0019] Figure 11 This is a waveform diagram of a key node in the inter-frame switching control circuit of the example in this application.

[0020] Figure 12 This is a flowchart illustrating the control method for the image sensor provided in this application.

[0021] The realization of the objectives, functional features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0022] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0023] It should be understood that although the terms first, second, third, etc., may be used in this document to describe various information, elements, units, or modules, these information, elements, units, or modules should not be limited to these terms. These terms are only used to distinguish information, elements, units, or modules of the same type from one another.

[0024] It should be noted that step designations such as S11 and S12 are used in this document for the purpose of more clearly and concisely describing the corresponding content, and do not constitute a substantial limitation on the order. In specific implementation, those skilled in the art may execute S12 first and then S11, etc., but these should all be within the protection scope of this application.

[0025] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0026] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0027] First Embodiment

[0028] See Figure 1 This embodiment provides an image sensor, including a pixel array and a control module. The pixel array includes multiple pixel rows including pixel circuits, and the control module includes an inter-frame switching control circuit, wherein:

[0029] The inter-frame switching control circuit determines the inter-frame state based on the exposure information of the first exposure frame and the exposure information of the second exposure frame. When there is an overlap between the first exposure frame and the second exposure frame, the control module is used to complete the quantization control corresponding to the first exposure frame in the pixel row, and during the process of performing the exposure control corresponding to the second exposure frame in the pixel row, the transmission transistor in the pixel circuit of the pixel row is kept off.

[0030] In one embodiment, the exposure information can characterize various information during the process of acquiring the exposure frame, such as the exposure time of the exposure frame, the time information of the charge clearing stage, etc.

[0031] In one embodiment, comparing the exposure information of two exposure frames can determine whether there is an overlap in the processing time of the two exposure frames.

[0032] In one embodiment, the inter-frame switching control circuit can characterize various circuits capable of comparing the exposure information of two exposure frames to determine whether there is an overlap in the processing times of the two exposure frames.

[0033] In one embodiment, there is an overlap between the first exposure frame and the second exposure frame, which can indicate that the complete process of acquiring the first exposure frame has not yet ended, and the process of acquiring the second exposure frame has begun.

[0034] In one embodiment, when there is an overlap between the first exposure frame and the second exposure frame, the first exposure frame is, for example, a short exposure frame, and the second exposure frame is, for example, a long exposure frame.

[0035] In one embodiment, a short exposure frame is defined as an image frame whose exposure information includes a very short exposure time. Understandably, image frames with an exposure time less than or equal to a first preset time can be defined as short exposure frames, depending on actual needs.

[0036] In one embodiment, a long exposure frame is defined as an image frame whose exposure information includes a longer exposure time. Understandably, an image frame with an exposure time greater than or equal to a second preset time can be defined as a long exposure frame, depending on actual needs. This can be achieved by the exposure time of a long exposure frame being greater than the exposure time of an exposure frame. Furthermore, it should be noted that the first preset time and the second preset time can be set according to actual operational requirements, such as the second preset time being greater than the first preset time.

[0037] In one embodiment, the exposure time corresponding to the short exposure frame and the exposure time corresponding to the long exposure frame can be defined based on the situation where the image sensor encounters a logic problem when continuously acquiring image frames (e.g., the exposure of the second exposure frame immediately follows the quantization of the first exposure frame, or the transmission transistor is turned on during the exposure of the second exposure frame, which negatively affects the exposure and quantization of the second exposure frame).

[0038] It should be noted that the description of rows (e.g., pixel rows) here refers to quantization. For example, when using full-row progressive quantization, one quantization row corresponds to one full-row pixel row; when using half-row progressive quantization, one quantization row is half a pixel row. In this embodiment, the method of using full-row pixel rows as quantization rows is described.

[0039] Understandably, quantization control characterizes the process of converting analog signals read from each row of pixels in an image sensor's pixel array into digital signals. In this process, the light intensity (usually expressed as charge) of the pixel formed by each pixel circuit in the pixel row is converted into a digital value that represents the brightness or color information of that pixel.

[0040] Understandably, exposure control precedes quantization control and characterizes the process by which an image sensor manages the duration of charge accumulation in optoelectronic devices during image capture when light shines on them.

[0041] In one embodiment, when the image sensor continuously acquires multiple frames, the control module can also be used to drive the pixel rows in the pixel array to perform quantization control according to each frame. That is, the control module can also be used to drive the pixel array to perform row-by-row quantization (or step-by-step quantization) according to each frame. Optionally, under the control of the control module, when a pixel row in the pixel array completes the exposure and quantization corresponding to the first exposure frame, the same pixel row can then begin to correspond to the exposure and quantization of the second exposure frame. At the same time or immediately afterward, another pixel row whose quantization order is after the aforementioned pixel row can begin to correspond to the exposure and quantization of the first exposure frame. According to the aforementioned pattern, the image sensor can obtain at least two frames of quantized data, so that the image sensor can obtain an image with better image quality based on at least two frames of quantized data. For example, the quantization data of short exposure frames and the quantization data of long exposure frames can enable the image sensor to obtain a clear image with moderate brightness.

[0042] In some implementations, when an image sensor continuously captures multiple frames where the first exposure frame and the second exposure frame overlap, the time when a pixel row enters the charge clearing stage after completing the exposure control corresponding to the first exposure frame may overlap with the time when the pixel row performs the exposure control corresponding to the second exposure frame. This can lead to a situation where the transmission transistor is abnormally turned on during the exposure control of the pixel row corresponding to the second exposure frame, thus causing a logic problem.

[0043] To address some shortcomings in existing implementations, the technical solution described in this embodiment addresses the issue that when the inter-frame switching control circuit in the image sensor's control module determines an overlap between the first and second exposure frames, the control module can perform quantization control corresponding to the first exposure frame in the pixel row. Furthermore, during the exposure control process corresponding to the second exposure frame, the transmission transistors in the pixel circuits of the pixel row are kept off to prevent abnormal conduction of these transistors during the exposure control process. This ensures that the pixel row can complete the exposure and quantization corresponding to the second exposure frame as designed. Thus, the technical solution of this embodiment enables the image sensor to avoid logic problems when performing separate quantization of two frames in situations where two frames overlap in processing time, allowing the image sensor to better complete quantization and obtain better images.

[0044] Second Embodiment

[0045] This embodiment provides an image sensor, including a pixel array and a control module. The pixel array includes multiple pixel rows, each including pixel circuitry. The control module includes an inter-frame switching control circuit, wherein:

[0046] The inter-frame switching control circuit determines the inter-frame state based on the exposure information of the first exposure frame and the exposure information of the second exposure frame. When there is an overlap between the first exposure frame and the second exposure frame, the control module is used to complete the quantization control corresponding to the first exposure frame in the pixel row, and during the process of performing the exposure control corresponding to the second exposure frame in the pixel row, the transmission transistor in the pixel circuit of the pixel row is kept off.

[0047] The pixel array includes multiple pixel units and multiple reset transistors. Each pixel unit includes a first pixel circuit and a second pixel circuit belonging to different pixel rows. The first pixel circuit in a pixel unit is connected to a shared pixel unit (e.g., a pixel unit in the preceding row) via a reset transistor, and the second pixel circuit is connected to a shared pixel unit (e.g., a pixel unit in the following row) via a reset transistor.

[0048] In one embodiment, the pixel unit further includes a row selection transistor, and the first pixel circuit and the second pixel circuit in the pixel unit are connected to the data line through the same row selection transistor.

[0049] In one embodiment, the pixel array further includes at least one of a first boundary unit and a second boundary unit. A first pixel circuit is connected to a shared pixel unit or the first boundary unit via a reset transistor; a second pixel circuit is connected to a shared pixel unit or the second boundary unit via a reset transistor.

[0050] In one embodiment, the pixel column of the pixel array includes multiple pixel units and multiple reset transistors. Correspondingly, the pixel column also includes at least one of a first boundary unit and a second boundary unit. The pixel column can be found in [reference needed]. Figure 2 As shown.

[0051] In one implementation, the first pixel circuit and the second pixel circuit in the pixel unit are connected to the data line through the same row of select transistors. The first pixel circuit is connected to the shared pixel unit through a reset transistor, and the second pixel circuit is connected to the shared pixel unit through a reset transistor.

[0052] Understandably, sharing between pixel units can be either adjacent sharing or staggered sharing. In the case of adjacent sharing, for example, the first pixel circuit is connected to the preceding pixel unit or the first boundary unit through a reset transistor, and the second pixel circuit is connected to the following pixel unit or the second boundary unit through a reset transistor. The sharing method between pixel units can also be selected according to the actual circuit connection method.

[0053] In one embodiment, when there is an overlap between the first exposure frame and the second exposure frame in the inter-frame state, the first exposure frame is a short exposure frame and the second exposure frame is a long exposure frame.

[0054] The multiple pixel units in the pixel column may include the first pixel unit, the middle pixel unit, the last pixel unit, and further include the corresponding first boundary unit and second boundary unit.

[0055] Optionally, the first pixel circuit and the second pixel circuit in the first pixel unit are connected to the data line through the same row of selection transistors. The first pixel circuit is connected to the first boundary unit through a reset transistor, and the second pixel circuit is connected to the pixel unit in the next row (i.e., the middle pixel unit) through a reset transistor.

[0056] In one embodiment, the first boundary unit can characterize any device or combination of devices that can serve as the boundary of the pixel array, such as an input interface for a specific signal, a wire for transmitting a specific signal, a boundary circuit including a dual-conversion gain transistor, or the same circuit as the pixel unit in the pixel array.

[0057] Optionally, the first pixel circuit and the second pixel circuit in the intermediate pixel unit are connected to the data line through the same row selection transistor. The first pixel circuit is connected to the preceding pixel unit (e.g., the first pixel unit or the preceding intermediate pixel unit) through the reset transistor, and the second pixel circuit is connected to the following pixel unit (e.g., the following intermediate pixel unit) through the reset transistor.

[0058] Optionally, the first pixel circuit and the second pixel circuit in the last pixel unit are connected to the data line through the same row selection transistor, the first pixel circuit is connected to the preceding pixel unit (e.g., the middle pixel unit) through the reset transistor, and the second pixel circuit is connected to the second boundary unit through the reset transistor.

[0059] In one embodiment, the second boundary unit can characterize any device or combination of devices that can serve as the boundary of the pixel array, such as an input interface for a specific signal, a wire for transmitting a specific signal, a boundary circuit including a dual-conversion gain transistor, or the same circuit as the pixel unit in the pixel array.

[0060] In this pixel unit, the first pixel circuit and the second pixel circuit belong to two pixel rows in the pixel array, respectively. Optionally, the first pixel circuit and the second pixel circuit in the pixel unit belong to two shared (e.g., adjacent) pixel rows in the pixel array. Optionally, the pixel row to which the first pixel circuit in the pixel unit belongs can be the preceding or succeeding stage of the pixel row to which the second pixel circuit in the pixel unit belongs.

[0061] Understandably, when two pixel circuits in a pixel unit correspond to the first pixel row and the second pixel row respectively, when performing quantization control on the first pixel row, it is necessary to change the reset transistor shared by the pixel circuits in the second pixel row and the pixel circuits in other pixel rows from high voltage to low voltage. For example, the drain voltage of the reset transistor is changed from high voltage to low voltage. This prevents the second pixel row from clamping the quantization signal of the first pixel row because the two pixel circuits in the pixel units corresponding to the first and second pixel rows share the row selection transistor connection data line. Therefore, changing the drain voltage of the reset transistor shared by the pixel circuits in the second pixel row and the pixel circuits in other pixel rows from high voltage to low voltage is called establishing a reset node.

[0062] by Figure 2 For example, when quantizing the (k+2)th level pixel row, the pixel circuits in the (k+3)th level pixel row need to be... <4> Pixel circuits in the (k+4)th pixel row <5> Shared reset transistor rst <3> The drain voltage changes from high voltage to low voltage, thereby preventing the two pixel circuits (such as those in the pixel units corresponding to the (k+2)th and (k+3)th level pixel rows from changing from high voltage to low voltage. Figure 2 Pixel circuits in <3> and pixel circuit <4> Common row selection transistor rs <2> The connection of the data cable caused the quantization signal of the (k+3)th pixel row to be clamped, thus affecting the pixel circuitry in the (k+3)th pixel row. <4> Pixel circuit with the (k+4)th pixel row <5> Shared reset transistor rst <3> The transition from high voltage to low voltage is called establishing a reset node.

[0063] The time or speed at which a reset node is established is affected by the presence of capacitive nodes in the connection structure at the reset transistor's path (i.e., by the environment or behavior in which the reset node is established). Examples of capacitive nodes in the connection structure at the reset transistor's path include low-gain nodes in dual-conversion-gain transistors, floating diffusion nodes, and optoelectronic devices when a transfer transistor is turned on. Therefore, when a reset transistor is shared between pixels in two pixel rows, the load on the reset transistor to establish the reset node is heavier, takes longer, and is slower, leading to an increase in the quantization time of the pixel row.

[0064] In some implementations, when an image sensor continuously captures multiple frames with short exposure frames followed by long exposure frames, the presence of shared reset transistors between pixel rows results in a shorter time required for a pixel row to complete exposure control corresponding to the first exposure frame (short exposure frame), but a longer time required to complete quantization control corresponding to the first exposure frame. This delays the time when the subsequent control module controls the transmission transistors in the pixel circuits of the aforementioned pixel rows to enter the charge clearing stage. Furthermore, since the second exposure frame is a long exposure frame with a longer exposure time and a faster entry into the exposure stage, logic problems may occur. For example, during the exposure control process of the pixel row for the second exposure frame, the transmission transistors of the aforementioned pixel row may be turned on, negatively impacting the exposure and quantization of the second exposure frame.

[0065] To address some shortcomings in existing implementations, the image sensor employing a shared reset transistor and shared row selection transistor layout in this embodiment can, when there is an overlap between the first and second exposure frames in the inter-frame state, and the pixel row including the pixel circuit completes the quantization control corresponding to the first exposure frame, keep the transmission transistor in the pixel circuit of the pixel row turned off during the exposure control process corresponding to the second exposure frame. This prevents the transmission transistor of the pixel row from being abnormally turned on during the exposure control process of the second exposure frame, thus ensuring that the pixel row can complete the exposure and quantization corresponding to the second exposure frame as designed. Therefore, the technical solution of this embodiment enables the image sensor to avoid logic problems when performing quantization corresponding to short exposure frames and quantization corresponding to long exposure frames, thereby allowing the image sensor to better complete quantization and obtain better images.

[0066] Third Embodiment

[0067] This embodiment provides an image sensor, including a pixel array and a control module. The pixel array includes multiple pixel rows, each including pixel circuitry. The control module includes an inter-frame switching control circuit, wherein:

[0068] The inter-frame switching control circuit determines the inter-frame state based on the exposure information of the first exposure frame and the exposure information of the second exposure frame. When there is an overlap between the first exposure frame and the second exposure frame, the control module is used to complete the quantization control corresponding to the first exposure frame in the pixel row, and during the process of performing the exposure control corresponding to the second exposure frame in the pixel row, the transmission transistor in the pixel circuit of the pixel row is kept off.

[0069] In one embodiment, the image sensor includes a pixel array, a control module, and a data line. The pixel array includes multiple pixel units and multiple reset transistors. Each pixel unit includes a first pixel circuit, a second pixel circuit, and a row selection transistor.

[0070] In this pixel unit, the first pixel circuit and the second pixel circuit are connected to the data line through the same row of selection transistors. The first pixel circuit is connected to the shared pixel unit through a reset transistor, and the second pixel circuit is connected to the shared pixel unit through a reset transistor.

[0071] Understandably, sharing between pixel units can be either adjacent sharing or staggered sharing. In the case of adjacent sharing, for example, the first pixel circuit is connected to the preceding pixel unit through a reset transistor, and the second pixel circuit is connected to the following pixel unit through a reset transistor. The sharing method between pixel units can also be selected according to the actual circuit connection method.

[0072] In one embodiment, the first exposure frame is a short exposure frame and the second exposure frame is a long exposure frame.

[0073] In one embodiment, when the inter-frame switching control circuit determines that the inter-frame state is "other" (or that there is no overlap between the first and second exposure frames) based on the exposure information of the first and second exposure frames, the control module controls the pixel row to enter the charge clearing stage when the pixel row to which the pixel circuit belongs completes the quantization control corresponding to the first exposure frame, and / or controls the pixel row to execute the exposure control corresponding to the second exposure frame after the charge clearing stage is completed. Here, "other" can characterize various inter-frame states other than the overlap between the first and second exposure frames.

[0074] Thus, in this embodiment, when there is an overlap between the first and second exposure frames in the inter-frame state, the control module can keep the transmission transistors in the pixel circuits of the pixel row off after completing the quantization control corresponding to the first exposure frame in the pixel row. This prevents the pixel row from entering the charge clearing stage corresponding to the first exposure frame during the exposure control process corresponding to the second exposure frame, thereby preventing the transmission transistors of the aforementioned pixel row from being abnormally turned on during the exposure control process of the second exposure frame. This ensures that the pixel row can complete the exposure and quantization corresponding to the second exposure frame as designed. Furthermore, when the inter-frame state is in other states (e.g., short exposure frame followed by short exposure frame, long exposure frame followed by long exposure frame, long exposure frame followed by short exposure frame, etc.), control can be performed according to currently mature control logic, making the technical solution provided in this embodiment easy to implement and promote.

[0075] In one embodiment, the control module includes an inter-frame switching control circuit and a signal generation circuit.

[0076] Among them, see Figure 3 The inter-frame switching control circuit includes a memory and a decision controller.

[0077] The memory stores at least the exposure information of the first exposure frame and the exposure information of the second exposure frame.

[0078] In one embodiment, the exposure information includes at least various information that can identify whether an image frame is a long exposure frame or a short exposure frame, such as exposure time.

[0079] In one embodiment, the memory may include an input interface (such as...) Figure 3 (frame_in) and at least two output interfaces (such as frame ... Figure 3 (frame_out1 and frame_out2 in the image). The memory is used to receive and latch the exposure information of the image frame through the input interface. The memory is also used to connect to the decision controller through two output interfaces to output the exposure information of the first exposure frame and the exposure information of the second exposure frame to the decision controller respectively.

[0080] The determination controller is connected to the memory and the signal generation circuit. It is used to determine the inter-frame state based on the exposure information of the first exposure frame and the second exposure frame obtained from the memory. When the inter-frame state is determined to be an overlap between the first and second exposure frames, it outputs a first frame control signal (such as...). Figure 3 The frame_ctrl_en1 signal is sent to the signal generation circuit, or when the inter-frame state is determined to be other (no overlap between the first exposure frame and the second exposure frame), the second frame control signal (such as...) is output. Figure 3 The frame_ctrl_en2 in the signal generation circuit.

[0081] In one embodiment, the determination controller may further include a control signal interface for determining the inter-frame state based on the determination result and the control signal input to the control signal interface (e.g., ...). Figure 3 (rp_add_en in the middle), outputs the first frame control signal or the second frame control signal.

[0082] In one embodiment, the determination controller may include a comparator, which includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the comparator receives the exposure time of a first exposure frame, and the second input terminal of the comparator receives the exposure time of a second exposure frame. When the difference between the exposure time of the first exposure frame and the exposure time of the second exposure frame meets a preset value representing overlap, the comparator determines a first frame control signal based on the control signal input from the control signal interface and outputs it through the comparator's output terminal. Alternatively, when the difference between the exposure time of the first exposure frame and the exposure time of the second exposure frame does not meet the preset value representing overlap, the comparator determines a second frame control signal based on the control signal input from the control signal interface and outputs it through the comparator's output terminal.

[0083] The technical solution of this embodiment can realize the determination of inter-frame state through a simple inter-frame switching control circuit.

[0084] The signal generation circuit is used to keep the transmission transistor in the pixel circuit of the pixel row off based on the control signal of the first frame after the pixel row completes the quantization control corresponding to the first exposure frame and during the exposure control of the pixel row corresponding to the second exposure frame.

[0085] The signal generation circuit can also be used to control the pixel row to enter the charge clearing stage based on the second frame control signal when the pixel row completes the quantization control corresponding to the first exposure frame, and / or control the pixel row to perform exposure control corresponding to the second exposure frame after the end of the charge clearing stage.

[0086] In one embodiment, the signal generation circuit can also be used to output a control signal to control the pixel row to enter the charge clearing stage according to the delay time.

[0087] Specifically, the delay time is greater than or equal to the time required for at least one quantization control to be completed by other pixel rows whose quantization order follows that pixel row. Thus, the technical solution of this embodiment can avoid entering the charge clearing stage after a specific pixel row has completed quantization control and before the first preset number of pixel rows whose quantization order follows it have all completed quantization control. In other words, the specific pixel row enters the charge clearing stage after the first preset number of pixel rows whose quantization order follows it have all completed quantization control.

[0088] In one embodiment, see Figure 4 The signal generation circuit includes a latch and an AND gate.

[0089] The control module is used to provide a second preset number of first address signals in an orderly manner, wherein the second preset number is greater than or equal to the number of pixel rows corresponding to the pixel array.

[0090] In one embodiment, the control module can use digital circuitry to sequentially provide a second preset number of first address signals. Optionally, the first address signal can be a sampling row address signal (such as...). Figure 4 The sequence number in the code corresponds to the sampling address signal rp_add of the a-th pixel row. Furthermore, the first address signal can also be obtained using other existing methods in image sensors. Pixel units or pixel rows can be configured according to existing address configuration methods in image sensors; that is, each pixel unit or row is configured with its own address, so that control signals for the pixel units or pixel rows are formed based on different addresses.

[0091] The AND gate includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the AND gate receives a control signal (such as...). Figure 4 The sequence number in the code corresponds to the sampling address signal rp_add of the a-th pixel row. The second input of the AND gate receives either the first frame control signal or the second frame control signal (e.g., ...). Figure 4 The output of the AND gate (frame_ctrl_en1 / frame_ctrl_en2) is connected to the first signal interface of the latch.

[0092] The control signal is a first address signal provided by the control module selected by the control module according to a preset selection rule. The preset selection rule can be based on a second preset number of first address signals provided by the control module, using the first address signal corresponding to the first preset number of first address signals after sequentially or in reverse order as the control signal.

[0093] The AND gate is used to output a control signal through its output when it receives the second frame control signal at its second input, so that the latch can control the pixel row to enter the charge clearing stage according to the delay time when it receives the control signal.

[0094] The AND gate is also used to stop outputting control signals when it receives the first frame control signal at its second input, so that the latch keeps the transmission transistor in the pixel circuit of the pixel row off when it does not receive a control signal.

[0095] Specifically, the latch is used to prevent the control signal of the transmission transistor in the pixel circuit of the pixel row from flipping when no control signal is received, thereby turning off the transmission transistor in the pixel circuit of the pixel row to wait for the execution of exposure control corresponding to the second exposure frame.

[0096] It should be understood that when the output of an AND gate can perform quantization control on at least some (partial or all) of the pixel rows in the pixel array, it will output control signals accordingly. In an image sensor, address signals can be used to select corresponding pixels or pixel rows based on a preset timing sequence. A latch can use multiple MOS transistors and inverters, etc., to output control signals based on the input related address signals according to a preset timing sequence to realize the operation of the image sensor. For example, as shown... Figure 4 As shown, the latch receives sp_add (exposure line address signal), sp_tx (exposure line transmission signal), rp_tx (sampling line transmission signal), and rp_add (sampling line address signal) to form lat_addb (the inverse signal of the latch line address signal) to control the transmission transistor and determine whether to turn it on to enter the charge clearing latch state. The above address signals can be provided by the digital circuit part of the image sensor in the existing way.

[0097] Thus, the technical solution of this embodiment can easily and conveniently determine the inter-frame state by combining the inter-frame switching control circuit and the signal generation circuit, and make the control signal of the transmission transistor in the pixel circuit of the control pixel row flip or not flip according to the determination result. So when the inter-frame state is that there is an overlap between the first exposure frame and the second exposure frame, the control signal of the transmission transistor in the pixel circuit of the control pixel row does not flip, and the transmission transistor in the pixel circuit of the control pixel row remains off (equivalent to not entering the charge clearing stage corresponding to the first exposure frame). Or when the inter-frame state is other states, the control signal of the transmission transistor in the pixel circuit of the control pixel row flips, and the transmission transistor in the pixel circuit of the control pixel row is turned on to enter the charge clearing stage.

[0098] In another embodiment, see Figure 5 The signal generation circuit includes a first AND gate, a second AND gate, and a selector.

[0099] The first AND gate includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first AND gate receives a first control signal (such as...). Figure 5 rp_add<a+b> The second input of the first AND gate receives either the first frame control signal or the second frame control signal (e.g., ...). Figure 5 In the first AND gate (frame_ctrl_en1 / frame_ctrl_en2), the output of the first AND gate is connected to the first input of the selector and the output of the selector is connected to the first signal interface of the latch. The first control signal is the first address signal corresponding to the first preset number of sequential bits pushed back in sequence.

[0100] The first AND gate is used to output a first control signal to the first input of the selector when it receives a second frame control signal at its second input, or to stop outputting the first control signal to the first input of the selector when it receives a first frame control signal at its second input.

[0101] The second AND gate includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second AND gate receives a second control signal (such as...). Figure 5 rp_add <a-b>The second input of the second AND gate receives either the first frame control signal or the second frame control signal (e.g., ...). Figure 5 In the second AND gate (frame_ctrl_en1 / frame_ctrl_en2), the output of the second AND gate is connected to the second input of the selector and the output of the selector is connected to the first signal interface of the latch. The first control signal is the first address signal corresponding to the first preset number of positions after being pushed forward in reverse order.

[0102] The second AND gate is used to output a second control signal to the second input of the selector when it receives a second frame control signal at its second input, or to stop outputting the second control signal to the second input of the selector when it receives a first frame control signal at its second input.

[0103] The selector is used to receive the enable signal (such as) input to its enable terminal. Figure 5 The dd_flip_en driver in this embodiment outputs either the first control signal received at its first input terminal or the second control signal received at its second input terminal. Thus, the signal generation circuit in this embodiment, through the function of the selector, can support the flip mode (or inversion mode) of the image sensor, determining the control signals sequentially or in reverse order in both forward and reverse readout states. Users can flexibly configure the device by selecting and setting the installation and readout order of the image sensor chip based on the flip mode.

[0104] The latch is used to control the pixel row to enter the charge clearing stage with a delay time when a first control signal or a second control signal is received, or to control the transmission transistor in the pixel circuit of the pixel row to remain off when no first control signal or second control signal is received.

[0105] In one embodiment, when the first preset number is b (b≥3), taking the quantization control of the a-th pixel row as an example, the signal generation circuit in the control module selects the first address signal corresponding to the a+b-th or ab-th sequence position as the control signal (e.g., Figure 3 rp_add<a+b> Or rp_add <a-b>), where the value of a corresponds to the ordinal position, which can correspond to the level position of the a-th pixel row in the pixel array.

[0106] In one embodiment, the control module further includes a control circuit, which includes multiple control circuit units, a signal generation circuit is included in the control circuit units, and the control circuit units are connected to the pixel rows of the pixel array.

[0107] The control circuit unit is used to control the transmission transistor in the pixel circuit of the pixel row connected to it when the latch in the signal generation circuit receives a control signal (such as a first control signal or a second control signal), so that the pixel row connected to it enters the charge clearing stage according to the delay time.

[0108] The control circuit unit is also used to keep the transmission transistor in the pixel circuit of the pixel row off when the latch in the signal generation circuit does not receive a control signal (such as the first control signal or the second control signal).

[0109] Optionally, each control circuit unit corresponds to a pixel row in the control pixel array. The control circuit unit can control the pixel circuit in the pixel row based on various signals output by the image sensor settings. For example, when the signal generation circuit outputs a control signal, the control circuit unit can control the transmission transistor in the pixel circuit of the pixel row it is connected to (e.g., delay its conduction), thereby delaying the aforementioned pixel row from entering the charge clearing stage. Alternatively, when the signal generation circuit does not output a control signal, the control circuit unit can control the transmission transistor in the pixel circuit of the pixel row it is connected to (e.g., keep it off) during the exposure control process corresponding to the second exposure frame.

[0110] The image sensor employing a shared reset transistor and a shared row selection transistor layout in its pixel array can perform quantization control corresponding to the first exposure frame within the pixel row, including the pixel circuit. When the inter-frame switching control circuit in the control module determines that there is an overlap between the first and second exposure frames, the signal generation circuit connected to the inter-frame switching control circuit in the control module stops outputting a control signal. This ensures that the transmission transistors in the pixel circuits of the pixel row remain off during the exposure control process corresponding to the second exposure frame. Therefore, in the case of a short exposure frame followed by a long exposure frame, the transmission transistors of the aforementioned pixel row are prevented from being abnormally turned on during the exposure control process of the second exposure frame, thus ensuring that the pixel row can complete the exposure and quantization corresponding to the second exposure frame as designed. Thus, the technical solution of this embodiment enables the image sensor to avoid logic problems when performing quantization corresponding to short and long exposure frames, thereby allowing the image sensor to better complete quantization and obtain better images.

[0111] Furthermore, through the above-mentioned technical solution of this application, the image sensor with a pixel array using a shared reset transistor and a shared row selection transistor layout can complete the quantization control corresponding to the first exposure frame in the pixel row including the pixel circuit. When the inter-frame switching control circuit in the control module determines that the inter-frame state is other, the control signal output by the signal generation circuit connected to the inter-frame switching control circuit in the control module controls the pixel row to directly enter the charge clearing stage or delay entering the charge clearing stage, thereby enabling the image sensor to better complete the quantization of multiple frames to obtain a better image.

[0112] Furthermore, the control module in the technical solution of this embodiment, which includes an inter-frame switching control circuit and a signal generation circuit, is equivalent to a pixel driving circuit. It can prevent the image sensor from performing exposure control corresponding to the second exposure frame when the transmission transistor in the pixel row is turned on in the case of short exposure frames followed by long exposure frames. This ensures that the pixel row can complete the exposure and quantization corresponding to the second exposure frame as designed. It can also enable the image sensor to perform quantization and charge clearing according to mature control logic in other inter-frame states. This ensures that the pixel row can complete the exposure, quantization, and charge clearing of the first exposure frame as designed, and complete the exposure, quantization, and charge clearing of the second exposure frame as designed.

[0113] In some implementations, because the pixel array is quantized step-by-step, and when the inter-frame state is other than the first exposure frame and the pixel row at each level completes the quantization control corresponding to the first exposure frame and / or the second exposure frame, it immediately enters the charge clearing stage; or when the inter-frame state overlaps between the first and second exposure frames, the pixel row at each level completes the quantization control corresponding to the second exposure frame and immediately enters the charge clearing stage. Therefore, for two levels of pixel rows corresponding to a pixel unit, the environment or behavior of establishing a reset node during quantization control of the preceding pixel row is different from that of establishing a reset node during quantization control of the following pixel row. This results in a significant difference in the time or speed at which a reset node is established during quantization control of the preceding pixel row compared to the time or speed at which a reset node is established during quantization control of the following pixel row. Figure 2 Taking the k-th pixel row, k+1-th pixel row, k+2-th pixel row, and k+3-th pixel row as examples, the following example illustrates the concept:

[0114] When performing quantization control on the k-th pixel row, the reset transistor rst connected between the (k+1)-th and (k+2)-th pixel rows needs to be reset. <2> The voltage changes from high to low to establish a reset node. At this time, since neither the (k+1)th nor the (k+2)th pixel row has undergone quantization control, the transmission transistors in the (k+1)th and (k+2)th pixel rows are in the off state. Therefore, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows... <2> It will not charge the photosensitive devices connected to the transmission transistor in the pixel circuit of the (k+1)th pixel row and the pixel circuit of the (k+2)th pixel row; and when the kth pixel completes quantization control, it will immediately turn on the transmission transistor of its pixel circuit to enter the charge clearing stage.

[0115] When performing quantization control on the (k+1)th level pixel row, it is necessary to reset the reset transistor rst connected between the kth level pixel row and the first boundary unit. <1> The voltage changes from high to low to establish a reset node. At this time, since the k-th pixel row has completed quantization control and entered the charge clearing stage, the reset transistor rst connected between the k-th pixel row and the first boundary cell is activated. <1> Compared to the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows, <2> Therefore, at least the photosensitive device connected to the transmission transistor in the k-th pixel row needs to be charged (i.e., the environment or behavior of establishing a reset node when performing quantization control on the k-th pixel row is different from the environment or behavior of establishing a reset node when performing quantization control on the (k+1)-th pixel row). Thus, compared to the reset transistor rst connected between the (k+1)-th and (k+2)-th pixel rows... <2> The reset transistor rst connected between the k-th pixel row and the first boundary unit <1> At least additional charging is required for the photosensitive device connected to the transmission transistor in the pixel circuit of the k-th pixel row, which results in a longer or slower time to establish the reset node.

[0116] In addition, when the (k+1)th level pixel completes quantization control, the transmission transistor of the pixel circuit will be turned on immediately to enter the charge clearing stage;

[0117] When performing quantization control on the (k+2)th pixel row, the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows needs to be reset. <3> The voltage changes from high to low to establish a reset node. At this time, since neither the (k+3)th nor the (k+4)th pixel row has quantization control, the transfer transistors in the pixel circuits of the (k+3)th and (k+4)th pixel rows are in the off state. Therefore, the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows... <3> It will not charge the photosensitive devices connected to the transmission transistors in the (k+3)th and (k+4)th pixel rows; in addition, when the (k+2)th pixel completes quantization control, it will immediately turn on the transmission transistors of the pixel circuits therein to enter the charge clearing stage.

[0118] When performing quantization control on the (k+3)th pixel row, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows needs to be reset. <2> The voltage changes from high to low to establish a reset node. At this point, since both the (k+1)th and (k+2)th pixel rows have completed quantization control and entered the charge clearing stage, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows... <2> Compared to the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows, <3> Therefore, at least the photosensitive devices connected to the transmission transistors in the pixel circuits of the (k+1)th and (k+2)th pixel rows also need to be charged (i.e., the environment or behavior of establishing a reset node when performing quantization control on the (k+3)th pixel row is different from the environment or behavior of establishing a reset node when performing quantization control on the (k+2)th pixel row). Therefore, compared to the reset transistors rst connected between the (k+3)th and (k+4)th pixel rows... <3> The reset transistor rst connected between the (k+1)th level pixel row and the (k+2)th level pixel row <2> At least additional charging is required for the photosensitive devices connected to the transmission transistors in the pixel circuits of the (k+1)th and (k+2)th pixel rows, which results in a longer or slower time to establish the reset node.

[0119] When performing quantization control on other pixel rows of the pixel array in some implementations, the situation of establishing a reset node can be deduced from the above content, and will not be repeated here.

[0120] To address the shortcomings of some implementation methods, the technical solution of this embodiment can achieve the following effects when the inter-frame state is in other states, or when there is an overlap between the first exposure frame and the second exposure frame and quantization is performed corresponding to the second exposure frame:

[0121] When performing quantization control on the k-th pixel row, the reset transistor rst connected between the (k+1)-th and (k+2)-th pixel rows is... <2> The voltage changes from high to low to establish a reset node. At this time, since neither the (k+1)th nor the (k+2)th pixel row has undergone quantization control, the transfer transistors in the pixel circuits of the (k+1)th and (k+2)th pixel rows are in the off state. Therefore, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows... <2> The system will not charge the photosensitive devices connected to the transmission transistors in the pixel circuits of the (k+1)th and (k+2)th pixel rows; and when the quantization control of the kth pixel row is completed, the control module outputs a control signal to control the kth pixel row to delay entering the charge clearing stage. For example, it will delay the quantization control until at least one pixel row after the kth pixel row (such as the 3rd pixel row after the kth pixel row) has completed the quantization control before controlling the transmission transistors in the kth pixel row to turn on to enter the charge clearing stage.

[0122] When performing quantization control on the (k+1)th pixel row, the reset transistor rst connected between the kth pixel row and the first boundary unit is... <1> The voltage changes from high to low to establish a reset node. At this time, since the k-th pixel row has completed quantization control but has not yet entered the charge clearing stage (i.e., the transfer transistor in the pixel circuit of the k-th pixel row is in the off state), the reset transistor rst connected between the k-th pixel row and the first boundary cell is activated. <1> It will not charge the photosensitive device connected to the transmission transistor in the pixel circuit of the k-th pixel row; therefore, the environment or behavior of establishing a reset node when performing quantization control on the (k+1)-th pixel row is similar to or the same as the environment or behavior of establishing a reset node when performing quantization control on the k-th pixel row, thus the reset transistor rst connected between the k-th pixel row and the first boundary unit will not be charged. <1> The time or speed at which the reset node is established, and the reset transistor rst connected between the (k+1)th and (k+2)th level pixel rows. <2> The time or speed at which reset nodes are established is similar or the same;

[0123] Furthermore, when the quantization control of the (k+1)th level pixel row is completed, the control module outputs a control signal to control the (k+1)th level pixel row to delay entering the charge clearing stage. For example, it delays until at least one level pixel row after the (k+1)th level pixel row (such as three level pixel rows after the (k+1)th level pixel row) has completed the quantization control before controlling the transmission transistor in the (k+1)th level pixel row to turn on to enter the charge clearing stage.

[0124] When performing quantization control on the (k+2)th pixel row, the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows is... <3> The voltage changes from high to low to establish a reset node. At this time, since neither the (k+3)th nor the (k+4)th pixel row has quantization control, the transfer transistors in the pixel circuits of the (k+3)th and (k+4)th pixel rows are in the off state. Therefore, the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows... <3> The system will not charge the photosensitive devices connected to the transmission transistors in the pixel circuits of the (k+3)th and (k+4)th pixel rows; and when the quantization control of the (k+2)th pixel row is completed, the control module outputs a control signal to delay the (k+2)th pixel row from entering the charge clearing stage. For example, it will delay the quantization control until at least one pixel row after the (k+2)th pixel row (such as the 3rd pixel row after the (k+2)th pixel row) is completed before controlling the transmission transistors in the (k+2)th pixel row to turn on to enter the charge clearing stage.

[0125] When performing quantization control on the (k+3)th pixel row, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows is... <2> The voltage changes from high to low to establish a reset node. At this time, since both the (k+1)th and (k+2)th pixel rows have completed quantization control but have not yet entered the charge clearing stage (i.e., the transfer transistors in the pixel circuits of the (k+1)th and (k+2)th pixel rows are in the off state), the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows is off. <2> Nor will it charge the photosensitive devices connected to the transmission transistors in the pixel circuits of the (k+1)th and (k+2)th pixel rows; therefore, the environment or behavior for establishing a reset node when performing quantization control on the (k+3)th pixel row is the same as that for establishing a reset node when performing quantization control on the (k+2)th pixel row, thus the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows will be deactivated. <2> The time or speed at which the reset node is established, and the reset transistor rst connected between the (k+3)th and (k+4)th level pixel rows. <3> The time or speed at which the reset node is established is the same;

[0126] Furthermore, when the quantization control of the (k+3)th pixel row is completed, the control module outputs a control signal to delay the (k+3)th pixel row from entering the charge clearing stage. For example, it delays the quantization control until at least one pixel row after the (k+3)th pixel row (such as three pixel rows after the (k+3)th pixel row) is completed before controlling the transmission transistor in the (k+3)th pixel row to turn on to enter the charge clearing stage.

[0127] When performing quantization control on other pixel rows of the pixel array in this embodiment, the situation of establishing a reset node can be deduced from the above content, and will not be repeated here.

[0128] According to the above technical content, the technical solution of this application can, when the inter-frame state is other states or when there is an overlap between the first exposure frame and the second exposure frame and quantization is performed corresponding to the second exposure frame, make the environment or behavior of the reset transistor establishing the reset node when each pixel row in the pixel array performs quantization control corresponding to the second exposure frame as similar or the same as the environment or behavior of the reset transistor establishing the reset node when performing quantization control of other pixel rows. This allows the image sensor to maintain a consistent or similar time or speed for establishing reset nodes between different pixel rows when performing line-by-line quantization, thereby enabling the image sensor to better complete the quantization corresponding to each frame.

[0129] In one embodiment, when the second preset number of first address signals provided by the control module is equal to the number of pixel rows corresponding to the pixel array, after each of the first preset number of pixel rows of the adjacent boundary unit (first boundary unit or second boundary unit) (hereinafter referred to as the tail-level pixel row) completes quantization control, the selector cannot select the first address signal corresponding to the a+b or ab sequence position from the control module as the control signal according to the preset rules. At this time, the output of the selector can be connected to a Class D flip-flop to generate and output a second address signal as the control signal through the Class D flip-flop, so as to support the tail-level pixel row to enter the charge clearing stage according to the delay time when quantization control is completed.

[0130] In one embodiment, each of the pixel rows in the pixel array that are adjacent to a first preset number of first boundary units or second boundary units can be defined as a tail-level pixel row. For example, when the first preset number is 3, the first-level pixel row, the second-level pixel row, and the third-level pixel row adjacent to the first boundary unit or second boundary unit in the pixel array can all be called tail-level pixel rows, and the first-level pixel row adjacent to the first boundary unit or second boundary unit can be the last valid pixel row of the pixel array. Based on the above description, pixel rows in the pixel array can include tail-level pixel rows and non-tail-level pixel rows.

[0131] In one embodiment, the signal generation circuit further includes a first preset number of Class D flip-flops.

[0132] In one embodiment, a first preset number of Class D flip-flops are connected in series at the first input of the AND gate. When the first address signal cannot be selected as the control signal according to the preset selection rules, at least one of the first preset number of Class D flip-flops generates and outputs a control signal to the first input of the AND gate.

[0133] In one embodiment, the control signal output by the selector, determined according to a preset selection rule, is used to cause the signal generation circuit to control the non-tail-level pixel row to complete the quantization control when the inter-frame state is in other states, or when there is an overlap between the first exposure frame and the second exposure frame and quantization is performed corresponding to the second exposure frame, so that the signal generation circuit controls the non-tail-level pixel row to enter the charge clearing stage according to the delay time.

[0134] In one embodiment, the output of the selector outputs a control signal generated by a second preset number of Class D flip-flops, which is used to cause the signal generation circuit to control the pixel row of the tail stage to complete the quantization control when the inter-frame state is other states, or when there is an overlap between the first exposure frame and the second exposure frame and quantization is performed corresponding to the second exposure frame, so that the signal generation circuit controls the pixel row of the tail stage to enter the charge clearing stage according to the delay time.

[0135] Based on the same inventive concept as the foregoing embodiments, the image sensor described in the foregoing embodiments will be illustrated by specific examples below:

[0136] In one embodiment, the first pixel circuit and the second pixel circuit belong to two pixel rows in the pixel array, respectively.

[0137] See Figure 6 This example provides a pixel array for an image sensor. The pixel column of the pixel array includes multiple pixel units, multiple reset transistors rst, a first boundary unit and a second boundary unit. The pixel unit includes a first pixel circuit, a second pixel circuit and a row selection transistor rs. The first pixel circuit and the second pixel circuit belong to two adjacent pixel rows in the pixel array (e.g., an odd-numbered pixel row and an even-numbered pixel row).

[0138] The first pixel circuit includes a first optoelectronic device pd, a first transmission transistor tx, a first floating diffusion node fd, a first source follower transistor sf, and a first dual conversion gain transistor dcg.

[0139] The control terminal of the first transmission transistor tx receives the control signal, and the two terminals of the first transmission transistor tx are respectively connected to the first optoelectronic device pd and the first floating diffusion node fd.

[0140] In this configuration, the control terminal of the first source follower transistor sf is connected to the first floating diffusion node fd, the second path terminal of the first source follower transistor sf is connected to the data line through the two path terminals of the row select transistor rs, the first path terminal of the first source follower transistor sf receives the power supply signal, and the control terminal of the row select transistor rs receives the control signal.

[0141] In this configuration, the control terminal of the first dual-conversion-gain transistor DCG receives a control signal, the first path terminal of the first dual-conversion-gain transistor DCG is connected to a shared pixel unit or a first boundary unit through the second path terminal of a reset transistor RST, and the second path terminal of the first dual-conversion-gain transistor DCG is connected to a first floating diffusion node FD; wherein, the control terminal of the reset transistor RST receives a control signal, and the first path terminal RSTD of the reset transistor RST receives a charging signal.

[0142] In the case where the first path terminal of the first dual-conversion-gain transistor dcg is connected to the shared pixel unit through the second path terminal of a reset transistor rst, it can be that the first path terminal of the first dual-conversion-gain transistor dcg is connected to the first path of the second dual-conversion-gain transistor dcg in the second pixel circuit of the preceding pixel unit through the second path terminal of a reset transistor rst.

[0143] Optionally, the first boundary unit may be composed of a dual-conversion-gain transistor (dcg).

[0144] The second pixel circuit includes a second optoelectronic device pd, a second transmission transistor tx, a second floating diffusion node fd, a second source follower transistor sf, and a second double conversion gain transistor dcg.

[0145] The control terminal of the second transmission transistor tx receives the control signal, and the two terminals of the second transmission transistor tx are respectively connected to the second optoelectronic device pd and the second floating diffusion node fd.

[0146] The control terminal of the second source follower transistor sf is connected to the second floating diffusion node fd, the second path terminal of the second source follower transistor sf is connected to the data line through the two path terminals of the shared row select transistor rs, and the first path terminal of the second source follower transistor sf receives the power signal.

[0147] In this configuration, the control terminal of the second dual-conversion gain transistor dcg receives a control signal, the second path terminal of the second dual-conversion gain transistor dcg is connected to the second floating diffusion node fd, and the first path terminal of the second dual-conversion gain transistor dcg is connected to the shared pixel unit or the second boundary unit through the second path terminal of another reset transistor rst; wherein, the control terminal of the other reset transistor rst receives a control signal, and the first path terminal of the other reset transistor rst receives a charging signal.

[0148] In the case where the first path terminal of the second dual-conversion gain transistor dcg is connected to the shared pixel unit through the second path terminal of another reset transistor rst, it can be that the first path terminal of the second dual-conversion gain transistor dcg is connected to the first path of the first dual-conversion gain transistor dcg of the first pixel circuit in the subsequent pixel unit through the second path terminal of another reset transistor rst.

[0149] Optionally, the second boundary unit can be composed of a dual-conversion-gain transistor (dcg).

[0150] In some implementations, because the pixel array is quantized level by level, each pixel row immediately enters the charge clearing stage after quantization control. Therefore, for two adjacent pixel rows corresponding to a pixel unit, the environment or behavior for establishing a reset node during quantization control of the preceding pixel row differs from that of the following pixel row. This results in a significant difference in the time or speed at which the reset node is established during quantization control of the preceding pixel row compared to the following pixel row. Combined with... Figure 2 and Figure 6 Taking the k-th pixel row, the (k+1)-th pixel row, the (k+2)-th pixel row, and the (k+3)-th pixel row as examples, the following is an illustration:

[0151] When performing quantization control on the k-th pixel row, the reset transistor rst connected between the (k+1)-th and (k+2)-th pixel rows needs to be reset. <2> The drain voltage changes from high to low to establish a reset node. At this time, since neither the (k+1)th nor the (k+2)th pixel row has quantization control, the transfer transistor tx in the (k+1)th and (k+2)th pixel rows is in the off state. Therefore, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows... <2> It will affect the two corresponding floating diffusion nodes (such as Figure 6 fd in<k+1> ,fd<k+2> ), two double-conversion gain transistors (such as Figure 6 DCG in<k+1> dcg<k+2> The corresponding LCG node () Figure 6 (not shown), but will not charge the photosensitive device pd connected to the transmission transistor tx in the pixel circuit of the (k+1)th pixel row and the pixel circuit of the (k+2)th pixel row; and when the kth pixel completes quantization control, it will immediately turn on the transmission transistor tx of the pixel circuit to enter the charge clearing stage.

[0152] When performing quantization control on the (k+1)th level pixel row, it is necessary to reset the reset transistor rst connected between the kth level pixel row and the first boundary unit. <1> The drain voltage changes from high to low to establish a reset node. At this time, since the k-th pixel row has completed quantization control and the transmission transistor tx has entered the charge clearing stage, the reset transistor rst connected between the k-th pixel row and the first boundary cell is activated. <1> It will affect the corresponding floating diffusion nodes (such as Figure 6 fd in <k>), two double-conversion gain transistors (such as Figure 6 DCG in <k>、dcg <k-1>The corresponding LCG node () Figure 6 (Not shown) and the photosensitive device pd connected to the transmission transistor tx in the pixel circuit of the k-th pixel row. <k>Charging; that is, the environment or behavior of establishing a reset node when performing quantization control on the k-th pixel row is different from the environment or behavior of establishing a reset node when performing quantization control on the (k+1)-th pixel row, and will result in the time to establish a reset node being longer or the speed being slower than that of establishing a reset node.

[0153] In addition, when the (k+1)th level pixel completes quantization control, the transmission transistor tx of the pixel circuit will be turned on immediately to enter the charge clearing stage;

[0154] When performing quantization control on the (k+2)th pixel row, the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows needs to be reset. <3> The drain voltage changes from high to low to establish a reset node. At this time, since neither the (k+3)th nor the (k+4)th pixel row is quantized, the transfer transistor tx in the pixel circuits of the (k+3)th and (k+4)th pixel rows is off. Therefore, the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows... <3> It will affect the two corresponding floating diffusion nodes (such as Figure 6 fd in<k+3> ,fd<k+4> ), two double-conversion gain transistors (such as Figure 6 DCG in<k+3> dcg<k+4> The corresponding LCG node () Figure 6 (not shown), but will not provide the photosensitive devices (such as pd) connected to the transmission transistor tx in the (k+3)th and (k+4)th pixel rows.<k+3> ,pd<k+4> ) Charging; In addition, when the (k+2)th level pixel completes quantization control, it will immediately turn on the transmission transistor tx of the pixel circuit to enter the charge clearing stage;

[0155] When performing quantization control on the (k+3)th pixel row, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows needs to be reset. <2> The drain voltage changes from high to low to establish a reset node. At this time, since both the (k+1)th and (k+2)th pixel rows have completed quantization control and both are conducting, the transmission transistor tx has entered the charge clearing stage. Therefore, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows... <2> It will affect the two corresponding floating diffusion nodes (such as Figure 6 fd in<k+1> ,fd<k+2> ), two double-conversion gain transistors (such as Figure 6 DCG in<k+1> dcg<k+2> The corresponding LCG node () Figure 6 (Not shown), the photosensitive devices (such as pd) connected to the transmission transistor tx in the (k+3)th and (k+4)th pixel rows respectively.<k+1> ,pd<k+2> Charging; that is, the environment or behavior of establishing a reset node when performing quantization control on the (k+3)th pixel row is different from the environment or behavior of establishing a reset node when performing quantization control on the (k+2)th pixel row, and will result in the establishment of a reset transistor rst. <2> Compared to establishing a reset transistor rst <3> The time taken is long or the speed is slow;

[0156] In addition, when the (k+3)th level pixel completes quantization control, the transmission transistor tx of the pixel circuit will be turned on immediately to enter the charge clearing stage;

[0157] When performing quantization control on other pixel rows of the pixel array in some implementations, the situation of establishing a reset node can be deduced from the above content, and will not be repeated here.

[0158] For waveform diagrams of key nodes entering the charge clearing phase in some implementations, please refer to [link / reference]. Figure 7 .

[0159] To address the shortcomings of some implementation methods, the technical solution in this example configures a control module in the image sensor that, after quantizing each pixel row, delays its entry into the charge clearing stage by three address signals. This ensures that the environment or behavior of the reset transistors establishing reset nodes during quantization control of each pixel row in the pixel array is similar or identical to the environment or behavior of the reset transistors establishing reset nodes during quantization control of other pixel rows. This allows the image sensor to maintain as consistent a time or speed as possible for establishing reset nodes between different pixel rows during row-by-row quantization, thereby enabling the image sensor to perform quantization more effectively. A specific example is shown below:

[0160] When performing quantization control on the k-th pixel row, the reset transistor rst connected between the (k+1)-th and (k+2)-th pixel rows is... <2> The drain voltage changes from high to low to establish a reset section. At this time, since neither the (k+1)th nor the (k+2)th pixel row is quantized, the transfer transistor tx in the pixel circuits of the (k+1)th and (k+2)th pixel rows is off. Therefore, the reset transistor rst connecting the (k+1)th and (k+2)th pixel rows is off. <2> It will affect the two corresponding floating diffusion nodes (such as Figure 6 fd in<k+1> ,fd<k+2> ), two double-conversion gain transistors (such as Figure 6 DCG in<k+1> dcg<k+2> The corresponding LCG node () Figure 6 (Not shown), but it will not charge the photosensitive device pd connected to the transmission transistor tx in the pixel circuit of the (k+1)th pixel row and the pixel circuit of the (k+2)th pixel row; and when the kth pixel completes quantization control, it will delay the three address signals and then turn on the transmission transistor tx of the pixel circuit to enter the charge clearing stage. That is to say, when the kth pixel completes quantization control, it will be controlled by the control module to complete quantization control of the subsequent 3 pixel rows before entering the charge clearing stage.

[0161] When performing quantization control on the (k+1)th pixel row, the reset transistor rst connected between the kth pixel row and the first boundary unit is... <1> The voltage changes from high to low to establish a reset node. At this time, since the k-th pixel row has completed quantization control but has not yet entered the charge clearing stage (i.e., the transfer transistor tx in the pixel circuit of the k-th pixel row is in the off state), the reset transistor rst connected between the k-th pixel row and the first boundary cell is activated. <1> It will affect the corresponding floating diffusion nodes (such as Figure 6 fd in <k>), two double-conversion gain transistors (such as Figure 6 DCG in <k>、dcg <k-1>The corresponding LCG node () Figure 6 (Not shown) Charging, but not charging the photosensitive device connected to the transmission transistor tx in the pixel circuit of the k-th pixel row; therefore, the environment or behavior of establishing a reset node when performing quantization control on the (k+1)-th pixel row is similar to the environment or behavior of establishing a reset node when performing quantization control on the k-th pixel row, thus the reset transistor rst connected between the k-th pixel row and the first boundary unit. <1> The time or speed at which the reset node is established, and the reset transistor rst connected between the (k+1)th and (k+2)th level pixel rows. <2> The time or speed for establishing reset nodes is similar;

[0162] Furthermore, when the quantization control of the (k+1)th level pixel row is completed, the transmission transistor tx of the pixel circuit will be turned on after a delay of three address signals to enter the charge clearing stage. In other words, when the quantization control of the (k+1)th level pixel is completed, it will enter the charge clearing stage only after the subsequent three levels of pixel rows have completed quantization control, under the control of the control module.

[0163] When performing quantization control on the (k+2)th pixel row, the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows is... <3> The drain voltage changes from high to low to establish a reset node. At this time, since neither the (k+3)th nor the (k+4)th pixel row has quantization control, the transfer transistors in the pixel circuits of the (k+3)th and (k+4)th pixel rows are in the off state. Therefore, the reset transistor rst connected between the (k+3)th and (k+4)th pixel rows... <3> ), will affect its two corresponding floating diffusion nodes (such as Figure 6 fd in<k+3> ,fd<k+4> ), two double-conversion gain transistors (such as Figure 6 DCG in<k+3> dcg<k+4> The corresponding LCG node () Figure 6 (not shown), but will not provide the photosensitive devices (such as pd) connected to the transmission transistor tx in the pixel circuits of the (k+3)th pixel row and the pixel circuits of the (k+4)th pixel row.<k+3> ,pd<k+4> ) charging; and when the quantization control of the (k+2)th level pixel row is completed, the transmission transistor tx of the pixel circuit will be turned on after the three address signals are delayed to enter the charge clearing stage. That is to say, when the (k+2)th level pixel is completed, it will be controlled by the control module to enter the charge clearing stage only after the subsequent 3 levels of pixel rows have completed the quantization control.

[0164] When performing quantization control on the (k+3)th pixel row, the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows is... <2> The drain voltage changes from high to low to establish a reset node. At this time, since both the (k+1)th and (k+2)th pixel rows have completed quantization control but have not yet entered the charge clearing stage (i.e., the transfer transistors tx in the pixel circuits of the (k+1)th and (k+2)th pixel rows are in the off state), the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows is turned off. <2> It will affect the two corresponding floating diffusion nodes (such as Figure 6 fd in<k+1> ,fd<k+2> ), two double-conversion gain transistors (such as Figure 6 DCG in<k+1> dcg<k+2> The corresponding LCG node () Figure 6 (Not shown), but it will not provide the photosensitive devices (such as pd) connected to the transmission transistor tx in the pixel circuits of the (k+1)th pixel row and the respective pixel circuits of the (k+2)th pixel row.<k+1> ,pd<k+2> Charging; therefore, the environment or behavior of establishing a reset node when performing quantization control on the (k+3)th pixel row is the same as that when performing quantization control on the (k+2)th pixel row, thus the reset transistor rst connected between the (k+1)th and (k+2)th pixel rows is activated. <2> The time or speed at which the reset node is established, and the reset transistor rst connected between the (k+3)th and (k+4)th level pixel rows. <3> The time or speed at which the reset node is established is the same;

[0165] Furthermore, when the quantization control of the (k+3)th pixel row is completed, the transmission transistor tx of the pixel circuit will be turned on after a delay of three address signals to enter the charge clearing stage. In other words, when the quantization control of the (k+3)th pixel is completed, it will be controlled by the control module to enter the charge clearing stage only after the subsequent three pixel rows have completed quantization control.

[0166] When performing quantization control on other pixel rows of the pixel array in this example, the situation of establishing a reset node can be deduced from the above content, and will not be repeated here.

[0167] In this example, the waveform diagram of the key node entering the charge clearing stage under the control of the control module can be found in [reference needed]. Figure 8 .

[0168] Furthermore, in some implementations, when the image sensor continuously captures multiple frames and there are short exposure frames followed by long exposure frames, the existence of shared reset transistors between pixel rows results in a shorter time required for a pixel row to complete exposure control corresponding to the first exposure frame (short exposure frame), but a longer time required to complete quantization control corresponding to the first exposure frame. Based on the aforementioned improvement of delaying the entry into the charge clearing stage provided in this embodiment, the time required for a pixel row to complete quantization control corresponding to the first exposure frame is further increased. This further delays the time when the subsequent control module controls the transmission transistors in the pixel circuits of the aforementioned pixel row to enter the charge clearing stage. Since the second exposure frame is a long exposure frame with a longer exposure time and a faster entry into the exposure stage, the possibility of logic problems is higher. For example, if the transmission transistors of the aforementioned pixel row are turned on during the exposure control of the second exposure frame, it will negatively affect the exposure and quantization of the second exposure frame. See [link to relevant documentation] for situations where the control module malfunctions during inter-frame control. Figure 9 , Figure 9 After the quantization control corresponding to the first frame (i.e., the first exposure frame) is completed in the a-level pixel row, before the address of the a+3 row (corresponding to the control result of the control signal) arrives (before the a-level pixel row enters the charge clearing stage corresponding to the first frame), the a-level pixel row has already entered the exposure control corresponding to the second frame (the second exposure frame). This ultimately causes the control signal lat_addb of the transmission transistor in the a-level pixel row to go from high to low when the address of the a+3 row of the first frame arrives, so as to turn on the transmission transistor in the a-level pixel row (so as to enter the charge clearing stage corresponding to the first frame), thereby affecting the a-level pixel row to perform the exposure corresponding to the second frame, causing a logic error.

[0169] To address the shortcomings of some implementation methods, the technical solution in this example, after the pixel row completes the quantization control corresponding to the first frame, stops outputting the control signal controlling the aforementioned pixel row to enter the charge clearing stage when the control module determines that there is an overlap between the first and second exposure frames. This keeps the transmission transistors in the pixel circuits of the aforementioned pixel row off, enabling normal execution of the exposure control corresponding to the second frame. Therefore, in the case of short exposure frames followed by long exposure frames, it avoids executing the exposure control corresponding to the second frame while the transmission transistors in the pixel row are on, thus ensuring that the pixel row can complete the exposure and quantization corresponding to the second frame as designed. The improved image sensor in this example performs inter-frame control as follows: Figure 10 As shown; where, after the pixel row completes the quantization control corresponding to the first frame, when the control module determines that there is an overlap between the first exposure frame and the second exposure frame, it stops outputting the control signal that controls the aforementioned pixel row to enter the charge clearing stage, so that the control signal lat_addb of the transmission transistor in the pixel circuit of the aforementioned pixel row does not flip, thereby preventing the transmission transistor in the pixel circuit of the aforementioned pixel row from flipping.

[0170] In one embodiment, the control module includes an inter-frame switching control circuit and a signal generation circuit. See also... Figure 3 The inter-frame switching control circuit includes a memory and a decision controller. See [link to relevant documentation]. Figure 5 The signal generation circuit includes a first AND gate, a second AND gate, a selector, and a latch.

[0171] The memory stores at least the exposure information of the first exposure frame and the exposure information of the second exposure frame. The determination controller is connected to the memory and the signal generation circuit. It is used to determine the inter-frame state based on the exposure information of the first and second exposure frames retrieved from the memory. When the inter-frame state is determined to be an overlap between the first and second exposure frames, it outputs a first frame control signal frame_ctrl_en1 (e.g., frame_ctrl_en1 is 0) to the signal generation circuit based on the control signal rp_add_en input from the determination controller's control signal interface. Alternatively, when the inter-frame state is determined to be any other state, it outputs a first frame control signal frame_ctrl_en2 (e.g., frame_ctrl_en2 is 1) to the signal generation circuit based on the control signal rp_add_en input from the determination controller's control signal interface.

[0172] Waveform diagrams of key nodes in the inter-frame switching control circuit can be found in [reference]. Figure 11 , Figure 11 The example shows that there is an overlap between the first exposure frame and the second exposure frame in frame2 (i.e., the first frame) to frame3 (i.e., the second frame), so the frame_ctrl_en output is frame_ctrl_en1, which represents 0; for other inter-frame states, the frame_ctrl_en output is frame_ctrl_en2, which represents 1.

[0173] The first AND gate includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first AND gate receives the first control signal rp_add.<a+3> The second input of the first AND gate receives either the first frame control signal `frame_ctrl_en1` or the second frame control signal `frame_ctrl_en2`. The output of the first AND gate is connected to the first input of a selector and, through the output of the selector, to the first signal interface of a latch. Specifically, when the first AND gate receives the second frame control signal `frame_ctrl_en2` at its second input, it outputs the first control signal `rp_add`.<a+3> The first input of the selector can be used to enable / disable the output of the first AND gate when the first frame control signal frame_ctrl_en1 is received at its second input, thus preventing the output of the first control signal rp_add.<a+3> .

[0174] The second AND gate includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second AND gate receives the second control signal rp_add. <a-3>The second input of the second AND gate receives either the first frame control signal `frame_ctrl_en1` or the second frame control signal `frame_ctrl_en2`. The output of the second AND gate is connected to the second input of a selector and, through the selector's output, to the first signal interface of a latch. Specifically, when the second AND gate receives the second frame control signal `frame_ctrl_en2` at its second input, it outputs the second control signal `rp_add`. <a-3>The output of the second AND gate is enabled and disabled when the first frame control signal frame_ctrl_en1 is received at its second input, thus preventing the output of the second control signal rp_add. <a-3>.

[0175] The selector is driven by the enable signal dd_flip_en connected to its enable terminal, and receives the first control signal rp_add at its first input terminal.<a+3> Output it through its output terminal, or receive the second control signal rp_add from its second input terminal. <a-3>The output is made through its output terminal; or, the output terminal is turned off when both its first and second input terminals receive a control signal.

[0176] When the output of the selector is turned off, the latch cannot receive control signals. Therefore, the control signal lat_addb of the transmission transistor for the pixel row output by the latch will not flip. The control signal lat_addb of the transmission transistor for the pixel row output by the latch will only flip after the control signal rp_add of the second frame takes effect, so as to enter the charge clearing stage corresponding to the second frame.

[0177] It should be understood that when the second input terminal of the first AND gate or the second AND gate receives the second frame control signal frame_ctrl_en2 representing 1, the output terminal of the first AND gate or the second AND gate can output a control signal to the latch through a selector. The control signal lat_addb of the transmission transistor of the pixel row output by the latch is flipped so that after the first frame completes the quantization control, it enters the charge clearing stage after delaying by 3 rows of addresses.

[0178] Thus, the technical solution of this example enables the image sensor to avoid logic problems when performing quantization corresponding to short exposure frames and quantization corresponding to long exposure frames. Furthermore, it ensures that the environment or behavior of the reset transistor establishing the reset node when each pixel row in the pixel array is quantized is as similar or identical as possible to the environment or behavior of the reset transistor establishing the reset node when other pixel rows are quantized. This allows the image sensor to maintain a consistent time or speed for establishing reset nodes between different pixel rows during line-by-line quantization. Therefore, the technical solution of this example enables the image sensor to perform quantization more effectively and obtain better images.

[0179] Based on the same inventive concept as the foregoing embodiments, see [link to previous document]. Figure 12 This application provides a control method for an image sensor, the image sensor including a pixel array and a control module, the pixel array including multiple pixel rows including pixel circuits; the control method includes the following steps:

[0180] S11: Determine the inter-frame state based on the exposure information of the first exposure frame and the exposure information of the second exposure frame.

[0181] S12: When it is determined that there is an overlap between the first exposure frame and the second exposure frame in the inter-frame state, after completing the quantization control corresponding to the first exposure frame for the pixel row, during the process of performing the exposure control corresponding to the second exposure frame for the pixel row, the transmission transistor in the pixel circuit of the control pixel row is kept off.

[0182] In one embodiment, when there is an overlap between the first exposure frame and the second exposure frame, the first exposure frame is a short exposure frame and the second exposure frame is a long exposure frame.

[0183] In one embodiment, the image sensor includes a pixel array, a control module, and a data line. The pixel array includes multiple pixel units and multiple reset transistors. Each pixel unit includes a first pixel circuit, a second pixel circuit, and a row selection transistor. The first pixel circuit and the second pixel circuit in the pixel unit are connected to the data line through the same row selection transistor. The first pixel circuit is connected to a shared pixel unit through a reset transistor, and the second pixel circuit is connected to the shared pixel unit through a reset transistor.

[0184] In one embodiment, step S11: after determining the inter-frame state based on the exposure information of the first exposure frame and the exposure information of the second exposure frame, further includes: when the inter-frame state is determined to be another state, after completing the quantization control corresponding to the first exposure frame for the pixel row including the pixel circuit, controlling the pixel row to enter the charge clearing stage, and / or controlling the pixel row to perform the exposure control corresponding to the second exposure frame after the charge clearing stage is completed.

[0185] In one embodiment, step S12: when it is determined that there is an overlap between the first exposure frame and the second exposure frame in the inter-frame state, after completing the quantization control corresponding to the first exposure frame for the pixel row including the pixel circuit, and after controlling the transmission transistor in the pixel circuit of the pixel row to remain off during the exposure control corresponding to the second exposure frame performed by the pixel row, the step includes: when the pixel row completes the exposure control and quantization control corresponding to the second exposure frame, controlling the pixel row to enter the charge clearing stage.

[0186] In one embodiment, controlling a pixel row to enter the charge clearing stage includes: controlling the pixel row to enter the charge clearing stage with a delay time, wherein the delay time is greater than or equal to the time required for a first preset number of other pixel rows that follow the pixel row in the quantization order to complete at least one quantization control.

[0187] The image sensor control method provided in this application embodiment can avoid logic problems when the image sensor performs quantization corresponding to short exposure frames and quantization corresponding to long exposure frames. Furthermore, it aims to make the environment or behavior of the reset transistor establishing the reset node when each pixel row in the pixel array performs quantization control similar or identical to the environment or behavior of the reset transistor establishing the reset node when other pixel rows perform quantization control. This ensures that the time or speed at which the image sensor establishes the reset node between different pixel rows remains as consistent as possible during line-by-line quantization. Therefore, the image sensor control method provided in this application embodiment enables the image sensor to better complete quantization and obtain better images.

[0188] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0189] In this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0190] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims. < / k> < / k> < / k> < / k> < / k>

Claims

1. An image sensor, characterized in that, The system includes a pixel array and a control module. The pixel array comprises multiple pixel rows including pixel circuits, and the control module includes an inter-frame switching control circuit, wherein: The inter-frame switching control circuit determines the inter-frame state based on the exposure information of the first exposure frame and the exposure information of the second exposure frame. When there is an overlap between the first exposure frame and the second exposure frame, the control module is used to control the transmission transistor in the pixel circuit of the pixel row to remain off during the process of the pixel row performing quantization control corresponding to the first exposure frame and the pixel row performing exposure control corresponding to the second exposure frame.

2. The image sensor according to claim 1, characterized in that, When there is an overlap between the first exposure frame and the second exposure frame, the first exposure frame is a short exposure frame and the second exposure frame is a long exposure frame.

3. The image sensor according to claim 1, characterized in that, The inter-frame switching control circuit determines the inter-frame state based on the exposure information of the first exposure frame and the exposure information of the second exposure frame. When there is no overlap between the first exposure frame and the second exposure frame, the control module is used to control the pixel row to enter the charge clearing stage when the pixel row to which the pixel circuit belongs completes the quantization control corresponding to the first exposure frame, and / or control the pixel row to perform the exposure control corresponding to the second exposure frame after the charge clearing stage is completed.

4. The image sensor according to claim 1, characterized in that, The control module also includes a signal generation circuit, and the inter-frame switching control circuit includes a memory and a decision controller; The memory stores at least the exposure information of the first exposure frame and the exposure information of the second exposure frame; The determination controller is connected to the memory and the signal generation circuit, and is used to determine the inter-frame state based on the exposure information of the first exposure frame and the exposure information of the second exposure frame obtained from the memory. When the inter-frame state is determined to be that there is an overlap between the first exposure frame and the second exposure frame, a first frame control signal is output to the signal generation circuit; or when the inter-frame state is determined to be that there is no overlap between the first exposure frame and the second exposure frame, a second frame control signal is output to the signal generation circuit. The signal generation circuit is used to control the transmission transistor in the pixel circuit of the pixel row to remain off based on the first frame control signal after the pixel row completes the quantization control corresponding to the first exposure frame and during the exposure control of the pixel row corresponding to the second exposure frame. or, The signal generation circuit is used to control the pixel row to enter the charge clearing stage based on the second frame control signal when the pixel row completes the quantization control corresponding to the first exposure frame, and / or control the pixel row to perform exposure control corresponding to the second exposure frame after the end of the charge clearing stage.

5. The image sensor according to claim 4, characterized in that, The signal generation circuit is used to output a control signal to control the pixel row to enter the charge clearing stage according to the delay time. Wherein, the delay time is greater than or equal to the time required for at least one quantization control to be completed for the first preset number of other pixel rows following the pixel row in quantization order.

6. The image sensor according to claim 5, characterized in that, The signal generation circuit includes a latch and an AND gate; The control module is also used to provide a second preset number of first address signals in an orderly manner, wherein the second preset number is greater than or equal to the number of pixel rows corresponding to the pixel array; The AND gate includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the AND gate receives a control signal, the second input terminal of the AND gate receives either the first frame control signal or the second frame control signal, and the output terminal of the AND gate is connected to the first signal interface of the latch. The control signal is a first address signal selected by the control module according to a preset selection rule. The AND gate is used to output a control signal through its output terminal when it receives the second frame control signal at its second input terminal, so that when the latch receives the control signal, it controls the pixel row to enter the charge clearing stage according to the delay time. The AND gate is also used to stop outputting control signals when it receives the first frame control signal at its second input, so that the latch controls the transmission transistors in the pixel circuit of the pixel row to remain off when it does not receive a control signal.

7. The image sensor according to claim 6, characterized in that, The signal generation circuit includes a first AND gate and a second AND gate, and the signal generation circuit also includes a selector; The first AND gate includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first AND gate receives a first control signal. The second input terminal of the first AND gate receives either the first frame control signal or the second frame control signal. The output terminal of the first AND gate is connected to the first input terminal of the selector and connected to the first signal interface of the latch through the output terminal of the selector. The first control signal is the first address signal corresponding to the first preset number of positions pushed back in sequence. The second AND gate includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second AND gate receives a second control signal, and the second input terminal of the second AND gate receives either the first frame control signal or the second frame control signal. The output terminal of the second AND gate is connected to the second input terminal of the selector and connected to the first signal interface of the latch through the output terminal of the selector. The first control signal is the first address signal corresponding to the first preset number of positions after advancing in reverse order. The first AND gate is used to output the first control signal to the first input of the selector through its output when it receives the second frame control signal at its second input, or to stop outputting the first control signal to the first input of the selector when it receives the first frame control signal at its second input. The second AND gate is used to output the second control signal to the second input of the selector through its output when it receives the second frame control signal at its second input, or to stop outputting the second control signal to the second input of the selector when it receives the first frame control signal at its second input; The selector is used to be driven by an enable signal connected to its enable terminal to output the first control signal received at its first input terminal through its output terminal, or to output the second control signal received at its second input terminal through its output terminal. The latch is used to control the pixel row to enter the charge clearing stage according to the delay time when the first control signal or the second control signal is received, or to control the transmission transistor in the pixel circuit of the pixel row to remain off when the first control signal or the second control signal is not received.

8. The image sensor according to claim 6 or 7, characterized in that, The control module further includes a control circuit, which includes multiple control circuit units. The signal generation circuit is included in the control circuit unit, and the control circuit unit is connected to the pixel row of the pixel array. The control circuit unit is used to control the transmission transistor in the pixel circuit of the pixel row to which the latch in the signal generation circuit is connected when the latch receives a control signal, so that the pixel row to which it is connected enters the charge clearing stage according to a delay time; or... The control circuit unit is used to control the transmission transistor in the pixel circuit of the pixel row to remain off when the latch in the signal generation circuit does not receive a control signal.

9. The image sensor according to claim 1, characterized in that, The pixel array includes multiple pixel units and multiple reset transistors. Each pixel unit includes a first pixel circuit and a second pixel circuit belonging to different pixel rows. The first pixel circuit in the pixel unit is connected to the shared pixel unit via a reset transistor, and the second pixel circuit is connected to the shared pixel unit via a reset transistor.

10. The image sensor according to claim 9, characterized in that, The pixel unit further includes a row selection transistor, and the first pixel circuit and the second pixel circuit in the pixel unit are connected to a data line through the same row selection transistor.

11. The image sensor according to claim 9, characterized in that, The pixel array further includes at least one of a first boundary unit and a second boundary unit; The first pixel circuit is connected to the shared pixel unit or the first boundary unit via a reset transistor; The second pixel circuit is connected to the shared pixel unit or the second boundary unit via a reset transistor.

12. The image sensor according to claim 9, characterized in that, The pixel unit further includes a row selection transistor, and the first pixel circuit and the second pixel circuit belong to two pixel rows in the pixel array, respectively. The first pixel circuit includes a first optoelectronic device, a first transmission transistor, a first floating diffusion node, a first source follower transistor, and a first dual-conversion gain transistor; The control terminal of the first transmission transistor receives a control signal, and the two terminals of the first transmission transistor are respectively connected to the first optoelectronic device and the first floating diffusion node; The control terminal of the first source follower transistor is connected to the first floating diffusion node, the second path terminal of the first source follower transistor is connected to the data line through the two path terminals of the row select transistor, the first path terminal of the first source follower transistor receives a power signal, and the control terminal of the row select transistor receives a control signal. The control terminal of the first dual-conversion-gain transistor receives a control signal, and the first path terminal of the first dual-conversion-gain transistor is connected to the shared pixel unit or the first boundary unit through the second path terminal of a reset transistor. The second path terminal of the first dual-conversion-gain transistor is connected to the first floating diffusion node. The control terminal of the reset transistor receives a control signal, and the first path terminal of the reset transistor receives a charging signal. The second pixel circuit includes a second optoelectronic device, a second transmission transistor, a second floating diffusion node, a second source follower transistor, and a second dual-conversion gain transistor; The control terminal of the second transmission transistor receives a control signal, and the two terminals of the second transmission transistor are respectively connected to the second optoelectronic device and the second floating diffusion node; The control terminal of the second source follower transistor is connected to the second floating diffusion node, the second path terminal of the second source follower transistor is connected to the data line through the two path terminals of the row select transistor, and the first path terminal of the second source follower transistor receives the power signal. The control terminal of the second dual-conversion-gain transistor receives a control signal, the second path terminal of the second dual-conversion-gain transistor is connected to the second floating diffusion node, and the first path terminal of the second dual-conversion-gain transistor is connected to the shared pixel unit or second boundary unit through the second path terminal of another reset transistor; wherein, the control terminal of the other reset transistor receives a control signal, and the first path terminal of the other reset transistor receives a charging signal.

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