Electrostatic protection circuit and semiconductor chip

Abstract

This application provides an electrostatic discharge (ESD) protection circuit and a semiconductor chip. The circuit includes: a first ESD protection module, a second ESD protection module, and a current limiting module. The first and second ESD protection modules each have at least one voltage divider and at least one conducting device. The input terminal of the first ESD protection module is connected to an input port, and its output terminal is connected to the first terminal of the current limiting module. The first terminal of the first ESD protection module is connected to a power supply voltage, and its second terminal is grounded. The input terminal of the second ESD protection module is connected to the second terminal of the current limiting module, and its output terminal is connected to the circuit to be protected. The first terminal of the second ESD protection module is connected to a power supply voltage, and its second terminal is grounded. The voltage divider is used to reduce the trigger voltage of the conducting device. The conducting device is used to conduct and discharge static electricity, thereby improving ESD protection performance.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically, to an electrostatic discharge protection circuit and a semiconductor chip. Background Technology

[0002] Electrostatic discharge (ESD) often occurs during chip manufacturing, packaging, and testing. The peak current generated during ESD discharge can reach several amperes, and the peak voltage can reach tens of thousands of volts. The instantaneous impact of high-energy electrostatic discharge can generate a large amount of heat inside the chip, which can easily cause the circuit components inside the chip to be damaged due to overheating, leading to permanent chip failure.

[0003] Currently, in traditional electrostatic discharge (ESD) protection designs, MOS devices are small in size, have low overcurrent capability, and have unreasonable layout design, resulting in poor ESD protection performance.

[0004] Therefore, existing electrostatic protection designs have certain limitations. Utility Model Content

[0005] The purpose of this application is to address the shortcomings of the prior art by providing an electrostatic discharge (ESD) protection circuit and semiconductor chip, thereby solving the practical problem of limitations in existing ESD protection designs.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0007] In a first aspect, embodiments of this application provide an electrostatic discharge (ESD) protection circuit, the circuit comprising: a first ESD protection module, a second ESD protection module, and a current limiting module; the first ESD protection module and the second ESD protection module are respectively provided with at least one voltage divider device and at least one conducting device.

[0008] The input terminal of the first electrostatic discharge protection module is connected to the input port, the output terminal of the first electrostatic discharge protection module is connected to the first terminal of the current limiting module, the first terminal of the first electrostatic discharge protection module is connected to the power supply voltage, and the second terminal of the first electrostatic discharge protection module is grounded.

[0009] The input terminal of the second electrostatic discharge protection module is connected to the second terminal of the current limiting module, the output terminal of the second electrostatic discharge protection module is connected to the circuit to be protected, the first terminal of the second electrostatic discharge protection module is connected to the power supply voltage, and the second terminal of the second electrostatic discharge protection module is grounded.

[0010] The voltage divider in the first electrostatic discharge (ESD) protection module is used to reduce the trigger voltage of the conducting device in the first ESD protection module; the voltage divider in the second ESD protection module is used to reduce the trigger voltage of the conducting device in the second ESD protection module.

[0011] The conducting device in the first electrostatic discharge protection module and the conducting device in the second electrostatic discharge protection module are respectively used to conduct and discharge static electricity.

[0012] As an optional implementation, the first electrostatic discharge (ESD) protection module includes: a first ESD protection unit and a second ESD protection unit;

[0013] The first terminal of the first electrostatic protection unit is connected to the power supply voltage, and the second terminal of the first electrostatic protection unit is connected to the input port, the first terminal of the current limiting module, and the first terminal of the second electrostatic protection unit, respectively.

[0014] The second terminal of the second electrostatic protection unit is grounded;

[0015] The first electrostatic discharge protection unit includes a first voltage divider device and a first conducting device; the second electrostatic discharge protection unit includes a second voltage divider device and a second conducting device.

[0016] As an optional implementation, the second electrostatic discharge (ESD) protection module includes: a third ESD protection unit and a fourth ESD protection unit;

[0017] The first terminal of the third electrostatic protection unit is connected to the power supply voltage, and the second terminal of the third electrostatic protection unit is connected to the second terminal of the current limiting module, the circuit to be protected, and the first terminal of the fourth electrostatic protection unit.

[0018] The second terminal of the fourth electrostatic protection unit is grounded;

[0019] The third electrostatic discharge protection unit includes a third voltage divider and a third conducting device; the fourth electrostatic discharge protection unit includes a fourth voltage divider and a fourth conducting device.

[0020] As an optional implementation, the first voltage divider includes a first resistor; the first conducting device includes a first P-channel metal-oxide-semiconductor field-effect transistor.

[0021] The source of the first P-channel metal-oxide-semiconductor field-effect transistor and one end of the first resistor are connected to the supply voltage;

[0022] The gate of the first P-channel metal-oxide-semiconductor field-effect transistor is connected to the other end of the first resistor.

[0023] The drain of the first P-channel metal-oxide-semiconductor field-effect transistor is connected to the input port, the first terminal of the current limiting module, and the first terminal of the second electrostatic protection unit, respectively.

[0024] As an optional implementation, the first P-channel metal-oxide-semiconductor field-effect transistor includes multiple source structures, multiple drain structures, and a gate structure. The source structures and the drain structures are interdigitated, and all of the multiple drain structures are connected to a first metal.

[0025] The distance between the first metal and the gate structure is greater than a first preset value;

[0026] The area of ​​each drain structure is greater than the second preset value.

[0027] As an optional implementation, the second voltage divider includes a second resistor; the second conducting device includes a first N-channel metal-oxide-semiconductor field-effect transistor.

[0028] The drain of the first N-channel metal-oxide-semiconductor field-effect transistor is connected to the input port, the first terminal of the current limiting module, and the second terminal of the first electrostatic protection unit, respectively.

[0029] The gate of the first N-channel metal-oxide-semiconductor field-effect transistor is connected to one end of the second resistor;

[0030] The source of the first N-channel metal-oxide-semiconductor field-effect transistor and the other end of the second resistor are grounded.

[0031] As an optional implementation, the third voltage divider includes a third resistor; the third conducting device includes a second P-channel metal-oxide-semiconductor field-effect transistor.

[0032] The source of the second P-channel metal-oxide-semiconductor field-effect transistor and one end of the third resistor are connected to the supply voltage;

[0033] The gate of the second P-channel metal-oxide-semiconductor field-effect transistor is connected to the other end of the third resistor;

[0034] The drain of the second P-channel metal-oxide-semiconductor field-effect transistor is connected to the second terminal of the current limiting module, the circuit to be protected, and the first terminal of the fourth electrostatic protection unit, respectively.

[0035] As an optional implementation, the fourth voltage divider device includes a fourth resistor; the fourth conducting device includes a second N-channel metal-oxide-semiconductor field-effect transistor.

[0036] The drain of the second N-channel metal-oxide-semiconductor field-effect transistor is connected to the second terminal of the current limiting module, the circuit to be protected, and the second terminal of the third electrostatic protection unit, respectively.

[0037] The gate of the second N-channel metal-oxide-semiconductor field-effect transistor is connected to one end of the fourth resistor;

[0038] The source of the second N-channel metal-oxide-semiconductor field-effect transistor and the other end of the fourth resistor are grounded.

[0039] Secondly, embodiments of this application provide an electrostatic protection layout structure, the layout structure including at least: a first layout area, a second layout area, a third layout area, and a fourth layout area;

[0040] The second map area is located below the first map area, the third map area is located to the right of the first map area, and the fourth map area is located below the third map area;

[0041] The first layout area is a first P-channel metal-oxide-semiconductor field-effect transistor layout area, the second layout area is a first N-channel metal-oxide-semiconductor field-effect transistor layout area, the third layout area is a second P-channel metal-oxide-semiconductor field-effect transistor layout area, and the fourth layout area is a second N-channel metal-oxide-semiconductor field-effect transistor layout area.

[0042] The first P-channel metal-oxide-semiconductor field-effect transistor layout region includes multiple source structures, multiple drain structures, and a first gate structure. The source structures and drain structures are interdigitated, and all of the multiple drain structures are connected to a first metal. The distance between the first metal and the gate structure is greater than a first preset value. The area of ​​each drain structure is greater than a second preset value.

[0043] The first N-channel metal-oxide-semiconductor field-effect transistor layout region includes multiple source structures, multiple drain structures, and a gate structure. The source structures and drain structures are interdigitated, and all of the multiple drain structures are connected to a second metal. The distance between the second metal and the gate structure is greater than a third preset value. The area of ​​each drain structure is greater than a fourth preset value.

[0044] Thirdly, embodiments of this application provide a semiconductor chip, including the electrostatic discharge protection circuit described in the first aspect above and a circuit to be protected connected to the electrostatic discharge protection circuit.

[0045] The beneficial effects of this application are:

[0046] This application provides an electrostatic discharge (ESD) protection circuit and a semiconductor chip. The ESD protection circuit includes a first ESD protection module, a second ESD protection module, and a current limiting module. The ESD protection circuit employs a two-stage protection structure, with the first ESD protection module serving as the first-stage protection structure and the second ESD protection module serving as the second-stage protection structure. Each of the first and second ESD protection modules contains at least one voltage divider and at least one conducting device. The input terminal of the first ESD protection module is connected to an input port, and its output terminal is connected to the first terminal of the current limiting module. The first terminal of the first ESD protection module is connected to a power supply voltage, and its second terminal is grounded. The input terminal of the second ESD protection module is connected to the second terminal of the current limiting module, and its output terminal is connected to the circuit to be protected. The first terminal of the second ESD protection module is connected to a power supply voltage, and its second terminal is grounded. By using the voltage divider in the first and second ESD protection modules to reduce the trigger voltage of the conducting devices in both modules, the trigger voltages of the conducting devices in the first and second ESD protection modules are reduced, allowing them to quickly conduct and discharge static electricity to ground when an ESD pulse occurs. A two-stage protection structure is adopted to provide electrostatic protection for the circuit under protection. By using a voltage divider device to reduce the trigger voltage of the conducting device, the electrostatic current is discharged as soon as possible, thereby improving the electrostatic protection performance. Attached Figure Description

[0047] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of the electrostatic protection circuit provided in the embodiments of this application;

[0049] Figure 2 This is another schematic diagram of the electrostatic protection circuit provided in the embodiments of this application;

[0050] Figure 3 Another structural schematic diagram of the electrostatic protection circuit provided in the embodiments of this application;

[0051] Figure 4 This is a schematic diagram of the electrostatic protection layout structure provided in the embodiments of this application;

[0052] Figure 5 Another schematic diagram of the electrostatic protection layout provided in the embodiments of this application.

[0053] Icons: First ESD Protection Module: 1; Second ESD Protection Module: 2; Current Limiting Module: 3; Voltage Divider: 4; Conducting Device: 5; Circuit to be Protected: 6; First ESD Protection Unit: 11; Second ESD Protection Unit: 12; First Voltage Divider: 111; First Conducting Device: 112; Second Voltage Divider: 171; Second Conducting Device: 172; Third ESD Protection Unit: 21; Fourth ESD Protection Unit: 22; Third Voltage Divider: 211; Third Conducting Device: 212; Fourth Voltage Divider: 221; Fourth Conducting Device: 222; First Resistor: R1; First PMOS Transistor: PM1; Second Resistor: R2; First NMOS Transistor: NM1; Third Resistor: R3; Second PMOS Transistor: PM2; Fourth Resistor: R4; Second NMOS Transistor: NM2; Current Limiting Resistor: R5; First Layout Area: 71; Second Layout Area: 72; Third Layout Area: 73; Fourth Layout Area: 74. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0055] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0056] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In the description of this application, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0057] In the description of this application, unless otherwise expressly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0058] In the semiconductor field, ESD (Electrostatic Discharge) phenomena frequently occur during chip manufacturing, packaging, and testing. ESD discharge can easily lead to permanent chip failure; therefore, electrostatic protection is necessary. In the CM30 process, because the CM30 process library does not provide standard ESD devices, the high-voltage transistors used in the ESD protection structure are of the same type as those in the internal circuitry, resulting in identical breakdown voltages, which does not conform to the rules of ESD protection structures. Currently, in the CM30 process, traditional ESD protection designs often use small-sized MOS devices with low overcurrent capability and unreasonable layout design, resulting in poor ESD protection performance and certain limitations.

[0059] Based on the aforementioned problems, this application proposes an electrostatic discharge (ESD) protection circuit. A voltage divider resistor is connected between the gate and source of each Metal-Oxide-Semiconductor Field-Effect Transistor (MOS) in the two-stage ESD protection module. This reduces the trigger voltage of each MOS transistor, allowing them to conduct at a lower voltage and quickly discharge electrostatic current, thus reducing the impact of ESD events on the internal circuitry and providing better ESD protection. Furthermore, increasing the distance between the gate and drain structures of each MOS transistor and widening the drain structure improves the voltage withstand capability and current discharge capability of each MOS transistor, thereby enhancing ESD protection performance.

[0060] Figure 1 This is a schematic diagram of the electrostatic protection circuit provided in the embodiments of this application, such as... Figure 1 As shown, the electrostatic discharge (ESD) protection circuit includes: a first ESD protection module 1, a second ESD protection module 2, and a current limiting module 3; the first ESD protection module 1 and the second ESD protection module 2 are respectively provided with at least one voltage divider device 4 and at least one conducting device 5.

[0061] Optionally, refer to Figure 1 The electrostatic discharge (ESD) protection circuit includes three modules: a first ESD protection module 1, a second ESD protection module 2, and a current limiting module 3. The first ESD protection module 1 and the second ESD protection module 2 are both connected to the current limiting module 3, and each of the first ESD protection module 1 and the second ESD protection module 2 contains at least one voltage divider device 4 and at least one conducting device 5. Figure 1 For example, both the first electrostatic protection module 1 and the second electrostatic protection module 2 are equipped with two voltage divider devices 4 and two conducting devices 5.

[0062] The input terminal of the first electrostatic discharge protection module 1 is connected to the input port, the output terminal of the first electrostatic discharge protection module 1 is connected to the first terminal of the current limiting module 3, the first terminal of the first electrostatic discharge protection module 1 is connected to the power supply voltage, and the second terminal of the first electrostatic discharge protection module 1 is grounded.

[0063] Optionally, continue to refer to Figure 1 The input terminal of the first electrostatic discharge (ESD) protection module 1 is connected to input port IO_1 to receive input signals. The first terminal of the first ESD protection module 1 is connected to the power supply voltage VDD, which provides electrical energy to the module. The output terminal of the first ESD protection module 1 is connected to the first terminal of the current limiting module 3, which limits the output current of the module. The second terminal of the first ESD protection module 1 is grounded, providing a discharge path for the electrostatic current and preventing the accumulation of electrostatic charge in the circuit.

[0064] The input terminal of the second electrostatic discharge protection module 2 is connected to the second terminal of the current limiting module 3, the output terminal of the second electrostatic discharge protection module 2 is connected to the circuit to be protected 6, the first terminal of the second electrostatic discharge protection module 2 is connected to the power supply voltage, and the second terminal of the second electrostatic discharge protection module 2 is grounded.

[0065] Optionally, continue to refer to Figure 1 The input terminal of the second electrostatic discharge (ESD) protection module 2 is connected to the second terminal of the current limiting module 3, and the output terminal is connected to the internal circuit to be protected 6. This ensures that the current flowing from the second ESD protection module 2 into the circuit to be protected is safe and stable, preventing damage to the circuit to be protected from excessive current. The first terminal of the second ESD protection module 2 is connected to the power supply voltage VDD, which also provides power to the second ESD protection module 2. The second terminal of the second ESD protection module 2 is grounded, providing another discharge path for the electrostatic current and preventing the accumulation of electrostatic charge in the circuit.

[0066] The voltage divider 4 in the first electrostatic discharge protection module 1 is used to reduce the trigger voltage of the conducting device 5 in the first electrostatic discharge protection module 1; the voltage divider 4 in the second electrostatic discharge protection module 2 is used to reduce the trigger voltage of the conducting device 5 in the second electrostatic discharge protection module 2.

[0067] Optionally, continue to refer to Figure 1 When an ESD pulse arrives, the voltage divider 4 in the first electrostatic discharge (ESD) protection module 1 reduces the trigger voltage of the conducting device 5, causing it to turn on quickly. This allows the conducting device 5 to conduct at a lower voltage, discharging the electrostatic current and reducing the impact of the ESD event on the protection circuit 6. Similarly, the voltage divider 4 in the second ESD protection module 2 reduces the trigger voltage of the conducting device 5, causing it to turn on quickly. This also allows the conducting device 5 to conduct at a lower voltage, discharging the electrostatic current and reducing the impact of the ESD event on the protection circuit 6, thus providing better ESD protection.

[0068] The conducting device 5 in the first electrostatic discharge protection module 1 and the conducting device 5 in the second electrostatic discharge protection module 2 are used to conduct and discharge static electricity.

[0069] Optionally, continue to refer to Figure 1 The conducting device 5 in the first electrostatic discharge (ESD) protection module 1, while reducing its trigger voltage with the voltage divider device 4 in the same module, can respond to ESD pulses in a shorter time and discharge electrostatic current to ground more quickly, thereby reducing the impact of electrostatic energy on the circuit to be protected 6. As the first-stage ESD protection structure in the ESD protection circuit, the first ESD protection module 1 can prevent Human-Body-Model (HBM) events. When an HBM event occurs, the first ESD protection module 1 can respond quickly and bypass most of the electrostatic current to ground, thus protecting the internal circuit to be protected 6 from excessive voltage and current. The first ESD protection module 1 is the first to withstand ESD impacts, providing primary protection for the circuit to be protected 6.

[0070] Correspondingly, the conducting device 5 in the second electrostatic discharge (ESD) module 2, under the premise that the voltage divider device 4 in the second ESD protection module 2 reduces its trigger voltage, responds to the ESD pulse in a shorter time and discharges the electrostatic current to ground more quickly, thereby reducing the impact of electrostatic energy on the circuit to be protected 6. The second ESD protection module 2, as the second-level ESD protection structure in the ESD protection circuit, can prevent Charged-Device Model (CDM) events. Due to the special nature of CDM events, the first-level ESD protection structure, i.e., the first ESD protection module 1, may not be able to fully cope. The second-level protection structure, i.e., the second ESD protection module 2, can further protect the circuit to be protected 6 on the basis of the first-level protection structure, safely releasing the remaining electrostatic energy and ensuring that the internal circuit to be protected 6 can still operate normally under CDM events.

[0071] In this embodiment, the electrostatic discharge (ESD) protection circuit includes a first ESD protection module, a second ESD protection module, and a current limiting module. The ESD protection circuit employs a two-stage protection structure, with the first ESD protection module serving as the first-stage protection structure and the second ESD protection module as the second-stage protection structure. Each of the first and second ESD protection modules contains at least one voltage divider and at least one conducting device. The input terminal of the first ESD protection module is connected to an input port, and its output terminal is connected to the first terminal of the current limiting module. The first terminal of the first ESD protection module is connected to the power supply voltage, and its second terminal is grounded. The input terminal of the second ESD protection module is connected to the second terminal of the current limiting module, and its output terminal is connected to the circuit to be protected. The first terminal of the second ESD protection module is connected to the power supply voltage, and its second terminal is grounded. By using the voltage divider in the first and second ESD protection modules to reduce the trigger voltage of the conducting devices in both modules, the trigger voltages of the conducting devices in the first and second ESD protection modules are reduced, allowing them to quickly conduct and discharge static electricity to ground when an ESD pulse arrives. A two-stage protection structure is adopted to provide electrostatic protection for the circuit under protection. By using a voltage divider device to reduce the trigger voltage of the conducting device, the electrostatic current is discharged as soon as possible, thereby improving the electrostatic protection performance.

[0072] Figure 2 Another schematic diagram of the electrostatic protection circuit provided in the embodiments of this application is shown below. Figure 2 As shown, the first electrostatic discharge protection module 1 includes: a first electrostatic discharge protection unit 11 and a second electrostatic discharge protection unit 12.

[0073] Optionally, refer to Figure 2 The first electrostatic discharge (ESD) protection module 1 includes two units: a first ESD protection unit 11 and a second ESD protection unit 12. The first ESD protection unit 11 and the second ESD protection unit 12 in the first ESD protection module 1 can provide ESD protection against ESD pulses of different polarities.

[0074] The first terminal of the first electrostatic discharge (ESD) protection unit 11 is connected to the power supply voltage. The second terminal of the first ESD protection unit 11 is connected to the input port, the first terminal of the current limiting module 3, and the first terminal of the second ESD protection unit 12. The second terminal of the second ESD protection unit 12 is grounded.

[0075] Optionally, continue to refer to Figure 2 The first terminal of the first electrostatic discharge (ESD) protection unit 11 serves as the first terminal of the first ESD protection module 1, and is connected to the power supply voltage VDD to obtain the electrical energy provided by the power supply voltage VDD. The second terminal of the first ESD protection unit 11 is connected to the input port IO_1, the first terminal of the current limiting module 3, and the first terminal of the second ESD protection unit 12, respectively. The second terminal of the second ESD protection unit 12 is grounded.

[0076] The first electrostatic discharge protection unit 11 and the second electrostatic discharge protection unit 12 can both directly monitor the electrostatic interference that occurs at the input port IO_1. For electrostatic interference of different polarities, the first electrostatic discharge protection unit 11 and the second electrostatic discharge protection unit 12 cooperate with each other to perform electrostatic protection, so that the static electricity is discharged to the ground.

[0077] The first electrostatic discharge protection unit 11 includes a first voltage divider device 111 and a first conducting device 112; the second electrostatic discharge protection unit 12 includes a second voltage divider device 171 and a second conducting device 172.

[0078] Optionally, continue to refer to Figure 2 The first electrostatic discharge (ESD) protection unit 11 includes a first voltage divider device 111 and a first conducting device 112. The first voltage divider device 111 reduces the trigger voltage of the first conducting device 112 by voltage division, thereby enabling the first conducting device 112 to conduct and discharge static electricity as quickly as possible. Correspondingly, the second ESD protection unit 12 includes a second voltage divider device 121 and a second conducting device 122. The second voltage divider device 121 reduces the trigger voltage of the second conducting device 122 by voltage division, thereby enabling the second conducting device 122 to conduct and discharge static electricity as quickly as possible.

[0079] In this embodiment, a first electrostatic discharge (ESD) protection unit and a second ESD protection unit are provided in the first ESD protection module. The first terminal of the first ESD protection unit is connected to the power supply voltage, and the second terminal is connected to the input port, the first terminal of the current limiting module, and the first terminal of the second ESD protection unit. The second terminal of the second ESD protection unit is grounded. Both ESD protection units can directly monitor electrostatic interference appearing at the input port and cooperate with each other to perform ESD protection. They provide ESD protection against ESD pulses of different polarities. Through a first voltage divider, a first conducting device, a second voltage divider, and a second conducting device, static electricity is discharged to ground as quickly as possible, achieving the first level of ESD protection for the circuit to be protected.

[0080] As an optional implementation, the second electrostatic discharge protection module 2 includes a third electrostatic discharge protection unit 21 and a fourth electrostatic discharge protection unit 22.

[0081] Optionally, continue to refer to Figure 2 The second electrostatic discharge (ESD) protection module 2 includes two units: a third ESD protection unit 21 and a fourth ESD protection unit 22. The third ESD protection unit 21 and the fourth ESD protection unit 22 can provide ESD protection against ESD pulses of different polarities.

[0082] The first terminal of the third electrostatic discharge (ESD) protection unit 21 is connected to the power supply voltage. The second terminal of the third ESD protection unit 21 is connected to the second terminal of the current limiting module 3, the circuit to be protected 6, and the first terminal of the fourth ESD protection unit 22. The second terminal of the fourth ESD protection unit 22 is grounded.

[0083] Optionally, continue to refer to Figure 2 The first terminal of the third electrostatic discharge protection unit 21 serves as the first terminal of the second electrostatic discharge protection module 2, and is connected to the power supply voltage VDD to obtain the electrical energy provided by the power supply voltage VDD. The second terminal of the third electrostatic discharge protection unit 21 is connected to the second terminal of the current limiting module 3, the circuit to be protected 6, and the first terminal of the fourth electrostatic discharge protection unit 22, respectively. The second terminal of the fourth electrostatic discharge protection unit 22 is grounded.

[0084] The third electrostatic discharge protection unit 21 and the fourth electrostatic discharge protection unit 22 can both indirectly monitor the electrostatic interference that occurs at the input port IO_1 through the current limiting module 3. For electrostatic interference of different polarities, the third electrostatic discharge protection unit 21 and the fourth electrostatic discharge protection unit 22 cooperate with each other to perform electrostatic protection, so that the electrostatic discharge is discharged to the ground.

[0085] The third electrostatic discharge protection unit 21 includes a third voltage divider device 211 and a third conducting device 212; the fourth electrostatic discharge protection unit 22 includes a fourth voltage divider device 221 and a fourth conducting device 222.

[0086] Optionally, continue to refer to Figure 2 The third electrostatic discharge (ESD) protection unit 21 includes a third voltage divider device 211 and a third conducting device 212. The third voltage divider device 211 reduces the trigger voltage of the third conducting device 212 by dividing the voltage, thereby enabling the third conducting device 212 to conduct and discharge static electricity as quickly as possible. Correspondingly, the fourth ESD protection unit 22 includes a fourth voltage divider device 221 and a fourth conducting device 222. The fourth voltage divider device 221 reduces the trigger voltage of the fourth conducting device 222 by dividing the voltage, thereby enabling the fourth conducting device 222 to conduct and discharge static electricity as quickly as possible.

[0087] In this embodiment, a third and a fourth electrostatic discharge (ESD) protection unit are configured in the second ESD protection module. The first terminal of the third ESD protection unit is connected to the power supply voltage, and the second terminal is connected to the second terminal of the current limiting module, the circuit to be protected, and the first terminal of the fourth ESD protection unit. The second terminal of the fourth ESD protection unit is grounded. Both ESD protection units can indirectly monitor electrostatic interference at the input port through the current limiting module and cooperate with each other to perform ESD protection. They provide ESD protection against ESD pulses of different polarities. Through the third voltage divider, the third conduction device, the fourth voltage divider, and the fourth conduction device, static electricity is discharged to ground as quickly as possible, achieving the second level of ESD protection for the circuit to be protected.

[0088] Figure 3 This is another schematic diagram of the electrostatic protection circuit provided in the embodiments of this application, as shown below. Figure 3 As shown, the first voltage divider device 111 includes a first resistor R1; the first conducting device 112 includes a first PMOS transistor PM1.

[0089] Optionally, refer to Figure 3 The first voltage divider device 111 includes a first resistor R1, and the first conducting device 112 includes a first PMOS transistor PM1. The first resistor R1 can be a resistor made of polysilicon. For example, the resistance value of the first resistor R1 can be 5K ohms.

[0090] The source of the first PMOS transistor PM1 and one end of the first resistor R1 are connected to the power supply voltage. The gate of the first PMOS transistor PM1 is connected to the other end of the first resistor R1. The drain of the first PMOS transistor PM1 is connected to the input port IO_1, the first end of the current limiting module 3, and the first end of the second electrostatic protection unit 12.

[0091] Optionally, continue to refer to Figure 3 The source of the first PMOS transistor PM1 and one end of the first resistor R1 both serve as the first terminal of the first electrostatic discharge (ESD) protection module 1 and the first terminal of the first ESD protection unit 11, respectively, and are connected to the power supply voltage VDD to obtain the electrical energy provided by the power supply voltage VDD. The other end of the first resistor R1 is connected to the gate of the first PMOS transistor PM1, and the drain of the first PMOS transistor PM1 serves as the second terminal of the first ESD protection unit 11, which is connected to the input port IO_1, the first terminal of the current limiting module 3, and the first terminal of the second ESD protection unit 12, respectively. It is worth noting that the current limiting module 3 may include a current limiting resistor R5, which limits the current. For example, the resistance value of the current limiting resistor R5 may be 300 ohms.

[0092] By connecting a first resistor R1 between the gate and source of the first PMOS transistor PM1, a certain voltage will be generated at the gate of the first PMOS transistor PM1 when an ESD high-voltage pulse arrives due to the presence of the first resistor R1. This voltage will cause the channel of the first PMOS transistor PM1 to turn on earlier, reducing the trigger voltage at which the first PMOS transistor PM1 starts conducting. A lower trigger voltage means that the first PMOS transistor PM1 can respond to the ESD pulse in a shorter time and discharge the electrostatic current to ground more quickly, achieving rapid electrostatic discharge.

[0093] In this embodiment, the first voltage divider includes a first resistor, and the first conducting device includes a first PMOS transistor. The source of the first PMOS transistor and one end of the first resistor are connected to a power supply voltage to obtain electrical energy. The gate of the first PMOS transistor is connected to the other end of the first resistor. The drain of the first PMOS transistor is connected to the input port, the first end of the current limiting module, and the first end of the second electrostatic protection unit. By connecting the first resistor between the gate and source of the first PMOS transistor, the trigger voltage for the first PMOS transistor to turn on is reduced, so that the first PMOS transistor can respond to the ESD pulse in a shorter time and discharge the electrostatic current to ground more quickly, thereby achieving rapid discharge of electrostatics.

[0094] As an optional implementation, the first PMOS transistor PM1 includes multiple source structures, multiple drain structures, and a gate structure. The source structures and drain structures are interdigitated, and the multiple drain structures are all connected to a first metal.

[0095] Optionally, the first PMOS transistor PM1 includes multiple source structures, multiple drain structures, and a gate structure. The source and drain structures of the first PMOS transistor PM1 are interdigitated to allow current to flow evenly into and out of the first PMOS transistor PM1. All drain structures are connected to a first metal, which connects the drain structures of the first PMOS transistor PM1 into a single unit.

[0096] The distance between the first metal and the gate structure is greater than a first preset value. The area of ​​each drain structure is greater than a second preset value.

[0097] Optionally, the distance between the first metal and the gate structure is greater than a first preset value, that is, the distance between the source structure and the gate structure of the first PMOS transistor PM1 is greater than the first preset value. Furthermore, the area of ​​each drain structure in the first PMOS transistor PM1 is greater than a second preset value. In other words, by ensuring that the distance between the drain structure and the gate structure of the first PMOS transistor PM1 is sufficiently large, and that the area of ​​each drain structure in the first PMOS transistor PM1 is sufficiently large, increasing the distance between the drain structure and the gate structure of the first PMOS transistor PM1, widening each drain structure, and increasing the area of ​​each drain structure can improve the breakdown voltage of the first PMOS transistor PM1, enhance its withstand voltage capability, and improve its current discharging capability.

[0098] For example, the aspect ratio of the first PMOS transistor PM1 can be 700 micrometers / 3 micrometers, and the first preset value can be 6 micrometers. Here, there are no specific restrictions on the aspect ratio, the first preset value, and the second preset value of the first PMOS transistor PM1.

[0099] In this embodiment, the first PMOS transistor includes multiple source structures, multiple drain structures, and a gate structure. The source and drain structures of the first PMOS transistor are interdigitated to allow current to flow evenly in and out of the transistor. All drain structures of the first PMOS transistor are connected to a first metal, and the distance between the first metal and the gate structure is greater than a first preset value. The area of ​​each drain structure is greater than a second preset value. This improves the breakdown voltage and withstand voltage of the first PMOS transistor, enhances its current dissipation capability, and thus improves its electrostatic discharge protection performance.

[0100] It is worth noting that the distance between the source and gate structures in the first NMOS transistor NM1, the second PMOS transistor PM2, and the second NMOS transistor NM2 is greater than a preset value, and the area of ​​each drain structure is greater than another preset value. This improves the voltage withstand capability and current discharge capability of the first NMOS transistor NM1, the second PMOS transistor PM2, and the second NMOS transistor NM2, which will not be elaborated here.

[0101] For example, the aspect ratio of the first NMOS transistor NM1 can be 500 micrometers / 3 micrometers, the aspect ratio of the second PMOS transistor PM2 can be 300 micrometers / 3 micrometers, and the aspect ratio of the second NMOS transistor NM2 can be 200 micrometers / 3 micrometers, without any specific limitations.

[0102] As an optional implementation, the second voltage divider device 121 includes a second resistor R3; the second conducting device 122 includes a first NMOS transistor NM1.

[0103] Optionally, continue to refer to Figure 3 The second voltage divider device 121 includes a second resistor R3, and the second conducting device 122 includes a first NMOS transistor NM1. The second resistor R3 can be a resistor made of Poly material. For example, the resistance value of the second resistor R3 can be 5K ohms.

[0104] The drain of the first NMOS transistor NM1 is connected to the input port, the first terminal of the current limiting module 3, and the second terminal of the first electrostatic protection unit 11. The gate of the first NMOS transistor NM1 is connected to one end of the second resistor R2. The source of the first NMOS transistor NM1 and the other end of the second resistor R2 are grounded.

[0105] Optionally, continue to refer to Figure 3The drain of the first NMOS transistor NM1 serves as the first terminal of the second electrostatic discharge (ESD) protection unit 12, and is connected to the input port IO_1, the first terminal of the current limiting module 3, and the second terminal of the first ESD protection unit 11, respectively. The gate of the first NMOS transistor NM1 is connected to one end of the second resistor R2, and the source of the first NMOS transistor NM1 and the other end of the second resistor R2 are both grounded as the second terminals of the first ESD protection module 1 and the second terminal of the second ESD protection unit 12.

[0106] By connecting a second resistor R2 between the gate and source of the first NMOS transistor NM1, a certain voltage will be generated at the gate of the first NMOS transistor NM1 when an ESD high-voltage pulse arrives due to the presence of the second resistor R2. This voltage will cause the channel of the first NMOS transistor NM1 to turn on earlier, reducing the trigger voltage at which the first NMOS transistor NM1 begins to conduct. A lower trigger voltage means that the first NMOS transistor NM1 can respond to the ESD pulse in a shorter time and discharge the electrostatic current to ground more quickly, achieving rapid electrostatic discharge.

[0107] In this embodiment, the second voltage divider device includes a second resistor, and the second conducting device includes a first NMOS transistor. The drain of the first NMOS transistor is connected to the input port, the first terminal of the current limiting module, and the second terminal of the first electrostatic discharge protection unit. The gate of the first NMOS transistor is connected to one end of the second resistor. The source of the first NMOS transistor and the other end of the second resistor are grounded. By connecting the second resistor between the gate and source of the first NMOS transistor, the trigger voltage for the first NMOS transistor to turn on is reduced, so that the first NMOS transistor can respond to the ESD pulse in a shorter time and discharge the electrostatic current to ground more quickly, thereby achieving rapid electrostatic discharge.

[0108] As an optional implementation, the third voltage divider device 211 includes a third resistor R3; the third conducting device 212 includes a second PMOS transistor PM2.

[0109] Optionally, continue to refer to Figure 3 The third voltage divider device 211 includes a third resistor R3, and the third conducting device 212 includes a second PMOS transistor PM2. The third resistor R3 can be a resistor made of Poly material. For example, the resistance value of the third resistor R3 can be 5K ohms.

[0110] The source of the second PMOS transistor PM2 and one end of the third resistor R3 are connected to the power supply voltage. The gate of the second PMOS transistor PM2 is connected to the other end of the third resistor R3. The drain of the second PMOS transistor PM2 is connected to the second terminal of the current limiting module 3, the circuit to be protected 6, and the first terminal of the fourth electrostatic protection unit 22.

[0111] Optionally, continue to refer to Figure 3The source of the second PMOS transistor PM2 and one end of the third resistor R3 both serve as the first terminal of the second electrostatic discharge (ESD) protection module 2 and the first terminal of the second ESD protection unit 21, respectively, and are connected to the power supply voltage VDD to obtain the electrical energy provided by the power supply voltage VDD. The other end of the third resistor R3 is connected to the gate of the second PMOS transistor PM2, and the drain of the second PMOS transistor PM2 serves as the second terminal of the second ESD protection unit 21, which is connected to the input port IO_1, the first terminal of the current limiting module 3, and the first terminal of the fourth ESD protection unit 22, respectively.

[0112] By connecting a third resistor R3 between the gate and source of the second PMOS transistor PM2, a certain voltage will be generated at the gate of PM2 when an ESD high-voltage pulse arrives due to the presence of the third resistor R3. This voltage will cause the channel of the second PMOS transistor PM2 to turn on earlier, reducing the trigger voltage at which the second PMOS transistor PM2 begins to conduct. A lower trigger voltage means that the second PMOS transistor PM2 can respond to the ESD pulse in a shorter time and discharge the electrostatic current to ground more quickly, achieving rapid electrostatic discharge.

[0113] In this embodiment, the third voltage divider includes a third resistor, and the third conducting device includes a second PMOS transistor. The source of the second PMOS transistor and one end of the third resistor are connected to the power supply voltage to obtain electrical energy. The gate of the second PMOS transistor is connected to the other end of the third resistor. The drain of the second PMOS transistor is connected to the second terminal of the current limiting module, the circuit to be protected 6, and the first terminal of the fourth electrostatic protection unit. By connecting the third resistor between the gate and source of the second PMOS transistor, the trigger voltage for the second PMOS transistor to turn on is reduced, so that the second PMOS transistor can respond to the ESD pulse in a shorter time and discharge the electrostatic current to ground more quickly, thereby achieving rapid discharge of electrostatics.

[0114] As an optional implementation, the fourth voltage divider device 221 includes a fourth resistor R4; the fourth conducting device 222 includes a second NMOS transistor NM2.

[0115] Optionally, continue to refer to Figure 3 The fourth voltage divider device 221 includes a fourth resistor R4, and the fourth conducting device 222 includes a second NMOS transistor NM2. The fourth resistor R4 can be a resistor made of Poly material. For example, the resistance value of the fourth resistor R4 can be 5K ohms.

[0116] The drain of the second NMOS transistor NM2 is connected to the second terminal of the current limiting module 3, the circuit to be protected 6, and the second terminal of the third electrostatic protection unit 21. The gate of the second NMOS transistor NM2 is connected to one end of the fourth resistor R4. The source of the second NMOS transistor NM2 and the other end of the fourth resistor R4 are grounded.

[0117] Optionally, continue to refer to Figure 3 The drain of the second NMOS transistor NM2 serves as the first terminal of the fourth electrostatic discharge (ESD) protection unit 22, and is connected to the second terminal of the current limiting module 3, the circuit to be protected 6, and the second terminal of the third ESD protection unit 21, respectively. The gate of the second NMOS transistor NM2 is connected to one end of the fourth resistor R4, and the source of the second NMOS transistor NM2 and the other end of the fourth resistor R4 are both grounded as the second terminals of the second ESD protection module 2 and the fourth ESD protection unit 22, respectively.

[0118] By connecting a fourth resistor R4 between the gate and source of the second NMOS transistor NM2, a certain voltage will be generated at the gate of the second NMOS transistor NM2 when an ESD high-voltage pulse arrives due to the presence of the fourth resistor R4. This voltage will cause the channel of the second NMOS transistor NM2 to turn on earlier, reducing the trigger voltage for the second NMOS transistor NM2 to start conducting. A lower trigger voltage means that the second NMOS transistor NM2 can respond to the ESD pulse in a shorter time and discharge the electrostatic current to ground more quickly, achieving rapid electrostatic discharge.

[0119] In this embodiment, the fourth voltage divider device includes a fourth resistor, and the fourth conducting device includes a second NMOS transistor. The drain of the second NMOS transistor is connected to the second terminal of the current limiting module, the circuit to be protected, and the second terminal of the third electrostatic protection unit. The gate of the second NMOS transistor is connected to one end of the fourth resistor. The source of the second NMOS transistor and the other end of the fourth resistor are grounded. By connecting the fourth resistor between the gate and source of the second NMOS transistor, the trigger voltage for the second NMOS transistor to turn on is reduced, so that the second NMOS transistor can respond to the ESD pulse in a shorter time and discharge the electrostatic current to ground more quickly, thereby achieving rapid electrostatic discharge.

[0120] Figure 4 This is a schematic diagram of the electrostatic protection layout structure provided in the embodiments of this application, such as... Figure 4 As shown, the electrostatic discharge protection layout structure includes at least: a first layout area 71, a second layout area 72, a third layout area 73, and a fourth layout area 74. The second layout area 72 is located below the first layout area 71, the third layout area 73 is located to the right of the first layout area 71, and the fourth layout area 74 is located below the third layout area 73.

[0121] Optionally, refer to Figure 4 The electrostatic discharge (ESD) protection layout is mainly divided into four areas: area 71 (first area), area 72 (second area), area 73 (third area), and area 74 (fourth area). Area 72 is located below area 71, area 73 is located to the right of area 71, and area 74 is located below area 73.

[0122] Figure 5 Another schematic diagram of the electrostatic protection layout provided in the embodiments of this application is shown below. Figure 5 As shown, the first layout area 71 is the layout area for the first PMOS transistor PM1, the second layout area 72 is the layout area for the first NMOS transistor NM1, the third layout area 73 is the layout area for the second PMOS transistor PM2, and the fourth layout area 74 is the layout area for the second NMOS transistor NM2.

[0123] Optionally, refer to Figure 5 Each layout area corresponds to a different device. Specifically, the first layout area 71 represents the layout area for the first PMOS transistor PM1, and corresponds to the first PMOS transistor PM1. The second layout area 72 represents the layout area for the first NMOS transistor NM1, and corresponds to the first NMOS transistor NM1. The third layout area 73 represents the layout area for the second PMOS transistor PM2, and corresponds to the second PMOS transistor PM2. The fourth layout area 74 represents the layout area for the second NMOS transistor NM2, and corresponds to the second NMOS transistor NM2.

[0124] The first PMOS transistor PM1 layout area includes multiple source structures, multiple drain structures, and a gate structure. The source structures and drain structures are interdigitated, and multiple drain structures are all connected to a first metal. The distance between the first metal and the gate structure is greater than a first preset value. The area of ​​each drain structure is greater than a second preset value.

[0125] Optionally, continue to refer to Figure 5 The first PMOS transistor PM1 includes multiple source structures S, multiple drain structures D, and a gate structure G. The source structures S and drain structures D of the first PMOS transistor PM1 are interdigitated to allow current to flow evenly into and out of the first PMOS transistor PM1. Each drain structure D is connected to a first metal, which connects the drain structures D of the first PMOS transistor PM1 into a single unit. The distance between the first metal and the gate structure G is greater than a first preset value, meaning the distance between the drain structures D and the gate structure G of the first PMOS transistor PM1 is greater than the first preset value. Furthermore, the area of ​​each drain structure D in the first PMOS transistor PM1 is greater than a second preset value. In other words, by ensuring that the distance between the drain structure D and the gate structure G of the first PMOS transistor PM1 is large enough, and that the area of ​​each drain structure D in the first PMOS transistor PM1 is large enough, the breakdown voltage of the first PMOS transistor PM1 can be increased, the withstand voltage capability can be improved, and the current discharge capability of the first PMOS transistor PM1 can be improved by increasing the distance between the drain structure D and the gate structure G of the first PMOS transistor PM1, widening each drain structure D, and increasing the area of ​​each drain structure D.

[0126] The first NMOS transistor NM1 layout area includes multiple source structures, multiple drain structures, and a gate structure. The source structures and drain structures are interdigitated, and multiple drain structures are all connected to a second metal. The distance between the second metal and the gate structure is greater than a third preset value. The area of ​​each drain structure is greater than a fourth preset value.

[0127] Optionally, continue to refer to Figure 5 The first NMOS transistor NM1 includes multiple source structures S, multiple drain structures D, and a gate structure G. The source structures S and drain structures D of the first NMOS transistor NM1 are interdigitated to allow current to flow evenly into and out of the transistor. Each drain structure D is connected to a second metal, which connects the drain structures D of the first NMOS transistor NM1 into a single unit. The distance between the second metal and the gate structure G is greater than a second preset value, meaning the distance between the drain structures D and the gate structure G of the first NMOS transistor NM1 is greater than the second preset value. Furthermore, the area of ​​each drain structure D in the first NMOS transistor NM1 is greater than a fourth preset value. In other words, by ensuring that the distance between the drain structure D and the gate structure G of the first NMOS transistor NM1 is large enough, and that the area of ​​each drain structure D in the first NMOS transistor NM1 is large enough, the breakdown voltage of the first NMOS transistor NM1 can be increased, its withstand voltage capability can be improved, and its current discharge capability can be improved by increasing the distance between the drain structure D and the gate structure G of the first NMOS transistor NM1, widening each drain structure D, and increasing the area of ​​each drain structure D.

[0128] In this embodiment, the electrostatic discharge (ESD) protection layout structure includes at least a first layout area, a second layout area, a third layout area, and a fourth layout area. The second layout area is located below the first layout area, the third layout area is located to the right of the first layout area, and the fourth layout area is located below the third layout area. The first layout area is the layout area for a first PMOS transistor, the second layout area is the layout area for a first NMOS transistor, the third layout area is the layout area for a second PMOS transistor, and the fourth layout area is the layout area for a second NMOS transistor. The first PMOS transistor includes multiple source structures, multiple drain structures, and a gate structure. The source and drain structures of the first PMOS transistor are interdigitated to allow current to flow evenly in and out of the first PMOS transistor. The multiple drain structures of the first PMOS transistor are all connected to a first metal, the distance between the first metal and the gate structure is greater than a first preset value, and the area of ​​each drain structure is greater than a second preset value. This improves the breakdown voltage of the first PMOS transistor, enhances its withstand voltage capability, and improves its current discharge capability, thereby improving the ESD protection performance. The first NMOS transistor includes multiple source structures, multiple drain structures, and a gate structure. The source and drain structures of the first NMOS transistor are interdigitated to allow for uniform current flow. All drain structures of the first NMOS transistor are connected to a second metal, and the distance between the second metal and the gate structure is greater than a third preset value. The area of ​​each drain structure is greater than a fourth preset value. This improves the breakdown voltage and withstand voltage of the first NMOS transistor, as well as its current discharging capability, thereby enhancing its electrostatic discharge protection performance. It also improves the rationality of the layout and the withstand voltage and current discharging capabilities of each MOS transistor.

[0129] It is worth noting that, continuing to refer to Figure 5 The first PMOS transistor PM1 layout area includes multiple source structures, multiple drain structures, and a gate structure. The source structures and drain structures are interdigitated, and multiple drain structures are all connected to a first metal. The distance between the first metal and the gate structure is greater than a first preset value. The area of ​​each drain structure is greater than a second preset value.

[0130] Optionally, continue to refer to Figure 5 The second PMOS transistor PM2 includes multiple source structures, multiple drain structures, and a gate structure in its layout area. The source and drain structures are interdigitated, and all drain structures are connected to a third metal. The distance between the third metal and the gate structure is greater than a fifth preset value, and the area of ​​each drain structure is greater than a sixth preset value. By increasing the distance between the drain and gate structures of the second PMOS transistor PM2, widening each drain structure, and increasing the area of ​​each drain structure, the breakdown voltage of the first PMOS transistor PM1 can be improved, its withstand voltage capability is enhanced, and its current discharging capability is also improved.

[0131] The layout area of ​​the second NMOS transistor NM2 includes multiple source structures, multiple drain structures, and a gate structure. The source and drain structures are interdigitated, and all drain structures are connected to a fourth metal. The distance between the fourth metal and the gate structure is greater than a seventh preset value, and the area of ​​each drain structure is greater than an eighth preset value. By increasing the distance between the drain and gate structures of the second NMOS transistor NM2, widening each drain structure, and increasing the area of ​​each drain structure, the breakdown voltage of the second NMOS transistor NM2 can be improved, its withstand voltage capability is enhanced, and its current discharging capability is also improved.

[0132] This application also provides a semiconductor chip, including the electrostatic discharge protection circuit described in the foregoing embodiments and a circuit to be protected connected to the electrostatic discharge protection circuit.

[0133] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. An electrostatic protection circuit, characterized by comprising: include: The system includes a first electrostatic discharge (ESD) protection module, a second ESD protection module, and a current limiting module. The first electrostatic discharge protection module and the second electrostatic discharge protection module are respectively provided with at least one voltage divider device and at least one conducting device; The input terminal of the first electrostatic discharge protection module is connected to the input port, the output terminal of the first electrostatic discharge protection module is connected to the first terminal of the current limiting module, the first terminal of the first electrostatic discharge protection module is connected to the power supply voltage, and the second terminal of the first electrostatic discharge protection module is grounded. The input terminal of the second electrostatic discharge protection module is connected to the second terminal of the current limiting module, the output terminal of the second electrostatic discharge protection module is connected to the circuit to be protected, the first terminal of the second electrostatic discharge protection module is connected to the power supply voltage, and the second terminal of the second electrostatic discharge protection module is grounded. The voltage divider in the first electrostatic discharge protection module is used to reduce the trigger voltage of the conducting device in the first electrostatic discharge protection module; The voltage divider in the second electrostatic discharge protection module is used to reduce the trigger voltage of the conducting device in the second electrostatic discharge protection module; The conducting device in the first electrostatic discharge protection module and the conducting device in the second electrostatic discharge protection module are respectively used to conduct and discharge static electricity.

2. The circuit of claim 1, wherein, The first electrostatic discharge (ESD) protection module includes: a first ESD protection unit and a second ESD protection unit; The first terminal of the first electrostatic protection unit is connected to the power supply voltage, and the second terminal of the first electrostatic protection unit is connected to the input port, the first terminal of the current limiting module, and the first terminal of the second electrostatic protection unit, respectively. The second terminal of the second electrostatic protection unit is grounded; The first electrostatic discharge protection unit includes a first voltage divider device and a first conducting device; the second electrostatic discharge protection unit includes a second voltage divider device and a second conducting device.

3. The circuit of claim 1, wherein, The second electrostatic discharge (ESD) protection module includes: a third ESD protection unit and a fourth ESD protection unit; The first terminal of the third electrostatic protection unit is connected to the power supply voltage, and the second terminal of the third electrostatic protection unit is connected to the second terminal of the current limiting module, the circuit to be protected, and the first terminal of the fourth electrostatic protection unit. The second terminal of the fourth electrostatic protection unit is grounded; The third electrostatic discharge protection unit includes a third voltage divider and a third conducting device; the fourth electrostatic discharge protection unit includes a fourth voltage divider and a fourth conducting device.

4. The circuit of claim 2, wherein, The first voltage divider device includes a first resistor; the first conducting device includes a first P-channel metal-oxide-semiconductor field-effect transistor. The source of the first P-channel metal-oxide-semiconductor field-effect transistor and one end of the first resistor are connected to the supply voltage; The gate of the first P-channel metal-oxide-semiconductor field-effect transistor is connected to the other end of the first resistor. The drain of the first P-channel metal-oxide-semiconductor field-effect transistor is connected to the input port, the first terminal of the current limiting module, and the first terminal of the second electrostatic protection unit, respectively.

5. The circuit of claim 4, wherein, The first P-channel metal-oxide-semiconductor field-effect transistor includes multiple source structures, multiple drain structures, and a gate structure. The source structures and the drain structures form an interdigitated structure, and all of the multiple drain structures are connected to a first metal. The distance between the first metal and the gate structure is greater than a first preset value; The area of ​​each drain structure is greater than the second preset value.

6. The circuit of claim 2, wherein, The second voltage divider includes a second resistor; the second conducting device includes a first N-channel metal-oxide-semiconductor field-effect transistor. The drain of the first N-channel metal-oxide-semiconductor field-effect transistor is connected to the input port, the first terminal of the current limiting module, and the second terminal of the first electrostatic protection unit, respectively. The gate of the first N-channel metal-oxide-semiconductor field-effect transistor is connected to one end of the second resistor; The source of the first N-channel metal-oxide-semiconductor field-effect transistor and the other end of the second resistor are grounded.

7. The circuit of claim 3, wherein, The third voltage divider device includes a third resistor; the third conducting device includes a second P-channel metal-oxide-semiconductor field-effect transistor. The source of the second P-channel metal-oxide-semiconductor field-effect transistor and one end of the third resistor are connected to the supply voltage; The gate of the second P-channel metal-oxide-semiconductor field-effect transistor is connected to the other end of the third resistor; The drain of the second P-channel metal-oxide-semiconductor field-effect transistor is connected to the second terminal of the current limiting module, the circuit to be protected, and the first terminal of the fourth electrostatic protection unit, respectively.

8. The circuit of claim 3, wherein, The fourth voltage divider device includes a fourth resistor; the fourth conducting device includes a second N-channel metal-oxide-semiconductor field-effect transistor. The drain of the second N-channel metal-oxide-semiconductor field-effect transistor is connected to the second terminal of the current limiting module, the circuit to be protected, and the second terminal of the third electrostatic protection unit, respectively. The gate of the second N-channel metal-oxide-semiconductor field-effect transistor is connected to one end of the fourth resistor; The source of the second N-channel metal-oxide-semiconductor field-effect transistor and the other end of the fourth resistor are grounded.

9. A semiconductor chip, characterized in that, include: The electrostatic discharge protection circuit according to any one of claims 1-8 and the circuit to be protected connected to the electrostatic discharge protection circuit.

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