Goa driving unit, goa driving circuit and display device
By setting a power-off reset module in the GOA driver unit and pulling down the intermediate sustain node after power-off, the problem of transistors failing to discharge after power-off is solved, extending the lifespan of transistors and achieving complete discharge of the GOA driver unit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ZHEJIANG LAIBAO DISPLAY TECHNOLOGY CO LTD
- Filing Date
- 2025-05-30
- Publication Date
- 2026-05-29
AI Technical Summary
Some transistors in the GOA driver unit cannot discharge after the display device is turned off, resulting in a shortened transistor lifespan.
A power-off reset module is set in the GOA driver unit, and a high-level power-off reset signal is input to the power-off reset module after the display device is powered off, so as to pull down the intermediate holding node to a low level and prevent the transistor from being in a forward bias state.
This improves the lifespan of transistors controlled by intermediate sustain nodes and ensures that the GOA drive unit can be fully discharged after power-off.
Smart Images
Figure CN224304341U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of display technology, and in particular relates to a GOA driving unit, a GOA driving circuit and a display device. Background Technology
[0002] Integrating gate driver on array (GOA) circuitry onto a glass substrate involves integrating the gate driver circuitry of the display panel onto the glass substrate, forming a scanning drive for the display panel. Compared to traditional gate chip-based driving technologies, GOA driving technology can significantly reduce manufacturing costs and reduce the left and right bezels of the display panel. A GOA driving circuit typically includes cascaded multi-stage GOA driving units. Each stage of the GOA driving unit drives one row of pixel units on the display panel. By cascading multiple stages of GOA driving units, line-by-line scanning of the display panel can be achieved.
[0003] Typically, when a display device is powered off, all internal nodes in the GOA driver unit used for storing and transmitting voltage levels need to be pulled down to a low level to discharge residual charge. Specifically, when the display device is powered off, each node is first pulled up to a high level and then pulled down to a low level. However, some transistors in the GOA driver unit are diode-connected. The source and gate of these transistors are synchronously pulled to the same high level after the display device is powered off. This causes these transistors to remain in an off state after the display device is powered off, preventing them from discharging the intermediate sustaining node corresponding to their drain. Consequently, other transistors controlled by this intermediate sustaining node remain forward-biased, shortening the lifespan of these other transistors. Summary of the Invention
[0004] In view of this, embodiments of this application provide a GOA driving unit, a GOA driving circuit, and a display device to solve the technical problem of short lifespan of some transistors in the GOA driving unit.
[0005] In a first aspect, embodiments of this application provide a GOA driving unit, including:
[0006] A pull-up control module, connected to a pull-up control node, is used to output a high-level pull-up control signal to the pull-up control node based on a high-level first input signal;
[0007] A pull-up module, connected to the pull-up control node and the output node, is used to output a gate drive signal from the output node according to the pull-up control signal and the scan clock signal;
[0008] A pull-down module, connected to the pull-up control node, is used to pull the pull-up control node down to a low level according to a high-level second input signal;
[0009] An inverting module, connected to the pull-up control node, the pull-down control node, and the intermediate sustaining node, is used to invert the pull-up control signal according to a preset high-level signal and the pull-up control signal, and output the inverted signal of the pull-up control signal to the pull-down control node.
[0010] A pull-down sustaining module, connected to the pull-up control node, the pull-down control node, and the output node, is used to maintain the pull-up control node and the output node at a low level according to the high-level inverted signal;
[0011] The power-off reset module, connected to the intermediate maintenance node, is used to pull the intermediate maintenance node down to a low level according to the high-level power-off reset signal received after the display device is powered off.
[0012] In one alternative implementation of the first aspect, it also includes:
[0013] The first reset module is connected to the pull-up control node and the output node, and is used to pull down and reset the pull-up control node and the output node according to the high-level first reset signal.
[0014] In one alternative implementation of the first aspect, the power-off reset module includes a first transistor;
[0015] The source of the first transistor is connected to the intermediate sustaining node, the gate of the first transistor is used to receive the high-level power-off reset signal after the display device is powered off, and the drain of the first transistor is connected to the low-level terminal.
[0016] In one alternative implementation of the first aspect, the pull-up control module includes a second transistor;
[0017] The gate and source of the second transistor are used to receive the first input signal, and the drain of the second transistor is connected to the pull-up control node.
[0018] In one alternative implementation of the first aspect, the pull-up module includes a third transistor and a first capacitor;
[0019] The gate of the third transistor and the first terminal of the first capacitor are both connected to the pull-up control node. The source of the third transistor is used to connect to the scan clock signal. The drain of the third transistor and the second terminal of the first capacitor are both connected to the output node.
[0020] In one alternative implementation of the first aspect, the pull-down module includes a fourth transistor;
[0021] The gate of the fourth transistor is used to receive the second input signal, the source of the fourth transistor is connected to the pull-up control node, and the drain of the fourth transistor is connected to the low-level terminal.
[0022] In one alternative implementation of the first aspect, the inverting module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
[0023] The gate, source, and source of the fifth transistor are used to connect to a preset high-level signal. The drain, source, and gate of the fifth transistor are connected to the intermediate sustaining node. The gate of the sixth transistor and the gate of the eighth transistor are connected to the pull-up control node. The drain of the sixth transistor and the drain of the eighth transistor are connected to a low-level terminal. The drain of the seventh transistor and the source of the eighth transistor are connected to the pull-down control node.
[0024] In one alternative implementation of the first aspect, the pull-down sustaining module includes a ninth transistor and a tenth transistor;
[0025] The gate of the ninth transistor and the gate of the tenth transistor are both connected to the pull-down control node. The source of the ninth transistor is connected to the pull-up control node. The source of the tenth transistor is connected to the output node. The drains of the ninth transistor and the tenth transistor are connected to a low-level terminal.
[0026] Secondly, embodiments of this application provide a GOA driving circuit, including cascaded multi-stage GOA driving units as described in any optional implementation of the first aspect; the first input signal connected to each stage of the GOA driving unit is the gate driving signal output by the upper k-stage GOA driving unit, and the second input signal connected to each stage of the GOA driving unit is the gate driving signal output by the lower k-stage GOA driving unit; k is a positive integer.
[0027] Thirdly, embodiments of this application provide a display device including the GOA driving circuit described in the second aspect.
[0028] Implementing the GOA driving unit, GOA driving circuit, and display device provided in the embodiments of this application has the following beneficial effects:
[0029] This application embodiment sets a power-off reset module in the GOA driving unit and connects the power-off reset module to the intermediate sustaining node. After the display device is powered off, a high-level power-off reset signal is connected to the power-off reset module, so that the power-off reset module can pull the intermediate sustaining node to a low level after the display device is powered off. This prevents the transistor controlled by the intermediate sustaining node from being in a forward biased state after the display device is powered off, thereby improving the service life of the transistor controlled by the intermediate sustaining node. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is a schematic diagram of the structure of a GOA driving unit provided in an embodiment of this application;
[0032] Figure 2 A schematic diagram of the structure of a GOA driving unit provided in another embodiment of this application;
[0033] Figure 3 A waveform diagram of each node and the access signal when a GOA driving unit is working normally, provided for an embodiment of this application;
[0034] Figure 4 A waveform diagram of each node and the access signal in the GOA driving unit of a display device after it is powered off, provided as an embodiment of this application;
[0035] Figure 5 This is a schematic diagram of the circuit structure of a GOA driving unit provided in an embodiment of this application. Detailed Implementation
[0036] The following embodiments are only used to illustrate the technical solutions of this application more clearly, and are therefore only examples and should not be used to limit the scope of protection of this application.
[0037] In the description of the embodiments of this application, the technical terms "comprising," "including," "having," and any variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. In the description of the embodiments of this application, unless otherwise stated, the technical term "multiple" refers to two or more, and the technical terms "at least one" or "one or more" refer to one, two, or more than two. The technical terms "first," "second," etc., are only used to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary / secondary relationship of the indicated technical features. The technical term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0038] This application first provides a GOA driving circuit, which may include cascaded multi-level GOA driving units. Each level of GOA driving unit can be used to drive a row of pixels on the display panel. The cascading of multiple levels of GOA driving units enables line-by-line scanning of the display panel.
[0039] This application also provides a GOA driving unit. Please refer to [link / reference]. Figure 1 This is a schematic diagram of the structure of a GOA driving unit provided in an embodiment of this application. Figure 1 As shown, in one optional implementation, the GOA driver unit may include a pull-up control module 10, a pull-up module 20, a pull-down module 30, an inverting module 40, a pull-down sustaining module 50, and a power-off reset module 60.
[0040] The pull-up control module 10 can be connected to the pull-up control node Qn. The pull-up control module 10 can be used to receive a first input signal G(nk) and output a pull-up control signal to the pull-up control node Qn based on the first input signal G(nk). For example, the pull-up control module 10 can output a high-level pull-up control signal to the pull-up control node Qn based on a high-level first input signal G(nk).
[0041] Pull-up module 20 can be connected to pull-up control node Qn and output node Rn. Pull-up module 20 can be used to receive scan clock signal CLK, and output gate drive signal G(n) from output node Rn according to pull-up control signal and scan clock signal CLK. For example, pull-up control module 20 can output high-level gate drive signal G(n) from output node Rn according to high-level pull-up control signal and high-level scan clock signal CLK to drive a row of pixel units corresponding to the current GOA driving unit, or as an input signal for other GOA driving units.
[0042] The pull-down module 30 can be connected to the pull-up control node Qn. The pull-down module 30 can be used to receive the second input signal G(n+k) and pull the pull-up control node Qn down to the low level VSS according to the high level of the second input signal G(n+k).
[0043] The inverting module 40 can be connected to the pull-up control node Qn, the pull-down control node Kn, and the intermediate sustaining node Sn. The inverting module 40 can be used to invert the pull-up control signal according to the preset high-level signal VGH and the pull-up control signal, and output the inverted pull-up control signal to the pull-down control node Kn.
[0044] The pull-down sustaining module 50 can be connected to the pull-up control node Qn, the pull-down control node Kn, and the output node Rn. The pull-down sustaining module 50 can be used to maintain the pull-up control node Qn and the output node Rn at a low level VSS based on a high-level inverted signal.
[0045] The power-off reset module 60 can be connected to the intermediate sustaining node Sn. The power-off reset module 60 can be used to pull the intermediate sustaining node Sn down to a low level VSS according to the high-level power-off reset signal Reset1 that is received after the display device is powered off.
[0046] Wherein, the first input signal G(nk) can be the gate drive signal output by the k-th stage GOA drive unit, and the second input signal G(n+k) can be the gate drive signal output by the k-th stage GOA drive unit, where k is a positive integer. k can be determined according to the number of cycles of the scan clock signal connected to the pull-up module 20.
[0047] In another alternative implementation, such as Figure 2 As shown, the GOA drive unit may also include a first reset module 70.
[0048] The first reset module 70 can be connected to the pull-up control node Qn and the output node Rn. The first reset module 70 can be used to receive the first reset signal Reset2, and pull the pull-up control node Qn and the output node Rn down to the low level VSS according to the high level first reset signal Reset2.
[0049] For example, please refer to Figure 3 This is a waveform diagram of each node and the access signal when a GOA driving unit is working normally, provided in an embodiment of this application.
[0050] like Figure 3As shown, during the A to B phase of normal operation of the GOA driving unit, the first input signal G(nk) is high, while the scan clock signal CLK and the second input signal G(n+k) are low. At this time, the pull-up control module 10 outputs a high-level pull-up control signal to the pull-up control node Qn based on the high-level first input signal G(nk), making the pull-up control node Qn a first high level. Since the pull-up control node Qn is a first high level and the scan clock signal CLK is low, the pull-up module 20 outputs a low-level signal to the output node Rn, making the output node Rn low. Since the second input signal G(n+k) is low, the pull-down module 30 is turned off. The inverting module 40 inverts the high-level pull-up control signal based on the preset high-level signal VGH and outputs a first low-level inverted signal to the pull-down control node Kn, making the pull-down control node Kn low.
[0051] During stages B to C, the scan clock signal CLK is high, and both the first input signal G(nk) and the second input signal G(n+k) are low. At this time, both the pull-up control module 10 and the pull-down module 30 are off. Due to the presence of the bootstrap capacitor in the pull-up module 20, the pull-up control node Qn is maintained at a second high level, which is higher than the first high level. Since both the scan clock signal CLK and the pull-up control node Qn are high, the pull-up control module 20 outputs a high-level gate drive signal G(n) based on the high-level scan clock signal CLK and the pull-up control signal, making the output node Rn high. It should be noted that the inverting module 40 inverts the high-level pull-up control signal according to the preset high-level signal VGH and outputs a low-level inverted signal to the pull-down control node Kn, making the pull-down control node Kn low.
[0052] During stages C to D, the scan clock signal CLK, the first input signal G(nk), and the second input signal G(n+k) are all at low levels. At this time, both the pull-up control module 10 and the pull-down module 30 are off, and the pull-up control node Qn maintains a first high level. Since the pull-up control node Qn is high and the scan clock signal CLK is low, the pull-up control module 20 outputs a low-level signal to the output node Rn, making the output node Rn low. The inverting module 40 inverts the high-level pull-up control signal according to the preset high-level signal VGH and outputs a low-level inverted signal to the pull-down control node Kn, making the pull-down control node Kn low.
[0053] During stages D to E, the second input signal G(n+k) is high, while the first input signal G(nk), the scan clock signal CLK, and the first reset signal Reset2 are all low. At this time, the pull-down module 30 is activated, pulling the pull-up control node Qn low. Since both the pull-up control node Qn and the scan clock signal CLK are low, the pull-up module 20 outputs a low-level signal to the output node Rn, making the output node Rn low. The inverting module 40 inverts the low-level pull-up control signal according to the preset high-level signal VGH and outputs a high-level inverted signal to the pull-down control node Kn, making the pull-down control node Kn high.
[0054] During stages F to G, the first reset signal Reset2 is high, while the first input signal G(nk), the second input signal G(n+k), and the scan clock signal CLK are all low. Since the first reset signal Reset2 is high, the first reset module 70 pulls the pull-up control node Qn down to low and the output node Rn down to low, thus maintaining the gate drive signal G(n) at a low level.
[0055] For example, please refer to Figure 4 This is a waveform diagram of each node / access signal in the GOA driving unit after the display device is powered off, provided in an embodiment of this application.
[0056] like Figure 4 As shown, the GOA driving unit provided in this embodiment can, during the power-off discharge phase after the display device is powered off, first pull up each signal (e.g., scan clock signal and gate drive signal, etc., not shown) and each internal node (e.g., pull-up control node Qn, pull-down control node Kn and intermediate sustaining node Sn, etc.) to a high level and then pull them down to a low level, thereby enabling complete discharge of each signal and each internal node after the display device is powered off.
[0057] As can be seen from the above, the embodiments of this application, by setting a power-off reset module in the GOA driving unit and connecting the power-off reset module to the intermediate sustaining node, and by providing a high-level power-off reset signal to the power-off reset module after the display device is powered off, enable the power-off reset module to pull the intermediate sustaining node down to a low level after the display device is powered off. This prevents the transistor controlled by the intermediate sustaining node from being in a forward biased state after the display device is powered off, thereby improving the lifespan of the transistor controlled by the intermediate sustaining node.
[0058] Furthermore, by setting a first reset module 70 in the GOA driver unit, when it is necessary to reset the pull-up control node Qn and the output node Rn, a high-level first reset signal Reset2 can be connected to the first reset module 70 to reset the pull-up control node Qn and the output node Rn, thereby realizing the initialization of the GOA driver unit or the synchronization between rows of the display device.
[0059] Please see Figure 5 This is a schematic diagram of the circuit structure of a GOA driving unit provided in an embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown, and are described in detail below:
[0060] like Figure 5 As shown, the power-off reset module 60 may include a first transistor T1. The source of the first transistor T1 may be connected to the intermediate sustaining node Sn, the gate of the first transistor T1 may be used to connect a high-level power-off reset signal Reset1 after the display device is powered off, and the drain of the first transistor T1 may be connected to a low-level terminal. The low-level terminal is used to provide a low-level signal VSS.
[0061] The pull-up control module 10 may include a second transistor T2. The gate and source of the second transistor T2 can be used to connect to the first input signal G(nk), and the drain of the second transistor T2 can be connected to the pull-up control node Qn.
[0062] The pull-up module 20 may include a third transistor T3 and a first capacitor C1. The gate of the third transistor T3 may be connected to the pull-up control node Qn along with the first terminal of the first capacitor C1. The source of the third transistor T3 may be used to connect to the scan clock signal CLK. The drain of the third transistor T3 may be connected to the output node Rn along with the second terminal of the first capacitor C1. For example, the first capacitor C1 may be a bootstrap capacitor.
[0063] The pull-down module 30 may include a fourth transistor T4. The gate of the fourth transistor T4 can be used to connect to the second input signal G(n+k), the source of the fourth transistor T4 can be connected to the pull-up control node Qn, and the drain of the fourth transistor T4 can be connected to the low-level terminal.
[0064] The inverting module 40 may include a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The gate and source of the fifth transistor T5 and the source of the seventh transistor T7 can be connected to a preset high-level signal VGH. The drain of the fifth transistor T5, the source of the sixth transistor T6, and the gate of the seventh transistor T7 can be connected together to an intermediate sustaining node Sn. The gate of the sixth transistor T6 and the gate of the eighth transistor T8 can be connected together to a pull-up control node Qn. The drain of the sixth transistor T6 and the drain of the eighth transistor T8 can be connected to a low-level terminal. The drain of the seventh transistor T7 and the source of the eighth transistor T8 can be connected together to a pull-down control node Kn.
[0065] The pull-down sustaining module 50 may include a ninth transistor T9 and a tenth transistor T10. The gate of the ninth transistor T9 and the gate of the tenth transistor T10 may be connected to the pull-down control node Kn, the source of the ninth transistor T9 may be connected to the pull-up control node Qn, the source of the tenth transistor T10 may be connected to the output node Rn, and the drains of the ninth transistor T9 and the tenth transistor T10 may be connected to a low-level terminal.
[0066] The first reset module 70 may include an eleventh transistor T11 and a twelfth transistor T12. The source of the eleventh transistor T11 may be connected to the pull-up control node Qn, the gates of the eleventh transistor T11 and the twelfth transistor T12 may be used to receive the first reset signal Reset2, the source of the twelfth transistor T12 may be connected to the output node Rn, and the drains of the eleventh transistor T11 and the twelfth transistor T12 may be connected to a low-level terminal.
[0067] The following combination Figure 3 and Figure 5 The working principle of the GOA driving unit will be further explained.
[0068] During phase A to B, the first input signal G(nk) is high, while the scan clock signal CLK, the second input signal G(n+k), and the first reset signal Reset2 are all low. At this time, the second transistor T2 in the pull-up control module 10 is turned on, outputting a high-level pull-up control signal to the pull-up control node Qn, making Qn a first high level. Since Qn is high, the third transistor T3 in the pull-up module 20 is turned on, outputting the low-level scan clock signal CLK to the output node Rn, making Rn low. Since the second input signal G(n+k) is low, the fourth transistor T4 in the pull-down module 30 is turned off, shutting down the pull-down module 30. The fifth transistor T5 in the inverting module 40 is turned on under the control of the preset high-level signal VGH, which in turn turns on the seventh transistor T7. The sixth transistor T6 and the eighth transistor T8 are turned on under the control of the high-level pull-up control signal, thereby realizing the inversion of the high-level pull-up control signal and outputting a low-level inverted signal to the pull-down control node Kn, making the pull-down control node Kn low.
[0069] During stages B to C, the scan clock signal CLK is high, and the first input signal G(nk), the first reset signal Reset, and the second input signal G(n+k) are all low. At this time, the second transistor T2 in the pull-up control module 10 is turned off, thus shutting down the pull-up control module 10. Since the second input signal G(n+k) is low, the fourth transistor T4 in the pull-down module 30 is turned off, thus shutting down the pull-down module 30. Due to the presence of the bootstrap capacitor (first capacitor C1) in the pull-up module 20, the pull-up control node Qn is maintained at a second high level, which is greater than the first high level. Since both the scan clock signal CLK and the pull-up control node Qn are high, the third transistor T3 in the pull-up control module 20 is turned on, outputting the high-level scan clock signal CLK to the output node Rn, making the gate drive signal G(n) high. The fifth transistor T5 in the inverting module 40 is turned on under the control of the preset high-level signal VGH, which in turn turns on the seventh transistor T7. The sixth transistor T6 and the eighth transistor T8 are turned on under the control of the high-level pull-up control signal, thereby realizing the inversion of the high-level pull-up control signal and outputting a low-level inverted signal to the pull-down control node Kn, making the pull-down control node Kn low.
[0070] During stages C to D, the scan clock signal CLK, the first input signal G(nk), and the second input signal G(n+k) are all at low levels. At this time, the second transistor T2 in the pull-up control module 10 is turned off, thereby shutting down the pull-up control module 10. Since the second input signal G(n+k) is low, the fourth transistor T4 in the pull-down module 30 is turned off, thereby shutting down the pull-down module 30, and the pull-up control node Qn remains at the first high level. Because the pull-up control node Qn is high and the scan clock signal CLK is low, the third transistor T3 in the pull-up control module 20 is turned on, outputting the low-level scan clock signal CLK to the output node Rn, making the gate drive signal G(n) low. The fifth transistor T5 in the inverting module 40 is turned on under the control of the preset high-level signal VGH, which in turn turns on the seventh transistor T7. The sixth transistor T6 and the eighth transistor T8 are turned on under the control of the high-level pull-up control signal, thereby realizing the inversion of the high-level pull-up control signal and outputting a low-level inverted signal to the pull-down control node Kn, making the pull-down control node Kn low.
[0071] During the D to E phase, the second input signal G(n+k) is high, while the first input signal G(nk), the scan clock signal CLK, and the first reset signal Reset2 are all low. At this time, the fourth transistor T4 in the pull-down module 30 is turned on, pulling the pull-up control node Qn down to a low level. Since both the pull-up control node Qn and the scan clock signal CLK are low, the third transistor T3 in the pull-up module 20 is turned off, and the pull-up module 30 outputs a low-level signal to the output node Rn, making the gate drive signal G(n) low. The fifth transistor T5 in the inverting module 40 is turned on under the control of the preset high-level signal VGH, thus turning on the seventh transistor T7. The sixth transistor T6 and the eighth transistor T8 are turned on under the control of the high-level pull-up control signal, thereby inverting the low-level pull-up control signal and outputting a high-level inverted signal to the pull-down control node Kn, making the pull-down control node Kn high.
[0072] During stages F to G, the first reset signal Reset2 is high, while the first input signal G(nk), the second input signal G(n+k), and the scan clock signal CLK are all low. Since the first reset signal Reset2 is high, both the eleventh transistor T11 and the twelfth transistor T12 in the first reset module 70 are turned on, thereby pulling the pull-up control node Qn down to a low level and pulling the output node Rn down to a low level, thus maintaining the gate drive signal G(n) at a low level.
[0073] This application also provides a display device, which includes the above-described GOA driving circuit.
[0074] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units is merely an example. In practical applications, the above functions can be assigned to different functional units as needed, that is, the internal structure of the GOA driver circuit can be divided into different functional units to complete all or part of the functions described above. Furthermore, the specific names of each functional unit are only for easy differentiation and are not intended to limit the scope of protection of this application.
[0075] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, refer to the relevant descriptions of other embodiments.
[0076] It should be noted that, unless otherwise specified, all technical terms used in the embodiments of this application have the same meaning as commonly understood by those skilled in the art to which this application belongs. The technical terms used in the embodiments of this application are only used to explain specific embodiments of this application and are not intended to limit this application.
[0077] The term "embodiment" as used in the description of embodiments in this application means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0078] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0079] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A GOA driving unit, characterized in that, include: A pull-up control module, connected to a pull-up control node, is used to output a high-level pull-up control signal to the pull-up control node based on a high-level first input signal; A pull-up module, connected to the pull-up control node and the output node, is used to output a gate drive signal from the output node according to the pull-up control signal and the scan clock signal; A pull-down module, connected to the pull-up control node, is used to pull the pull-up control node down to a low level according to a high-level second input signal; An inverting module, connected to the pull-up control node, the pull-down control node, and the intermediate sustaining node, is used to invert the pull-up control signal according to a preset high-level signal and the pull-up control signal, and output the inverted signal of the pull-up control signal to the pull-down control node. A pull-down sustaining module, connected to the pull-up control node, the pull-down control node, and the output node, is used to maintain the pull-up control node and the output node at a low level according to the high-level inverted signal; The power-off reset module, connected to the intermediate maintenance node, is used to pull the intermediate maintenance node down to a low level according to the high-level power-off reset signal received after the display device is powered off.
2. The GOA driving unit according to claim 1, characterized in that, Also includes: The first reset module is connected to the pull-up control node and the output node, and is used to pull down and reset the pull-up control node and the output node according to the high-level first reset signal.
3. The GOA driving unit according to claim 1 or 2, characterized in that, The power-off reset module includes a first transistor; The source of the first transistor is connected to the intermediate sustaining node, the gate of the first transistor is used to receive the high-level power-off reset signal after the display device is powered off, and the drain of the first transistor is connected to the low-level terminal.
4. The GOA driving unit according to claim 1 or 2, characterized in that, The pull-up control module includes a second transistor; The gate and source of the second transistor are used to receive the first input signal, and the drain of the second transistor is connected to the pull-up control node.
5. The GOA driving unit according to claim 1 or 2, characterized in that, The pull-up module includes a third transistor and a first capacitor; The gate of the third transistor and the first terminal of the first capacitor are both connected to the pull-up control node. The source of the third transistor is used to connect to the scan clock signal. The drain of the third transistor and the second terminal of the first capacitor are both connected to the output node.
6. The GOA driving unit according to claim 1 or 2, characterized in that, The pull-down module includes a fourth transistor; The gate of the fourth transistor is used to receive the second input signal, the source of the fourth transistor is connected to the pull-up control node, and the drain of the fourth transistor is connected to the low-level terminal.
7. The GOA driving unit according to claim 1 or 2, characterized in that, The inverting module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; The gate, source, and source of the fifth transistor are used to connect to a preset high-level signal. The drain, source, and gate of the fifth transistor are connected to the intermediate sustaining node. The gate of the sixth transistor and the gate of the eighth transistor are connected to the pull-up control node. The drain of the sixth transistor and the drain of the eighth transistor are connected to a low-level terminal. The drain of the seventh transistor and the source of the eighth transistor are connected to the pull-down control node.
8. The GOA driving unit according to claim 1 or 2, characterized in that, The pull-down sustaining module includes a ninth transistor and a tenth transistor; The gate of the ninth transistor and the gate of the tenth transistor are both connected to the pull-down control node. The source of the ninth transistor is connected to the pull-up control node. The source of the tenth transistor is connected to the output node. The drains of the ninth transistor and the tenth transistor are connected to a low-level terminal.
9. A GOA driving circuit, characterized in that, The system includes cascaded multi-stage GOA driving units as described in any one of claims 1-8; the first input signal of each stage of the GOA driving unit is the gate driving signal output by the upper k-stage GOA driving unit, and the second input signal of each stage of the GOA driving unit is the gate driving signal output by the lower k-stage GOA driving unit; k is a positive integer.
10. A display device, characterized in that, Includes the GOA driving circuit as described in claim 9.