Goa driving unit, goa driving circuit and display device
By designing a pull-up control module in the GOA driver unit and utilizing a combination of input signals and scan clock signals, the problem of the large size of the GOA driver unit was solved, resulting in a narrower bezel for the display screen.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ZHEJIANG LAIBAO DISPLAY TECHNOLOGY CO LTD
- Filing Date
- 2025-05-30
- Publication Date
- 2026-05-29
AI Technical Summary
Existing GOA driver units are large in size due to the large number of transistors, making it impossible to achieve narrower display bezels.
By designing a pull-up control module in the GOA driver unit and simultaneously connecting it to the first input signal and the first scan clock signal, the pull-up control module can output a high-level pull-up control signal and also pull down to a low level, eliminating the need for a pull-down module and thus reducing the size of the GOA driver unit.
It achieves a reduction in the size of the GOA drive unit, supporting narrower bezel designs for displays.
Smart Images
Figure CN224304347U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of display technology, and in particular relates to a GOA driving unit, a GOA driving circuit and a display device. Background Technology
[0002] Integrating gate driver on array (GOA) circuitry onto a glass substrate creates a scanning drive for the display panel. Compared to traditional gate chip-based driving techniques, GOA technology significantly reduces manufacturing costs and allows for smaller left and right bezels on the display panel. A typical GOA driving circuit includes cascaded multi-stage GOA driving units. Each stage drives one row of pixels on the display panel, and the cascading of multiple GOA driving units enables line-by-line scanning of the display panel.
[0003] However, the existing GOA drive unit has a large number of transistors, resulting in a large size of the GOA drive unit, which makes it impossible for the display to achieve a narrower bezel. Summary of the Invention
[0004] In view of this, embodiments of this application provide a GOA driving unit, a GOA driving circuit, and a display device to solve the technical problem of the large size of existing GOA drivers.
[0005] In a first aspect, embodiments of this application provide a GOA driving unit, including:
[0006] A pull-up control module, connected to a pull-up control node, is used to output a high-level pull-up control signal to the pull-up control node based on a high-level first input signal and a high-level first scan clock signal, and to pull the pull-up control node down to a low level based on a low-level first input signal and an arbitrary-level first scan clock signal.
[0007] A pull-up module, connected to the pull-up control node and the output node, is used to output a high-level gate drive signal from the output node according to the high-level pull-up control signal and the high-level second scan clock signal;
[0008] An inverting module, connected to the pull-up control node and the pull-down control node, is used to invert the pull-up control signal according to a preset high-level signal and output the inverted signal of the pull-up control signal to the pull-down control node.
[0009] A pull-down sustaining module, connected to the pull-up control node, the pull-down control node, and the output node, is used to maintain the pull-up control node and the output node at a low level according to the high-level inverted signal;
[0010] A reset module, connected to the pull-up control node and the output node, is used to pull the pull-up control node and the output node down to a low level according to a high-level reset signal.
[0011] In one alternative implementation of the first aspect, the pull-up control module includes a first transistor;
[0012] The gate of the first transistor is used to receive the first scan clock signal, the source of the first transistor is used to receive the first input signal, and the drain of the first transistor is connected to the pull-up control node.
[0013] In one alternative implementation of the first aspect, the pull-up control module includes a first transistor and a second transistor;
[0014] The source of the first transistor is used to receive the first input signal, the gate of the first transistor is connected to the drain of the second transistor, the drain of the first transistor is connected to the pull-up control node, and the source and gate of the second transistor are used to receive the first scan clock signal.
[0015] In one alternative implementation of the first aspect, the pull-up module includes a third transistor and a first capacitor;
[0016] The gate of the third transistor and the first terminal of the first capacitor are both connected to the pull-up control node. The source of the third transistor is used to connect to the second scan clock signal. The drain of the third transistor and the second terminal of the first capacitor are both connected to the output node.
[0017] In one alternative implementation of the first aspect, the inverting module includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;
[0018] The gate, source, and source of the fourth transistor are used to connect to the preset high-level signal. The drain, source, and gate of the fourth transistor, the fifth transistor, and the sixth transistor are all connected to the intermediate sustaining node. The drain and source of the sixth transistor are all connected to the pull-down control node. The gates of the fifth and seventh transistors are connected to the pull-up control node. The drains of the fifth and seventh transistors are connected to the low-level terminal.
[0019] In one alternative implementation of the first aspect, the pull-down sustaining module includes an eighth transistor and a ninth transistor;
[0020] The gate of the eighth transistor and the gate of the ninth transistor are both connected to the pull-down control node. The source of the eighth transistor is connected to the pull-up control node. The source of the ninth transistor is connected to the output node. The drains of the eighth transistor and the drains of the ninth transistor are connected to a low-level terminal.
[0021] In one alternative implementation of the first aspect, the pull-down sustaining module includes an eighth transistor;
[0022] The gate of the eighth transistor is connected to the pull-down control node, the source of the eighth transistor is connected to the output node, and the drain of the eighth transistor is connected to a low-level terminal.
[0023] In one alternative implementation of the first aspect, the first capacitor is a bootstrap capacitor.
[0024] Secondly, embodiments of this application provide a GOA driving circuit, including n cascaded GOA driving units; wherein, the first to k-th GOA driving units are first GOA driving units, and the (k+1)-th to n-th GOA driving units are GOA driving units as described in any optional implementation of the first aspect above; the first input signal, the first scan clock signal, and the second scan clock signal connected to any GOA driving unit among the (k+1)-th to n-th GOA driving units are respectively the gate driving signal output by the upper k-th GOA driving unit, the scan clock signal corresponding to the upper k-th GOA driving unit, and the scan clock signal corresponding to the current GOA driving unit; k is a positive integer.
[0025] Thirdly, embodiments of this application provide a display device including the GOA driving circuit described in the second aspect.
[0026] Implementing the GOA driving unit, GOA driving circuit, and display device provided in the embodiments of this application has the following beneficial effects:
[0027] The GOA driving unit provided in this application embodiment simultaneously connects to the first input signal and the first scan clock signal through the pull-up control module. This enables the pull-up control module to not only output a high-level pull-up control signal to the pull-up control node, but also to pull the pull-up control node down to a low level. In other words, the level change control of the pull-up control node can be realized through only one pull-up control module. This eliminates the need for a pull-down module to pull the pull-up control node down to a low level in the GOA driving unit, thereby reducing the size of the GOA driving unit and facilitating a narrower bezel for the display screen. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 This is a schematic diagram of the structure of a GOA driving circuit provided in an embodiment of this application;
[0030] Figure 2 This is a schematic diagram of the structure of a GOA driving unit provided in an embodiment of this application;
[0031] Figure 3 A schematic diagram of the circuit structure of a GOA driving unit provided in an embodiment of this application;
[0032] Figure 4 A waveform diagram of each node and the access signal when a GOA driving unit is working normally, provided for an embodiment of this application;
[0033] Figure 5 A schematic diagram of the circuit structure of a GOA driving unit provided in another embodiment of this application;
[0034] Figure 6 This is a schematic diagram of the circuit structure of a GOA driving unit provided in another embodiment of this application. Detailed Implementation
[0035] The following embodiments are only used to illustrate the technical solutions of this application more clearly, and are therefore only examples and should not be used to limit the scope of protection of this application.
[0036] In the description of the embodiments of this application, the technical terms "comprising," "including," "having," and any variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. In the description of the embodiments of this application, unless otherwise stated, the technical term "multiple" refers to two or more, and the technical terms "at least one" or "one or more" refer to one, two, or more than two. The technical terms "first," "second," etc., are only used to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary / secondary relationship of the indicated technical features. The technical term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0037] This application first provides a GOA driving circuit. Please refer to... Figure 1 This is a schematic diagram of a GOA driving circuit provided in an embodiment of this application. Figure 1 The GOA driving circuit shown can include n cascaded GOA driving units. Each GOA driving unit can drive one row of pixels on the display panel. Cascading multiple GOA driving units enables line-by-line scanning of the display panel.
[0038] Optionally, the GOA driving units from level 1 to level k can be the first GOA driving unit. The first GOA driving unit can be an existing GOA driving unit including a pull-down module. Each GOA driving unit from level 1 to level k is used to access the start control signal STV. Any GOA driving unit from level 1 to level k is also used to access the scan clock signal corresponding to its level. For example, the level 1 GOA driving unit can be used to access the scan clock signal CLK(1) corresponding to the level 1 GOA driving unit, the level 2 GOA driving unit can be used to access the scan clock signal CLK(2) corresponding to the level 2 GOA driving unit, and so on.
[0039] Optionally, the GOA driving units from level k+1 to level n are the GOA driving units provided in subsequent embodiments of this application. For details regarding the GOA driving units provided in the embodiments of this application, please refer to the relevant descriptions in subsequent embodiments; they will not be detailed here.
[0040] This application also provides a GOA driving unit. Multiple levels of this GOA driving unit can be cascaded to obtain the aforementioned GOA driving circuit. Please refer to... Figure 2 This is a schematic diagram of the structure of a GOA driving unit provided in an embodiment of this application. Figure 2 As shown, in one optional implementation, the GOA driver unit may include a pull-up control module 10, a pull-up module 20, an inverting module 30, a pull-down sustaining module 40, and a reset module 50. Wherein:
[0041] The pull-up control module 10 can be connected to the pull-up control node Qn. The pull-up control module 10 can be used to receive the first input signal G(nk) and the first scan clock signal CLK(nk), and output a high-level pull-up control signal to the pull-up control node Qn according to the high-level first input signal G(nk) and the high-level first scan clock signal CLK(nk); the pull-up control module 10 can also be used to pull the pull-up control node Qn to a low level according to the low-level first input signal G(nk) and the arbitrary level first scan clock signal CLK(nk).
[0042] The pull-up module 20 can be connected to the pull-up control node Qn and the output node Rn. The pull-up module 20 can be used to receive the second scan clock signal CLK(n), and based on the high-level pull-up control signal and the high-level second scan clock signal CLK(n), it outputs a high-level gate drive signal G(n) from the output node Rn. The gate drive signal G(n) can be used to drive a row of pixel units corresponding to this level of GOA driving unit, or it can be used as an input signal for other levels of GOA driving units.
[0043] The inverting module 30 can be connected to the pull-up control node Qn and the pull-down control node Kn. The inverting module 30 can be used to receive a preset high-level signal VGH, invert the pull-up control signal according to the preset high-level signal VGH, and output the corresponding inverted signal to the pull-down control node Kn.
[0044] The pull-down sustaining module 40 can be connected to the pull-up control node Qn, the pull-down control node Kn, and the output node Rn. The pull-down sustaining module 40 can be used to maintain the pull-up control node Qn and the output node Rn at a low level VSS based on a high-level inverted signal.
[0045] The reset module 50 can be connected to the pull-up control node Qn and the output node Rn. The reset module 50 can be used to pull down the pull-up control node Qn and the output node Rn to a low level VSS according to a high-level reset signal.
[0046] Wherein, the first input signal G(nk) can be the gate drive signal output by the k-th stage GOA drive unit, the first scan clock signal CLK(nk) can be the scan clock signal corresponding to the k-th stage drive circuit, and the second scan clock signal CLK(n) can be the scan clock signal corresponding to the current stage drive circuit. Here, k is a positive integer, for example, k can be 3.
[0047] As can be seen from the above, the embodiments of this application, by simultaneously connecting the first input signal and the first scan clock signal to the pull-up control module, enable the pull-up control module to not only output a high-level pull-up control signal to the pull-up control node, but also to pull the pull-up control node down to a low level. That is, the level change control of the pull-up control node can be realized through only one pull-up control module, so that the GOA driving unit can eliminate the pull-down module used to pull the pull-up control node down to a low level, thereby reducing the size of the GOA driving unit and making it easier for the display screen to achieve a narrower bezel.
[0048] Please see Figure 3 This is a schematic diagram of the circuit structure of a GOA driving unit provided in an embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown, and are described in detail below:
[0049] like Figure 3 As shown, in one optional implementation, the pull-up control module 10 may include a first transistor T1. The gate of the first transistor T1 can be used to connect to a first scan clock signal CLK(nk), the source of the first transistor T1 can be used to connect to a first input signal G(nk), and the drain of the first transistor T1 can be connected to the pull-up control node Qn.
[0050] The pull-up module 20 may include a third transistor T3 and a first capacitor C1. The gate of the third transistor T3 and the first terminal of the first capacitor C1 may be connected to the pull-up control node Qn. The source of the third transistor T3 may be used to connect to the second scan clock signal CLK(n). The drain of the third transistor T3 and the second terminal of the first capacitor C1 may be connected to the output node Rn. The first capacitor C1 may be a bootstrap capacitor.
[0051] The inverting module 30 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The gate and source of the fourth transistor T4, and the source of the sixth transistor T6, can be connected to a preset high-level signal VGH. The drain of the fourth transistor T4, the source of the fifth transistor T5, and the gate of the sixth transistor T6 can be connected to an intermediate sustaining node Sn. The drain of the sixth transistor T6 and the source of the seventh transistor T7 can be connected to a pull-down control node Kn. The gate of the fifth transistor T5 and the gate of the seventh transistor T7 can be connected to a pull-up control node Qn. The drain of the fifth transistor T5 and the drain of the seventh transistor T7 can be connected to a low-level terminal. The low-level terminal is used to provide a low-level signal VSS.
[0052] In one alternative implementation, the pull-down sustaining module 40 may include an eighth transistor T8 and a ninth transistor T9. The gates of the eighth transistor T8 and the ninth transistor T9 may be connected to the pull-down control node Kn, the source of the eighth transistor T8 may be connected to the pull-up control node Qn, the source of the ninth transistor T9 may be connected to the output node Rn, and the drains of the eighth transistor T8 and the ninth transistor T9 may be connected to a low-level terminal.
[0053] The reset module 50 may include a tenth transistor T10 and an eleventh transistor T11. The source of the tenth transistor T10 may be connected to the pull-up control node Qn, and the source of the eleventh transistor T11 may be connected to the output node Rn. The gates of the tenth transistor T10 and the eleventh transistor T11 may be used to receive the reset signal Reset, and the drains of the tenth transistor T10 and the eleventh transistor T11 may be connected to a low-level terminal.
[0054] Please see Figure 4This is a waveform diagram of each node and the access signal when a GOA driving unit is working normally, as provided in an embodiment of this application. The following is in conjunction with... Figure 4 ,right Figure 3 The working principle of the GOA driver unit in the document will be explained in detail.
[0055] like Figure 4 As shown, during phases A to B, both the first scan clock signal CLK(nk) and the first input signal G(nk) are at high levels, while both the second scan clock signal CLK(n) and the reset signal Reset are at low levels. At this time, the first transistor T1 in the pull-up control module 10 is turned on, outputting a high-level pull-up control signal to the pull-up control node Qn, making the pull-up control node Qn a first high level. The pull-up control node Qn charges the first capacitor C1 in the pull-up module 20, causing the voltage level across the first capacitor C1 to rise.
[0056] During stages B to C, the first scan clock signal CLK(nk), the first input signal G(nk), and the reset signal Reset are all at low levels, while the second scan clock signal CLK(n) is at a high level. At this time, the first transistor T1 in the pull-up control module 10 is turned off. Since the first capacitor C1 is a bootstrap capacitor, it pulls the pull-up control node Qn high to a second high level (the second high level is greater than the first high level). Furthermore, the energy stored in the first capacitor C1 also turns on the third transistor T3 in the pull-up module 20, transmitting the high-level second scan clock signal CLK(n) to the output node Rn, causing the output node Rn to output a high-level gate drive signal G(n).
[0057] During stages C to D, the first scan clock signal CLK(nk), the first input signal G(nk), the second scan clock signal CLK(n), and the reset signal Reset are all at low levels. At this time, the first transistor T1 in the pull-up control module is turned off, and the pull-up control node Qn briefly maintains a first high level before going low.
[0058] During stages D to E, the first scan clock signal CLK(nk) is high, while the first input signal G(nk), the second scan clock signal CLK(n), and the reset signal Reset are all low. The first transistor T1 in the pull-up control module 10 is turned on, transmitting the low-level first input signal G(nk) to the pull-up control node Qn, causing the pull-up control node Qn to be low.
[0059] During stages F to G, the first scan clock signal CLK(nk), the first input signal G(nk), and the second scan clock signal CLK(n) are all at low level, while the reset signal Reset is at high level. At this time, the tenth transistor T10 and the eleventh transistor T11 in the reset module 50 are both turned on, thereby pulling down and resetting the pull-up control node Qn and the output node Rn to a low level VSS.
[0060] As can be seen, in this embodiment, by connecting the gate and source of the first transistor T1 in the pull-up control module 10 to the first scan clock signal CLK(nk) and the first input signal G(nk) respectively, the first transistor T1 can both output a high-level pull-up control signal to the pull-up control node Qn and pull the pull-up control node Qn down to a low level. That is, the level change control of the pull-up control node Qn can be realized through only one pull-up control module 10, thereby eliminating the need for the pull-down module in the existing GOA driver unit.
[0061] Understandably, since the pull-up control module 10 can pull the pull-up control node Qn low based on the first scan clock signal CLK(nk) and the first input signal G(nk), therefore, as Figure 5 As shown, in another alternative implementation, the pull-down sustaining module 40 may consist of only the eighth transistor T8.
[0062] In this design, the gate of the eighth transistor T8 can be connected to the pull-down control node Kn, the source of the eighth transistor T8 can be connected to the output node Rn, and the drain of the eighth transistor T8 can be connected to a low-level terminal. The eighth transistor T8 can be used to maintain the output node Rn at a low level VSS according to a high-level pull-down control signal. This not only allows the GOA drive unit to perform its original function but also eliminates the need for the transistor in the pull-down holding module 40 used to maintain the pull-up control node Qn at a low level, thereby further reducing the size of the GOA drive unit and making it easier to achieve narrower bezels in the display screen.
[0063] Please see Figure 6 This is a schematic diagram of the circuit structure of a GOA driving unit provided in another embodiment of this application. Figure 6 As shown, with Figure 5 Compared to the corresponding embodiments, the pull-up control module 10 in this embodiment may include a first transistor T1 and a second transistor T2. The source of the first transistor T1 can be used to connect to a first input signal G(nk), the gate of the first transistor T1 can be connected to the drain of the second transistor T2, the drain of the first transistor T1 can be connected to the pull-up control node Qn, and the source and gate of the second transistor T2 can be used to connect to a first scan clock signal G(nk).
[0064] The GOA driving circuit provided in this embodiment saves the pull-down module. Since the second transistor T2 is connected as a diode, the gate level of the first transistor T1 remains stable when the first scan clock signal G(nk) changes from high level to low level. It will not fluctuate with the change of the first scan clock signal G(nk), thereby improving the stability of the first transistor T1 and thus improving the stability of the entire GOA driving unit.
[0065] This application also provides a display device, which includes the above-described GOA driving circuit.
[0066] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units is merely an example. In practical applications, the above functions can be assigned to different functional units as needed, that is, the internal structure of the GOA driver circuit can be divided into different functional units to complete all or part of the functions described above. Furthermore, the specific names of each functional unit are only for easy differentiation and are not intended to limit the scope of protection of this application.
[0067] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, refer to the relevant descriptions of other embodiments.
[0068] It should be noted that, unless otherwise specified, all technical terms used in the embodiments of this application have the same meaning as commonly understood by those skilled in the art to which this application belongs. The technical terms used in the embodiments of this application are only used to explain specific embodiments of this application and are not intended to limit this application.
[0069] The term "embodiment" as used in the description of embodiments in this application means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0070] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0071] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A GOA driving unit, characterized in that, include: A pull-up control module, connected to a pull-up control node, is used to output a high-level pull-up control signal to the pull-up control node based on a high-level first input signal and a high-level first scan clock signal, and to pull the pull-up control node down to a low level based on a low-level first input signal and an arbitrary-level first scan clock signal. A pull-up module, connected to the pull-up control node and the output node, is used to output a high-level gate drive signal from the output node according to the high-level pull-up control signal and the high-level second scan clock signal; An inverting module, connected to the pull-up control node and the pull-down control node, is used to invert the pull-up control signal according to a preset high-level signal and output the inverted signal of the pull-up control signal to the pull-down control node. A pull-down sustaining module, connected to the pull-up control node, the pull-down control node, and the output node, is used to maintain the pull-up control node and the output node at a low level according to the high-level inverted signal; A reset module, connected to the pull-up control node and the output node, is used to pull the pull-up control node and the output node down to a low level according to a high-level reset signal.
2. The GOA driving unit according to claim 1, characterized in that, The pull-up control module includes a first transistor; The gate of the first transistor is used to receive the first scan clock signal, the source of the first transistor is used to receive the first input signal, and the drain of the first transistor is connected to the pull-up control node.
3. The GOA driving unit according to claim 1, characterized in that, The pull-up control module includes a first transistor and a second transistor; The source of the first transistor is used to receive the first input signal, the gate of the first transistor is connected to the drain of the second transistor, the drain of the first transistor is connected to the pull-up control node, and the source and gate of the second transistor are used to receive the first scan clock signal.
4. The GOA driving unit according to claim 1, characterized in that, The pull-up module includes a third transistor and a first capacitor; The gate of the third transistor and the first terminal of the first capacitor are both connected to the pull-up control node. The source of the third transistor is used to connect to the second scan clock signal. The drain of the third transistor and the second terminal of the first capacitor are both connected to the output node.
5. The GOA driving unit according to claim 1, characterized in that, The inverting module includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; The gate, source, and source of the fourth transistor are used to connect to the preset high-level signal. The drain, source, and gate of the fourth transistor, the fifth transistor, and the sixth transistor are all connected to the intermediate sustaining node. The drain and source of the sixth transistor are all connected to the pull-down control node. The gates of the fifth and seventh transistors are connected to the pull-up control node. The drains of the fifth and seventh transistors are connected to the low-level terminal.
6. The GOA driving unit according to claim 2, characterized in that, The pull-down sustaining module includes an eighth transistor and a ninth transistor; The gate of the eighth transistor and the gate of the ninth transistor are both connected to the pull-down control node. The source of the eighth transistor is connected to the pull-up control node. The source of the ninth transistor is connected to the output node. The drains of the eighth transistor and the drains of the ninth transistor are connected to a low-level terminal.
7. The GOA driving unit according to claim 2 or 3, characterized in that, The pull-down sustaining module includes an eighth transistor; The gate of the eighth transistor is connected to the pull-down control node, the source of the eighth transistor is connected to the output node, and the drain of the eighth transistor is connected to a low-level terminal.
8. The GOA driving unit according to claim 4, characterized in that, The first capacitor is a bootstrap capacitor.
9. A GOA driving circuit, characterized in that, It includes n cascaded GOA driving units; wherein, the first to the kth level GOA driving units are the first GOA driving units, and the (k+1)th to the nth level GOA driving units are the GOA driving units as described in any one of claims 1-8; the first input signal, the first scan clock signal, and the second scan clock signal connected to any GOA driving unit in the (k+1)th to the nth level GOA driving units are respectively the gate driving signal output by the kth level GOA driving unit, the scan clock signal corresponding to the kth level GOA driving unit, and the scan clock signal corresponding to the current level GOA driving unit; k is a positive integer.
10. A display device, characterized in that, Includes the GOA driving circuit as described in claim 9.