Analog signal output stabilizing circuit

Abstract

Analog signal output stabilizing circuit, including signal input module, signal processing module and signal output module, signal input module's input with control unit's PWM output end connection, signal input module is used for converting the PWM signal into direct current signal, and signal output is given to signal processing module, signal processing module includes complex processing unit, output sampling unit and feedback unit, complex processing unit with signal input module's output is connected, complex processing unit's output with signal output module's input is connected, complex processing unit's output with output sampling unit's input is connected, in the utility model, signal input module converts PWM signal into direct current signal, feedback unit in signal processing module gathers output current signal, and the composite sampling signal with signal input module output signal, improves the stability of output signal.

Description

Technical Field

[0001] This utility model relates to the field of electrical engineering, and more particularly to signal processing, specifically an analog signal output stabilization circuit. Background Technology

[0002] When outputting analog signals, fluctuations and instability often occur due to load variations, especially in applications where high output stability is required, such as measuring instruments like temperature transmitters. Output instability affects data accuracy and overall system performance; therefore, an analog signal output stabilization circuit is needed to improve the stability of the analog signal output. Summary of the Invention

[0003] The purpose of this invention is to provide an analog signal output stabilization circuit, which aims to solve the technical problem of insufficient stability of analog signal output in the prior art.

[0004] This analog output stabilization circuit of the present invention includes a signal input module, a signal processing module, and a signal output module;

[0005] The output terminal of the signal input module is connected to the input terminal of the signal processing module, and is used to output DC signals to the signal processing module;

[0006] The signal processing module includes a composite processing unit, an output sampling unit, and a feedback unit. The composite processing unit includes a first input terminal and a second input terminal. The first input terminal is connected to the output terminal of the signal input module, the output terminal of the composite processing unit is connected to the input terminal of the signal output module, and the output terminal of the composite processing unit is connected to the input terminal of the output sampling unit. The feedback unit includes a third input terminal and a fourth input terminal. The third input terminal is connected to the input terminal of the output sampling unit, and the fourth input terminal is connected to the output terminal of the output sampling unit.

[0007] The input terminal of the signal output module is connected to the output terminal of the output sampling unit, and is used to output the signal processed by the signal processing module.

[0008] Furthermore, the signal input module includes a ninth resistor, a tenth resistor, a third capacitor, a second operational amplifier, a third capacitor, a fourth capacitor, an eleventh resistor, and a twelfth resistor.

[0009] One end of the ninth resistor is connected to the PWM signal source. The other end of the ninth resistor is connected to one end of the tenth resistor and one end of the third capacitor. The other end of the tenth resistor is connected to the non-inverting input of the second operational amplifier and one end of the fourth capacitor. The other end of the fourth capacitor is grounded. The inverting input of the second operational amplifier is connected to one end of the eleventh resistor and one end of the twelfth resistor. The other end of the eleventh resistor is connected to the reference voltage. The output of the second operational amplifier is connected to the other end of the twelfth resistor, the other end of the third capacitor, and the first input of the composite processing unit.

[0010] Furthermore, the composite processing unit includes a thirteenth resistor, a fifth capacitor, a third operational amplifier, a sixth capacitor, a fifteenth resistor, a seventh capacitor, a sixteenth resistor, and a first transistor.

[0011] One end of the thirteenth resistor is the first input terminal of the composite processing unit. The other end of the thirteenth resistor is connected to one end of the fifth capacitor and the non-inverting input terminal of the third operational amplifier. The inverting input terminal of the third operational amplifier is connected to one end of the sixth capacitor. The output terminal of the third operational amplifier is connected to one end of the fourteenth resistor and one end of the fifteenth resistor. The other end of the fourteenth resistor is connected to one end of the seventh capacitor and the base of the first transistor. The collector of the first transistor is connected to one end of the sixteenth resistor. The other end of the sixteenth resistor is connected to a 15V power supply. The other end of the fifteenth resistor is connected to the other end of the sixth capacitor, the other end of the seventh capacitor, and the emitter of the first transistor.

[0012] The output sampling unit includes a first resistor and a second resistor. One end of the first resistor is connected to the emitter of the first transistor, and the other end of the first resistor is connected to one end of the second resistor.

[0013] The feedback unit includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a first operational amplifier.

[0014] One end of the fourth resistor is connected to the other end of the second resistor. The other end of the fourth resistor is connected to the non-inverting input of the first operational amplifier and one end of the fifth resistor. The other end of the fifth resistor is grounded. The other end of the third resistor is connected to the inverting input of the first operational amplifier and one end of the sixth resistor. The output of the first operational amplifier is connected to the other end of the sixth resistor and one end of the seventh resistor. The other end of the seventh resistor is connected to one end of the eighth resistor. The other end of the eighth resistor is connected to the inverting input of the third operational amplifier.

[0015] Furthermore, the signal output module includes a first bidirectional Zener diode, a first capacitor, a first inductor, a second inductor, and an output terminal. Port 2 of the output terminal is connected to one end of the first bidirectional Zener diode, one end of the first capacitor, and one end of the first inductor. Port 3 of the output terminal is connected to one end of the first bidirectional Zener diode, the other end of the first capacitor, and one end of the second inductor. The other end of the first inductor is connected to one end of the second capacitor, one end of the first resistor, and the output terminal of the output sampling unit. The other ends of the second inductor and the other end of the second capacitor are grounded.

[0016] Compared with existing technologies, the advantages of this invention are positive and significant. In this invention, the signal input module inputs a DC signal to the signal processing module, the output sampling unit in the signal processing module generates a sampling signal, the feedback unit processes the sampling signal, and then feeds the processed signal back to the composite processing unit, thereby improving output stability. Attached Figure Description

[0017] Figure 1 This is the circuit diagram of this utility model.

[0018] In the diagram, the following are the markings: 100, Signal Input Module; 200, Signal Processing Module; 210, Composite Processing Unit; 220, Output Sampling Unit; 230, Feedback Unit; 300, Signal Output Module; P1, Output Terminal; D3, First Bidirectional Zener Diode; C66, First Capacitor; L7, First Inductor; L8, Second Inductor; C42, Second Capacitor; R64, First Resistor; R91, Second Resistor; R47, Third Resistor; R50, Fourth Resistor; R53, Fifth Resistor; R44, Sixth Resistor; U9C, First Operating... Operational amplifier; R46, seventh resistor; R49, eighth resistor; R42, ninth resistor; R43, tenth resistor; U9A, second operational amplifier; C36, third capacitor; C35, fourth capacitor; R36, eleventh resistor; R37, twelfth resistor; R38, thirteenth resistor; C51, fifth capacitor; U9D, third operational amplifier; C40, sixth capacitor; R61, fourteenth resistor; R63, fifteenth resistor; C41, seventh capacitor; R58, sixteenth resistor; U13, first transistor. Detailed Implementation

[0019] The present invention will be further described below with reference to the accompanying drawings and embodiments, but this does not limit the present invention.

[0020] like Figure 1As shown, the present invention provides an analog signal output stabilization circuit, which includes a signal input module 100, a signal processing module 200, and a signal output module 300.

[0021] The output terminal of the signal input module 100 is connected to the input terminal of the signal processing module 200, and is used to output a DC signal to the signal processing module 200.

[0022] The signal processing module 200 includes a composite processing unit 210, an output sampling unit 220, and a feedback unit 230.

[0023] The composite processing unit 210 includes a thirteenth resistor R38, a fifth capacitor C51, a third operational amplifier U9D, a sixth capacitor C40, a fifteenth resistor R63, a seventh capacitor C41, a sixteenth resistor R58, and a first transistor U13. One end of the thirteenth resistor R38 is connected to the signal input module 100, and the other end of the thirteenth resistor R38 is connected to one end of the fifth capacitor C51 and the non-inverting input terminal of the third operational amplifier U9D. The inverting input terminal of the third operational amplifier U9D is connected to one end of the sixth capacitor C40. The connection is as follows: the output terminal of the third operational amplifier U9D is connected to one end of the fourteenth resistor R61 and one end of the fifteenth resistor R63; the other end of the fourteenth resistor R61 is connected to one end of the seventh capacitor C41 and the base of the first transistor U13; the collector of the first transistor U13 is connected to one end of the sixteenth resistor R58; the other end of the sixteenth resistor R58 is connected to a 15V power supply; and the other end of the fifteenth resistor R63 is connected to the other ends of the sixth capacitor C40, the other end of the seventh capacitor C41, and the emitter of the first transistor U13.

[0024] The output sampling unit 220 includes a first resistor R64 and a second resistor R91. One end of the first resistor R64 is connected to the emitter of the first transistor U13, and the other end of the first resistor R64 is connected to one end of the second resistor R91.

[0025] The feedback unit 230 includes a third resistor R47, a fourth resistor R50, a fifth resistor R53, a sixth resistor R44, and a first operational amplifier U9C. One end of the fourth resistor R50 is connected to the other end of the second resistor R91. The other end of the fourth resistor R50 is connected to the non-inverting input terminal of the first operational amplifier U9C and one end of the fifth resistor R53. The other end of the fifth resistor R53 is grounded. The other end of the third resistor R47 is connected to the inverting input terminal of the first operational amplifier U9C and one end of the sixth resistor R44. The output terminal of the first operational amplifier U9C is connected to the other end of the sixth resistor R44 and one end of the seventh resistor R46. The other end of the seventh resistor R46 is connected to one end of the eighth resistor R49. The other end of the eighth resistor R49 is connected to the inverting input terminal of the third operational amplifier U9D.

[0026] The input terminal of the signal output module 300 is connected to the other end of the second resistor R91. The signal output module 300 is used to output the signal processed by the signal processing module 200.

[0027] Furthermore, the signal input module 100 includes a ninth resistor R42, a tenth resistor R43, a third capacitor C36, a second operational amplifier U9A, a fourth capacitor C35, an eleventh resistor R36, and a twelfth resistor R37.

[0028] One end of the ninth resistor R42 is connected to the PWM signal source. The other end of the ninth resistor R42 is connected to one end of the tenth resistor R43 and one end of the third capacitor C36. The other end of the tenth resistor R43 is connected to the non-inverting input terminal of the second operational amplifier U9A and one end of the fourth capacitor C35. The other end of the fourth capacitor C35 is grounded. The inverting input terminal of the second operational amplifier U9A is connected to one end of the eleventh resistor R36 and one end of the twelfth resistor R37. The other end of the eleventh resistor R36 is connected to the reference voltage input terminal. The output terminal of the second operational amplifier U9A is connected to the other end of the twelfth resistor R37, the other end of the third capacitor C36, and the first input terminal of the composite processing unit 210.

[0029] Furthermore, the signal output module 300 includes a first bidirectional Zener diode D3, a first capacitor C66, a first inductor L7, a second inductor L8, and an output terminal P1. Port 2 of the output terminal P1 is connected to one end of the first bidirectional Zener diode D3, one end of the first capacitor C66, and one end of the first inductor L7. Port 3 of the output terminal P1 is connected to one end of the first bidirectional Zener diode D3, the other end of the first capacitor C66, and one end of the second inductor L8. The other end of the first inductor L7 is connected to one end of the second capacitor C42, one end of the first resistor R64, and the output terminal of the output sampling unit 220. The other ends of the second inductor L8 and the other ends of the second capacitor C42 are grounded.

[0030] When this utility model is used, the signal input module 100 performs low-pass filtering on the input PWM signal through the ninth resistor R42 and the third capacitor C34, as well as the tenth resistor and the fourth capacitor C35, to convert the PWM signal into a DC signal. Then, the DC signal is amplified by the second operational amplifier U9A and output to the signal processing module 200.

[0031] In the signal processing module 200, one end of the thirteenth resistor R38 receives the DC signal output by the signal input module 100. The output current of the composite processing unit 210 generates a voltage drop through the first resistor R64 and the second resistor R91 of the output sampling unit 220. By sampling the voltage drop, the magnitude of the current of the output signal can be obtained. Therefore, one end of the fourth resistor R50 is connected to the input terminal of the output sampling unit 220, and one end of the third resistor R47 is connected to the output terminal of the output sampling unit 220. The voltage signal across the output sampling unit 220 is input into the first operational amplifier U9C. The first operational amplifier U9C and the sixth resistor R44 cooperate to perform a subtraction operation. The difference between the voltage signals across the feedback unit 230 is output at the output terminal of the first operational amplifier U9C, thereby sampling the current signal output by the composite processing unit 210. Then, the sampled signal is input into the composite processing unit 210 after passing through the eighth resistor R49. In the composite processing unit 210, the DC signal output from the signal input module 100 is filtered by the thirteenth resistor R38 and the fifth capacitor C51 before entering the non-inverting input of the second operational amplifier U9D. The sampled signal is filtered by the sixth capacitor C40 before entering the inverting input of the second operational amplifier U9D, forming negative feedback. The second operational amplifier U9D adjusts the voltage at its output terminal to make the voltages at the non-inverting and inverting input terminals approximately equal, thereby stabilizing the current and voltage difference of the output sampling unit 220, and ultimately stabilizing the output current and voltage of the control signal processing module 200. The output terminal of the third operational amplifier U9D is filtered by the fourteenth resistor R61 and the seventh capacitor C41 and connected to the base of the first transistor U13. The first transistor U13 is an NPN transistor. The collector of the first transistor U13 is connected to a 15V power supply through the sixteenth resistor R58. The base input current of the first transistor U13 controls the output current of the emitter of the first transistor U13, thereby improving the signal current driving capability.

[0032] In the signal output module 300, the analog voltage signal output from the feedback unit 230 of the signal processing module 200 passes through the first inductor L7 and is connected to port 2 of the output terminal P1 as the positive terminal of the output analog signal. The ground terminal passes through the second inductor L8 and is connected to port 3 of the output terminal P1 as the negative terminal of the output analog signal. The first bidirectional Zener diode D3 plays the role of overvoltage protection, limiting the output voltage and preventing excessive voltage from damaging subsequent equipment. The first inductor L7, the second inductor L8, the first capacitor C66, and the second capacitor C42 all play the role of filtering, which can attenuate the high-frequency part of the signal, thereby making the output analog signal more stable.

Claims

1. An analog signal output stabilization circuit, characterized in that: It includes a signal input module, a signal processing module, and a signal output module; The output terminal of the signal input module is connected to the input terminal of the signal processing module, and is used to output DC signals to the signal processing module; The signal processing module includes a composite processing unit, an output sampling unit, and a feedback unit. The composite processing unit includes a thirteenth resistor, a fifth capacitor, a third operational amplifier, a sixth capacitor, a fifteenth resistor, a seventh capacitor, a sixteenth resistor, and a first transistor. One end of the thirteenth resistor is connected to the signal input module, and the other end is connected to one end of the fifth capacitor and the non-inverting input of the third operational amplifier. The inverting input of the third operational amplifier is connected to one end of the sixth capacitor. The output of the third operational amplifier is connected to one end of the fourteenth resistor and one end of the fifteenth resistor. The other end of the fourteenth resistor is connected to one end of the seventh capacitor and the base of the first transistor. The collector of the first transistor is connected to one end of the sixteenth resistor. The other end of the sixteenth resistor is connected to a 15V power supply. The other end of the fifteenth resistor is connected to the other ends of the sixth and seventh capacitors and the emitter of the first transistor. The output sampling unit includes a first resistor and a second resistor. One end of the first resistor is connected to the emitter of a first transistor, and the other end of the first resistor is connected to one end of the second resistor. The feedback unit includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a first operational amplifier. One end of the fourth resistor is connected to the other end of the second resistor. The other end of the fourth resistor is connected to the non-inverting input terminal of the first operational amplifier and one end of the fifth resistor. The other end of the fifth resistor is grounded. The other end of the third resistor is connected to the inverting input terminal of the first operational amplifier and one end of the sixth resistor. The output terminal of the first operational amplifier is connected to the other end of the sixth resistor and one end of the seventh resistor. The other end of the seventh resistor is connected to one end of the eighth resistor. The other end of the eighth resistor is connected to the inverting input terminal of the third operational amplifier. The input terminal of the signal output module is connected to the other end of the second resistor, and the signal output module is used to output the signal processed by the signal processing module.

2. The analog signal output stabilization circuit as described in claim 1, characterized in that: The signal input module includes a ninth resistor, a tenth resistor, a third capacitor, a second operational amplifier, a fourth capacitor, an eleventh resistor, and a twelfth resistor. One end of the ninth resistor is connected to the PWM signal source. The other end of the ninth resistor is connected to one end of the tenth resistor and one end of the third capacitor. The other end of the tenth resistor is connected to the non-inverting input of the second operational amplifier and one end of the fourth capacitor. The other end of the fourth capacitor is grounded. The inverting input of the second operational amplifier is connected to one end of the eleventh resistor and one end of the twelfth resistor. The other end of the eleventh resistor is connected to the reference voltage input. The output of the second operational amplifier is connected to the other end of the twelfth resistor, the other end of the third capacitor, and the first input of the composite processing unit.

3. The analog signal output stabilization circuit as described in claim 1, characterized in that: The signal output module includes a first bidirectional Zener diode, a first capacitor, a first inductor, a second inductor, and an output terminal. Port 2 of the output terminal is connected to one end of the first bidirectional Zener diode, one end of the first capacitor, and one end of the first inductor. Port 3 of the output terminal is connected to one end of the first bidirectional Zener diode, the other end of the first capacitor, and one end of the second inductor. The other end of the first inductor is connected to one end of the second capacitor, one end of the first resistor, and the output terminal of the output sampling unit. The other ends of the second inductor and the other end of the second capacitor are grounded.

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