A low-frequency time code receiving antenna module selection system
By using a low-frequency time code receiving antenna module optimization system, the performance inconsistency problem of low-frequency time code user receiving terminals under low signal-to-noise ratio conditions was solved, achieving stable signal transmission and performance evaluation, and improving user satisfaction and terminal consistency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- 封开低频时码授时台
- Filing Date
- 2025-02-26
- Publication Date
- 2026-05-29
Smart Images
Figure CN224305778U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of radio timing signal receiving and processing technology, specifically relating to a low-frequency time code receiving antenna module selection system. Background Technology
[0002] Low-frequency time code user receiving terminals, such as radio-controlled clocks, radio-controlled watches, and low-frequency time code receivers, often exhibit inconsistent receiving performance under low signal-to-noise ratio conditions when produced in the same batch. For example, under the same receiving conditions, multiple user receiving terminals of the same model may have different decoding times. Some user receiving terminals may fail to decode or have large fluctuations in the 1PPS (Pulse Per Second) output. For users who need to operate multiple receiving terminals simultaneously, this inconsistency greatly reduces user satisfaction and user experience.
[0003] In order to keep the performance of low-frequency time code user receiving terminals as consistent as possible and improve user satisfaction and user experience, this patent proposes a method and device for optimizing low-frequency time code receiving antenna modules. Utility Model Content
[0004] This invention provides a low-frequency time code receiving antenna module optimization system to solve the technical problem in the prior art where low-frequency time code user receiving terminals produced in the same batch have inconsistent receiving performance under low signal-to-noise ratio conditions, resulting in different decoding times, inability to decode, or large fluctuations in 1PPS, thereby reducing user satisfaction and user experience.
[0005] To achieve the above objectives, the present invention adopts the following technical solution:
[0006] A low-frequency time-code receiving antenna module selection system includes a low-frequency time-code analog source, a receiving antenna test board, and a digital signal processing board. The receiving antenna test board includes a multi-stage low-frequency time-code receiving module. The digital signal processing board includes a ZYNQ 7010 FPGA processing module. The ZYNQ 7010 FPGA processing module includes a decoding module and a measurement module with the same number of stages as the low-frequency time-code receiving modules, as well as an RTC module and an ARM hard core module. The decoding module and the measurement module are connected one-to-one. The output of the low-frequency time-code analog source is connected to the input of the low-frequency time-code receiving module, the RTC module, and the measurement module, respectively. The output of the RTC module and the output of the measurement module are both connected to the ARM module.
[0007] The digital signal processing board includes a 485 to TTL module with the same number of stages as the decoding module. The output of the 485 to TTL module is connected to the input of the decoding module in a one-to-one correspondence. The input of the 485 to TTL module is connected to the output of the receiving antenna test board.
[0008] The receiving antenna test board includes a TTL to 485 module with the same number of stages as the low-frequency time code receiving module. The input terminals of the TTL to 485 module are connected one-to-one with the output terminals of the low-frequency time code receiving module, and the output terminals of the TTL to 485 module are connected one-to-one with the input terminals of the 485 to TTL module.
[0009] The receiving antenna test board also includes a ferrite rod antenna with the same number of stages as the low-frequency time code receiving module. The ferrite rod antenna is connected in series with the low-frequency time code receiving module and the TTL to 485 module in a one-to-one correspondence.
[0010] The number of stages in the low-frequency time code receiving module in the receiving antenna test board can be flexibly adjusted according to the chip resources and test efficiency.
[0011] A transmitting antenna is installed on the low-frequency time code analog source, and a ferrite rod antenna receives the radio signals transmitted by the transmitting antenna.
[0012] The distance between the transmitting antenna and the ferrite rod antenna is 3 meters, and this distance can be flexibly adjusted according to the actual test conditions.
[0013] The ARM hard core module is connected to a serial port display screen, which displays the output results of the ARM hard core module.
[0014] The serial port display uses the TJC8048K050 serial port display.
[0015] The low-frequency time code analog source uses an analog source with adjustable transmit power.
[0016] Compared with the prior art, the present invention has the following beneficial effects:
[0017] This utility model discloses a low-frequency time-code receiving antenna module optimization system. The system design is flexible and highly scalable, allowing adjustment of the position or number of ferrite rod antennas to adapt to different application scenarios. Simultaneously, the ARM architecture-based design facilitates easier software-level functional improvements. The receiving antenna test board includes a TTL-to-485 module, and the digital signal processing board includes a 485-to-TTL module, with one-to-one connections. This design facilitates stable signal conversion and reliable transmission between different level standards, ensuring the accuracy and stability of data transmission between the low-frequency time-code receiving module and the digital signal processing board. The reasonable connection architecture between the low-frequency time-code analog source, the receiving antenna test board, and the digital signal processing board ensures smooth operation from analog signal generation and reception to digital signal processing, contributing to improved overall system anti-interference capabilities and reduced bit error rate issues during signal transmission. The decoding and measurement modules in the ZYNQ 7010 FPGA processing module have the same number of stages as the low-frequency time-code receiving modules and are connected one-to-one, enabling precise decoding and measurement of the signals received by each low-frequency time-code receiving module, facilitating accurate analysis of each receiving module's performance. The RTC module provides a time reference for the system. Combined with the output of the measurement module, it can accurately record and analyze the performance of different low-frequency time code receiving modules at different time points, which helps to evaluate the stability of the modules under different time conditions.
[0018] Furthermore, the low-frequency time code analog source uses an adjustable transmit power analog source, which can simulate environments with different signal strengths. It can test the low-frequency time code receiving antenna module under different power conditions, and more comprehensively evaluate the module's receiving performance under different signal-to-noise ratio conditions.
[0019] Furthermore, the distance between the transmitting antenna and the ferrite rod antenna is fixed at 3 meters. This distance can be flexibly adjusted according to the actual test conditions, providing a unified and standardized signal transmission environment for the test, ensuring that the conditions for each test are consistent, and improving the comparability and reliability of the test results.
[0020] Furthermore, the ARM hard core module is connected to a serial port display screen, which can intuitively display the system's processing results, making it convenient for operators to observe and analyze test data in real time, understand the performance of each module in a timely manner, and improve the visualization and work efficiency of the optimization process. Attached Figure Description
[0021] Figure 1 Block diagram of the principle of low-frequency time code receiving antenna optimization. Detailed Implementation
[0022] To further understand the present invention, the following detailed description is provided in conjunction with the accompanying drawings and specific embodiments. It should be understood that the embodiments are merely illustrative and not intended to limit the scope of the invention.
[0023] See Figure 1 Three low-frequency time-code antenna receiving modules are inserted into the receiving antenna test board: Module 1, Module 2, and Module 3. Each of these modules has a ferrite rod antenna connected to its input: Module 1, Module 2, and Module 3. A transmitting antenna is mounted on the low-frequency time-code analog source, with the ferrite rod antennas 3 meters away from it. Each of the three receiving modules has a TTL-to-485 converter connected to its output: Module 1, Module 2, and Module 3. The ferrite rod antennas receive the radio signals transmitted by the analog source's transmitting antenna and transmit them to the receiving modules. The receiving modules demodulate the signals and output a TTL digital signal. The TTL signal is then converted to a 485 signal via the TTL-to-485 converters. The receiving antenna test board outputs the 485 signal to a digital signal processing board, which includes three 485-to-TTL converters and a ZYNQ converter. The ZYNQ 7010 FPGA processing module contains three decoding modules, three measurement modules, an RTC module, and an ARM hard core module. The three 485-to-TTL modules are designated as 485-to-TTL Module 1, 485-to-TTL Module 2, and 485-to-TTL Module 3, corresponding to the three TTL-to-485 modules on the receiving antenna test board. The outputs of these three modules are connected to the three decoding modules (Decoding Module 1, Decoding Module 2, and Decoding Module 3). The three measurement modules are designated as Measurement Module 1, Measurement Module 2, and Measurement Module 3. The inputs of these modules are connected to the outputs of the decoding and RTC modules. The outputs of the measurement modules are connected to the ARM hard core module, which is connected to a serial display screen. The ARM hard core module displays the calculation results on the serial display screen.
[0024] This embodiment provides a low-frequency time-code receiving antenna module optimization system, the specific implementation method of which is as follows:
[0025] Taking the ferrite rod antenna 1, low-frequency time code receiving module 1, TTL to 485 module 1, 485 to TTL module 1, decoding module 1, and measurement module 1 as an example, the 485 to TTL module converts the 485 signal to a TTL signal. The TTL signal is decoded by the decoding module 1, which outputs the frame parsing success flag dec1, the decoded time code value tod1, and the 1PPS signal d1_1pps to the ARM hard core module. The measurement module 1 measures the interval between the moni_1pps output by the low-frequency time code analog source and the d1_1pps output by the decoding module 1, and then outputs the measured value mea1 to the ARM hard core module. The RTC module receives the moni_tod and moni_1pps output by the low-frequency time code analog source and outputs the current time code value rtc_local to the ARM hard core module. The ARM hard core module reads the frame parsing success flag dec1 and the decoded time code value tod1. 1. The ARM hard core module generates data such as the 1PPS signal d1_1pps and the current time code value rtc_local, and performs corresponding calculations on the above data. The ARM hard core module is connected to a serial port display screen, and displays the calculation results on the serial port display screen. The displayed data includes the maximum value, minimum value, peak-to-peak value, standard deviation, number of successful decodings, and measurement time. Decoding modules 2 and 3 output the corresponding frame parsing success flag dec2, decoding time code value tod2, and 1PPS signal d2_1pps, respectively. Decoding modules 2 and 3 output the corresponding measurement values mea2 and mea3, respectively. Decoding modules 2 and 3 perform the same tasks as decoding modules 1 and measurement modules 1.
[0026] In a shielded room environment, the room temperature is 25℃, and the humidity is constant, typically 50%RH. The low-frequency time code receiver module uses C-MAX's CME6005 AM demodulation chip, Xilinx's ZYNQ 7010 FPGA, and Taojingchi's TJC8048K050 serial display screen. The low-frequency time code analog source is a self-developed adjustable transmit power analog source. Taking my country's low-frequency time code BPC timing system as an example, the transmission carrier frequency is 68.5kHz, the frame period is 20s, and the symbol period is 1s. The 1PPS signal moni_1pps output by the low-frequency time code analog source is strictly synchronized with the start time of each symbol of its transmitted low-frequency time code radio signal. The low-frequency time code analog source outputs time code information through the serial port within each symbol. The hardware component of this solution consists of a receiving antenna test board, a digital signal processing board, and a serial port display. The receiving antenna test board can accommodate three low-frequency timecode antenna receiving modules. In actual use, the number of test slots can be flexibly increased according to the chip resources and testing efficiency, while adhering to the same principle.
[0027] The receiving antenna test board is equipped with three ferrite rod antennas, three low-frequency time-code antenna receiving modules, and three TTL-to-485 modules, namely ferrite rod antenna 1, ferrite rod antenna 2, and ferrite rod antenna 3; the three low-frequency time-code antenna receiving modules are low-frequency time-code antenna receiving module 1, low-frequency time-code antenna receiving module 2, and low-frequency time-code antenna receiving module 3; the three TTL-to-485 modules are TTL-to-485 module 1, TTL-to-485 module 2, and TTL-to-485 module 3; align the three ferrite rod antennas with the direction of the incoming wave from the low-frequency time-code analog source transmitting antenna, as shown... Figure 1 As shown, the three ferrite rod antennas are 3 meters away from the transmitting antenna. The low-frequency time-code analog source transmits radio signals through its transmitting antenna. The three ferrite rod antennas on the receiving antenna test board receive the radio signals and send them to the corresponding three low-frequency time-code receiving modules. The radio signals are resonantly selected within the three low-frequency time-code receiving modules and then demodulated by the CME6005 to output three TTL signals. The three TTL signals are then converted into three 485 signals by three TTL-to-485 converters. During the decoding process described above, the receiving antenna test board gradually reduces the transmitting power of the low-frequency time-code analog source until all three low-frequency time-code receiving modules cannot decode normally. Then, it gradually increases the transmitting power of the low-frequency time-code analog source until at least one of the three receiving modules can decode normally.
[0028] To reduce interference from the digital signal processing board to the receiving antenna test board, the TTL-to-485 module of the receiving antenna test board outputs its three-channel 485 signal to the digital signal processing board. The digital signal processing board includes three 485-to-TTL modules and a ZYNQ 7010 FPGA processing module. The ZYNQ 7010 FPGA processing module includes measurement modules 1, 2, and 3, as well as decoding modules 1, 2, and 3, and an ARM module. After the 485 signal is converted by the 485-to-TTL module on the digital signal processing board, it outputs three TTL signals, which then enter the ZYNQ 7010 FPGA processing module. Figure 1 The gray box in the digital processing board represents the design of the ZYNQ 7010 FPGA processing module. Specifically, the ZYNQ 7010 FPGA processing module includes three decoding modules, three measurement modules, and one RTC module. The three decoding modules are designated as Decoding Module 1, Decoding Module 2, and Decoding Module 3, and the three measurement modules are designated as Measurement Module 1, Measurement Module 2, and Measurement Module 3. Figure 1 The principle block diagram is shown below. The following process takes the signal transmission between decoding module 1, measurement module 1, RTC module, and ARM hard core module as an example.
[0029] The RTC module in the ZYNQ 7010 FPGA processing module receives the moni_1pps signal and time code information moni_tod sent by the analog source, performs RTC synchronization, and outputs the current time code value rtc_local to the ARM hard core module.
[0030] Decoding module 1 parses the TTL signal output from 485 to TTL module 1 and outputs the decoded time code value tod1, the 1PPS signal d1_1pps, and the frame parsing success flag dec1. Decoding module 1 outputs the decoded time code value tod1, the 1PPS signal d1_1pps, and the frame parsing success flag dec1 to the ARM hard core module. At the same time, decoding module 1 transmits the 1PPS signal d1_1pps to measurement module 1. The low-frequency time code analog source outputs the moni_1pps signal and the time code information moni_tod. The RTC module receives the moni_1pps signal and the time code information moni_tod, performs RTC synchronization on the two signals, outputs the current time code value rtc_local, and then outputs the current time code value rtc_local to the ARM hard core module. The frame parsing success flag dec1 indicates that a frame of data has been successfully parsed. The dec1 signal serves as an interrupt signal for the ARM hard core module. Upon receiving this interrupt, the ARM hard core module reads the current timecode value rtc_local output from the RTC module and the decoding timecode value tod1 output from decoding module 1, and compares them. If the current timecode value rtc_local is 20 seconds longer than the decoding timecode value tod1, it indicates that the frame was decoded correctly, because the decoding time lags behind the analog source time by one frame period, i.e., 20 seconds. If decoding is correct, the number of successful decodings is counted. Decoding modules 2 and 3 are similar to decoding module 1. The ARM hard core module responds to the dec2 and dec3 interrupts output by decoding modules 2 and 3 respectively, determines whether the decoding is correct, and counts the number of successful decodings. The ARM hard core module then sends the number of successful decodings to the serial port display screen for display.
[0031] Measurement module 1 simultaneously receives the 1PPS signal d1_1pps output by decoding module 1 and the moni_1pps signal sent by the low-frequency timecode analog source. Measurement module 1 measures the interval between the moni_1pps signal and the d1_1pps signal. d1_1pps serves as an interrupt for the ARM hard core module. After measurement, it outputs a measurement value mea1 to the ARM hard core module. The ARM hard core module responds to the d1_1pps interrupt and reads the measurement value mea1 from FPGA measurement module 1. As the number of measurement data samples increases, the ARM hard core module calculates the maximum, minimum, peak-to-peak value, and standard deviation of these data. Measurement modules 2-3 are similar to module 1. The ARM hard core module responds to the d2_1pps and d3_1pps interrupts output by measurement modules 2 and 3 respectively, reads the corresponding measurement values, and calculates the maximum, minimum, peak-to-peak value, and standard deviation of the measurement values.
[0032] After system initialization, the ARM hard core module waits for the command to start measurement from the serial port screen. If no start command is received, it waits in a loop. If a start command is received, the various modules in the FPGA's internal processing module begin working. Then, it checks if the measurement time has expired. If the measurement time has not expired, it continues; otherwise, it terminates the measurement.
[0033] After detecting any interruption of the dec1~dec3 signals output by decoding modules 1, 2, and 3, the ARM hard core module reads the current time code value rtc_local output by the RTC module and the corresponding decoded time code values tod1~tod3 output by decoding modules 1, 2, and 3. After judging the correctness of decoding, the ARM hard core module sends the corresponding number of successful decodings to the serial port screen for display. After detecting any interruption of the d1_1pps~d3_1pps signals output by decoding modules 1, 2, and 3, the ARM hard core module calculates the maximum, minimum, peak-to-peak, and standard deviation of the measured values and sends the corresponding calculated values to the serial port screen for display. Finally, based on the calculated values, the best-performing ferrite rod antenna is selected, and its corresponding receiving antenna module is further selected.
[0034] The above embodiments are only used to illustrate the technical solution of this utility model and are not intended to limit it. Although the utility model has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of this utility model. Any modifications or equivalent substitutions that do not depart from the spirit and scope of this utility model should be covered within the protection scope of the claims of this utility model.
Claims
1. A low-frequency time-code receiving antenna module selection system, characterized in that, The system includes a low-frequency timecode analog source, a receiving antenna test board, and a digital signal processing board. The receiving antenna test board includes a multi-stage low-frequency timecode receiving module, a ferrite rod antenna with the same number of stages as the low-frequency timecode receiving module, and a TTL-to-485 module. The ferrite rod antenna is connected in series with the low-frequency timecode receiving module and the TTL-to-485 module in a one-to-one correspondence. A transmitting antenna is mounted on the low-frequency timecode analog source, and the transmitting antenna interacts with the ferrite rod antenna. The digital signal processing board includes a ZYNQ 7010 FPGA processing module. The FPGA processing module includes a 485-to-TTL module, a decoding module, and a measurement module with the same number of stages as the low-frequency time code receiving module, as well as an RTC module and an ARM hard core module. The input terminals of the TTL-to-485 module are connected one-to-one with the output terminals of the low-frequency time code receiving module, the output terminals of the TTL-to-485 module are connected one-to-one with the input terminals of the 485-to-TTL module, the output terminals of the 485-to-TTL module are connected one-to-one with the input terminals of the decoding module, and the decoding module and measurement module are connected one-to-one. The output terminals of the low-frequency time code analog source are connected to the input terminals of the low-frequency time code receiving module, the RTC module, and the measurement module, respectively. The output terminals of the RTC module and the measurement module are both connected to the ARM module.
2. The low-frequency time-code receiving antenna module selection system according to claim 1, characterized in that, The distance between the transmitting antenna and the ferrite rod antenna is 3 meters.
3. The low-frequency time-code receiving antenna module optimization system according to claim 1, characterized in that, The ARM hard core module is connected to a serial port display screen, which displays the output results of the ARM hard core module.
4. The low-frequency time-code receiving antenna module selection system according to claim 3, characterized in that, The serial port display uses the TJC8048K050 serial port display.
5. The low-frequency time-code receiving antenna module selection system according to claim 1, characterized in that, The low-frequency time code analog source uses an analog source with adjustable transmit power.