Flip-flop and master latch circuit
By employing a single-phase master latch circuit in the flip-flop, receiving single-phase timing signals, and utilizing clock gate circuits and combinational logic circuits, the problems of slow data propagation speed and race failures are solved, thereby improving the performance of the flip-flop.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2025-01-10
- Publication Date
- 2026-06-02
AI Technical Summary
Existing flip-flops suffer from slow data propagation and data contention faults when receiving timing signals of different phases.
A single-phase master latch circuit is adopted to receive single-phase timing signals. Through the design of clock gate circuit and combinational logic circuit, the time required for data to reach the output node from the rising edge of the clock signal is reduced, thus avoiding data contention.
It improves data transmission speed, reduces data contention failures, and optimizes the performance of the flip-flop.
Smart Images
Figure CN224319340U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to flip-flop and master latch circuits in digital electronic devices. Background Technology
[0002] A flip-flop is a device used in digital electronic devices for storing and transmitting binary data. In some flip-flops, the time between receiving data and generating data at the output node is equal to the setup time (e.g., the time it takes for the data to remain constant on the rising edge of a clock signal) plus the amount of time it takes for the data to travel from the rising edge of the clock signal to the output node. Some flip-flops use clock signals with different phases to control both the master and slave circuits within the flip-flop. In such flip-flops, there is a tradeoff between the setup time and the amount of time it takes for the data to travel from the rising edge of the clock signal to the output node. This can result in slower data propagation in some flip-flops. Furthermore, some flip-flop designs can lead to data racing failures (e.g., a race condition where data captured by the master circuit is incorrectly transmitted to the slave circuit before the pass gate between the master and slave circuits closes). Summary of the Invention
[0003] A circuit includes a single-phase master latch configured to receive a data signal and a first timing signal having a first phase. The circuit is configured to generate a master latch output signal based on the data signal and the first timing signal. The single-phase master latch is not configured to receive a second timing signal having a second phase. The circuit further includes a slave latch coupled to the single-phase master latch. The slave latch is configured to: receive the master latch output signal and the second timing signal having a second phase; store digital data based on the master latch output signal; and generate a flip-flop output signal based on the master latch output signal.
[0004] A master latch circuit includes a clock-gated circuit comprising a plurality of clock-gated transistors. The clock-gated circuit is configured to: receive a first timing signal and a data signal, the first timing signal having a first phase; and generate a clock-gated output signal based on the first timing signal and the data signal. The master latch circuit further includes combinational logic coupled to the clock-gated circuit. The combinational logic is configured to receive the clock-gated output signal and the first timing signal. The clock-gated circuit is further configured to store the clock-gated output signal and invert the clock-gated output signal.
[0005] A method for storing data includes receiving a data signal and a first timing signal at a master latch, the first timing signal having a first phase. The method further includes generating a master latch output signal based on the data signal and the first timing signal. The method further includes receiving the master latch output signal and a second timing signal at a slave latch, the second timing signal having a second phase. The second timing signal is not received at the master latch. The method further includes storing digital data in the slave latch based on the master latch output signal. The method further includes generating a flip-flop output signal based on the master latch output signal. Attached Figure Description
[0006] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
[0007] Figure 1 A block diagram of a flip-flop with a single-phase master latch is shown according to some embodiments;
[0008] Figure 2 A single-phase master latch according to some embodiments is illustrated;
[0009] Figure 3 A unit cell flip-flop with a single-phase master latch is illustrated according to some embodiments;
[0010] Figure 4 A PMOS single-phase master latch according to some embodiments is illustrated;
[0011] Figure 5 An NMOS single-phase master latch according to some embodiments is illustrated;
[0012] Figure 6A A single-phase master latch according to some embodiments is illustrated;
[0013] Figure 6B A timing diagram of a single-phase master latch according to some embodiments is shown;
[0014] Figure 7 A flip-flop with a single-phase master latch is illustrated according to some embodiments;
[0015] Figure 8 A flip-flop with a single-phase master latch is illustrated according to some embodiments;
[0016] Figure 9 A flip-flop with a single-phase master latch is illustrated according to some embodiments;
[0017] Figure 10 A flip-flop with a single-phase master latch is illustrated according to some embodiments;
[0018] Figure 11 A multi-bit flip-flop with a single-phase master latch is illustrated according to some embodiments;
[0019] Figure 12 A detailed illustration of a multi-bit flip-flop with a single-phase master latch is shown according to some embodiments;
[0020] Figure 13 A method for storing data according to some embodiments is illustrated. Detailed Implementation
[0021] The following detailed description is provided to help readers fully understand the methods, apparatus, and / or systems described herein. Therefore, various changes, modifications, and equivalents of the systems, apparatus, and / or methods described herein will be suggested to those skilled in the art. Furthermore, for clarity and brevity, descriptions of well-known functions and structures may be omitted.
[0022] It should be understood that the wording and terminology used herein are for illustrative purposes and should not be considered limiting. For example, the use of singular terms (e.g., "a") is not intended to limit the number of items. Furthermore, for clarity, the use of related terms in the description (e.g., but not limited to "top," "bottom," "left," "right," "upper," "lower," "down," "up," "side") is not intended to limit the scope of the invention or the appended claims. Moreover, it should be understood that any of these features may be used alone or in combination with other features. Other systems, methods, features, and advantages of the invention will become apparent to those skilled in the art upon review of the detailed description. It is intended that all such additional systems, methods, features, and advantages be included in this description, within the scope of the invention, and protected by the appended claims.
[0023] As mentioned above, flip-flops are used in digital electronic devices to store and transmit binary data. In some flip-flops, the main latch circuit receives two different timing signals with different phases. In such flip-flops, there is a trade-off between the set time and the amount of time required for data to reach the output node from the rising edge of the clock signal. This can cause slow data propagation in some flip-flops. Furthermore, some flip-flop designs can lead to data race failures.
[0024] In embodiments, the flip-flop may include a master latch circuit that receives a timing signal having a single phase. The embodiments disclosed herein relate to a master latch circuit that receives a timing signal having a single phase. These embodiments can mitigate the trade-off between the setpoint time and the amount of time required for data to reach the output node from the rising edge of the clock signal, increase data propagation time, and reduce data contention failures.
[0025] Figure 1 A block diagram of a flip-flop with a single-phase master latch is shown according to some embodiments. Figure 1 In the example shown, the flip-flop 100 includes a single-phase master latch 101 and a slave latch 102. The flip-flop 100 further includes a first inverter 109 and a second inverter 110 coupled to the first inverter 109. The first inverter 109 receives a clock pulse signal CP 105 and generates an inverted clock signal clkb 107. The second inverter 110 receives the inverted clock signal clkb 107 and generates a double-inverted clock signal clkbb 106. The double-inverted clock signal clkbb 106 is received at the single-phase master latch 101 and the slave latch 102. The inverted clock signal clkb 107 is also received at the slave latch 102. The single-phase master latch 101 also receives a data signal D 104 and a serial input signal SI 103. A single-phase master latch 101 is configured to store a data signal D 104 during a transition of the inverting clock signal clkb 107 (e.g., from 0 to 1). The data signal D 104 is fixed within the single-phase master latch 101. Based on the data signal D 104 and the serial input signal SI 103, the single-phase master latch 101 generates a master latch output signal 111. The master latch output signal 111 may be the same value as the data signal D 104, or it may be the inverted value of the data signal D 104. The master latch output signal 111 is received from the slave latch 102. When the inverting clock signal clkb 107 transitions again (e.g., from 1 to 0), the master latch output signal 111 is fixed within the slave latch 102. When the master latch output signal 111 is fixed within the slave latch 102, the single-phase master latch 101 begins receiving the new value of the data signal D 104. Based on the master latch output signal 111, the inverting clock signal clkb 107, and the dual inverting clock signal clkbb 106, the slave latch 102 generates a flip-flop output signal Q 108. The flip-flop output signal Q can be equal to the value of the data signal D 104 from the previous clock cycle.
[0026] Figure 2 A single-phase master latch according to some embodiments is illustrated. Figure 2In the example shown, the single-phase master latch 101 includes a clock gate circuit 201 and a combinational logic circuit 202. The clock gate circuit 201 receives a data signal D 104 and a dual-inverted clock signal clkbb 106. Based on the data signal D 104 and the dual-inverted clock signal clkbb 106, the clock gate circuit 201 generates a gated output signal 203. The combinational logic circuit 202 receives the gated output signal 203. The combinational logic circuit 202 also receives the dual-inverted clock signal clkbb 106. Based on the gated output signal 203 and the dual-inverted clock signal clkbb 106, the combinational logic circuit 202 generates a master latch output signal 111.
[0027] Figure 3 A unit cell flip-flop with a single-phase master latch is illustrated according to some embodiments. Figure 3 In the example shown, the flip-flop 300 includes a single-phase master latch 101, a transmit gate 301, and a slave latch 102. The single-phase master latch 101 includes a clock gate circuit 201 and a combinational logic circuit 202. Both the clock gate circuit 201 and the combinational logic circuit 202 include multiple transistors. The clock gate circuit 201 receives a bi-inverted clock signal clkbb 106 at the gate terminal of a first PMOS transistor 310, which has a source terminal coupled to an operating voltage node 308. The clock gate circuit 201 receives a serial enable signal 302 at a serial enable PMOS transistor 311. The clock gate circuit 201 also receives a data signal D 104 at a data PMOS transistor 313, a serial input signal SI 304 at a serial input PMOS transistor 314, and an inverted serial enable signal SEB 303 at an inverted serial enable PMOS transistor 312.
[0028] Furthermore, the clock gate circuit 201 receives the data signal D 104 at the data NMOS transistor 315, the serial input signal SI 304 at the serial input NMOS transistor, the serial enable signal SE 302 at the serial enable NMOS transistor 318, and the inverting serial enable signal SEB 303 at the inverting serial enable NMOS transistor 317. When the dual inverting clock signal clkbb 106 is lower than the threshold voltage of the first PMOS transistor 310, the first PMOS transistor 310 will be turned on, and the voltage at the operating voltage node 308 will appear at the drain terminal of the first PMOS transistor 310. Furthermore, if both the data signal D 104 and the serial enable signal SE 302 are lower than the threshold voltage levels of the data PMOS transistor 313 and the serial enable PMOS transistor 311 (e.g., logic low), then when the dual-inverting clock signal clkbb 106 is sufficiently low, the voltage at the operating voltage node 308 will appear at the first master latch node 305. Alternatively, if both the inverting serial enable signal SEB 303 and the serial input signal SI 304 are lower than the threshold voltage levels of the inverting serial enable PMOS transistor 312 and the serial input PMOS transistor 314, then when the dual-inverting clock signal clkbb 106 is sufficiently low, the voltage at the operating voltage node 308 will appear at the first master latch node 305. If the voltage at the operating voltage node 308 appears at the first master latch node 305, then the first master latch node 305 will have a logic high voltage level.
[0029] Data NMOS transistor 315 includes a drain terminal coupled to the first master latch node 305. Inverting serial enable NMOS transistor 317 includes a drain terminal coupled to the source terminal of data NMOS transistor 315. The source terminal of inverting serial enable NMOS transistor 317 is coupled to ground node 309. Serial input NMOS transistor 316 includes a drain terminal coupled to the first master latch node 305. Serial enable NMOS transistor 318 includes a drain terminal coupled to the source terminal of serial input NMOS transistor 316 and a source terminal coupled to ground node 309. Data NMOS transistor 315 is turned on when data signal D 104 is higher than the threshold voltage level. If inverting serial enable signal SEB 303 is also higher than the threshold voltage level, then inverting serial enable NMOS transistor 317 will be turned on and the voltage at ground node 309 (e.g., zero volts) will appear at the first master latch node 305. Alternatively, if both the serial input signal SI 304 and the serial enable signal SE 302 are above the voltage threshold level, then both the serial input NMOS transistor 316 and the serial enable NMOS transistor 318 will be turned on, and the voltage at ground node 309 will appear at the first master latch node 305. If the voltage at ground node 309 appears at the first master latch node 305, then the first master latch node 305 will have a logic low voltage level.
[0030] The clock gate circuit 201 further includes a first NMOS transistor 319 and a second NMOS transistor 320. The first NMOS transistor 319 has a drain terminal coupled to a first master latch node 305. The first NMOS transistor has a gate terminal receiving a bi-inverted clock signal clkbb 106 and a source terminal coupled to the drain terminal of the second NMOS transistor 320. The second NMOS transistor 320 has a source terminal coupled to a ground node 309. The clock gate circuit 201 further includes a second PMOS transistor 321, which has a source terminal coupled to an operating voltage node 308. The second PMOS transistor 321 has a gate terminal receiving a bi-inverted clock signal clkbb 106. The second PMOS transistor 321 includes a drain terminal coupled to the source terminal of a third PMOS transistor 322. The third PMOS transistor 322 includes a gate terminal coupled to the first master latch node 305. The third PMOS transistor 322 further includes a drain terminal coupled to the drain terminal of the third NMOS transistor 323. The third NMOS transistor 323 includes a gate terminal coupled to the first master latch node 305 and a source terminal coupled to the ground node 309.
[0031] The combinational logic circuit 202 includes a fourth PMOS transistor 326 and a fourth NMOS transistor 327. The fourth PMOS transistor 326 includes a source terminal coupled to the operating voltage node 308. The gate terminal of the fourth PMOS transistor 326 is coupled to the second master latch node 306. The drain terminal of the fourth PMOS transistor 326 is coupled to the third master latch node 307 and to the drain terminal of the fourth NMOS transistor 327. The gate terminal of the fourth NMOS transistor 327 is coupled to the second master latch node 306. The source terminal of the fourth NMOS transistor 327 is coupled to the ground node 309. The combinational logic circuit 202 further includes a fifth NMOS transistor 324 and a sixth NMOS transistor 325. The fifth NMOS transistor 324 includes a drain terminal coupled to the second master latch node 306 and a gate terminal receiving the bi-inverting clock signal clkbb 106. The fifth NMOS transistor 324 further includes a source terminal coupled to the drain terminal of the sixth NMOS transistor 325. The sixth NMOS transistor 325 further includes a gate terminal coupled to the third master latch node 307 and a source terminal coupled to the ground node 309.
[0032] The third master latch node 307 is coupled to the transmit gate 301. The transmit gate 301 includes a PMOS transmit transistor 328 and an NMOS transmit transistor 329. The transmit gate 301 is configured to receive signals at the third master latch node 307 and transmit signals to the slave latch 102, as further described below. The slave latch 102 is configured to store data transmitted to the slave latch 102 via the transmit gate 301.
[0033] Figure 4 A PMOS single-phase master latch according to some embodiments is illustrated. Figure 4 In the example shown, the PMOS single-phase master latch 401 is configured to receive a dual-inverting clock signal clkbb 106 at the first PMOS transistor 310, the second PMOS transistor 321, the first NMOS transistor 319, and the fifth NMOS transistor 324. The PMOS single-phase master latch 401 is used in a flip-flop with an even number of clock inverter stages. When an even number of clock inverter stages are present, it may be advantageous for the clock gate circuit 201 to receive the dual-inverting clock signal clkbb 106, because the dual-inverting clock signal clkbb 106 is similar to the inverted clock signal clkb 107 (see [link to example]). Figure 1Compared to including an additional inverter delay, the inverted clock signal clkb 107 no longer affects the set rise time (e.g., the time it takes for the data to stabilize before the edge of the timing signal being used), thus mitigating the trade-off between the set time and the amount of time required for data to reach the output node from the rising edge of the clock signal. Furthermore, the additional inverter delay can improve the set rise time by increasing the data stabilization time. Additionally, the additional inverter delay can mitigate or eliminate the possibility of data race failures because the dual inverted clock signal clkbb 106 in the multiplexer within the PMOS single-phase master latch 401 begins acquiring the data signal D 104 simultaneously with or after the inverted clock signal clkb 107 at the transmit gate 301 is turned off.
[0034] Figure 5 An NMOS single-phase master latch according to some embodiments is illustrated. Figure 4 In the example shown, the NMOS single-phase master latch 501 is configured to receive the inverted clock signal clkb 107 at the first NMOS transistor 502, the second PMOS transistor 504, the third NMOS transistor 507, and the fifth PMOS transistor 509. The NMOS single-phase master latch 501 is used in a flip-flop with an odd number of clock inverter stages. When there are an odd number of clock inverter stages, it may be advantageous for the clock gate circuit 201 to receive the inverted clock signal clkb 107 because the inverted clock signal clkb 107 is similar to the dual inverted clock signal clkbb 106 (see...). Figure 1 Compared to including additional inverter delays, this is the case when the flip-flop has an odd number of clock inverter stages. Figure 4 The advantages described in the PMOS single-phase master latch 401 can be applied to Figure 5 The NMOS single-phase master latch 501 shown is illustrated.
[0035] Figure 6A A single-phase master latch according to some embodiments is illustrated. Figure 6B Timing diagrams of a single-phase master latch according to some embodiments are shown. When combined with… Figure 6B The operation of the single-phase master latch 601 can be best understood by illustrating the timing diagram 609. Figure 6AIn the example shown, the data signal D 104 is logic high (e.g., "1"). When the inverting serial enable signal SEB 303 is also logic high, both the inverting serial enable NMOS transistor 317 and the data NMOS transistor 315 are turned on, and the voltage at ground node 309 appears at the first master latch node 305. Therefore, the first master latch signal ml_ax 602 is logic low (e.g., "0"). The logic low first master latch signal ml_ax 602 is received at the third PMOS transistor 322, and the third PMOS transistor 322 is turned on. When the dual inverting clock signal clkbb 106 is also logic low, the second PMOS transistor 321 is also turned on, and the voltage from the operating voltage node 308 is coupled to the second master latch node 603. Therefore, the second master latch signal ml_bx 603 is logic high. The second master latch signal ml_bx 603 is received at the inverter 605. Inverter 605 then generates a logic-low third master latch signal ml_cx 604. The third master latch signal ml_cx 604 is the output of single-phase master latch 601 and is received at transmit gate 610.
[0036] Figure 7 A flip-flop with a single-phase master latch is illustrated according to some embodiments. Figure 7 In the example shown, the flip-flop 700 includes a single-phase master latch 101, a transfer gate 301, and a slave latch 102. The single-phase master latch 101 is substantially similar to... Figure 6A The diagram illustrates a PMOS single-phase master latch 601. A slave latch 102 includes a first inverter 701, a second inverter 702, and a feedback inverter 703. The slave latch receives the output of the transfer gate (e.g., a latch input signal) at the first inverter 701 and the second inverter 702. The second inverter 702 then generates a flip-flop output signal 108. The output of the first inverter 701 is coupled to the input of the feedback inverter 703. The output of the feedback inverter 703 is coupled to the output of the transfer gate 301.
[0037] Figure 8 A flip-flop with a single-phase master latch is illustrated according to some embodiments. Figure 8 In the example shown, the operation of the single-phase master latch 101 and slave latch 102 can be substantially similar to Figure 7 The operation of the single-phase master latch 101 and slave latch 102 is illustrated in the figure. Figure 8 Includes a transmit gate 801 with a stacked gate structure. When the third master latch signal ml_cx 604 ( Figure 6AWhen the inverting clock signal clkb 107 is low or when the third master latch signal ml_cx604 and the dual inverting clock signal clkbb 106 are high, the transmit gate 801 is used as an inverter.
[0038] Figure 9 A flip-flop with a single-phase master latch is illustrated according to some embodiments. Figure 9 In the example shown, the single-phase main latch 101 includes an inverter 901. The inverter 901 receives a clear data signal CD 902 as an input. Additionally, the feedback inverter 703 includes an additional PMOS transistor and an additional NMOS transistor for receiving the clear data signal CD 902. When the inverter 901 and the feedback inverter 703 receive the clear data signal CD 902, the flip-flop output signal Q 108 is reset to a predetermined value (e.g., "1").
[0039] Figure 10 A flip-flop with a single-phase master latch is illustrated according to some embodiments. Figure 10 In the example shown, the flip-flop 100 includes an NMOS single-phase master latch 101. The operation of the NMOS single-phase master latch 101 is substantially similar to... Figure 5 The operation of the NMOS single-phase master latch 501 is shown below. (Refer to...) Figure 5 The NMOS single-phase master latch 101 is used in a flip-flop with an odd number of clock inverter stages. The NMOS single-phase master latch 101 uses the inverted clock signal clkb 107 instead of the dual inverted clock signal clkbb 106.
[0040] Figure 11 A multi-bit flip-flop with a single-phase master latch is illustrated according to some embodiments. Figure 11In the example shown, the multi-bit flip-flop 1100 includes a first flip-flop 1101, a second flip-flop 1102, a third flip-flop 1103, and a final flip-flop 1104. Each flip-flop 1101, 1102, 1103, and 1104 within the multi-bit flip-flop 1100 receives a bi-inverting clock signal clkbb 106 as input. The first flip-flop 1101 receives a serial input signal SI 304 and a first data signal D11105. Based on the serial input signal SI 304 and the first data signal D1105, the first flip-flop 1101 generates a first flip-flop output signal Q1 1109. The first flip-flop output signal Q1 1109 is received as input to the second flip-flop 1102. The second flip-flop 1102 also receives a second data signal 1106. Based on the first flip-flop output signal Q1 1109 and the second data signal 1106, the second flip-flop 1102 generates a second flip-flop output signal Q2 1110. The second flip-flop output signal Q2 1110 and the third data signal D3 1107 are received by the third flip-flop 1103. The output of the previous flip-flop is received as the input of the subsequent flip-flop. In addition, each flip-flop includes a dedicated data signal. The configuration and function of each individual flip-flop 1101, 1102, 1103, and 1104 may be substantially similar to any flip-flop with a single-phase master latch disclosed herein.
[0041] Figure 12 Detailed illustrations of multi-bit flip-flops with single-phase master latches according to some embodiments are shown. Figure 12 In the example shown, the multi-bit flip-flop 1100 includes a first flip-flop 1101 and a second flip-flop 1102. The first flip-flop 1101 and the second flip-flop 1102 are connected in series with each other. The operation of each individual flip-flop 1101, 1102 can be substantially similar to Figure 7 The operation of the flip-flop 700 shown.
[0042] Figure 13 The diagram illustrates methods for storing data according to some embodiments. Figure 13 In the example shown, method 1300 includes a first step 1301 of receiving a data signal and a first timing signal at a master latch, the first timing signal having a first phase. Figure 4 The diagram illustrates the first step 1301. The clock gate circuit 201 receives the data signal D 104 and the dual-inverting clock signal clkbb 106. Method 1300 further includes a second step 1302 of generating a master latch output signal based on the data signal and the first timing signal. Figure 1The second step 1302 is shown. The single-phase master latch 101 generates a master latch output signal 111. Method 1300 further includes a third step 1303 of receiving the master latch output signal and a second timing signal having a second phase from the latch. The second timing signal is not received at the master latch. Figure 1 The third step 1303 is shown. The main latch output signal 111 and the inverted clock signal clkb 107 are received from latch 102. (Example...) Figure 1 As shown, the inverted clock signal clkb 107 is not received at the master latch 101. Method 1300 further includes a fourth step 1304 of storing digital data in the slave latch based on the master latch output signal. Figure 4 As shown, digital data is stored at the third master latch node 307. Method 1300 further includes a fifth step 1305 of generating a flip-flop output signal based on the master latch output signal. Figure 1 As shown, flip-flop 100 generates flip-flop output signal Q 108.
[0043] This document describes systems and methods. In one example, a circuit includes a single-phase master latch configured to receive a data signal and a first timing signal having a first phase. The circuit is configured to generate a master latch output signal based on the data signal and the first timing signal. The single-phase master latch is not configured to receive a second timing signal having a second phase. The circuit further includes a slave latch coupled to the single-phase master latch. The slave latch is configured to: receive the master latch output signal and the second timing signal having a second phase; store digital data based on the master latch output signal; and generate a flip-flop output signal based on the master latch output signal.
[0044] In some embodiments, the circuit further includes a transmit gate coupled to the master latch and the slave latch, the transmit gate being configured to transmit the output signal of the master latch from the master latch to the slave latch.
[0045] In some embodiments, the master latch does not receive the second timing signal.
[0046] In some embodiments, the master latch is a single-phase master latch that receives a single timing signal having a single phase.
[0047] In some embodiments, the master latch is further configured to receive serial input signals.
[0048] In some embodiments, the first timing signal is a dual-inverting clock signal.
[0049] In some embodiments, the master latch is a P-type metal-oxide-semiconductor single-phase master latch.
[0050] In some embodiments, the first timing signal is an inverted clock signal.
[0051] In some embodiments, the master latch is an N-type metal-oxide-semiconductor single-phase master latch.
[0052] In another example, a master latch circuit includes a clock-gated circuit comprising a plurality of clock-gated transistors. The clock-gated circuit is configured to: receive a first timing signal and a data signal, the first timing signal having a first phase; and generate a clock-gated output signal based on the first timing signal and the data signal. The master latch circuit further includes combinational logic coupled to the clock-gated circuit. The combinational logic is configured to receive the clock-gated output signal and the first timing signal. The clock-gated circuit is further configured to store the clock-gated output signal and invert the clock-gated output signal.
[0053] In some embodiments, the master latch is a single-phase master latch that receives a single timing signal having a single phase.
[0054] In some embodiments, the first timing signal is a dual-inverting clock signal.
[0055] In some embodiments, the second timing signal is an inverted clock signal.
[0056] In some embodiments, the clock gate circuit receives the first timing signal at a plurality of P-type metal-oxide-semiconductor transistors.
[0057] In some embodiments, the clock gate circuit receives the first timing signal at a plurality of N-type metal-oxide-semiconductor transistors.
[0058] In another example, a method of storing data includes receiving a data signal and a first timing signal having a first phase at a master latch. The method further includes generating a master latch output signal based on the data signal and the first timing signal. The method further includes receiving the master latch output signal and a second timing signal having a second phase at a slave latch. The second timing signal is not received at the master latch. The method further includes storing digital data in a slave latch based on the master latch output signal. The method further includes generating a flip-flop output signal based on the master latch output signal.
[0059] In some embodiments, the method further includes receiving the first timing signal from the latch.
[0060] In some embodiments, the first timing signal is a dual-inverting clock signal.
[0061] In some embodiments, the second timing signal is an inverted clock signal.
[0062] In some embodiments, the master latch includes a plurality of transistors.
[0063] Those skilled in the art will understand that changes can be made to the above embodiments without departing from the broad inventive concept disclosed herein. Therefore, it should be understood that the invention disclosed herein is not limited to the specific embodiments disclosed, and is intended to cover modifications within the spirit and scope of the invention.
Claims
1. A flip-flop, characterized in that, include: A master latch is configured to receive a data signal and a first timing signal and generate a master latch output signal based on the data signal and the first timing signal, wherein the first timing signal has a first phase; as well as The slave latch, coupled to the master latch, is configured to: receive the output signal of the master latch and a second timing signal having a second phase; store digital data based on the output signal of the master latch; and generate a flip-flop output signal based on the output signal of the master latch.
2. The flip-flop according to claim 1, further comprising a transmit gate coupled to the master latch and the slave latch, the transmit gate being configured to transmit the output signal of the master latch from the master latch to the slave latch.
3. The flip-flop according to claim 1, wherein the master latch does not receive the second timing signal.
4. The flip-flop according to claim 1, wherein the master latch is a master latch that receives a single timing signal having a single phase.
5. The flip-flop of claim 1, wherein the master latch is further configured to receive a serial input signal.
6. A master latch circuit, characterized in that, include: A clock gate circuit includes a plurality of clock gate transistors, the clock gate circuit being configured to receive a first timing signal and a data signal and generate a clock gate output signal based on the first timing signal and the data signal, wherein the first timing signal has a first phase; as well as A combinational logic circuit is coupled to the clock gate circuit, the combinational logic circuit being configured to receive the clock gate output signal and the first timing signal, and the clock gate circuit being further configured to store the clock gate output signal and invert the clock gate output signal.
7. The master latch circuit according to claim 6, wherein the master latch is a single-phase master latch that receives a single timing signal having a single phase.
8. The main latch circuit according to claim 6, wherein the first timing signal is a dual inverted clock signal.
9. The master latch circuit according to claim 7, wherein the clock gate circuit receives the first timing signal at a plurality of P-type metal-oxide-semiconductor transistors.
10. The master latch circuit of claim 7, wherein the clock gate circuit receives the first timing signal at a plurality of N-type metal-oxide-semiconductor transistors.