A flip chip three-dimensional hybrid encapsulation structure based on a chip-on-film

Abstract

The utility model discloses a kind of three-dimensional combined sealing structures of heterogeneous chip based on die attach film, it is related to the field of semiconductor packaging technology, including middle layer substrate, the double-sided integration RDL layer of middle layer substrate, and the position of middle layer substrate corresponding RDL layer is formed LCV copper via by laser drilling;The upper of middle layer substrate is respectively provided with display drive IC and touch sensor IC, and display drive IC and touch sensor IC are formed with micro copper column bump on the side close to middle layer substrate, the utility model, by adopting flexible polyimide substrate as the interlayer of carrier, double-sided rewiring, form micro via array by laser drilling, inner wall fills nano copper paste, LCV copper via is formed by low-temperature sintering;Upper chip is flip-chip soldered on die attach film circuit by micro copper column bump, interconnection is realized by the wiring on die attach film, and NCF is filled in the gap between upper chip and interlayer;Lower substrate pad is directly interconnected with die attach film circuit by LCV copper via.

Description

Technical Field

[0001] This utility model specifically relates to the field of semiconductor packaging technology, and more specifically to a three-dimensional composite packaging structure for heterogeneous chips based on flip-chip film. Background Technology

[0002] As smart terminal devices evolve towards thinner, more flexible, and multifunctional integration, traditional packaging technologies face the following bottlenecks: Interlayer thickness is typically greater than 100μm and has high rigidity, failing to meet the bending requirements of flexible display modules; traditional TSV processes require deep silicon etching and electroplating, resulting in complex and costly processes; the use of discrete packaging for display driver ICs and touch sensors leads to long signal transmission paths and significant delays; existing interconnect technologies struggle to achieve high-density vertical interconnects on ultra-thin flexible substrates. Existing solutions such as Fan-Out wafer-level packaging suffer from insufficient circuit precision, while silicon interposers are prone to thermal stress failure due to thermal expansion coefficient (CTE) mismatch. Traditional COF-based solutions can only achieve single-sided chip integration, failing to meet the requirements of three-dimensional stacking.

[0003] Traditional silicon interposers are typically thicker than 100 μm and have high rigidity, which cannot meet the flexibility requirements of flexible display modules. Existing flexible substrates (such as PI films) lack high-density vertical interconnect capabilities, making it difficult to achieve three-dimensional stacking. This patent uses flip-chip tape to replace silicon as the interposer carrier, solving the problem of rigid silicon interposers being unable to bend, and providing a flexible three-dimensional interconnect structure with a thickness of ≤50 μm, overcoming the shortcomings of insufficient vertical interconnect capabilities in traditional flexible substrates.

[0004] Traditional TSV (Through Silicon Via) technology requires complex deep silicon etching and electroplating filling processes, resulting in high manufacturing costs. Existing microbump technology is difficult to achieve high-density interconnects with a pitch of ≤20μm on ultrathin flexible substrates. Utility Model Content

[0005] The purpose of this invention is to provide a three-dimensional heterogeneous chip packaging structure based on flip-chip thin film. This device solves the problem of three-dimensional heterogeneous integration in the field of flexible electronics. Specifically, it realizes an ultra-thin, flexible, bendable three-dimensional stacked structure, increases the interconnection spacing of heterogeneous chips, reduces signal transmission delay, lowers manufacturing cost compared to traditional TSV process, and improves thermal reliability, thereby solving the problems mentioned in the background technology.

[0006] To achieve the above objectives, this utility model provides the following technical solution:

[0007] A three-dimensional heterogeneous chip packaging structure based on flip-chip thin film includes a middle substrate, wherein the middle substrate has double-sided integrated RDL layers, and LCV copper vias are formed at the positions of the middle substrate corresponding to the RDL layers by laser drilling.

[0008] A display driver IC and a touch sensor IC are respectively disposed on the upper part of the middle substrate. Micro copper pillar bumps are formed on the side of the display driver IC and the touch sensor IC near the middle substrate. The display driver IC and the touch sensor IC are flip-chip soldered to the RDL layer of the middle substrate through the micro copper pillar bumps to achieve high-density interconnection. A non-conductive thin film is filled between the display driver IC and the touch sensor IC and the middle substrate.

[0009] A lower substrate is disposed below the middle substrate, and an aluminum / copper pad is disposed on the side of the lower substrate near the middle substrate. The aluminum / copper pad is connected to the circuit of the middle substrate through LCV copper vias.

[0010] As a further technical solution of this utility model, the middle layer substrate uses a flexible polyimide substrate as a carrier, and the thickness is controlled at 30-50μm;

[0011] As a further technical solution of this utility model, the RDL layer adopts a semi-additive process to achieve fine lines with line width and spacing of less than or equal to 2μm;

[0012] As a further technical solution of this utility model, the laser drilling at the middle substrate forms a micro-hole array with a hole diameter of 3-5μm. After the inner wall is chemically plated with copper, it is filled with nano copper paste and sintered at a low temperature of 150-200℃ to form LCV copper perforations.

[0013] As a further technical solution of this utility model, the display driver IC and the touch sensor IC are collectively referred to as the upper layer chip. The non-conductive film fills the gap between the upper layer chip and the middle layer substrate. The thickness of the non-conductive film is controlled at 5-8μm. It is formed by step curing (pre-curing at 80℃ for 60 seconds + final curing at 150℃ for 180 seconds) to form a low stress buffer layer with an elastic modulus ≤3GPa.

[0014] As a further technical solution of this utility model, the forming process of the micro copper pillar bump mainly includes the following steps:

[0015] Under-Bump Metallization (UBM) Fabrication: Ti or Cu is sputtered onto the surface of the chip's pads as a seed layer for electroplating to form a copper pillar bump UBM.

[0016] Thick photoresist pattern preparation: After coating with thick photoresist, the area to be prepared as copper pillars is exposed through pre-baking, exposure, development, and post-baking.

[0017] Copper pillar electroplating: Copper is electroplated in the patterned area of ​​UBM that is not covered by photoresist to form a copper pillar of the required height;

[0018] Photoresist removal: Photoresist is removed using chemical solvents or plasma cleaning;

[0019] Seed layer removal: Use an appropriate etching solution to remove excess metal seed layer, ensuring that the already formed copper pillars and solder layer are not damaged;

[0020] Reflow molding: The chip is heated to the melting point of tin, causing the tin to melt and form smooth bumps under the action of surface tension.

[0021] Compared with the prior art, the beneficial effects of this utility model are:

[0022] 1. In this utility model, the display driver IC and the touch sensor IC are flip-chip soldered onto the flip-chip thin film circuit through micro copper pillar bumps. Both the copper pillars and the nano copper paste are copper-based materials, and their conductivity is far superior to that of traditional solders (such as tin-silver alloys), reducing signal loss and delay.

[0023] 2. In this utility model and patent, a non-conductive thin film is used to fill the gap between the upper chip and the middle substrate to form a stress buffer layer. The non-conductive thin film and the nano copper paste work together to reduce the risk of thermal expansion mismatch, reduce warping or cracking caused by the mismatch of thermal expansion coefficients, and improve thermal stress reliability.

[0024] 3. This utility model solves the problem of three-dimensional heterogeneous integration in the field of flexible electronics. Specifically, it realizes an ultra-thin, flexible, bendable three-dimensional stacked structure, increases the interconnection spacing of heterogeneous chips, reduces signal transmission delay, lowers manufacturing costs compared to traditional TSV processes, and improves thermal reliability. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the overall structure of this utility model.

[0026] In the diagram: 1-Middle substrate, 2-RDL layer, 3-LCV copper via, 4-Display driver IC, 5-Touch sensor IC, 6-Micro copper pillar bump, 7-Non-conductive thin film, 8-Lower substrate, 9-Substrate aluminum / copper pads. Detailed Implementation

[0027] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0028] Please see Figure 1In this embodiment of the present invention, a three-dimensional bonding structure for heterogeneous chips based on flip-chip thin film includes a middle substrate 1, wherein the middle substrate 1 has a double-sided integrated RDL layer 2, and LCV copper through-holes 3 are formed at the positions of the middle substrate 1 corresponding to the RDL layer 2 by laser drilling.

[0029] By adopting the above scheme, vertical interconnection is achieved through low-temperature sintering (150-200℃) of nano copper paste (CuNP-Ag composite slurry, particle size 50-100nm), forming an LCV transmission channel. This enables the interconnection of display and touch signals within the tape layer and co-encapsulation with heterogeneous chips, breaking through the technical limitations of traditional flexible packaging.

[0030] A display driver IC4 and a touch sensor IC5 are respectively disposed on the upper part of the middle substrate 1. Micro copper pillar bumps 6 are formed on the side of the display driver IC4 and the touch sensor IC5 near the middle substrate 1. The display driver IC4 and the touch sensor IC5 are flip-chip soldered to the RDL layer 2 of the middle substrate 1 through the micro copper pillar bumps 6 to achieve high-density interconnection. A non-conductive thin film 7 is filled between the display driver IC4 and the touch sensor IC5 and the middle substrate 1.

[0031] A lower substrate 8 is disposed below the middle substrate 1, and a substrate aluminum / copper pad 9 is disposed on the side of the lower substrate 8 near the middle substrate 1. The substrate aluminum / copper pad 9 is connected to the circuit of the middle substrate 1 through LCV copper through-hole 3.

[0032] By adopting the above scheme, the aluminum / copper pads of the lower substrate 8 are directly interconnected with the circuit of the middle substrate 1 through the LCV of the nano copper paste embedded in the middle substrate 1. The bump-free design eliminates the need for traditional μBump or solder balls, achieving ultra-thin integration.

[0033] As a further technical solution of this utility model, the middle layer substrate 1 uses a flexible polyimide substrate as a carrier, and the thickness is controlled at 30-50μm;

[0034] As a further technical solution of this utility model, the RDL layer 2 adopts a semi-additive process to achieve fine lines with line width and spacing of less than or equal to 2μm;

[0035] As a further technical solution of this utility model, the laser drilling at the middle substrate 1 forms a micro-hole array with a hole diameter of 3-5μm. After chemically plating copper on the inner wall, it is filled with nano copper paste (CuNP-Ag composite paste) to replace the traditional TSV. The LCV copper perforation 3 is formed by low-temperature sintering at 150-200℃.

[0036] As a further technical solution of this utility model, the display driver IC4 and the touch sensor IC5 are collectively referred to as the upper layer chip. The non-conductive film 7 fills the gap between the upper layer chip and the middle layer substrate 1. The thickness of the non-conductive film 7 is controlled at 5-8μm. It is formed by step curing (pre-curing at 80℃ for 60 seconds + final curing at 150℃ for 180 seconds) to form a low stress buffer layer with an elastic modulus ≤3GPa.

[0037] The working principle of this utility model is as follows: during installation, the middle layer structure uses flexible polyimide (PI) substrate TAPE as a carrier, and the thickness is controlled at 30-50μm;

[0038] High-precision redistribution layers (RDLs) are integrated on both sides of the middle substrate 1, using a semi-additive process (SAP) to achieve fine lines with line width / spacing ≤2μm / 2μm.

[0039] A micro-hole array (pore diameter 3-5μm) is formed by laser drilling, and the inner wall is chemically plated with copper and then filled with nano copper paste (CuNP-Ag composite paste) to replace the traditional TSV. The LCV copper perforated structure is formed by low temperature sintering at 150-200℃.

[0040] The upper-layer display driver IC4 and touch sensor IC5 are flip-chip bonded to the middle-layer substrate 1 circuit via micro copper pillar bumps (μCuPillar, height 10-15μm, spacing ≤20μm) to achieve high-density interconnection;

[0041] A non-conductive thin film 7 is used to fill the gap between the upper chip and the middle substrate 1. The thickness of the non-conductive thin film 7 is controlled at 5-8μm. Step curing (pre-curing at 80℃ for 60 seconds + final curing at 150℃ for 180 seconds) is used to form a low stress buffer layer with an elastic modulus ≤3GPa.

[0042] The aluminum / copper pads of the lower substrate 8 are directly interconnected with the circuit of the middle substrate 1 through the LCV of the nano copper paste embedded in the middle substrate 1. The bumpless design eliminates the need for traditional μBump or solder balls, achieving ultra-thin integration.

[0043] Vertical interconnection is achieved by using nano copper paste (CuNP-Ag composite paste, particle size 50-100nm) sintered at low temperature (150-200℃) to form LCV transmission channels, realizing the interconnection of display and touch signals within the tape layer, and co-packaging with heterogeneous chips, breaking through the technical limitations of traditional flexible packaging.

[0044] The above structure solves the problem of three-dimensional heterogeneous integration in the field of flexible electronics. Specifically, it realizes an ultra-thin, flexible, bendable three-dimensional stacked structure, improves the interconnection spacing of heterogeneous chips, reduces signal transmission delay, reduces manufacturing cost compared to traditional TSV process, and improves thermal reliability.

[0045] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0046] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A three-dimensional heterogeneous chip encapsulation structure based on flip-chip thin film, characterized in that: It includes a middle substrate (1), a double-sided integrated RDL layer (2) of the middle substrate (1), and LCV copper through-holes (3) are formed by laser drilling at the position of the middle substrate (1) corresponding to the RDL layer (2). A display driver IC (4) and a touch sensor IC (5) are respectively disposed on the upper part of the middle substrate (1). Micro copper pillar bumps (6) are formed on the side of the display driver IC (4) and the touch sensor IC (5) close to the middle substrate (1). The display driver IC (4) and the touch sensor IC (5) are flip-chip bonded to the RDL layer (2) of the middle substrate (1) through the micro copper pillar bumps (6) to achieve high-density interconnection. A non-conductive film (7) is filled between the display driver IC (4) and the touch sensor IC (5) and the middle substrate (1). A lower substrate (8) is provided below the middle substrate (1), and a substrate aluminum / copper pad (9) is provided on the side of the lower substrate (8) close to the middle substrate (1). The substrate aluminum / copper pad (9) is connected to the circuit of the middle substrate (1) through LCV copper through-hole (3).

2. The heterogeneous chip three-dimensional bonding structure based on flip-chip thin film according to claim 1, characterized in that: The middle layer substrate (1) uses a flexible polyimide substrate as a carrier, with a thickness controlled at 30-50μm.

3. The heterogeneous chip three-dimensional bonding structure based on flip-chip thin film according to claim 1, characterized in that: The RDL layer (2) uses a semi-additive process to achieve fine lines with line width and spacing of less than or equal to 2μm.

4. The heterogeneous chip three-dimensional bonding structure based on flip-chip thin film according to claim 1, characterized in that: The display driver IC (4) and the touch sensor IC (5) are collectively referred to as the upper chip. The non-conductive film (7) fills the gap between the upper chip and the middle substrate (1). The thickness of the non-conductive film (7) is controlled at 5-8 μm, and a low-stress buffer layer is formed by step curing.

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