Ultrasonic transceiving processing circuit for bolt fastening stress intelligent measuring sleeve

Abstract

This utility model discloses an ultrasonic transceiver circuit for an intelligent bolt tightening stress measuring sleeve, including an MCU, a power supply module, an ultrasonic signal transmitting module, an ultrasonic signal receiving module, and an ultrasonic signal processing module. The ultrasonic signal processing module includes a high-speed AD module and an FPGA data acquisition and processing module. Using this ultrasonic transceiver circuit for the intelligent bolt tightening stress measuring sleeve, the ultrasonic signal transmitting module can control the ultrasonic probe to emit ultrasonic waves towards the bolt. Furthermore, the ultrasonic signal receiving module can amplify the returned ultrasonic information captured by the ultrasonic probe to generate a reflection time analog signal, which is then sent to the high-speed AD module for conversion into a reflection time digital signal. Finally, the FPGA data acquisition and processing module converts the reflection time digital signal into the current bolt tightening stress value before transmitting it outwards. This provides an accurate reference for the tightening gun to precisely control the bolt tightening stress.

Description

Technical Field

[0001] This utility model relates to the field of bolt fastening stress measurement technology, specifically to an ultrasonic transceiver circuit for an intelligent bolt fastening stress measurement sleeve. Background Technology

[0002] Bolt tightening stress is the axial force generated between the bolt and the connected parts under the tightening torque during the bolt tightening process, along the bolt axis. The control of bolt tightening stress has an important impact on the consistency of assembly performance and the stability of the overall machine performance.

[0003] Therefore, the applicant has designed a series of intelligent bolt fastening stress detection devices, such as the intelligent washer with publication number CN217002622U, the intelligent preload nut with publication number CN113380012B, and the intelligent bolt loosening detection device with publication number CN112432779B.

[0004] However, existing intelligent bolt tightening stress detection devices either can only detect bolt tightening stress separately after bolt installation, which is a two-step process that is not only cumbersome to operate but also inconvenient to install on tightening guns; or they are used in conjunction with bolts, and while tightening the workpiece, they are also permanently installed on the workpiece, resulting in high usage costs.

[0005] Furthermore, while some existing tightening guns come with built-in bolt tightening stress detection functions, their detection accuracy is not high due to inherent design flaws, making them unsuitable for applications requiring extremely high bolt tightening stress accuracy.

[0006] For this purpose, please see Figure 10 The applicant has designed an intelligent bolt tightening stress measuring sleeve, which includes a drive shaft 2 and an ultrasonic probe 3 synchronously mounted in the drive shaft 2. The upper end of the drive shaft 2 is synchronously mounted on the output shaft of a tightening gun via a quick-connect groove 234. The lower end of the drive shaft 2 is provided with a bolt head positioning groove 211 adapted to the bolt head. The detection end face 31 of the ultrasonic probe 3 is exposed in the bottom of the bolt head positioning groove 211. During the tightening process, the ultrasonic probe 3 can emit and capture the returned ultrasonic waves when the bolt head positioning groove 211 is fitted onto the bolt head. Based on this structure, the applicant hopes to design an ultrasonic transceiver processing circuit that can control the ultrasonic probe 3 to emit ultrasonic waves and receive and process the captured returned ultrasonic wave information, converting it into the current tightening stress value of the bolt, thereby providing an accurate reference for the tightening gun to precisely control the tightening stress of the bolt. Utility Model Content

[0007] In view of this, the present invention provides an ultrasonic transceiver processing circuit for an intelligent measuring sleeve for bolt fastening stress.

[0008] The technical solution is as follows:

[0009] The first aspect of this application relates to an ultrasonic transceiver circuit for an intelligent bolt fastening stress measuring sleeve, comprising an MCU, a power supply module, an ultrasonic signal transmitting module, an ultrasonic signal receiving module, and an ultrasonic signal processing module. The ultrasonic signal processing module includes a high-speed AD module and an FPGA data acquisition and processing module. The power supply module supplies power to the MCU. The ultrasonic signal transmitting module transmits a high-voltage ultrasonic transmission signal to an ultrasonic probe according to control commands issued by the MCU. The ultrasonic signal receiving module processes the ultrasonic waves acquired by the ultrasonic probe, amplifies them to generate a reflection time analog signal, and then sends the obtained reflection time analog signal to the high-speed AD module. The high-speed AD module converts the received reflection time analog signal into a reflection time digital signal and sends the reflection time digital signal to the FPGA data acquisition and processing module. The FPGA data acquisition and processing module converts the received reflection time digital signal into the current bolt fastening stress value and transmits the current bolt fastening stress value externally through a communication interface.

[0010] The ultrasonic transceiver processing circuit used in the intelligent bolt tightening stress measuring sleeve described above can not only control the ultrasonic probe to emit ultrasonic waves towards the bolt through the ultrasonic signal transmitting module, but also amplify the reflected ultrasonic information captured by the ultrasonic probe through the ultrasonic signal receiving module to generate a reflection time analog signal, which is then sent to the high-speed AD module to be converted into a reflection time digital signal. Finally, the FPGA data acquisition and processing module converts the reflection time digital signal into the current bolt tightening stress value and sends it outward, thus providing an accurate reference for the tightening gun to precisely control the bolt tightening stress.

[0011] In some embodiments, the power module includes a voltage conversion circuit, an isolated power supply circuit, and a communication digital isolation circuit;

[0012] The voltage conversion circuit includes a first-stage buck circuit and a second-stage buck circuit connected in sequence. The input terminal of the first-stage buck circuit receives the input power, and the output terminal of the second-stage buck circuit outputs the operating voltage to the MCU.

[0013] The isolation power supply circuit includes a first step-down isolation module and a second step-down isolation module connected in sequence. The input terminal of the first step-down isolation module receives the input power, and the second step-down isolation module outputs an isolation voltage to the communication digital isolation circuit.

[0014] The communication digital isolation circuit is equipped with dual-channel digital isolators U8 and U9, and the FPGA data acquisition and processing module is equipped with terminal blocks JP2 and JP3.

[0015] The first voltage input terminal VDDA of the dual-channel digital isolator U8 is connected to the output terminal of the second-stage step-down circuit. The signal channel output terminal VO1 and the signal channel input terminal VI2 of the dual-channel digital isolator U8 are respectively connected to the MCU-TX terminal and the MCU-RX terminal of the MCU. The second voltage input terminal VDDB of the dual-channel digital isolator U8 is connected to the output terminal of the second step-down isolation module via pin 1 of the terminal JP2. The signal channel input terminal VI1 of the dual-channel digital isolator U8 is connected to the FPGA-TX terminal of the FPGA data acquisition and processing module. The signal channel output terminal VO2 of the dual-channel digital isolator U8 is connected to the FPGA-RX terminal of the FPGA data acquisition and processing module.

[0016] The first voltage input terminal VDDA of the dual-channel digital isolator U9 is connected to the output terminal of the second-stage step-down circuit. The signal channel output terminal VO1 of the dual-channel digital isolator U9 is connected to the Enable terminal of the MCU after series resistor R2. The signal channel output terminal VO1 is also connected to the Input terminal of the MCU after series resistor R3. The second voltage input terminal VDDB of the dual-channel digital isolator U9 is connected to the output terminal of the second step-down isolation module through pin 1 of terminal JP3. The signal channel input terminal VI1 of the dual-channel digital isolator U9 is connected to the FPGA-IO terminal of the FPGA data acquisition and processing module.

[0017] In some embodiments, the first-stage step-down circuit is provided with a first three-terminal regulator U0. The input terminal of the first three-terminal regulator U0 is connected to a 12V input power supply. The input terminal is also connected in series with a capacitor C2 and then grounded. The output terminal of the first three-terminal regulator U0 is connected in series with a ferrite bead FB1 and then outputs a 5V voltage. The rear end of the ferrite bead FB1 is connected in series with a capacitor C3 and then grounded. The rear end is also connected in series with a capacitor C4 and then grounded. The rear end is also connected in series with a capacitor C5 and then grounded. The ground terminal of the first three-terminal regulator U0 is grounded.

[0018] The second-stage step-down circuit includes a second three-terminal regulator U1. The input terminal of the second three-terminal regulator U1 is connected to the rear end of the ferrite bead FB4 in series. The input terminal is also connected to ground in series with capacitor C8. The output terminal of the second three-terminal regulator U1 outputs a 3.3V operating voltage to the MCU. The output terminal is also connected to the first voltage input terminal VDDA of the dual-channel digital isolator U8 and the first voltage input terminal VDDA of the dual-channel digital isolator U9. The output terminal is also connected to ground in series with capacitor C6 and capacitor C7. The ground terminal of the second three-terminal regulator U1 is grounded.

[0019] In some embodiments, the first step-down isolation module is provided with a converter U3. The grounding terminal GND and the grounding terminal 0V of the converter U3 are independently grounded. The voltage input terminal VIN of the converter U3 is connected to a 12V input power supply. The input terminal is also connected in series with a capacitor C9 and then grounded together with the grounding terminal GND of the converter U3. The voltage output terminal VO of the converter U3 outputs a 5V isolation voltage. The voltage output terminal VO is also connected in series with a capacitor C10 and then grounded together with the grounding terminal 0V of the converter U3.

[0020] The second step-down isolation module is equipped with a voltage regulator chip U5. The voltage input terminal VIN of the voltage regulator chip U5 is connected to the voltage output terminal VO of the converter U3. The voltage output terminal VOUT of the voltage regulator chip U5 outputs a 3.3V isolation voltage and is connected to the second voltage input terminal VDDB of the dual-channel digital isolator U8 and the second voltage input terminal VDDB of the dual-channel digital isolator U9. The voltage output terminal VOUT is also connected in series with a capacitor C11 and grounded together with the ground terminal 0V of the converter U3. The ground terminal GND of the voltage regulator chip U5 is grounded together with the ground terminal 0V of the converter U3.

[0021] In some embodiments, the ultrasonic signal transmitting module includes a boost control chip U6, the ground terminal GND of the boost control chip U6 is grounded, the common terminal of the enable pin CE and the power supply terminal VDD of the boost control chip U6 is connected in series with a ferrite bead FB2 and then connected to the output terminal of the first-stage buck circuit, the common terminal is also connected in series with a capacitor C28 and then grounded, the common terminal is also connected in series with a capacitor C29 and then grounded, and the common terminal between the ferrite bead FB2 and the output terminal of the first-stage buck circuit is connected in series with a capacitor C30 and then grounded.

[0022] The feedback pin FB of the boost control chip U6 is connected to the sampling terminal U2-29 of the MCU after being connected in series with resistor R11. Sampling terminal U2-29 is also connected in series with Zener diode Z1 and then grounded. Sampling terminal U2-29 is also connected in series with capacitor C25 and then grounded. The feedback pin FB of the boost control chip U6 is connected in series with lower voltage divider resistor R15 and then grounded. The feedback pin FB is connected to a high level via upper voltage divider resistor R13. This high level is connected in series with capacitor C27 and then grounded. This high level is also connected to the cathode of fast recovery diode D8. The anode of the MOSFET is connected to the drain of the MOSFET Q2. The gate of the MOSFET Q2 is connected to the external control terminal EXT of the boost control chip U6. The source of the MOSFET Q2 is grounded. The anode of the fast recovery diode D8 is connected to the output terminal of the first-stage buck circuit after being connected in series with inductor L1 and ferrite bead FB3. The common terminal of inductor L1 and ferrite bead FB3 is connected in series with capacitor C33 and then grounded. The common terminal is also connected in series with inductor C34 and then grounded. The common terminal between ferrite bead FB3 and the output terminal of the first-stage buck circuit is connected in series with capacitor C32 and then grounded.

[0023] The high-level signal is connected to the RX terminal of the ultrasonic probe via a series resistor R12 and capacitor C26. A resistor R14 is connected in series between the RX terminal of the ultrasonic probe and the ground terminal. The common terminal of the resistor R12 and capacitor C26 is connected to the drain of the MOSFET Q3. The source of the MOSFET Q3 is grounded. The gate of the MOSFET Q3 is connected to the Enable terminal of the MCU. The gate is also connected in series with resistor R26 and then grounded.

[0024] In some embodiments, the ultrasonic signal receiving module includes a capacitor C35. The front end of capacitor C35 is connected to the RX terminal of the ultrasonic probe. The RX terminal of the ultrasonic probe is grounded after being connected in series with resistor R27. The rear end of capacitor C35 is connected to the negative input terminal of operational amplifier U7A after being connected in series with resistor R36. The output terminal of operational amplifier U7A is connected to the positive input terminal of operational amplifier U7B after being connected in series with capacitor C43. The common terminal between resistor R36 and the negative input terminal of operational amplifier U7A is connected to the front end of capacitor C43 after resistor R37. The positive power supply pin of operational amplifier U7A is connected to the output terminal of the first-stage buck circuit. The power supply pin is connected to ground via capacitor C41. The negative power supply pin of the operational amplifier U7A is grounded. The rear end of capacitor C35 is connected to the positive input terminal of operational amplifier U7A via resistor R22. This rear end is connected to the common terminal between the cathode of the first diode and the anode of the second diode of switching diode D9. The cathode of the second diode of switching diode D9 is connected to the output terminal of the first stage buck circuit. The anode of the first diode of switching diode D9 is grounded. The rear end of resistor R22 is connected to ground via resistor R28. This rear end is also connected to ground via capacitor C37. This rear end is also connected to ground via resistors R23, R31 and R34 in sequence.

[0025] The resistor R31 is connected to ground after a capacitor C42 in series at its rear end. After a resistor R35 in series at its rear end, it is connected to the common terminal between capacitor C43 and the positive input terminal of operational amplifier U7B. After a resistor R32 in series at its rear end, it is connected to the negative input terminal of operational amplifier U7B. After a resistor R33 in series at its rear end, it is connected to the output terminal of operational amplifier U7B. After a capacitor C40 in series at the common terminal between the output terminal of operational amplifier U7B and resistor R33, it is connected to the positive input terminal of operational amplifier U7C.

[0026] The rear end of resistor R23 is connected in series with resistor R20 and then to the output terminal of the first-stage buck circuit. A capacitor C38 is also connected in series with this rear end and then grounded. Resistors R24 and R29 are then connected in series with this rear end and then grounded. A capacitor C39 is connected in series with the rear end of resistor R24 ​​and then grounded. A resistor R25 is also connected in series with this rear end and then to the positive input terminal of operational amplifier U7C. A resistor R19 is also connected in series with this rear end and then to the negative input terminal of operational amplifier U7C. Resistors R17, R6, and C13 are then connected in series with the rear end of resistor R19 and then grounded. The output terminal of operational amplifier U7C is connected to the front end of resistor R6, and the rear end of resistor R6 is connected to the SMA connector J1 of the high-speed AD module. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of an ultrasonic transceiver processing circuit.

[0028] Figure 2 This is the circuit diagram for the MCU.

[0029] Figure 3 This is the circuit diagram for the first-stage step-down circuit;

[0030] Figure 4 This is the circuit diagram for the second-stage step-down circuit;

[0031] Figure 5 This is the circuit diagram for the first-stage step-down isolation module;

[0032] Figure 6 This is the circuit diagram for the second-stage step-down isolation module;

[0033] Figure 7 This is a circuit diagram of a digital isolation circuit for communication.

[0034] Figure 8 This is a circuit diagram of the ultrasonic signal transmitting module;

[0035] Figure 9 This is a circuit diagram of an ultrasonic signal receiving module.

[0036] Figure 10 This is a cross-sectional view of the intelligent bolt tightening stress measuring sleeve. Detailed Implementation

[0037] The present invention will be further described below with reference to the embodiments and accompanying drawings.

[0038] Example 1:

[0039] Please see Figure 10A smart bolt tightening stress measuring sleeve includes a drive shaft 2 and an ultrasonic probe 3 installed in the drive shaft 2. One end of the drive shaft 2 is provided with a quick-change connection structure for connecting to the output shaft of a tightening gun. Specifically, the quick-change connection structure includes a quick-connect groove 234 coaxially recessed on the end face of one end of the drive shaft 2. The quick-connect groove 234 has internal threaded holes 235 on at least two opposite sides of the groove wall. Each internal threaded hole 235 is equipped with a set screw 26 that engages with its thread. This not only ensures quick-change connection with the tightening tool, but also ensures the reliability and stability of the connection through the set screws 26. That is, the set screws 26 can move axially inward by rotation to tighten the output shaft of the tightening gun, and the set screws 26 can move axially outward by rotation to release the output shaft of the tightening gun.

[0040] The drive shaft 2 is provided with a main mounting channel 212. One end of the main mounting channel 212 is connected to the bottom of the bolt head positioning groove 211. The ultrasonic probe 3 is installed in the main mounting channel 212, and the detection end face 31 of the ultrasonic probe 3 protrudes to the bottom of the bolt head positioning groove 211. Specifically, the main mounting channel 212 is provided with an elastic component 4 for making the detection end face 31 of the ultrasonic probe 3 tend to protrude from the bottom of the bolt head positioning groove 211.

[0041] Therefore, when the bolt head positioning groove 211 is fitted onto the bolt head, the elastic component 4 forces the detection end face 31 of the ultrasonic probe 3 to always be in contact with the bolt head end face. The ultrasonic probe 3 emits and captures the returning ultrasonic waves. By measuring the change in ultrasonic speed, the change in bolt fastening stress can be accurately reflected in real time. The specific principle is as follows:

[0042] Based on the acoustoelastic effect, when the stress inside the bolt changes, the propagation speed of the ultrasonic wave will change accordingly. Therefore, there is a correspondence between the propagation time of the ultrasonic wave and the stress. Through this correspondence, the ultrasonic probe 3 can measure the propagation time of the ultrasonic wave in the bolt and thus measure the stress of the bolt.

[0043] Example 2:

[0044] like Figures 1-9As shown, an ultrasonic transceiver circuit for an intelligent bolt tightening stress measuring sleeve in Embodiment 1 mainly includes an MCU, a power supply module, an ultrasonic signal transmitting module, an ultrasonic signal receiving module, and an ultrasonic signal processing module. Preferably, the MCU in this embodiment is a 32-bit microcontroller, model STM32F103C8T6. The power supply module supplies power to the MCU. The ultrasonic signal processing module includes a high-speed AD module and an FPGA data acquisition and processing module. The ultrasonic signal transmitting module transmits high-voltage ultrasonic transmission signals to the ultrasonic probe 3 according to control commands issued by the MCU. The ultrasonic signal receiving module processes the ultrasonic waves acquired by the ultrasonic probe 3, amplifies them to generate a reflection time analog signal, and then sends the obtained reflection time analog signal to the high-speed AD module. The high-speed AD module converts the received reflection time analog signal into a reflection time digital signal and sends the reflection time digital signal to the FPGA data acquisition and processing module. The FPGA data acquisition and processing module uses an embedded data receiving and processing algorithm to convert the received reflection time digital signal into the current bolt tightening stress value and sends the current bolt tightening stress value outward through the communication interface.

[0045] In this embodiment, the power module includes a voltage conversion circuit, an isolated power supply circuit, and a communication digital isolation circuit.

[0046] Please see Figure 3 and Figure 4 The voltage conversion circuit includes a first-stage buck circuit and a second-stage buck circuit connected in sequence. The input terminal of the first-stage buck circuit obtains the input power supply, and the voltage of the input power supply is 12V. The output terminal of the first-stage buck circuit and the input terminal of the second-stage buck circuit both have a voltage of 5V. The output terminal of the second-stage buck circuit outputs the working voltage to the MCU, and the working voltage is 3.3V.

[0047] Please see Figure 3 The first-stage buck circuit includes a first three-terminal regulator U0. The input of U0 is connected to a 12V power supply, and a capacitor C2 is connected in series with this input before grounding. The output of U0 is a 5V voltage output via a ferrite bead FB1 connected in series. A capacitor C3 is connected in series with the rear end of FB1 before grounding, followed by another capacitor C4 and then another capacitor C5. The ground terminal of U0 is also grounded. This first-stage buck circuit can stably convert a 12V DC voltage to a 5V DC voltage.

[0048] Please see Figure 4The second-stage buck circuit includes a second three-terminal regulator U1. The input of regulator U1 is connected in series with a ferrite bead FB4 and then to the rear end of FB4. This input is also connected in series with a capacitor C8 and then grounded. The output of regulator U1 provides a 3.3V operating voltage to the MCU. This output is also connected to the first voltage inputs VDDA of dual-channel digital isolators U8 and U9. This output is connected in series with capacitors C6 and C7 and then grounded. The ground terminal of regulator U1 is also grounded. This second-stage buck circuit can stably convert 5V DC voltage to 3.3V DC voltage.

[0049] Please see Figure 5 and Figure 6 The isolation power supply circuit includes a first step-down isolation module and a second step-down isolation module connected in sequence. The input terminal of the first step-down isolation module receives the input power, and the second step-down isolation module outputs an isolation voltage to the communication digital isolation circuit. This isolation power supply circuit is used to isolate and protect the FPGA data acquisition and processing module.

[0050] Please see Figure 5 The first step-down isolation module includes a converter U3. The grounding terminals GND and 0V of converter U3 are independently grounded. The voltage input terminal VIN of converter U3 is connected to a 12V input power supply. This input terminal is connected in series with capacitor C9 and then grounded together with the grounding terminal GND of converter U3. The voltage output terminal VO of converter U3 outputs a 5V isolation voltage. This voltage output terminal VO is also connected in series with capacitor C10 and then grounded together with the grounding terminal 0V of converter U3. The first step-down isolation module can stably convert a 12V DC voltage to a 5V isolation voltage.

[0051] Please see Figure 6 The second step-down isolation module includes a voltage regulator chip U5. The voltage input terminal VIN of voltage regulator chip U5 is connected to the voltage output terminal VO of converter U3. The voltage output terminal VOUT of voltage regulator chip U5 outputs a 3.3V isolation voltage, which is connected to the second voltage input terminals VDDB of dual-channel digital isolators U8 and U9. A capacitor C11 is connected in series with the voltage output terminal VOUT, and then it is grounded together with the 0V ground terminal of converter U3. The ground terminal GND of voltage regulator chip U5 is also grounded together with the 0V ground terminal of converter U3. The second step-down isolation module can stably convert a 5V isolation voltage to a 3.3V isolation voltage.

[0052] Please see Figure 7 The communication digital isolation circuit is equipped with dual-channel digital isolators U8 and U9, and the FPGA data acquisition and processing module is equipped with terminal blocks JP2 and JP3.

[0053] The first voltage input terminal VDDA of the dual-channel digital isolator U8 is connected to the output terminal of the second-stage step-down circuit, i.e., 3.3V DC voltage. The signal channel output terminal VO1 and the signal channel input terminal VI2 of the dual-channel digital isolator U8 are connected to the MCU-TX terminal and the MCU-RX terminal of the MCU, respectively. The second voltage input terminal VDDB of the dual-channel digital isolator U8 is connected to the output terminal of the second step-down isolation module through pin 1 of terminal JP2, i.e., 3.3V isolation voltage. The signal channel input terminal VI1 of the dual-channel digital isolator U8 is connected to the FPGA-TX terminal of the FPGA data acquisition and processing module through pin 2 of terminal JP2. The signal channel output terminal VO2 of the dual-channel digital isolator U8 is connected to the FPGA-RX terminal of the FPGA data acquisition and processing module through pin 3 of terminal JP2.

[0054] The first voltage input terminal VDDA of the dual-channel digital isolator U9 is connected to the output terminal of the second-stage step-down circuit, i.e., 3.3V DC voltage. The signal channel output terminal VO1 of the dual-channel digital isolator U9 is connected to the Enable terminal of the MCU after series resistor R2. The signal channel output terminal VO1 is also connected to the Input terminal of the MCU after series resistor R3. The second voltage input terminal VDDB of the dual-channel digital isolator U9 is connected to the output terminal of the second step-down isolation module through pin 1 of terminal JP3, i.e., 3.3V isolation voltage. The signal channel input terminal VI1 of the dual-channel digital isolator U9 is connected to the FPGA-IO terminal of the FPGA data acquisition and processing module through pin 2 of terminal JP3.

[0055] The dual-channel digital isolators U8 and U9 have a signal transmission rate of 150Mbps and an isolation voltage of up to 5KV, thus exhibiting excellent electromagnetic interference immunity, precise timing characteristics, and low power loss. With Schmitt trigger inputs, they achieve high noise immunity and high insulation capability, effectively preventing noise and surges from the data bus or other circuits from entering the local ground terminal, thereby interfering with or damaging sensitive circuits and protecting the circuit.

[0056] Please see Figure 8 The ultrasonic signal transmitting module includes a boost control chip U6. The ground terminal GND of the boost control chip U6 is grounded. The common terminal of the enable pin CE and the power supply terminal VDD of the boost control chip U6 is connected in series with a ferrite bead FB2 and then connected to the output terminal of the first-stage buck circuit, i.e., 5V DC voltage. The common terminal is also connected in series with a capacitor C28 and then grounded. The common terminal between the ferrite bead FB2 and the output terminal of the first-stage buck circuit is connected in series with a capacitor C30 and then grounded.

[0057] The feedback pin FB of the boost control chip U6 is connected to the sampling terminal U2-29 of the MCU after being connected in series with resistor R11. Sampling terminal U2-29 is also connected in series with Zener diode Z1 and then grounded. Sampling terminal U2-29 is also connected in series with capacitor C25 and then grounded. The feedback pin FB of the boost control chip U6 is connected in series with the lower voltage divider resistor R15 and then grounded. The feedback pin FB is connected to a high level through the upper voltage divider resistor R13. This high level is connected in series with capacitor C27 and then grounded. This high level is also connected to the cathode of fast recovery diode D8, and the anode of fast recovery diode D8... The drain of MOSFET Q2 is connected to the gate of MOSFET Q2, which is connected to the external control terminal EXT of the boost control chip U6. The source of MOSFET Q2 is grounded. The anode of fast recovery diode D8 is connected in series with inductor L1 and ferrite bead FB3 and then connected to the output terminal of the first-stage buck circuit, i.e., 5V DC voltage. The common terminal of inductor L1 and ferrite bead FB3 is connected in series with capacitor C33 and then grounded. This common terminal is also connected in series with inductor C34 and then grounded. The common terminal between ferrite bead FB3 and the output terminal of the first-stage buck circuit is connected in series with capacitor C32 and then grounded.

[0058] The high-level signal is connected to the RX terminal of the ultrasonic probe 3 via a series resistor R12 and capacitor C26. A resistor R14 is connected in series between the RX terminal of the ultrasonic probe 3 and the ground terminal. The common terminal of the resistor R12 and capacitor C26 is connected to the drain of the MOSFET Q3. The source of the MOSFET Q3 is grounded. The gate of the MOSFET Q3 is connected to the Enable terminal of the MCU. The gate is also connected in series with a resistor R26 and then grounded.

[0059] The ultrasonic signal transmitting module described above is controlled by the MCU to transmit ultrasonic waves at a frequency that is also controlled by the MCU. It also boosts the 5V voltage output from the first-stage step-down circuit to 95V, thereby providing sufficient energy to the ultrasonic probe 3.

[0060] Please see Figure 9The ultrasonic signal receiving module includes a capacitor C35. The front end of capacitor C35 is connected to the RX terminal of ultrasonic probe 3. The RX terminal of ultrasonic probe 3 is connected to ground via resistor R27. The rear end of capacitor C35 is connected to the negative input terminal of operational amplifier U7A via resistor R36. The output terminal of operational amplifier U7A is connected to the positive input terminal of operational amplifier U7B via capacitor C43. The common terminal between resistor R36 and the negative input terminal of operational amplifier U7A is connected to the front end of capacitor C43 via resistor R37. The positive power supply pin of operational amplifier U7A is connected to the output terminal of the first-stage buck circuit. This positive power supply pin is also connected in series with capacitor C. 41 is grounded, the negative power supply pin of operational amplifier U7A is grounded, the rear end of capacitor C35 is connected in series with resistor R22 and then connected to the positive input terminal of operational amplifier U7A. This rear end is connected to the common terminal between the cathode of the first diode and the anode of the second diode of switching diode D9. The cathode of the second diode of switching diode D9 is connected to the output terminal of the first stage buck circuit, i.e., 5V DC voltage. The anode of the first diode of switching diode D9 is grounded. The rear end of resistor R22 is connected in series with resistor R28 and then grounded. This rear end is also connected in series with capacitor C37 and then grounded. This rear end is also connected in series with resistors R23, R31 and R34 in sequence and then grounded.

[0061] Resistor R31 is connected to ground via capacitor C42 in series at its rear end. Resistor R35 is then connected to the common terminal between capacitor C43 and the positive input terminal of operational amplifier U7B. Resistor R32 is then connected to the negative input terminal of operational amplifier U7B. Resistor R33 is then connected to the output terminal of operational amplifier U7B via series at its rear end. The common terminal between the output terminal of operational amplifier U7B and resistor R33 is connected to the positive input terminal of operational amplifier U7C via capacitor C40 in series.

[0062] The rear end of resistor R23 is connected in series with resistor R20 and then to the output of the first-stage buck circuit. This rear end is also connected in series with capacitor C38 and then grounded. Resistors R24 and R29 are then connected in series with this rear end and grounded. Resistors R24 and R29 are then connected in series with capacitor C39 and then grounded. Resistors R24 and R25 are then connected in series with this rear end and then to the positive input of operational amplifier U7C. Resistors R19 are then connected in series with this rear end and then to the negative input of operational amplifier U7C. Resistors R17, R6, and C13 are then connected in series with this rear end and grounded. The output of operational amplifier U7C is connected to the front end of resistor R6, and the rear end of resistor R6 is connected to the SMA connector J1 of the high-speed AD module.

[0063] This ultrasonic signal receiving module first amplifies the reflected ultrasonic signal by 14 times through transimpedance amplification, and then amplifies the transimpedance amplified signal by 20 times through in-phase amplification. This is used both to increase the signal frequency and for signal processing.

[0064] In this embodiment, both the high-speed AD module and the FPGA data acquisition and processing module are conventional electronic devices and are common techniques used by those skilled in the art, so they will not be described in detail here.

[0065] In this embodiment, the data receiving and processing algorithm proceeds according to the following steps:

[0066] Ignoring the change in medium density caused by stress state variations, we establish the longitudinal wave propagation velocity v of ultrasound under stress-free conditions. L0 And the propagation velocity of ultrasonic transverse waves under no stress v S0 The steps of the relational expression.

[0067] Specifically, bolts are typically made of metal, which is an isotropic solid medium. For an isotropic solid medium, the vector field can be expressed as the sum of the scalar gradient and the vector curl, therefore:

[0068] v=gradφ+rotψ (1)

[0069] divψ=0 (2)

[0070] In equations (1) and (2), v represents the velocity vector, φ represents the scalar potential, and ψ represents the vector potential. Separating the scalar potential and vector potential, we obtain:

[0071]

[0072]

[0073] In equations (3) and (4), ρ represents the density of the bolt, and λ and μ are the second-order elastic coefficients of the bolt. Generally speaking, scalar potential and vector potential describe longitudinal and transverse waves, respectively. Therefore, under stress-free conditions, the propagation speeds of ultrasonic longitudinal and transverse waves in a metallic medium can be expressed as:

[0074]

[0075] In equations (5) and (6), v L0 and v S0 They represent the propagation speeds of ultrasonic longitudinal waves under stress-free conditions, v and v', respectively. L0 The propagation speed v of ultrasonic transverse waves under stress-free conditions S0 Depending on the direction of ultrasonic wave propagation, the acoustic elasticity equations for different propagation directions can be expressed as follows:

[0076]

[0077] In equations (7)-(10), σ represents the bolt tightening stress, ρ0 represents the bolt density under no stress, l, m, and n represent the third-order elastic coefficients of the bolt, and vLII The longitudinal wave velocity of ultrasound parallel to the direction of stress, v L⊥ v represents the longitudinal wave propagation velocity of ultrasound perpendicular to the direction of stress. SII v represents the propagation velocity of ultrasonic longitudinal and transverse waves parallel to the direction of stress. S⊥ This represents the propagation velocity of the ultrasonic transverse wave perpendicular to the direction of stress. Since ultrasonic transverse waves are shear waves, their polarization direction is perpendicular to the stress direction, but their propagation direction is not uniform. Because ultrasonic longitudinal waves parallel to the direction of stress are most sensitive to stress changes, and ultrasonic longitudinal wave transducers are more commonly used and less expensive, most time-of-flight methods use ultrasonic longitudinal waves to detect the tightening stress of bolts. Therefore, combining equations (5) and (7), ignoring the change in medium density caused by stress state changes, i.e., ρ0 = ρ, we can obtain:

[0078]

[0079] make:

[0080]

[0081] In equations (11) and (12), K a Let be the acoustoelastic coefficient of the material. From equation (12), it can be seen that the acoustoelastic coefficient is only related to the second and third elastic coefficients of the material and is not affected by other factors. Therefore, substituting equation (12) into equation (11) yields:

[0082] v Lσ =v L0 (1+K a σ) (13)

[0083] Equation (13) is the longitudinal wave propagation velocity v of ultrasound under stress-free conditions. L0 And the propagation velocity of ultrasonic transverse waves under no stress v S0 The relational expression.

[0084] Establish the ultrasonic transit time Δt under stress conditions σ The steps for determining the relationship between the ultrasonic transit time Δt0 under stress-free conditions.

[0085] Specifically, establish the relationship between bolt elongation under tightening stress:

[0086]

[0087] In equation (14), L0 is the total length of the bolt when it is not under stress, and L σ E is the total length of the bolt under stress, and E is the elastic modulus of the bolt.

[0088] Combining equations (13) and (14), the transit time Δt of the ultrasonic wave under stress is calculated. σ The transit time Δt0 of ultrasound under stress-free conditions is expressed as:

[0089]

[0090] For metallic materials, the acoustoelastic coefficient K a The order of magnitude is extremely small, typically K within the safe stress range of the bolt. a σ << 1, therefore, equation (15) is approximately simplified to:

[0091]

[0092] Equation (17) is the formula for establishing the ultrasonic transit time Δt under stress. σ The relationship between the ultrasonic transit time Δt0 under stress-free conditions.

[0093] Establish the ultrasonic transit time Δt under stress conditions σ The steps for calculating the relationship between the ultrasonic transit time Δt0 and the stress coefficient K under stress-free conditions and the bolt fastening stress σ are as follows.

[0094] Specifically, by extracting the bolt tightening stress σ from equation (17), we obtain:

[0095]

[0096] Therefore, the formula for calculating the bolt tightening stress σ is:

[0097]

[0098] In equation (19), K represents the stress coefficient, which is obtained through calibration experiments and is related to the material properties of the bolt and the geometric dimensions of the bolt.

[0099] Equation (19) is based on the ultrasonic transit time Δt under stress. σ The relationship between the ultrasonic transit time Δt0 and the stress coefficient K under stress-free conditions for calculating the bolt fastening stress σ.

[0100] Finally, it should be noted that the above description is merely a preferred embodiment of the present utility model. Those skilled in the art, under the guidance of the present utility model, can make various similar representations without departing from the spirit and claims of the present utility model, and such modifications all fall within the protection scope of the present utility model.

Claims

1. An ultrasonic transceiver circuit for an intelligent measuring sleeve for bolt fastening stress, characterized in that, The system includes an MCU, a power supply module, an ultrasonic signal transmitting module, an ultrasonic signal receiving module, and an ultrasonic signal processing module. The ultrasonic signal processing module includes a high-speed AD module and an FPGA data acquisition and processing module. The power supply module supplies power to the MCU. The ultrasonic signal transmitting module transmits high-voltage ultrasonic signals to the ultrasonic probe according to control commands from the MCU. The ultrasonic signal receiving module processes the ultrasonic waves acquired by the ultrasonic probe, amplifies them to generate a reflection time analog signal, and then sends the obtained reflection time analog signal to the high-speed AD module. The high-speed AD module converts the received reflection time analog signal into a reflection time digital signal and sends the reflection time digital signal to the FPGA data acquisition and processing module. The FPGA data acquisition and processing module converts the received reflection time digital signal into the current bolt tightening stress value and sends the current bolt tightening stress value outward through a communication interface.

2. The ultrasonic transceiver circuit for an intelligent bolt fastening stress measuring sleeve according to claim 1, characterized in that, The power module includes a voltage conversion circuit, an isolation power supply circuit, and a communication digital isolation circuit; The voltage conversion circuit includes a first-stage buck circuit and a second-stage buck circuit connected in sequence. The input terminal of the first-stage buck circuit receives the input power, and the output terminal of the second-stage buck circuit outputs the operating voltage to the MCU. The isolation power supply circuit includes a first step-down isolation module and a second step-down isolation module connected in sequence. The input terminal of the first step-down isolation module receives the input power, and the second step-down isolation module outputs an isolation voltage to the communication digital isolation circuit. The communication digital isolation circuit is equipped with dual-channel digital isolators U8 and U9, and the FPGA data acquisition and processing module is equipped with terminal blocks JP2 and JP3. The first voltage input terminal VDDA of the dual-channel digital isolator U8 is connected to the output terminal of the second-stage step-down circuit. The signal channel output terminal VO1 and the signal channel input terminal VI2 of the dual-channel digital isolator U8 are respectively connected to the MCU-TX terminal and the MCU-RX terminal of the MCU. The second voltage input terminal VDDB of the dual-channel digital isolator U8 is connected to the output terminal of the second step-down isolation module via pin 1 of the terminal JP2. The signal channel input terminal VI1 of the dual-channel digital isolator U8 is connected to the FPGA-TX terminal of the FPGA data acquisition and processing module. The signal channel output terminal VO2 of the dual-channel digital isolator U8 is connected to the FPGA-RX terminal of the FPGA data acquisition and processing module. The first voltage input terminal VDDA of the dual-channel digital isolator U9 is connected to the output terminal of the second-stage step-down circuit. The signal channel output terminal VO1 of the dual-channel digital isolator U9 is connected to the Enable terminal of the MCU after series resistor R2. The signal channel output terminal VO1 is also connected to the Input terminal of the MCU after series resistor R3. The second voltage input terminal VDDB of the dual-channel digital isolator U9 is connected to the output terminal of the second step-down isolation module through pin 1 of terminal JP3. The signal channel input terminal VI1 of the dual-channel digital isolator U9 is connected to the FPGA-IO terminal of the FPGA data acquisition and processing module.

3. The ultrasonic transceiver circuit for an intelligent bolt fastening stress measuring sleeve according to claim 2, characterized in that, The first-stage step-down circuit is equipped with a first three-terminal regulator U0. The input terminal of the first three-terminal regulator U0 is connected to a 12V input power supply. The input terminal is also connected in series with a capacitor C2 and then grounded. The output terminal of the first three-terminal regulator U0 is connected in series with a ferrite bead FB1 and then outputs a 5V voltage. The rear end of the ferrite bead FB1 is connected in series with a capacitor C3 and then grounded. The rear end is also connected in series with a capacitor C4 and then grounded. The rear end is also connected in series with a capacitor C5 and then grounded. The ground terminal of the first three-terminal regulator U0 is grounded. The second-stage step-down circuit includes a second three-terminal regulator U1. The input terminal of the second three-terminal regulator U1 is connected to the rear end of the ferrite bead FB4 in series. The input terminal is also connected to ground in series with capacitor C8. The output terminal of the second three-terminal regulator U1 outputs a 3.3V operating voltage to the MCU. The output terminal is also connected to the first voltage input terminal VDDA of the dual-channel digital isolator U8 and the first voltage input terminal VDDA of the dual-channel digital isolator U9. The output terminal is also connected to ground in series with capacitor C6 and capacitor C7. The ground terminal of the second three-terminal regulator U1 is grounded.

4. The ultrasonic transceiver circuit for an intelligent bolt fastening stress measuring sleeve according to claim 2, characterized in that, The first step-down isolation module is equipped with a converter U3. The grounding terminal GND and the grounding terminal 0V of the converter U3 are independently grounded. The voltage input terminal VIN of the converter U3 is connected to a 12V input power supply. The input terminal is also connected in series with a capacitor C9 and then grounded together with the grounding terminal GND of the converter U3. The voltage output terminal VO of the converter U3 outputs a 5V isolation voltage. The voltage output terminal VO is also connected in series with a capacitor C10 and then grounded together with the grounding terminal 0V of the converter U3. The second step-down isolation module is equipped with a voltage regulator chip U5. The voltage input terminal VIN of the voltage regulator chip U5 is connected to the voltage output terminal VO of the converter U3. The voltage output terminal VOUT of the voltage regulator chip U5 outputs a 3.3V isolation voltage and is connected to the second voltage input terminal VDDB of the dual-channel digital isolator U8 and the second voltage input terminal VDDB of the dual-channel digital isolator U9. The voltage output terminal VOUT is also connected in series with a capacitor C11 and grounded together with the ground terminal 0V of the converter U3. The ground terminal GND of the voltage regulator chip U5 is grounded together with the ground terminal 0V of the converter U3.

5. The ultrasonic transceiver circuit for an intelligent bolt fastening stress measuring sleeve according to claim 3, characterized in that, The ultrasonic signal transmitting module includes a boost control chip U6. The ground terminal GND of the boost control chip U6 is grounded. The common terminal of the enable pin CE and the power supply terminal VDD of the boost control chip U6 is connected in series with a ferrite bead FB2 and then connected to the output terminal of the first-stage buck circuit. The common terminal is also connected in series with a capacitor C28 and then grounded. The common terminal between the ferrite bead FB2 and the output terminal of the first-stage buck circuit is connected in series with a capacitor C30 and then grounded. The feedback pin FB of the boost control chip U6 is connected to the sampling terminal U2-29 of the MCU after being connected in series with resistor R11. Sampling terminal U2-29 is also connected in series with Zener diode Z1 and then grounded. Sampling terminal U2-29 is also connected in series with capacitor C25 and then grounded. The feedback pin FB of the boost control chip U6 is connected in series with lower voltage divider resistor R15 and then grounded. The feedback pin FB is connected to a high level via upper voltage divider resistor R13. This high level is connected in series with capacitor C27 and then grounded. This high level is also connected to the cathode of fast recovery diode D8. The anode of the MOSFET is connected to the drain of the MOSFET Q2. The gate of the MOSFET Q2 is connected to the external control terminal EXT of the boost control chip U6. The source of the MOSFET Q2 is grounded. The anode of the fast recovery diode D8 is connected to the output terminal of the first-stage buck circuit after being connected in series with inductor L1 and ferrite bead FB3. The common terminal of inductor L1 and ferrite bead FB3 is connected in series with capacitor C33 and then grounded. The common terminal is also connected in series with inductor C34 and then grounded. The common terminal between ferrite bead FB3 and the output terminal of the first-stage buck circuit is connected in series with capacitor C32 and then grounded. The high-level signal is connected to the RX terminal of the ultrasonic probe via a series resistor R12 and capacitor C26. A resistor R14 is connected in series between the RX terminal of the ultrasonic probe and the ground terminal. The common terminal of the resistor R12 and capacitor C26 is connected to the drain of the MOSFET Q3. The source of the MOSFET Q3 is grounded. The gate of the MOSFET Q3 is connected to the Enable terminal of the MCU. The gate is also connected in series with resistor R26 and then grounded.

6. The ultrasonic transceiver circuit for an intelligent bolt fastening stress measuring sleeve according to claim 3, characterized in that, The ultrasonic signal receiving module includes a capacitor C35. The front end of capacitor C35 is connected to the RX terminal of the ultrasonic probe. The RX terminal of the ultrasonic probe is grounded after being connected in series with resistor R27. The rear end of capacitor C35 is connected to the negative input terminal of operational amplifier U7A after being connected in series with resistor R36. The output terminal of operational amplifier U7A is connected to the positive input terminal of operational amplifier U7B after being connected in series with capacitor C43. The common terminal between resistor R36 and the negative input terminal of operational amplifier U7A is connected to the front end of capacitor C43 after resistor R37. The positive power supply pin of operational amplifier U7A is connected to the output terminal of the first-stage buck circuit. This positive power supply pin also... After capacitor C41 is connected in series, the negative power supply pin of the operational amplifier U7A is grounded. After capacitor C35 is connected in series with resistor R22, it is connected to the positive input terminal of operational amplifier U7A. This end is connected to the common terminal between the cathode of the first diode and the anode of the second diode of switching diode D9. The cathode of the second diode of switching diode D9 is connected to the output terminal of the first stage buck circuit. The anode of the first diode of switching diode D9 is grounded. After resistor R22 is connected in series with resistor R28, it is grounded. After this end, capacitor C37 is also connected in series and then grounded. After this end, resistors R23, R31 and R34 are connected in series in sequence and then grounded. The resistor R31 is connected to ground after a capacitor C42 in series at its rear end. After a resistor R35 in series at its rear end, it is connected to the common terminal between capacitor C43 and the positive input terminal of operational amplifier U7B. After a resistor R32 in series at its rear end, it is connected to the negative input terminal of operational amplifier U7B. After a resistor R33 in series at its rear end, it is connected to the output terminal of operational amplifier U7B. After a capacitor C40 in series at the common terminal between the output terminal of operational amplifier U7B and resistor R33, it is connected to the positive input terminal of operational amplifier U7C. The rear end of resistor R23 is connected in series with resistor R20 and then to the output terminal of the first-stage buck circuit. A capacitor C38 is also connected in series with this rear end and then grounded. Resistors R24 and R29 are then connected in series with this rear end and then grounded. A capacitor C39 is connected in series with the rear end of resistor R24 ​​and then grounded. A resistor R25 is also connected in series with this rear end and then to the positive input terminal of operational amplifier U7C. A resistor R19 is also connected in series with this rear end and then to the negative input terminal of operational amplifier U7C. Resistors R17, R6, and C13 are then connected in series with the rear end of resistor R19 and then grounded. The output terminal of operational amplifier U7C is connected to the front end of resistor R6, and the rear end of resistor R6 is connected to the SMA connector J1 of the high-speed AD module.

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