A dual Type-C interface circuit, tablet computer

Abstract

This utility model discloses a dual Type-C interface circuit and a tablet computer. The dual Type-C interface circuit includes: a Type-C1 interface, a Type-C2 interface, a PMU chip, a CPU chip, a charging chip, a battery, a PD protocol chip, and a control circuit. The PMU chip is connected to the DP1 / DM1 and CC1 pins of the Type-C1 interface and the CPU chip. The CPU chip is connected to the CPU_INT1 pin of the Type-C1 interface, the CPU_INT2 pin of the Type-C2 interface, the charging chip, and the PD protocol chip. The charging chip is connected to the battery and the DP2 / DM2 pin of the Type-C2 interface. The CC2 pin of the Type-C2 interface is connected to the PD protocol chip. The control circuit is connected to the VBUS1 pin of the Type-C1 interface, the VBUS2 pin of the Type-C2 interface, the CPU chip, the battery, and the charging chip. This utility model designs a USB fast charging circuit and a logic judgment circuit to realize the dual Type-C interface function and meet usage requirements.

Description

Technical Field

[0001] This utility model relates to the field of interface circuit technology for electronic devices, and in particular to a dual Type-C interface circuit and a tablet computer. Background Technology

[0002] Tablets typically only have one Type-C port. If you need to plug in a peripheral device (such as a USB flash drive, keyboard, or mouse) while the tablet is charging, you need to add a docking station to the tablet's Type-C port, which is quite inconvenient. Summary of the Invention

[0003] According to an embodiment of the present invention, a dual Type-C interface circuit is provided, comprising: a Type-C1 interface, a Type-C2 interface, a PMU chip, a CPU chip, a charging chip, a battery, a PD protocol chip, and a control circuit.

[0004] The PMU chip is connected to the DP1 / DM1 pin and CC1 pin of the Type-C1 interface and the CPU chip;

[0005] The CPU chip is connected to the CPU_INT1 pin of the Type-C1 interface, the CPU_INT2 pin of the Type-C2 interface, the charging chip, and the PD protocol chip.

[0006] The charging chip is connected to the battery and the DP2 / DM2 pins of the Type-C2 interface;

[0007] The CC2 pin of the Type-C2 interface is connected to the PD protocol chip;

[0008] The control circuit is connected to the VBUS1 pin of the Type-C1 interface, the VBUS2 pin of the Type-C2 interface, the CPU chip, the battery, and the charging chip.

[0009] Furthermore, the control circuit includes: a power switching circuit and an OTG circuit;

[0010] The power switching circuit is connected to the VBUS1 pin of the Type-C1 interface, the VBUS2 pin of the Type-C2 interface, and the charging chip.

[0011] The OTG circuit is connected to the VBUS1 pin of the Type-C1 interface, the power switching circuit, the CPU chip, and the battery.

[0012] Furthermore, the power switching circuit includes: a first MOSFET, a first resistor, a second resistor, a second MOSFET, a first capacitor, a third MOSFET, a third resistor, a fourth resistor, a fourth MOSFET, a second capacitor, a fifth resistor, a sixth resistor, a fifth MOSFET, a seventh resistor, an eighth resistor, and a ninth resistor.

[0013] Pin 6 of the first MOSFET, VBUS1 pin of the Type-C1 interface, one end of the eighth resistor are connected, pins 1 and 3 of the first MOSFET, one end of the first resistor and one end of the first capacitor are connected, pins 2 and 4 of the first MOSFET, the other end of the first resistor, the other end of the first capacitor and one end of the second resistor are connected, pin 5 of the first MOSFET, pin 5 of the third MOSFET and one end of the seventh resistor are connected to the charging chip.

[0014] The drain of the second MOSFET is connected to the other end of the second resistor, the gate of the drain of the second MOSFET, the other end of the eighth resistor, the OTG circuit, and the drain of the fifth MOSFET. The source of the second MOSFET is grounded.

[0015] The third MOSFET's pin 6, one end of the ninth resistor, and the VBUS2 pin of the Type-C2 interface are connected. The third MOSFET's pins 1 and 3, one end of the third resistor, and one end of the second capacitor are connected. The third MOSFET's pins 2 and 4, the other end of the third resistor, the other end of the second capacitor, and one end of the fourth resistor are connected.

[0016] The drain of the fourth MOSFET is connected to the other end of the fourth resistor, the gate of the fourth MOSFET is connected to the other end of the ninth resistor, and the source of the fourth MOSFET is grounded.

[0017] The gate of the fifth MOSFET is connected to one end of the fifth resistor and one end of the sixth resistor, and the source of the fifth MOSFET is grounded.

[0018] The other end of the fifth resistor is connected to the VBUS2 pin of the Type-C2 interface, and the other end of the sixth resistor is grounded.

[0019] Furthermore, the power switching circuit also includes: a tenth resistor and a third capacitor; one end of the tenth resistor and one end of the third capacitor are connected to one end of the eighth resistor, and the other end of the tenth resistor and the other end of the third capacitor are grounded.

[0020] Furthermore, the power switching circuit also includes: an eleventh resistor and a fourth capacitor; one end of the eleventh resistor and one end of the fourth capacitor are connected to one end of the ninth resistor, and the other end of the eleventh resistor and the other end of the fourth capacitor are grounded.

[0021] Furthermore, the OTG circuit includes: a conversion chip, an inductor, a fifth capacitor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a sixth MOSFET, a fifteenth resistor, a sixteenth resistor, a sixth capacitor, a seventh capacitor, and a diode;

[0022] Pin 5 of the conversion chip is connected to one end of the inductor; pin 6 of the conversion chip is connected to the other end of the inductor and the battery; pin 4 of the conversion chip is connected to one end of the twelfth resistor, one end of the thirteenth resistor, and the CPU chip; pin 2 of the conversion chip is connected to one end of the fifteenth resistor, one end of the sixth capacitor, one end of the seventh capacitor, and one end of the diode; pin 3 of the conversion chip is connected to the other end of the fifteenth resistor, one end of the sixteenth resistor, and the other end of the sixth capacitor.

[0023] The drain of the sixth MOSFET is connected to the power switching circuit, the gate of the sixth MOSFET is connected to the other end of the thirteenth resistor and one end of the fourteenth resistor, and the sixth MOSFET is grounded.

[0024] The other end of the fifth capacitor, the other end of the twelfth resistor, the other end of the fourteenth resistor, the other end of the sixteenth resistor, and the other end of the seventh capacitor are grounded;

[0025] The other end of the diode is connected to the VBUS1 pin of the Type-C1 interface.

[0026] Furthermore, it also includes: the seventh MOSFET, the seventeenth resistor, the eighteenth resistor, the eighth MOSFET, the nineteenth resistor, and the twentieth resistor;

[0027] The drain of the seventh MOSFET is connected to the CPU_INT1 pin of the Type-C1 interface, the gate of the seventh MOSFET is connected to one end of the seventeenth resistor and one end of the eighteenth resistor, and the source of the seventh MOSFET is grounded.

[0028] The other end of the seventeenth resistor is connected to the VBUS1 pin of the Type-C1 interface, and the other end of the eighteenth resistor is grounded.

[0029] The drain of the eighth MOSFET is connected to the CPU_INT2 pin of the Type-C2 interface, the gate of the eighth MOSFET is connected to one end of the nineteenth resistor and one end of the twentieth resistor, and the source of the eighth MOSFET is grounded.

[0030] The other end of the nineteenth resistor is connected to the VBUS2 pin of the Type-C2 interface, and the other end of the twentieth resistor is grounded.

[0031] According to another embodiment of the present invention, a tablet computer is provided, which includes the dual Type-C interface circuit of the previous embodiment.

[0032] According to an embodiment of the present invention, a dual Type-C interface circuit is designed, including a USB fast charging circuit and a logic judgment circuit, to realize the dual Type-C interface function and meet the usage requirements.

[0033] It should be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further illustration of the claimed technology. Attached Figure Description

[0034] Figure 1 This is a hardware block diagram of a dual Type-C interface circuit according to an embodiment of the present invention.

[0035] Figure 2 This is a circuit diagram of a power switching circuit for a dual Type-C interface circuit according to an embodiment of the present invention.

[0036] Figure 3 This is a circuit diagram of an OTG circuit with dual Type-C interface circuit according to an embodiment of the present invention.

[0037] Figure 4 This is a circuit diagram of a CPU interrupt circuit with a dual Type-C interface circuit according to an embodiment of the present invention. Detailed Implementation

[0038] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, further illustrating the present invention.

[0039] First, combine Figures 1-4 This invention describes a dual Type-C interface circuit according to an embodiment of the present invention, which provides dual Type-C interfaces to meet usage requirements and has a wide range of applications.

[0040] like Figures 1-4 As shown, an embodiment of the present invention provides a dual Type-C interface circuit, which includes a Type-C1 interface, a Type-C2 interface, a PMU chip, a CPU chip, a charging chip, a battery, a PD protocol chip, and a control circuit.

[0041] Specifically, such as Figure 1As shown, the PMU chip is connected to the DP1 / DM1 and CC1 pins of the Type-C1 interface and the CPU chip; the CPU chip is connected to the CPU_INT1 pin of the Type-C1 interface, the CPU_INT2 pin of the Type-C2 interface, the charging chip, and the PD protocol chip; the charging chip is connected to the battery and the DP2 / DM2 pin of the Type-C2 interface; the CC2 pin of the Type-C2 interface is connected to the PD protocol chip; and the control circuit is connected to the VBUS1 pin of the Type-C1 interface, the VBUS2 pin of the Type-C2 interface, the CPU chip, the battery, and the charging chip.

[0042] In this embodiment, the DP1 / DM1 and CC1 signals of the USB port of the Type-C1 interface are connected to the Unisoc PMU chip UMP9620. When a charger is plugged into the Type-C1 interface but no charger is plugged into the Type-C2 interface, the PMU chip UMP9620 notifies the IIC_1 communication interface of the CPU chip UMS9621S to control the two charging chips ETA6963 to charge the battery in parallel at a power of 22.5W.

[0043] In this embodiment, the Type-C2 interface implements the basic charging function of the BC1.2 protocol through the DP2 / DM2 of the charging chip ETA6963, while the 22.5W PD fast charging is implemented through the PD protocol chip AW35615. When the Type-C2 interface sends an interrupt CPU_INT2 signal to the CPU chip, the CPU chip UMS9621S controls the PD protocol chip AW35615 through IIC_2 to output the VBUS2 voltage of the charger at 22.5W power, which is then supplied to the two charging chips ETA6963 in parallel to charge the battery.

[0044] In this embodiment, CPU_INT1 of the Type-C1 interface and CPU_INT2 of the Type-C2 interface are connected to the CPU chip UMS9621S.

[0045] When there is a CPU_INT1 interrupt signal but no CPU_INT2 interrupt signal, the CPU chip UMS9621S starts the charging process of the Type-C1 interface.

[0046] When there is no CPU_INT1 interrupt signal but there is a CPU_INT2 interrupt signal, the CPU chip UMS9621S starts the charging process of the Type-C2 interface.

[0047] When there is a CPU_INT1 interrupt signal and a CPU_INT2 interrupt signal, the UMS9621S CPU chip will still start the charging process of the Type-C2 interface.

[0048] Furthermore, such as Figure 1 , 2 As shown, the control circuit includes a power switching circuit and an OTG circuit; the power switching circuit is connected to the VBUS1 pin of the Type-C1 interface, the VBUS2 pin of the Type-C2 interface, and the charging chip; the OTG circuit is connected to the VBUS1 pin of the Type-C1 interface, the power switching circuit, the CPU chip, and the battery.

[0049] Furthermore, such as Figure 1 , 2As shown, the power switching circuit includes: a first MOSFET Q101, a first resistor R107, a second resistor R108, a second MOSFET Q105, a first capacitor C106, a third MOSFET Q102, a third resistor R114, a fourth resistor R115, a fourth MOSFET Q106, a second capacitor C107, a fifth resistor R118, a sixth resistor R119, a fifth MOSFET Q107, a seventh resistor R100, an eighth resistor R105, and a ninth resistor R112; pin 6 of the first MOSFET Q101 and the VBUS1 pin of the Type-C1 interface. One end of the eighth resistor R105 is connected to pins 1 and 3 of the first MOSFET Q101, one end of the first resistor R107, and one end of the first capacitor C106. Pins 2 and 4 of the first MOSFET Q101, the other end of the first resistor R107, the other end of the first capacitor C106, and one end of the second resistor R108 are connected to pin 5 of the first MOSFET Q101, pin 5 of the third MOSFET Q102, and one end of the seventh resistor R100. The drain of the second MOSFET Q105 is connected to the other end of the second resistor R108. The drain and gate of the second MOSFET Q105, the other end of the eighth resistor R105, the OTG circuit, and the drain of the fifth MOSFET Q107 are connected. The source of the second MOSFET Q105 is grounded. Pin 6 of the third MOSFET Q102, one end of the ninth resistor R112, and the VBUS2 pin of the Type-C2 interface are connected. Pins 1 and 3 of the third MOSFET Q102, one end of the third resistor R114, and one end of the second capacitor C107 are connected. Pins 2 and 4 of the third MOSFET Q102, the other end of the third resistor R114, and the second capacitor C107 are connected. The other end of resistor Q7 is connected to one end of the fourth resistor R115; the drain of the fourth MOSFET Q106 is connected to the other end of the fourth resistor R115, the gate of the fourth MOSFET Q106 is connected to the other end of the ninth resistor R112, and the source of the fourth MOSFET Q106 is grounded; the gate of the fifth MOSFET Q107 is connected to one end of the fifth resistor R118 and one end of the sixth resistor R119, and the source of the fifth MOSFET Q107 is grounded; the other end of the fifth resistor R118 is connected to the VBUS2 pin of the Type-C2 interface, and the other end of the sixth resistor R119 is grounded.

[0050] Furthermore, such as Figure 1 , 2 As shown, the power switching circuit also includes: a tenth resistor R106 and a third capacitor C104; one end of the tenth resistor R106 and one end of the third capacitor C104 are connected to one end of the eighth resistor R105, and the other end of the tenth resistor R106 and the other end of the third capacitor C104 are grounded.

[0051] Furthermore, such as Figure 1 ,2 As shown, the power switching circuit also includes: an eleventh resistor R113 and a fourth capacitor C105; one end of the eleventh resistor R113 and one end of the fourth capacitor C105 are connected to one end of the ninth resistor R112, and the other end of the eleventh resistor R113 and the other end of the fourth capacitor C105 are grounded.

[0052] Furthermore, such as Figures 1-3 As shown, the OTG circuit includes: a conversion chip U101, an inductor L105, a fifth capacitor C108, a twelfth resistor R120, a thirteenth resistor R116, a fourteenth resistor R117, a sixth MOSFET Q108, a fifteenth resistor R121, a sixteenth resistor R122, a sixth capacitor C110, a seventh capacitor C109, and a diode D105. Pin 5 of the conversion chip U101 is connected to one end of the inductor L105, pin 6 of the conversion chip U101 is connected to the other end of the inductor L105 and the battery, pin 4 of the conversion chip U101 is connected to one end of the twelfth resistor R120, one end of the thirteenth resistor R116, and the CPU chip, and pin 2 of the conversion chip U101 is connected to one end of the fifteenth resistor R121 and one end of the sixth capacitor C110. One end of the seventh capacitor C109 and one end of the diode D105 are connected. Pin 3 of the conversion chip U101 is connected to the other end of the fifteenth resistor R121, one end of the sixteenth resistor R122, and the other end of the sixth capacitor C110. The drain of the sixth MOSFET Q108 is connected to the power switching circuit. The gate of the sixth MOSFET Q108 is connected to the other end of the thirteenth resistor R116 and one end of the fourteenth resistor R117. The sixth MOSFET Q108 is grounded. The other end of the fifth capacitor C108, the other end of the twelfth resistor R120, the other end of the fourteenth resistor R117, the other end of the sixteenth resistor R122, and the other end of the seventh capacitor C109 are grounded. The other end of the diode D105 is connected to the VBUS1 pin of the Type-C1 interface.

[0053] Furthermore, such as Figure 1 , 4As shown, a dual Type-C interface circuit according to an embodiment of this utility model further includes: a seventh MOSFET Q103, a seventeenth resistor R103, an eighteenth resistor R104, an eighth MOSFET Q104, a nineteenth resistor R110, and a twentieth resistor R111; the drain of the seventh MOSFET Q103 is connected to the CPU_INT1 pin of the Type-C1 interface, the gate of the seventh MOSFET Q103 is connected to one end of the seventeenth resistor R103 and one end of the eighteenth resistor R104, and the source of the seventh MOSFET Q103 is grounded; the seventeenth resistor R104 is connected to the CPU_INT1 pin of the Type-C1 interface, the gate of the seventh MOSFET Q103 is connected to one end of the seventeenth resistor R103 and one end of the eighteenth resistor R104, and the source of the seventh MOSFET Q103 is grounded; the seventeenth resistor R104 is connected to the CPU_INT1 pin of the Type-C1 interface, the gate of the seventh MOSFET Q104 is connected to one end of the seventeenth resistor R103 and one end of the eighteenth resistor R104, and the source of the seventh MOSFET Q103 is grounded; the seventeenth resistor R104 is connected to the CPU_INT1 pin of the Type-C1 interface, the gate of the seventeenth MOSFET Q104 is connected to one end of the seventeenth resistor R103 and one end of the eighteenth resistor R104, and the source of the seventeenth MOSFET Q104 ... The other end of resistor R103 is connected to the VBUS1 pin of the Type-C1 interface, and the other end of the eighteenth resistor R104 is grounded; the drain of the eighth MOSFET Q104 is connected to the CPU_INT2 pin of the Type-C2 interface, the gate of the eighth MOSFET Q104 is connected to one end of the nineteenth resistor R110 and one end of the twentieth resistor R111, and the source of the eighth MOSFET Q104 is grounded; the other end of the nineteenth resistor R110 is connected to the VBUS2 pin of the Type-C2 interface, and the other end of the twentieth resistor R111 is grounded.

[0054] In this embodiment, as Figure 1 , 2 As shown, electronic switch 1, composed of first MOSFET Q101, second MOSFET Q105, first resistor R107, second resistor R108, and first capacitor C106, and electronic switch 2, composed of third MOSFET Q102, fourth MOSFET Q106, third resistor R114, fourth resistor R115, and second capacitor C107, are used to switch the input of charging voltages VBUS1 of the tablet's Type-C1 interface and VBUS2 of the Type-C2 interface.

[0055] When a charger is plugged into Type-C1 but not into Type-C2, VBUS1 turns on electronic switch 1, and VBUS1 of Type-C1 outputs to VBUS to charge the tablet.

[0056] When no charger is plugged into Type-C1 but a charger is plugged into Type-C2, VBUS2 turns on electronic switch 2, and VBUS2 of Type-C2 outputs to VBUS to charge the tablet.

[0057] When a charger is plugged into both Type-C1 and Type-C2, VBUS2 turns on electronic switch 2. At the same time, VBUS2 turns off electronic switch 1 through the fifth MOSFET Q107, thereby isolating the power input of VBUS1 to VBUS. VBUS2 of Type-C2 outputs to VBUS to charge the tablet.

[0058] In this embodiment, as Figure 4As shown, VBUS1 of Type-C1 outputs interrupt CPU_INT1 through the seventh MOS transistor Q103 to report the status to the CPU chip, and VBUS2 of Type-C2 outputs interrupt CPU_INT2 through the eighth MOS transistor Q104 to report the status to the CPU chip.

[0059] In this embodiment, as Figure 3 As shown, the power supply for the Type-C1 interface OTG is provided by the output of the conversion chip U101. The OTG output provides 5V power to VBUS1. At the same time, the GPIO_OTG_EN signal also turns off the electronic switch 1 through the sixth MOSFET Q108 to prevent VBUS from affecting the output of the OTG voltage.

[0060] As described above, in a dual Type-C interface circuit according to an embodiment of the present invention, a USB fast charging circuit and a logic judgment circuit are designed to realize the dual Type-C interface function and meet the usage requirements.

[0061] The above combined with the appendix Figures 1-4 A dual Type-C interface circuit according to an embodiment of the present invention is described. Furthermore, the present invention can also be applied to a tablet computer.

[0062] According to another embodiment of the present invention, a tablet computer is provided, which includes the dual Type-C interface circuit of the previous embodiment to meet the usage requirements.

[0063] It should be noted that, in this specification, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0064] Although the present invention has been described in detail through the above preferred embodiments, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above content. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A dual Type-C interface circuit, characterized in that, Includes: Type-C1 interface, Type-C2 interface, PMU chip, CPU chip, charging chip, battery, PD protocol chip, and control circuit; The PMU chip is connected to the DP1 / DM1 pin and CC1 pin of the Type-C1 interface and the CPU chip; The CPU chip is connected to the CPU_INT1 pin of the Type-C1 interface, the CPU_INT2 pin of the Type-C2 interface, the charging chip, and the PD protocol chip. The charging chip is connected to the battery and the DP2 / DM2 pin of the Type-C2 interface; The CC2 pin of the Type-C2 interface is connected to the PD protocol chip; The control circuit is connected to the VBUS1 pin of the Type-C1 interface, the VBUS2 pin of the Type-C2 interface, the CPU chip, the battery, and the charging chip.

2. The dual Type-C interface circuit as described in claim 1, characterized in that, The control circuit includes: a power switching circuit and an OTG circuit; The power switching circuit is connected to the VBUS1 pin of the Type-C1 interface, the VBUS2 pin of the Type-C2 interface, and the charging chip. The OTG circuit is connected to the VBUS1 pin of the Type-C1 interface, the power switching circuit, the CPU chip, and the battery.

3. The dual Type-C interface circuit as described in claim 2, characterized in that, The power switching circuit includes: a first MOSFET, a first resistor, a second resistor, a second MOSFET, a first capacitor, a third MOSFET, a third resistor, a fourth resistor, a fourth MOSFET, a second capacitor, a fifth resistor, a sixth resistor, a fifth MOSFET, a seventh resistor, an eighth resistor, and a ninth resistor; Pin 6 of the first MOSFET, the VBUS1 pin of the Type-C1 interface, one end of the eighth resistor are connected, pins 1 and 3 of the first MOSFET, one end of the first resistor and one end of the first capacitor are connected, pins 2 and 4 of the first MOSFET, the other end of the first resistor, the other end of the first capacitor and one end of the second resistor are connected, and pin 5 of the first MOSFET, pin 5 of the third MOSFET and one end of the seventh resistor are connected to the charging chip. The drain of the second MOS transistor is connected to the other end of the second resistor, the gate of the drain of the second MOS transistor, the other end of the eighth resistor, the OTG circuit, and the drain of the fifth MOS transistor are connected, and the source of the second MOS transistor is grounded. Pin 6 of the third MOSFET, one end of the ninth resistor, and the VBUS2 pin of the Type-C2 interface are connected. Pins 1 and 3 of the third MOSFET, one end of the third resistor, and one end of the second capacitor are connected. Pins 2 and 4 of the third MOSFET, the other end of the third resistor, the other end of the second capacitor, and one end of the fourth resistor are connected. The drain of the fourth MOS transistor is connected to the other end of the fourth resistor, the gate of the fourth MOS transistor is connected to the other end of the ninth resistor, and the source of the fourth MOS transistor is grounded. The gate of the fifth MOS transistor is connected to one end of the fifth resistor and one end of the sixth resistor, and the source of the fifth MOS transistor is grounded. The other end of the fifth resistor is connected to the VBUS2 pin of the Type-C2 interface, and the other end of the sixth resistor is grounded.

4. The dual Type-C interface circuit as described in claim 3, characterized in that, The power switching circuit further includes: a tenth resistor and a third capacitor; one end of the tenth resistor and one end of the third capacitor are connected to one end of the eighth resistor, and the other end of the tenth resistor and the other end of the third capacitor are grounded.

5. The dual Type-C interface circuit as described in claim 3, characterized in that, The power switching circuit further includes: an eleventh resistor and a fourth capacitor; one end of the eleventh resistor and one end of the fourth capacitor are connected to one end of the ninth resistor, and the other end of the eleventh resistor and the other end of the fourth capacitor are grounded.

6. The dual Type-C interface circuit as described in claim 2, characterized in that, The OTG circuit includes: a conversion chip, an inductor, a fifth capacitor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a sixth MOSFET, a fifteenth resistor, a sixteenth resistor, a sixth capacitor, a seventh capacitor, and a diode; Pin 5 of the conversion chip is connected to one end of the inductor; pin 6 of the conversion chip is connected to the other end of the inductor and the battery; pin 4 of the conversion chip is connected to one end of the twelfth resistor, one end of the thirteenth resistor, and the CPU chip; pin 2 of the conversion chip is connected to one end of the fifteenth resistor, one end of the sixth capacitor, one end of the seventh capacitor, and one end of the diode; and pin 3 of the conversion chip is connected to the other end of the fifteenth resistor, one end of the sixteenth resistor, and the other end of the sixth capacitor. The drain of the sixth MOS transistor is connected to the power switching circuit, the gate of the sixth MOS transistor is connected to the other end of the thirteenth resistor and one end of the fourteenth resistor, and the sixth MOS transistor is grounded. The other end of the fifth capacitor, the other end of the twelfth resistor, the other end of the fourteenth resistor, the other end of the sixteenth resistor, and the other end of the seventh capacitor are grounded; The other end of the diode is connected to the VBUS1 pin of the Type-C1 interface.

7. The dual Type-C interface circuit as described in claim 1, characterized in that, It also includes: the seventh MOSFET, the seventeenth resistor, the eighteenth resistor, the eighth MOSFET, the nineteenth resistor, and the twentieth resistor; The drain of the seventh MOS transistor is connected to the CPU_INT1 pin of the Type-C1 interface, the gate of the seventh MOS transistor is connected to one end of the seventeenth resistor and one end of the eighteenth resistor, and the source of the seventh MOS transistor is grounded. The other end of the seventeenth resistor is connected to the VBUS1 pin of the Type-C1 interface, and the other end of the eighteenth resistor is grounded. The drain of the eighth MOS transistor is connected to the CPU_INT2 pin of the Type-C2 interface, the gate of the eighth MOS transistor is connected to one end of the nineteenth resistor and one end of the twentieth resistor, and the source of the eighth MOS transistor is grounded. The other end of the nineteenth resistor is connected to the VBUS2 pin of the Type-C2 interface, and the other end of the twentieth resistor is grounded.

8. A tablet computer, characterized in that, It includes the dual Type-C interface circuit as described in any one of claims 1 to 7.

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