A 4G communication control circuit

Abstract

This utility model relates to the field of IoT intelligent control technology, and in particular to a 4G communication control circuit applied to a smart cloud box device. The circuit includes a System-on-Chip (SOC) system, and further includes a Wi-Fi module, a 4G module, a power module, and a storage module. The Wi-Fi module, 4G module, power module, and storage module are all electrically connected to the SOC system. The 4G module uses an EG915N 4G chip. The EG915N 4G communication chip is a high-performance, multi-band 4G chip with stable wireless connectivity and high-speed data transmission capabilities, effectively meeting the communication needs of the smart cloud box in mobile network environments. Through the organic combination of multiple modules, this 4G communication control circuit effectively solves the problem of the lack of a 4G module in the smart cloud box, while also considering local area network requirements, significantly improving communication stability, coverage, and response speed.

Description

Technical Field

[0001] This utility model relates to the field of Internet of Things (IoT) intelligent control technology, and in particular to a 4G communication control circuit. Background Technology

[0002] The smart cloud box is an intelligent device integrating data acquisition, processing, and communication functions, enabling remote management and intelligent control of devices. With the rapid development of the Internet of Things (IoT) and smart homes, the smart cloud box plays an increasingly important role as a key node connecting various smart devices and cloud platforms. At the same time, as its functions continue to expand and application scenarios become increasingly diverse, user demands for smart cloud boxes are becoming more varied and complex. Especially in terms of wireless communication, the smart cloud box not only needs to support multiple wireless connection methods to achieve stable and high-speed data transmission, but also must ensure communication reliability and low power consumption to adapt to the needs of different environments and applications. However, current smart cloud boxes do not integrate a 4G communication module, which to some extent limits the device's connectivity in mobile network environments. The lack of a 4G module prevents the smart cloud box from achieving wide-area wireless coverage, affecting the flexibility and real-time performance of remote management and data transmission, and hindering its application and promotion in more complex scenarios. Utility Model Content

[0003] In view of this, this utility model proposes a 4G communication control circuit, which aims to solve the problem that the current smart cloud box has not yet integrated a 4G communication module.

[0004] This utility model proposes a 4G communication control circuit for use in a smart cloud box device, including a SOC system, and further including a WIFI module, a 4G module, a power module and a storage module; wherein, the WIFI module, the 4G module, the power module and the storage module are all electrically connected to the SOC system, and the 4G module adopts an EG915N type 4G chip.

[0005] Furthermore, the WIFI module includes an AIC8800D80 type WIFI chip UW4, resistors RW1, RW10, and RW20R, capacitors CW15, CW13, and CW34, resistors RW21, RW22, and RW23, capacitors CW35, CW33, CW31, CW32, and CW29, inductors LW5, CW14, CW16, and CW30, resistor RW3, antenna interface ANT3, antenna WF-ANT, and S... The LFD18-5R950G-07 model includes the following components: RF duplexer UW5, antenna WF-24G-ANT-1, antenna WF-5G-ANT-1, inductor LW4, capacitor CW12, capacitor CW9, capacitor CW10, antenna WF-24G-ANT-2, antenna WF-5G-ANT-2, inductor LW7, capacitor CW1, capacitor CW2, inductor LW2, inductor LW3, capacitor CW6, capacitor CW7, resistor RW13, antenna BT-ANT, antenna RF-BT-ANT, and antenna interface ANT1.

[0006] Specifically, pin 1 of the UW4 WIFI chip is connected to the HST_WAK_WF signal terminal via resistor RW1 and to the AP-WAKE-BT signal terminal via resistor RW10. Pin 2 of the UW4 WIFI chip is grounded. Pin 3 of the UW4 WIFI chip is connected to the BT-UART-RX signal terminal via resistor RW20R. Pin 4 of the UW4 WIFI chip is grounded via capacitor CW15. Pin 5 of the UW4 WIFI chip is grounded via capacitor CW13. Pin 6 of the UW4 WIFI chip is connected to the XTAL0 signal terminal. Pin 7 of the UW4 Wi-Fi chip is grounded; pins 8 and 9 of the UW4 Wi-Fi chip are both floating; pin 10 of the UW4 Wi-Fi chip is grounded through capacitor CW34; pin 11 of the UW4 Wi-Fi chip is connected to the BT-UART-TX signal terminal through resistor RW21; pin 12 of the UW4 Wi-Fi chip is connected to the BT-UART-CTS signal terminal through resistor RW22; and pin 13 of the UW4 Wi-Fi chip is connected to the BT-UART-RTS signal terminal through resistor RW23. Pin 14 is connected to the WL-DEBUG-RX signal terminal. Pin 15 of the UW4 WIFI chip is connected to the WL-DEBUG-TX signal terminal. Pin 16 of the UW4 WIFI chip is connected to one end of capacitor CW35 and the WIFI-IO signal terminal, with the other end of capacitor CW35 grounded. Pin 17 of the UW4 WIFI chip is connected to the WL-SDIO-D2 signal terminal. Pin 18 of the UW4 WIFI chip is connected to the WL-SDIO-D3 signal terminal. Pin 19 of the UW4 WIFI chip is connected to the WL-SDIO-CMD signal terminal. Pin 20 of the WIFI chip UW4 is connected to the WL-SDIO-CLK signal terminal, pin 21 of the WIFI chip UW4 is connected to the WL-SDIO-D0 signal terminal, pin 22 of the WIFI chip UW4 is connected to the WL-SDIO-D1 signal terminal, pin 23 of the WIFI chip UW4 is grounded through capacitor CW33, and pin 24 of the WIFI chip UW4 is connected to one end of capacitor CW31, one end of capacitor CW32 and VCC33-WIFI signal terminal respectively. The other ends of capacitor CW31 and capacitor CW32 are both grounded.

[0007] Pins 26, 28, 29, 30, and 32 of the UW4 Wi-Fi chip are all left floating. Pin 25 of the UW4 Wi-Fi chip is grounded sequentially through inductor LW5 and capacitor CW29. Pin 27 of the UW4 Wi-Fi chip is grounded through capacitor CW29. Pin 31 of the UW4 Wi-Fi chip is grounded through capacitor CW14. Pin 33 of the UW4 Wi-Fi chip is connected to one end of capacitor CW16, one end of capacitor CW30, and the VCC33-WIFI signal terminal. The other ends of capacitors CW16 and CW30 are grounded. Pin 34 of the UW4 Wi-Fi chip is connected to one end of resistor RW3 and the WL-REG-ON signal terminal. The other end of resistor RW3 is connected to the WIFI-IO signal terminal. Pins 40, 49, 50, 51, 52, 35, and 36 of the UW4 Wi-Fi chip are all grounded. Pin 37 of the UW4 Wi-Fi chip is connected to one end of antenna WF-5G-ANT-2; pin 38 of the UW4 Wi-Fi chip is connected to one end of antenna WF-24G-ANT-2; pin 39 of the UW4 Wi-Fi chip is grounded through inductor LW7; pin 41 of the UW4 Wi-Fi chip is grounded through capacitor CW1; pin 42 of the UW4 Wi-Fi chip is grounded through capacitor CW2; pin 43 of the UW4 Wi-Fi chip is grounded through inductor LW2; pin 44 of the UW4 Wi-Fi chip is connected to one end of antenna BT-ANT; pin 45 of the UW4 Wi-Fi chip is grounded through resistor RW13; pin 46 of the UW4 Wi-Fi chip is connected to the HST_WAK_WF signal terminal; pin 47 of the UW4 Wi-Fi chip is connected to the WL-WAKE-AP signal terminal; and pin 48 of the UW4 Wi-Fi chip is connected to the BT-WAKE-AP signal terminal.

[0008] The other end of the antenna BT-ANT is connected to one end of capacitor CW7 and one end of inductor LW3, with the other end of capacitor CW7 grounded. The other end of inductor LW3 is connected to one end of capacitor CW6 and one end of antenna RF-BT-ANT, with the other end of capacitor CW6 grounded. The other end of antenna RF-BT-ANT is connected to one end of antenna interface ANT1, with the other end of antenna interface ANT1 grounded. One end of inductor LW4 and one end of capacitor CW12 are both grounded. The other end of inductor LW4 is connected to antenna WF-24G-ANT-2 via capacitor CW9. The other end of the resistor CW12 is connected to the first pin of the RF duplexer UW5 via the antenna WF-24G-ANT-1. The other end of the resistor CW12 is connected to the other end of the antenna WF-5G-ANT-2 via the capacitor CW10 and to the third pin of the RF duplexer UW5 via the antenna WF-5G-ANT-1. The second, fourth, and sixth pins of the RF duplexer UW5 are all grounded. The fifth pin of the RF duplexer UW5 is connected to one end of the antenna interface ANT3 via the antenna WF-ANT. The other end of the antenna interface ANT3 is grounded.

[0009] Furthermore, the 4G module includes an EG915N type 4G chip U4A, an ACM2012-2P type transformer 6L1, a capacitor CW39, a resistor R8517, a resistor R8518, a capacitor CW36, and a capacitor CW40; wherein, pins 1, 4, 5, 6, 7, 11, 12, 13, 14, 16, 18, 19, 25, 26, and 27 of the 4G chip U4A are... Pins 28, 56, and 57 are all left floating. Pin 2 of the 4G chip U4A is connected to the 2T1 test point. Pin 3 of the 4G chip U4A is grounded. Pin 8 of the 4G chip U4A is connected to the USB_VBUS signal terminal and one end of capacitor CW39, with the other end of capacitor CW39 grounded. Pin 9 of the 4G chip U4A is connected to the primary 4 terminal of transformer 6L1. The primary 1 terminal of transformer 6L1 is connected to the USBHOST_A_DP signal terminal. The secondary... The secondary winding of transformer 6L1 is connected to pin 10 of the 4G chip U4A. Pin 15 of the 4G chip U4A is connected to test point 2T26 and the 4G_PWRKEY signal terminal via resistor R8517. Pin 17 of the 4G chip U4A is connected to test point 2T27 and the 4G_RST signal terminal via resistor R8518. Pin 20 of the 4G chip U4A is connected to test point 2T2. Pin 21 of the 4G chip U4A... Pin 22 of the 4G chip U4A is connected to test point 2T14; pin 23 of the 4G chip U4A is connected to test point 2T16; pin 24 of the 4G chip U4A is connected to test point 2T17; pin 29 of the 4G chip U4A is connected to one end of capacitor CW36 and the VDD_EXT signal terminal respectively, and the other end of capacitor CW36 is grounded; pin 30 of the 4G chip U4A is connected to test point 2T37; and pin 31 of the 4G chip U4A is grounded.

[0010] Pin 32 of the 4G chip U4A is connected to one end of capacitor CW40, pin 33 of the 4G chip U4A, and the VBAT_BB signal terminal, respectively. The other end of capacitor CW40 is grounded. Pin 34 of the 4G chip U4A is connected to test point 2T25. Pin 35 of the 4G chip U4A is connected to test point 2T24. Pin 36 of the 4G chip U4A is connected to test point 2T23. Pin 37 of the 4G chip U4A is connected to test point 2T19. Pin 38 of the 4G chip U4A is connected to test point 2T18. Pin 39 of the 4G chip U4A is connected to test point 2T20. Pin 40 of the 4G chip U4A is connected to test point 2T21. Pin 41 of the 4G chip U4A is connected to test point 2T22. Pin 42 of the 4G chip U4A is connected to the UIM_DET signal terminal. Pin 43 of the 4G chip U4A is connected to the UIM_PW signal terminal. The R signal terminal, pin 44 of the 4G chip U4A is connected to the UIM_RESET signal terminal, pin 45 of the 4G chip U4A is connected to the UIM_DATA signal terminal, pin 46 of the 4G chip U4A is connected to the UIM_CLK signal terminal, pin 47 of the 4G chip U4A is connected to the USIM_GND signal terminal, pin 48 of the 4G chip U4A is grounded, pin 49 of the 4G chip U4A is connected to the ANT_GNSS signal terminal, pins 50, 54, 55, 58, 59, 61 and 62 of the 4G chip U4A are all grounded, pin 51 of the 4G chip U4A is connected to the PPS_GNSS_ANT signal terminal, pins 52 and 53 of the 4G chip U4A are both connected to the VBAT_BB signal terminal, and pin 60 of the 4G chip U4A is connected to the ANT-4G signal terminal.

[0011] Furthermore, the power module includes an AXP313A type power management chip U2, capacitors CP8 and CP11, ferrite bead T7, capacitors C316 and T6, capacitors C317 and CP7, inductor LP3, capacitor CP9, capacitor CP10, capacitor CP12, inductor LP4, capacitor CP13, capacitor CP14, capacitor CP15, inductor LP5, and capacitor CP16.

[0012] Specifically, pin 15 of power management chip U2 is connected to the VCC-ALDO signal terminal and one end of capacitor CP8; pin 12 of power management chip U2 is connected to the VCC-DLDO signal terminal and one end of capacitor CP11; pin 7 of power management chip U2 is connected to the VCC_RTC signal terminal; pin 5 of power management chip U2 is connected to the PMU-SDA signal terminal; pin 6 of power management chip U2 is connected to the PMU-SCK signal terminal; pin 11 of power management chip U2 is connected to ferrite bead T7; pin 13 of power management chip U2 is connected to the AP-RESET signal terminal and one end of capacitor C316; pin 14 of power management chip U2 is connected to the 2.4G_PWRON signal terminal and ferrite bead T6; the other ends of capacitors CP8, CP11, and C316 are all grounded; pin 8 of power management chip U2 is grounded through capacitor C317; and pin 10 of power management chip U2 is left floating.

[0013] Pin 17 of the power management chip U2 is connected to the VCC-5V signal terminal and one end of capacitor CP7. Pin 18 of the power management chip U2 is connected to one end of inductor LP3. The other end of inductor LP3 is connected to one end of capacitor CP9, one end of capacitor CP10, and the VDD-GPU signal terminal. Pin 16 of the power management chip U2 is connected to the VDD-GPUFB signal terminal. Pin 20 of the power management chip U2 is connected to the VCC-5V signal terminal and one end of capacitor CP12. Pin 19 of the power management chip U2 is connected to one end of inductor LP4. The other end of inductor LP4 is connected to one end of capacitor CP13, one end of capacitor CP14, and the VDD-CPU signal terminal. Pin 1 of the power management chip U2 is connected to the VDD-CPUFB signal terminal. Pin 2 of the power management chip U2 is connected to the VCC-5V signal terminal and one end of capacitor CP15. Pin 3 of the power management chip U2 is connected to one end of inductor LP5. The other end of inductor LP5 is connected to one end of capacitor CP16, the VDD-DRAM signal terminal, and pin 4 of the power management chip U2. The other ends of capacitors CP7, CP9, CP10, CP12, CP13, CP14, CP15, and CP16 are all grounded. Pins 9 and 21 of the power management chip U2 are both grounded.

[0014] Furthermore, the storage module includes an LPDDR4_FBGA200 type memory chip UD1A, resistors RD1, RD2, RD5, and RD4; wherein, pin B2 of memory chip UD1A is connected to the SDQ13 signal terminal, pin C2 of memory chip UD1A is connected to the SDQ10 signal terminal, pin E2 of memory chip UD1A is connected to the SDQ12 signal terminal, pin F2 of memory chip UD1A is connected to the SDQ14 signal terminal, pin F4 of memory chip UD1A is connected to the SDQ8 signal terminal, pin E4 of memory chip UD1A is connected to the SDQ9 signal terminal, and pin C4 of memory chip UD1A is connected to the SDQ14 signal terminal. 1. For the memory chip UD1A, pin B4 is connected to the SDQ15 signal terminal; pin D3 is connected to the SDQS1P signal terminal; pin E3 is connected to the SDQS1N signal terminal; pin C3 is connected to the SDQM1 signal terminal; pin B11 is connected to the SDQ6 signal terminal; pin C11 is connected to the SDQ4 signal terminal; pin E11 is connected to the SDQ1 signal terminal; pin F11 is connected to the SDQ3 signal terminal; and pin F9 is connected to the SDQ7 signal terminal. The memory chip UD1A has the following pins connected: E9 to SDQ5, C9 to SDQ0, B9 to SDQ2, D10 to SDQS0P, E10 to SDQS0N, C10 to SDQM0, AA2 to SDQ16, Y2 to SDQ18, and V2 to SDQ23. Pin U2 of memory chip UD1A is connected to the SDQ21 signal terminal; pin U4 of memory chip UD1A is connected to the SDQ22 signal terminal; pin V4 of memory chip UD1A is connected to the SDQ19 signal terminal; pin Y4 of memory chip UD1A is connected to the SDQ20 signal terminal; pin AA4 of memory chip UD1A is connected to the SDQ17 signal terminal; pin W3 of memory chip UD1A is connected to the SDQS2P signal terminal; pin V3 of memory chip UD1A is connected to the SDQS2N signal terminal; pin Y3 of memory chip UD1A is connected to the SDQM2 signal terminal; and pin AA11 of memory chip UD1A is connected to the SDQ29 signal terminal.The memory chip UD1A has the following pins connected: Y11 pin to SDQ24, V11 pin to SDQ26, U11 pin to SDQ25, U9 pin to SDQ30, V9 pin to SDQ31, Y9 pin to SDQ28, AA9 pin to SDQ27, W10 pin to SDQS3P, V10 pin to SDQS3N, and Y10 pin to SDQM3.

[0015] The memory chip UD1A has its H2 pin connected to the SA0 signal terminal, its J2 pin connected to the SA1 signal terminal, its H9 pin connected to the SA2 signal terminal, its H10 pin connected to the SA3 signal terminal, its H11 pin connected to the SA4 signal terminal, its J11 pin connected to the SA5 signal terminal, its R2 pin connected to the SA0 signal terminal, and its P2 pin connected to the SA1 signal terminal. The signal terminals of memory chip UD1A are as follows: pin R9 is connected to signal terminal SA2; pin R10 is connected to signal terminal SA3; pin R11 is connected to signal terminal SA4; pin P11 is connected to signal terminal SA5; pin J4 is connected to signal terminal SCKE0; pin J5 is connected to signal terminal SCKE1; and pin P4 is connected to signal terminal SCKE0. Pin P5 is connected to the SCKE1 signal terminal; pin J9 of memory chip UD1A is connected to the SCKN signal terminal; pin J8 of memory chip UD1A is connected to the SCKP signal terminal; pin P9 of memory chip UD1A is connected to the SCKN signal terminal; pin P8 of memory chip UD1A is connected to the SCKP signal terminal; pin H4 of memory chip UD1A is connected to the SCS0 signal terminal; pin H3 of memory chip UD1A is connected to the SCS1 signal terminal; pin R4 of memory chip UD1A is connected to the SCS0 signal terminal. The R3 pin of the memory chip UD1A is connected to the SCS1 signal terminal. The G2 pin of the memory chip UD1A is connected to the VCC-DRAM signal terminal through resistor RD1. The T2 pin of the memory chip UD1A is connected to the VCC-DRAM signal terminal through resistor RD2. The T11 pin of the memory chip UD1A is connected to the SRST signal terminal. The A5 pin of the memory chip UD1A is connected to the VCC-DRAM signal terminal through resistor RD5. The A8 pin of the memory chip UD1A is connected to the VCC-DRAM signal terminal through resistor RD4.

[0016] Compared with existing technologies, the beneficial effects of this utility model are as follows: A 4G communication control circuit, applied to a smart cloud box device, includes a SOC system, and further includes a WIFI module, a 4G module, a power module, and a storage module; wherein, the WIFI module, the 4G module, the power module, and the storage module are all electrically connected to the SOC system, and the 4G module adopts an EG915N type 4G chip. The EG915N type 4G communication chip is a high-performance, multi-band supported 4G chip, with stable wireless connection and high-speed data transmission capabilities, which can effectively meet the communication needs of the smart cloud box in a mobile network environment. Combined with a highly integrated SOC system, it achieves efficient management and data processing of the 4G network, improving remote management and intelligent control capabilities. Simultaneously, the integrated WIFI module supports high-speed wireless LAN communication, enhancing LAN access and device interconnection, and improving communication flexibility and compatibility. The storage module is responsible for protocol storage and data caching, ensuring smooth communication and data security. The power module provides a stable low-power supply, ensuring communication continuity and long-term device operation. By organically combining multiple modules, this 4G communication control circuit effectively solves the problem of the lack of a 4G module in the smart cloud box, while also taking into account the needs of the local area network, significantly improving communication stability, coverage and response speed, and meeting the diverse wireless communication needs in complex environments. Attached Figure Description

[0017] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0018] Figure 1 A structural block diagram of the 4G communication control circuit provided in this embodiment of the utility model;

[0019] Figure 2 A circuit diagram of the WIFI module provided in an embodiment of this utility model;

[0020] Figure 3 A circuit structure diagram of a 4G module provided for an embodiment of this utility model;

[0021] Figure 4 A circuit diagram of the power module provided for an embodiment of this utility model;

[0022] Figure 5 A circuit diagram of the storage module provided in an embodiment of this utility model. Detailed Implementation

[0023] The solutions in the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this utility model.

[0024] It should be noted that if the embodiments of this utility model involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0025] Furthermore, if the embodiments of this utility model involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0026] Please refer to Figure 1 As shown, this utility model proposes a 4G communication control circuit, including a SOC system, and further including a WIFI module, a 4G module, a power module and a storage module; wherein, the WIFI module, the 4G module, the power module and the storage module are all electrically connected to the SOC system, and the 4G module adopts an EG915N type 4G chip.

[0027] Specifically, a System-on-Chip (SoC) is a microelectronic system that highly integrates a processor core, memory, input / output interfaces, and various functional modules onto a single chip. By integrating multiple hardware resources, it achieves advantages such as small size, low power consumption, and high performance, and is widely used in smart terminals and embedded devices. In this 4G communication control circuit, the SoC system acts as the core control unit, responsible for coordinating the collaborative work of the 4G module, Wi-Fi module, and other peripheral modules. It possesses powerful data processing and multi-task management capabilities, ensuring efficient and stable communication operation. Simultaneously, its low-power design improves the device's battery life, meeting the demands of complex application environments in smart cloud boxes.

[0028] Compared to existing technologies, the EG915N 4G communication chip is a high-performance, multi-band supported 4G chip with stable wireless connectivity and high-speed data transmission capabilities, effectively meeting the communication needs of smart cloud boxes in mobile network environments. Combined with a highly integrated SOC system, it enables efficient management and data processing of the 4G network, enhancing remote management and intelligent control capabilities. Simultaneously, the integrated Wi-Fi module supports high-speed wireless LAN communication, enhancing LAN access and device interconnection, and improving communication flexibility and compatibility. The storage module handles protocol storage and data caching, ensuring smooth communication and data security. The power module provides a stable, low-power supply, guaranteeing continuous communication and long-term device operation. Through the organic combination of multiple modules, this 4G communication control circuit effectively solves the problem of the lack of a 4G module in smart cloud boxes, while also considering LAN requirements, significantly improving communication stability, coverage, and response speed, meeting diverse wireless communication needs in complex environments.

[0029] Please refer to Figure 2 As shown in some embodiments of this application, the WIFI module includes an AIC8800D80 type WIFI chip UW4, resistors RW1, RW10, RW20R, capacitors CW15, CW13, CW34, RW21, RW22, RW23, CW35, CW33, CW31, CW32, CW29, inductors LW5, CW14, CW16, CW30, resistor RW3, antenna interface ANT3, and antenna WF- The following components are included: ANT, SLFD18-5R950G-07 type RF duplexer UW5, antenna WF-24G-ANT-1, antenna WF-5G-ANT-1, inductor LW4, capacitor CW12, capacitor CW9, capacitor CW10, antenna WF-24G-ANT-2, antenna WF-5G-ANT-2, inductor LW7, capacitor CW1, capacitor CW2, inductor LW2, inductor LW3, capacitor CW6, capacitor CW7, resistor RW13, antenna BT-ANT, antenna RF-BT-ANT, and antenna interface ANT1;

[0030] Specifically, pin 1 of the UW4 WIFI chip is connected to the HST_WAK_WF signal terminal via resistor RW1 and to the AP-WAKE-BT signal terminal via resistor RW10. Pin 2 of the UW4 WIFI chip is grounded. Pin 3 of the UW4 WIFI chip is connected to the BT-UART-RX signal terminal via resistor RW20R. Pin 4 of the UW4 WIFI chip is grounded via capacitor CW15. Pin 5 of the UW4 WIFI chip is grounded via capacitor CW13. Pin 6 of the UW4 WIFI chip is connected to the XTAL0 signal terminal. Pin 7 of the UW4 Wi-Fi chip is grounded; pins 8 and 9 of the UW4 Wi-Fi chip are both floating; pin 10 of the UW4 Wi-Fi chip is grounded through capacitor CW34; pin 11 of the UW4 Wi-Fi chip is connected to the BT-UART-TX signal terminal through resistor RW21; pin 12 of the UW4 Wi-Fi chip is connected to the BT-UART-CTS signal terminal through resistor RW22; and pin 13 of the UW4 Wi-Fi chip is connected to the BT-UART-RTS signal terminal through resistor RW23. Pin 14 is connected to the WL-DEBUG-RX signal terminal. Pin 15 of the UW4 WIFI chip is connected to the WL-DEBUG-TX signal terminal. Pin 16 of the UW4 WIFI chip is connected to one end of capacitor CW35 and the WIFI-IO signal terminal, with the other end of capacitor CW35 grounded. Pin 17 of the UW4 WIFI chip is connected to the WL-SDIO-D2 signal terminal. Pin 18 of the UW4 WIFI chip is connected to the WL-SDIO-D3 signal terminal. Pin 19 of the UW4 WIFI chip is connected to the WL-SDIO-CMD signal terminal. Pin 20 of the WIFI chip UW4 is connected to the WL-SDIO-CLK signal terminal, pin 21 of the WIFI chip UW4 is connected to the WL-SDIO-D0 signal terminal, pin 22 of the WIFI chip UW4 is connected to the WL-SDIO-D1 signal terminal, pin 23 of the WIFI chip UW4 is grounded through capacitor CW33, and pin 24 of the WIFI chip UW4 is connected to one end of capacitor CW31, one end of capacitor CW32 and VCC33-WIFI signal terminal respectively. The other ends of capacitor CW31 and capacitor CW32 are both grounded.

[0031] Pins 26, 28, 29, 30, and 32 of the UW4 Wi-Fi chip are all left floating. Pin 25 of the UW4 Wi-Fi chip is grounded sequentially through inductor LW5 and capacitor CW29. Pin 27 of the UW4 Wi-Fi chip is grounded through capacitor CW29. Pin 31 of the UW4 Wi-Fi chip is grounded through capacitor CW14. Pin 33 of the UW4 Wi-Fi chip is connected to one end of capacitor CW16, one end of capacitor CW30, and the VCC33-WIFI signal terminal. The other ends of capacitors CW16 and CW30 are grounded. Pin 34 of the UW4 Wi-Fi chip is connected to one end of resistor RW3 and the WL-REG-ON signal terminal. The other end of resistor RW3 is connected to the WIFI-IO signal terminal. Pins 40, 49, 50, 51, 52, 35, and 36 of the UW4 Wi-Fi chip are all grounded. Pin 37 of the UW4 Wi-Fi chip is connected to one end of antenna WF-5G-ANT-2; pin 38 of the UW4 Wi-Fi chip is connected to one end of antenna WF-24G-ANT-2; pin 39 of the UW4 Wi-Fi chip is grounded through inductor LW7; pin 41 of the UW4 Wi-Fi chip is grounded through capacitor CW1; pin 42 of the UW4 Wi-Fi chip is grounded through capacitor CW2; pin 43 of the UW4 Wi-Fi chip is grounded through inductor LW2; pin 44 of the UW4 Wi-Fi chip is connected to one end of antenna BT-ANT; pin 45 of the UW4 Wi-Fi chip is grounded through resistor RW13; pin 46 of the UW4 Wi-Fi chip is connected to the HST_WAK_WF signal terminal; pin 47 of the UW4 Wi-Fi chip is connected to the WL-WAKE-AP signal terminal; and pin 48 of the UW4 Wi-Fi chip is connected to the BT-WAKE-AP signal terminal.

[0032] The other end of the antenna BT-ANT is connected to one end of capacitor CW7 and one end of inductor LW3, with the other end of capacitor CW7 grounded. The other end of inductor LW3 is connected to one end of capacitor CW6 and one end of antenna RF-BT-ANT, with the other end of capacitor CW6 grounded. The other end of antenna RF-BT-ANT is connected to one end of antenna interface ANT1, with the other end of antenna interface ANT1 grounded. One end of inductor LW4 and one end of capacitor CW12 are both grounded. The other end of inductor LW4 is connected to antenna WF-24G-ANT-2 via capacitor CW9. The other end of the resistor CW12 is connected to the first pin of the RF duplexer UW5 via the antenna WF-24G-ANT-1. The other end of the resistor CW12 is connected to the other end of the antenna WF-5G-ANT-2 via the capacitor CW10 and to the third pin of the RF duplexer UW5 via the antenna WF-5G-ANT-1. The second, fourth, and sixth pins of the RF duplexer UW5 are all grounded. The fifth pin of the RF duplexer UW5 is connected to one end of the antenna interface ANT3 via the antenna WF-ANT. The other end of the antenna interface ANT3 is grounded.

[0033] Specifically, the AIC8800D80 Wi-Fi chip, leveraging its domestic production advantages and low cost, combines support for Wi-Fi 6 (802.11ax) and Bluetooth 5.4 (BT / BLE) dual-mode wireless standards, covering both 2.4GHz and 5.8GHz frequency bands to achieve high-performance wireless connectivity. Its superior communication capabilities and stability have led to a rapid increase in its application penetration in consumer electronics and industrial IoT fields, making it an ideal choice for wireless communication in smart devices. This Wi-Fi chip supports higher data transmission rates and lower latency, effectively improving network efficiency and user experience. Simultaneously, advanced energy-saving technology ensures stable operation of devices over extended periods, meeting diverse application needs in complex environments.

[0034] Please refer to Figure 3As shown, in some embodiments of this application, the 4G module includes an EG915N type 4G chip U4A, an ACM2012-2P type transformer 6L1, a capacitor CW39, a resistor R8517, a resistor R8518, a capacitor CW36, and a capacitor CW40; wherein, the 1st, 4th, 5th, 6th, 7th, 11th, 12th, 13th, 14th, 16th, 18th, 19th, 25th, and 2nd pins of the 4G chip U4A are... Pins 6, 27, 28, 56, and 57 are all left floating. Pin 2 of the 4G chip U4A is connected to the 2T1 test point. Pin 3 of the 4G chip U4A is grounded. Pin 8 of the 4G chip U4A is connected to the USB_VBUS signal terminal and one end of capacitor CW39, with the other end of capacitor CW39 grounded. Pin 9 of the 4G chip U4A is connected to terminal 4 of the primary winding of transformer 6L1. Terminal 1 of the primary winding of transformer 6L1 is connected to the USBHOST_A_DP signal terminal. The secondary winding 2 of transformer 6L1 is connected to the USBHOST_A_DM signal terminal. The secondary winding 3 of transformer 6L1 is connected to pin 10 of 4G chip U4A. Pin 15 of 4G chip U4A is connected to test point 2T26 and the 4G_PWRKEY signal terminal via resistor R8517. Pin 17 of 4G chip U4A is connected to test point 2T27 and the 4G_RST signal terminal via resistor R8518. Pin 20 of 4G chip U4A is connected to test point 2T2. Pin 1 is connected to test point 2T14; pin 22 of the 4G chip U4A is connected to test point 2T15; pin 23 of the 4G chip U4A is connected to test point 2T16; pin 24 of the 4G chip U4A is connected to test point 2T17; pin 29 of the 4G chip U4A is connected to one end of capacitor CW36 and the VDD_EXT signal terminal respectively, and the other end of capacitor CW36 is grounded; pin 30 of the 4G chip U4A is connected to test point 2T37; and pin 31 of the 4G chip U4A is grounded.

[0035] Pin 32 of the 4G chip U4A is connected to one end of capacitor CW40, pin 33 of the 4G chip U4A, and the VBAT_BB signal terminal, respectively. The other end of capacitor CW40 is grounded. Pin 34 of the 4G chip U4A is connected to test point 2T25. Pin 35 of the 4G chip U4A is connected to test point 2T24. Pin 36 of the 4G chip U4A is connected to test point 2T23. Pin 37 of the 4G chip U4A is connected to test point 2T19. Pin 38 of the 4G chip U4A is connected to test point 2T18. Pin 39 of the 4G chip U4A is connected to test point 2T20. Pin 40 of the 4G chip U4A is connected to test point 2T21. Pin 41 of the 4G chip U4A is connected to test point 2T22. Pin 42 of the 4G chip U4A is connected to the UIM_DET signal terminal. Pin 43 of the 4G chip U4A is connected to the UIM_PW signal terminal. The R signal terminal, pin 44 of the 4G chip U4A is connected to the UIM_RESET signal terminal, pin 45 of the 4G chip U4A is connected to the UIM_DATA signal terminal, pin 46 of the 4G chip U4A is connected to the UIM_CLK signal terminal, pin 47 of the 4G chip U4A is connected to the USIM_GND signal terminal, pin 48 of the 4G chip U4A is grounded, pin 49 of the 4G chip U4A is connected to the ANT_GNSS signal terminal, pins 50, 54, 55, 58, 59, 61 and 62 of the 4G chip U4A are all grounded, pin 51 of the 4G chip U4A is connected to the PPS_GNSS_ANT signal terminal, pins 52 and 53 of the 4G chip U4A are both connected to the VBAT_BB signal terminal, and pin 60 of the 4G chip U4A is connected to the ANT-4G signal terminal.

[0036] Specifically, the EG915N 4G chip supports the LTE Cat 1 standard, with a maximum downlink speed of 10Mbps and an uplink speed of 5Mbps, meeting the needs of medium- and low-speed data transmission. It is compatible with multiple network standards including LTE, GSM, GPRS, and EDGE, and supports seamless switching between 2G and 4G networks, improving communication stability and flexibility. With its low cost, multi-network compatibility, and industrial-grade high stability, the EG915N 4G chip has become a mainstream communication solution for medium- and low-speed IoT scenarios, widely used in smart devices and industrial control fields. Furthermore, this 4G chip features excellent anti-interference capabilities and a low-power design, ensuring stable operation of devices in complex environments for extended periods, meeting diverse application requirements.

[0037] Please refer to Figure 4As shown, in some embodiments of this application, the power module includes an AXP313A type power management chip U2, capacitors CP8 and CP11, ferrite bead T7, capacitors C316 and T6, capacitors C317 and CP7, inductor LP3, capacitor CP9, capacitor CP10, capacitor CP12, inductor LP4, capacitor CP13, capacitor CP14, capacitor CP15, inductor LP5, and capacitor CP16.

[0038] Specifically, pin 15 of power management chip U2 is connected to the VCC-ALDO signal terminal and one end of capacitor CP8; pin 12 of power management chip U2 is connected to the VCC-DLDO signal terminal and one end of capacitor CP11; pin 7 of power management chip U2 is connected to the VCC_RTC signal terminal; pin 5 of power management chip U2 is connected to the PMU-SDA signal terminal; pin 6 of power management chip U2 is connected to the PMU-SCK signal terminal; pin 11 of power management chip U2 is connected to ferrite bead T7; pin 13 of power management chip U2 is connected to the AP-RESET signal terminal and one end of capacitor C316; pin 14 of power management chip U2 is connected to the 2.4G_PWRON signal terminal and ferrite bead T6; the other ends of capacitors CP8, CP11, and C316 are all grounded; pin 8 of power management chip U2 is grounded through capacitor C317; and pin 10 of power management chip U2 is left floating.

[0039] Pin 17 of the power management chip U2 is connected to the VCC-5V signal terminal and one end of capacitor CP7. Pin 18 of the power management chip U2 is connected to one end of inductor LP3. The other end of inductor LP3 is connected to one end of capacitor CP9, one end of capacitor CP10, and the VDD-GPU signal terminal. Pin 16 of the power management chip U2 is connected to the VDD-GPUFB signal terminal. Pin 20 of the power management chip U2 is connected to the VCC-5V signal terminal and one end of capacitor CP12. Pin 19 of the power management chip U2 is connected to one end of inductor LP4. The other end of inductor LP4 is connected to one end of capacitor CP13, one end of capacitor CP14, and the VDD-CPU signal terminal. Pin 1 of the power management chip U2 is connected to the VDD-CPUFB signal terminal. Pin 2 of the power management chip U2 is connected to the VCC-5V signal terminal and one end of capacitor CP15. Pin 3 of the power management chip U2 is connected to one end of inductor LP5. The other end of inductor LP5 is connected to one end of capacitor CP16, the VDD-DRAM signal terminal, and pin 4 of the power management chip U2. The other ends of capacitors CP7, CP9, CP10, CP12, CP13, CP14, CP15, and CP16 are all grounded. Pins 9 and 21 of the power management chip U2 are both grounded.

[0040] Specifically, the AXP313A power management chip, launched by X-Powers, is designed for embedded devices with multi-power rail requirements, offering high performance and flexible power management capabilities. Its industrial-grade stability ensures reliable operation in complex environments, effectively improving system power efficiency and safety. The AXP313A supports multiple voltage outputs and various power mode switching to meet the power supply needs of different modules and optimize overall power consumption. Simultaneously, this power management chip integrates multiple protection mechanisms, such as overvoltage, overcurrent, and overtemperature protection, ensuring safe device operation. With its high integration and excellent performance, the AXP313A power management chip is an ideal choice for power management in smart terminals and IoT devices.

[0041] Please refer to Figure 5As shown in some embodiments of this application, the storage module includes an LPDDR4_FBGA200 type memory chip UD1A, resistors RD1, RD2, RD5, and RD4; wherein, pin B2 of memory chip UD1A is connected to the SDQ13 signal terminal, pin C2 of memory chip UD1A is connected to the SDQ10 signal terminal, pin E2 of memory chip UD1A is connected to the SDQ12 signal terminal, pin F2 of memory chip UD1A is connected to the SDQ14 signal terminal, pin F4 of memory chip UD1A is connected to the SDQ8 signal terminal, pin E4 of memory chip UD1A is connected to the SDQ9 signal terminal, and pin C4 of memory chip UD1A is connected to the SDQ9 signal terminal. Pin B4 of the memory chip UD1A is connected to the SDQ11 signal terminal. Pin D3 of the memory chip UD1A is connected to the SDQS1P signal terminal. Pin E3 of the memory chip UD1A is connected to the SDQS1N signal terminal. Pin C3 of the memory chip UD1A is connected to the SDQM1 signal terminal. Pin B11 of the memory chip UD1A is connected to the SDQ6 signal terminal. Pin C11 of the memory chip UD1A is connected to the SDQ4 signal terminal. Pin E11 of the memory chip UD1A is connected to the SDQ1 signal terminal. Pin F11 of the memory chip UD1A is connected to the SDQ3 signal terminal. Pin F9 of the memory chip UD1A is connected to the SDQ15 signal terminal. The Q7 signal terminal is connected to the SDQ5 signal terminal via pin E9, pin C9 of the UD1A memory chip, pin B9 of the UD1A memory chip, pin D10 of the UD1A memory chip, pin E10 of the UD1A memory chip, pin C10 of the UD1A memory chip, pin AA2 of the UD1A memory chip, pin Y2 of the UD1A memory chip, and pin V2 of the UD1A memory chip. The memory chip UD1A has the following pins connected: U2 pin connected to SDQ21; U4 pin connected to SDQ22; V4 pin connected to SDQ19; Y4 pin connected to SDQ20; AA4 pin connected to SDQ17; W3 pin connected to SDQS2P; V3 pin connected to SDQS2N; Y3 pin connected to SDQM2; and AA11 pin connected to SDQ29.The memory chip UD1A has the following pins connected: Y11 pin to SDQ24, V11 pin to SDQ26, U11 pin to SDQ25, U9 pin to SDQ30, V9 pin to SDQ31, Y9 pin to SDQ28, AA9 pin to SDQ27, W10 pin to SDQS3P, V10 pin to SDQS3N, and Y10 pin to SDQM3.

[0042] The memory chip UD1A has its H2 pin connected to the SA0 signal terminal, its J2 pin connected to the SA1 signal terminal, its H9 pin connected to the SA2 signal terminal, its H10 pin connected to the SA3 signal terminal, its H11 pin connected to the SA4 signal terminal, its J11 pin connected to the SA5 signal terminal, its R2 pin connected to the SA0 signal terminal, and its P2 pin connected to the SA1 signal terminal. The signal terminals of memory chip UD1A are as follows: pin R9 is connected to signal terminal SA2; pin R10 is connected to signal terminal SA3; pin R11 is connected to signal terminal SA4; pin P11 is connected to signal terminal SA5; pin J4 is connected to signal terminal SCKE0; pin J5 is connected to signal terminal SCKE1; and pin P4 is connected to signal terminal SCKE0. Pin P5 is connected to the SCKE1 signal terminal; pin J9 of memory chip UD1A is connected to the SCKN signal terminal; pin J8 of memory chip UD1A is connected to the SCKP signal terminal; pin P9 of memory chip UD1A is connected to the SCKN signal terminal; pin P8 of memory chip UD1A is connected to the SCKP signal terminal; pin H4 of memory chip UD1A is connected to the SCS0 signal terminal; pin H3 of memory chip UD1A is connected to the SCS1 signal terminal; pin R4 of memory chip UD1A is connected to the SCS0 signal terminal. The R3 pin of the memory chip UD1A is connected to the SCS1 signal terminal. The G2 pin of the memory chip UD1A is connected to the VCC-DRAM signal terminal through resistor RD1. The T2 pin of the memory chip UD1A is connected to the VCC-DRAM signal terminal through resistor RD2. The T11 pin of the memory chip UD1A is connected to the SRST signal terminal. The A5 pin of the memory chip UD1A is connected to the VCC-DRAM signal terminal through resistor RD5. The A8 pin of the memory chip UD1A is connected to the VCC-DRAM signal terminal through resistor RD4.

[0043] Specifically, the LPDDR4_FBGA200 memory chip utilizes fourth-generation low-power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR4) technology, designed specifically for mobile devices. It boasts high bandwidth and low power consumption, significantly improving data transfer speeds while effectively reducing energy consumption and extending device battery life. Furthermore, its compact size makes it suitable for space-constrained embedded systems and smart terminal applications, meeting the demands for both high performance and energy efficiency. Its advanced memory architecture supports more efficient data access and multitasking capabilities, enhancing overall system responsiveness and stability, and contributing to smooth operation and superior performance in smart devices.

[0044] It should be noted that other pin connection structures and related component parameters not mentioned in the text description can be found in the attached diagram, and will not be elaborated upon here. Furthermore, the above connection layout is only an example; in actual applications, other connection schemes can be adopted according to specific requirements, and will not be further illustrated here.

[0045] The 4G communication control circuit provided in this embodiment of the invention is based on a high-performance SOC system, integrating a domestically produced and low-cost AIC8800D80 WIFI chip, a stable and reliable EG915N 4G chip supporting multiple network standards, a high-efficiency and flexible AXP313A power management chip, and a high-speed and low-power LPDDR4_FBGA200 memory chip. The modules work together to achieve efficient and stable communication, low-power operation, and rapid response, meeting the diverse communication needs of the smart cloud box in complex wireless environments, and possessing excellent performance and wide application adaptability.

[0046] It should be noted that the technical solutions of the various embodiments of this utility model can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0047] The above description is only a part or preferred embodiment of this utility model. Neither the text nor the drawings should limit the scope of protection of this utility model. All equivalent structural transformations made using the content of this utility model specification and drawings under the overall concept of this utility model, or direct / indirect applications in other related technical fields, are included within the scope of protection of this utility model.

Claims

1. A 4G communication control circuit, applied to a smart cloud box device, comprising a SOC system, characterized in that, It also includes a WIFI module, a 4G module, a power module, and a storage module; wherein the WIFI module, the 4G module, the power module, and the storage module are all electrically connected to the SOC system, and the 4G module uses an EG915N type 4G chip; The 4G module includes an EG915N type 4G chip U4A, an ACM2012-2P type transformer 6L1, a capacitor CW39, a resistor R8517, a resistor R8518, a capacitor CW36, and a capacitor CW40; wherein pins 1, 4, 5, 6, 7, 11, 12, 13, 14, 16, 18, 19, 25, 26, and 27 of the 4G chip U4A are... Pins 28, 56, and 57 are all left floating. Pin 2 of the 4G chip U4A is connected to the 2T1 test point. Pin 3 of the 4G chip U4A is grounded. Pin 8 of the 4G chip U4A is connected to the USB_VBUS signal terminal and one end of capacitor CW39, with the other end of capacitor CW39 grounded. Pin 9 of the 4G chip U4A is connected to terminal 4 of the primary winding of transformer 6L1. Terminal 1 of the primary winding of transformer 6L1 is connected to the USBHOST_A_DP signal terminal. The secondary winding of transformer 6L1... Pin 2 is connected to the USBHOST_A_DM signal terminal. Pin 3 of the secondary winding of transformer 6L1 is connected to pin 10 of 4G chip U4A. Pin 15 of 4G chip U4A is connected to test point 2T26 and the 4G_PWRKEY signal terminal via resistor R8517. Pin 17 of 4G chip U4A is connected to test point 2T27 and the 4G_RST signal terminal via resistor R8518. Pin 20 of 4G chip U4A is connected to test point 2T2. Pin 21 of 4G chip U4A... Connect test point 2T14; pin 22 of the 4G chip U4A is connected to test point 2T15; pin 23 of the 4G chip U4A is connected to test point 2T16; pin 24 of the 4G chip U4A is connected to test point 2T17; pin 29 of the 4G chip U4A is connected to one end of capacitor CW36 and the VDD_EXT signal terminal respectively, and the other end of capacitor CW36 is grounded; pin 30 of the 4G chip U4A is connected to test point 2T37; and pin 31 of the 4G chip U4A is grounded. Pin 32 of the 4G chip U4A is connected to one end of capacitor CW40, pin 33 of the 4G chip U4A, and the VBAT_BB signal terminal, respectively. The other end of capacitor CW40 is grounded. Pin 34 of the 4G chip U4A is connected to test point 2T25. Pin 35 of the 4G chip U4A is connected to test point 2T24. Pin 36 of the 4G chip U4A is connected to test point 2T23. Pin 37 of the 4G chip U4A is connected to test point 2T19. Pin 38 of the 4G chip U4A is connected to test point 2T18. Pin 39 of the 4G chip U4A is connected to test point 2T20. Pin 40 of the 4G chip U4A is connected to test point 2T21. Pin 41 of the 4G chip U4A is connected to test point 2T22. Pin 42 of the 4G chip U4A is connected to the UIM_DET signal terminal. Pin 43 of the 4G chip U4A is connected to the UIM_PW signal terminal. The R signal terminal, pin 44 of the 4G chip U4A is connected to the UIM_RESET signal terminal, pin 45 of the 4G chip U4A is connected to the UIM_DATA signal terminal, pin 46 of the 4G chip U4A is connected to the UIM_CLK signal terminal, pin 47 of the 4G chip U4A is connected to the USIM_GND signal terminal, pin 48 of the 4G chip U4A is grounded, pin 49 of the 4G chip U4A is connected to the ANT_GNSS signal terminal, pins 50, 54, 55, 58, 59, 61 and 62 of the 4G chip U4A are all grounded, pin 51 of the 4G chip U4A is connected to the PPS_GNSS_ANT signal terminal, pins 52 and 53 of the 4G chip U4A are both connected to the VBAT_BB signal terminal, and pin 60 of the 4G chip U4A is connected to the ANT-4G signal terminal.

2. The 4G communication control circuit according to claim 1, characterized in that, The WIFI module includes an AIC8800D80 type WIFI chip UW4, resistors RW1, RW10, and RW20R, capacitors CW15, CW13, and CW34, resistors RW21, RW22, and RW23, capacitors CW35, CW33, CW31, CW32, and CW29, inductors LW5, CW14, CW16, and CW30, resistor RW3, antenna interface ANT3, antenna WF-ANT, an SLFD18-5R950G-07 type RF duplexer UW5, antennas WF-24G-ANT-1 and WF-5G-ANT-1, inductor LW4, capacitors CW12, CW9, and CW10, antennas WF-24G-ANT-2, and antenna WF-5G. -ANT-2, Inductor LW7, Capacitor CW1, Capacitor CW2, Inductor LW2, Inductor LW3, Capacitor CW6, Capacitor CW7, Resistor RW13, Antenna BT-ANT, Antenna RF-BT-ANT and Antenna Interface ANT1; Specifically, pin 1 of the UW4 WIFI chip is connected to the HST_WAK_WF signal terminal via resistor RW1 and to the AP-WAKE-BT signal terminal via resistor RW10. Pin 2 of the UW4 WIFI chip is grounded. Pin 3 of the UW4 WIFI chip is connected to the BT-UART-RX signal terminal via resistor RW20R. Pin 4 of the UW4 WIFI chip is grounded via capacitor CW15. Pin 5 of the UW4 WIFI chip is grounded via capacitor CW13. Pin 6 of the UW4 WIFI chip is connected to the XTAL0 signal terminal. Pin 7 of the UW4 Wi-Fi chip is grounded; pins 8 and 9 of the UW4 Wi-Fi chip are both floating; pin 10 of the UW4 Wi-Fi chip is grounded through capacitor CW34; pin 11 of the UW4 Wi-Fi chip is connected to the BT-UART-TX signal terminal through resistor RW21; pin 12 of the UW4 Wi-Fi chip is connected to the BT-UART-CTS signal terminal through resistor RW22; and pin 13 of the UW4 Wi-Fi chip is connected to the BT-UART-RTS signal terminal through resistor RW23. Pin 14 is connected to the WL-DEBUG-RX signal terminal. Pin 15 of the UW4 WIFI chip is connected to the WL-DEBUG-TX signal terminal. Pin 16 of the UW4 WIFI chip is connected to one end of capacitor CW35 and the WIFI-IO signal terminal, with the other end of capacitor CW35 grounded. Pin 17 of the UW4 WIFI chip is connected to the WL-SDIO-D2 signal terminal. Pin 18 of the UW4 WIFI chip is connected to the WL-SDIO-D3 signal terminal. Pin 19 of the UW4 WIFI chip is connected to the WL-SDIO-CMD signal terminal. Pin 20 of the WIFI chip UW4 is connected to the WL-SDIO-CLK signal terminal, pin 21 of the WIFI chip UW4 is connected to the WL-SDIO-D0 signal terminal, pin 22 of the WIFI chip UW4 is connected to the WL-SDIO-D1 signal terminal, pin 23 of the WIFI chip UW4 is grounded through capacitor CW33, and pin 24 of the WIFI chip UW4 is connected to one end of capacitor CW31, one end of capacitor CW32 and VCC33-WIFI signal terminal respectively. The other ends of capacitor CW31 and capacitor CW32 are both grounded. Pins 26, 28, 29, 30, and 32 of the UW4 Wi-Fi chip are all left floating. Pin 25 of the UW4 Wi-Fi chip is grounded sequentially through inductor LW5 and capacitor CW29. Pin 27 of the UW4 Wi-Fi chip is grounded through capacitor CW29. Pin 31 of the UW4 Wi-Fi chip is grounded through capacitor CW14. Pin 33 of the UW4 Wi-Fi chip is connected to one end of capacitor CW16, one end of capacitor CW30, and the VCC33-Wi-Fi signal terminal. The other ends of capacitors CW16 and CW30 are grounded. Pin 34 of the UW4 Wi-Fi chip is connected to one end of resistor RW3 and the WL-REG-ON signal terminal. The other end of resistor RW3 is connected to the WIFI-IO signal terminal. Pins 40, 49, 50, 51, 52, 35, and 36 of the WIFI chip UW4 are all grounded. Pin 37 of the WIFI chip UW4 is connected to one end of the antenna WF-5G-ANT-2. Pin 38 of the WIFI chip UW4 is connected to one end of the antenna WF-24G-ANT-2. Pin 39 of the WIFI chip UW4 is grounded through inductor LW7. Pin 41 of the WIFI chip UW4 is grounded through capacitor CW1. Pin 42 of the WIFI chip UW4 is grounded through capacitor CW2. Pin 43 of the WIFI chip UW4 is grounded through inductor LW2. Pin 44 of the WIFI chip UW4 is connected to antenna BT. -ANT one end, the 45th pin of the WIFI chip UW4 is grounded through resistor RW13, the 46th pin of the WIFI chip UW4 is connected to the HST_WAK_WF signal terminal, the 47th pin of the WIFI chip UW4 is connected to the WL-WAKE-AP signal terminal, and the 48th pin of the WIFI chip UW4 is connected to the BT-WAKE-AP signal terminal; The other end of the antenna BT-ANT is connected to one end of capacitor CW7 and one end of inductor LW3, respectively. The other end of capacitor CW7 is grounded. The other end of inductor LW3 is connected to one end of capacitor CW6 and one end of antenna RF-BT-ANT, respectively. The other end of capacitor CW6 is grounded. The other end of ANT is connected to one end of antenna interface ANT1, and the other end of antenna interface ANT1 is grounded. One end of inductor LW4 and one end of capacitor CW12 are both grounded. The other end of inductor LW4 is connected to the other end of antenna WF-24G-ANT-2 via capacitor CW9 and to pin 1 of RF duplexer UW5 via antenna WF-24G-ANT-1. The other end of resistor CW12 is connected to the other end of antenna WF-5G-ANT-2 via capacitor CW10 and to pin 3 of RF duplexer UW5 via antenna WF-5G-ANT-1. Pins 2, 4, and 6 of RF duplexer UW5 are all grounded. Pin 5 of RF duplexer UW5 is connected to one end of antenna interface ANT3 via antenna WF-ANT, and the other end of antenna interface ANT3 is grounded.

3. The 4G communication control circuit according to claim 1, characterized in that, The power module includes an AXP313A type power management chip U2, capacitors CP8 and CP11, ferrite bead T7, capacitors C316 and T6, capacitors C317 and CP7, inductor LP3, capacitor CP9, capacitor CP10, capacitor CP12, inductor LP4, capacitor CP13, capacitor CP14, capacitor CP15, inductor LP5, and capacitor CP16. Specifically, pin 15 of power management chip U2 is connected to the VCC-ALDO signal terminal and one end of capacitor CP8; pin 12 of power management chip U2 is connected to the VCC-DLDO signal terminal and one end of capacitor CP11; pin 7 of power management chip U2 is connected to the VCC_RTC signal terminal; pin 5 of power management chip U2 is connected to the PMU-SDA signal terminal; pin 6 of power management chip U2 is connected to the PMU-SCK signal terminal; pin 11 of power management chip U2 is connected to ferrite bead T7; pin 13 of power management chip U2 is connected to the AP-RESET signal terminal and one end of capacitor C316; pin 14 of power management chip U2 is connected to the 2.4G_PWRON signal terminal and ferrite bead T6; the other ends of capacitors CP8, CP11, and C316 are all grounded; pin 8 of power management chip U2 is grounded through capacitor C317; and pin 10 of power management chip U2 is left floating. Pin 17 of the power management chip U2 is connected to the VCC-5V signal terminal and one end of capacitor CP7. Pin 18 of the power management chip U2 is connected to one end of inductor LP3. The other end of inductor LP3 is connected to one end of capacitor CP9, one end of capacitor CP10, and the VDD-GPU signal terminal. Pin 16 of the power management chip U2 is connected to the VDD-GPUFB signal terminal. Pin 20 of the power management chip U2 is connected to the VCC-5V signal terminal and one end of capacitor CP12. Pin 19 of the power management chip U2 is connected to one end of inductor LP4. The other end of inductor LP4 is connected to one end of capacitor CP13, one end of capacitor CP14, and the VDD-CPU signal terminal. Pin 1 of the power management chip U2 is connected to the VDD-CPUFB signal terminal. Pin 2 of the power management chip U2 is connected to the VCC-5V signal terminal and one end of capacitor CP15. Pin 3 of the power management chip U2 is connected to one end of inductor LP5. The other end of inductor LP5 is connected to one end of capacitor CP16, the VDD-DRAM signal terminal, and pin 4 of the power management chip U2. The other ends of capacitors CP7, CP9, CP10, CP12, CP13, CP14, CP15, and CP16 are all grounded. Pins 9 and 21 of the power management chip U2 are both grounded.

4. The 4G communication control circuit according to claim 1, characterized in that, The storage module includes an LPDDR4_FBGA200 type memory chip UD1A, resistors RD1, RD2, RD5, and RD4; wherein, pin B2 of memory chip UD1A is connected to the SDQ13 signal terminal, pin C2 of memory chip UD1A is connected to the SDQ10 signal terminal, pin E2 of memory chip UD1A is connected to the SDQ12 signal terminal, pin F2 of memory chip UD1A is connected to the SDQ14 signal terminal, pin F4 of memory chip UD1A is connected to the SDQ8 signal terminal, pin E4 of memory chip UD1A is connected to the SDQ9 signal terminal, and pin C4 of memory chip UD1A is connected to the SDQ11 signal terminal. The memory chip UD1A has the following pins connected: B4 pin connected to SDQ15, D3 pin connected to SDQS1P, E3 pin connected to SDQS1N, C3 pin connected to SDQM1, B11 pin connected to SDQ6, C11 pin connected to SDQ4, E11 pin connected to SDQ1, F11 pin connected to SDQ3, and F9 pin connected to SDQ7. The memory chip UD1A has the following pins connected: E9 to SDQ5, C9 to SDQ0, B9 to SDQ2, D10 to SDQS0P, E10 to SDQS0N, C10 to SDQM0, AA2 to SDQ16, Y2 to SDQ18, and V2 to SDQ23. Pin U2 of memory chip UD1A is connected to the SDQ21 signal terminal; pin U4 of memory chip UD1A is connected to the SDQ22 signal terminal; pin V4 of memory chip UD1A is connected to the SDQ19 signal terminal; pin Y4 of memory chip UD1A is connected to the SDQ20 signal terminal; pin AA4 of memory chip UD1A is connected to the SDQ17 signal terminal; pin W3 of memory chip UD1A is connected to the SDQS2P signal terminal; pin V3 of memory chip UD1A is connected to the SDQS2N signal terminal; pin Y3 of memory chip UD1A is connected to the SDQM2 signal terminal; and pin AA11 of memory chip UD1A is connected to the SDQ29 signal terminal.The memory chip UD1A has the following pins connected: Y11 pin to SDQ24, V11 pin to SDQ26, U11 pin to SDQ25, U9 pin to SDQ30, V9 pin to SDQ31, Y9 pin to SDQ28, AA9 pin to SDQ27, W10 pin to SDQS3P, V10 pin to SDQS3N, and Y10 pin to SDQM3. The memory chip UD1A has its H2 pin connected to the SA0 signal terminal, its J2 pin connected to the SA1 signal terminal, its H9 pin connected to the SA2 signal terminal, its H10 pin connected to the SA3 signal terminal, its H11 pin connected to the SA4 signal terminal, its J11 pin connected to the SA5 signal terminal, its R2 pin connected to the SA0 signal terminal, and its P2 pin connected to the SA1 signal terminal. The signal terminals of memory chip UD1A are as follows: pin R9 is connected to signal terminal SA2; pin R10 is connected to signal terminal SA3; pin R11 is connected to signal terminal SA4; pin P11 is connected to signal terminal SA5; pin J4 is connected to signal terminal SCKE0; pin J5 is connected to signal terminal SCKE1; and pin P4 is connected to signal terminal SCKE0. Pin P5 is connected to the SCKE1 signal terminal; pin J9 of memory chip UD1A is connected to the SCKN signal terminal; pin J8 of memory chip UD1A is connected to the SCKP signal terminal; pin P9 of memory chip UD1A is connected to the SCKN signal terminal; pin P8 of memory chip UD1A is connected to the SCKP signal terminal; pin H4 of memory chip UD1A is connected to the SCS0 signal terminal; pin H3 of memory chip UD1A is connected to the SCS1 signal terminal; pin R4 of memory chip UD1A is connected to the SCS0 signal terminal. The R3 pin of the memory chip UD1A is connected to the SCS1 signal terminal. The G2 pin of the memory chip UD1A is connected to the VCC-DRAM signal terminal through resistor RD1. The T2 pin of the memory chip UD1A is connected to the VCC-DRAM signal terminal through resistor RD2. The T11 pin of the memory chip UD1A is connected to the SRST signal terminal. The A5 pin of the memory chip UD1A is connected to the VCC-DRAM signal terminal through resistor RD5. The A8 pin of the memory chip UD1A is connected to the VCC-DRAM signal terminal through resistor RD4.

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