Multilevel diagnostic link status indication device for very high frequency data exchange system

Abstract

This invention provides a multi-level diagnostic link status indication device for VHF data exchange systems, relating to the technical field of communication equipment monitoring. It includes: a multi-level signal acquisition module, a cross-layer correlation diagnostic module, an intelligent visualization indication module, and a visible range extension structure. The output of the multi-level signal acquisition module is connected to the input of the cross-layer correlation diagnostic module; the output of the cross-layer correlation diagnostic module is connected to the input of the intelligent visualization indication module; the intelligent visualization indication module includes: a three-dimensional LED dot matrix and a buzzer. This invention utilizes the multi-level signal acquisition module and the cross-layer correlation diagnostic module to achieve full-dimensional parameter monitoring from physical layer signal degradation to protocol layer anomalies, eliminating the single-dimensional detection blind spots of traditional solutions.

Description

Technical Field

[0001] This utility model relates to the technical field of communication equipment monitoring, and more particularly to a multi-level diagnostic link status indication device for VHF data exchange systems. Background Technology

[0002] Traditional link status indication schemes typically only display the physical connection status using LED indicators, failing to deeply reflect signal quality degradation (such as noise interference, excessive TDMA channel load, and excessive VSWR, etc.) or simultaneously detect potential protocol layer faults (such as data frame checksum errors, handshake protocol timeouts, and lost ACK responses). This single-dimensional detection mechanism leads to a high false positive rate for link health assessment and lacks multi-level correlation analysis between physical layer signal characteristics and protocol layer behavior. It is difficult to provide timely warnings of latent faults caused by signal attenuation or protocol conflicts, severely restricting the operational efficiency of VHF Data Exchange Systems (VDES). Utility Model Content

[0003] To address the technical problems mentioned in the background section regarding traditional link status indication schemes, such as single-dimensional detection blind spots, lack of correlation between physical layer and protocol layer faults, delayed early warning of hidden faults, and small indication visibility range, this invention provides a multi-level diagnostic link status indication device for VHF data exchange systems. This invention achieves comprehensive health assessment from physical layer signal degradation to protocol layer anomalies through hardware-accelerated signal analysis and cross-layer intelligent diagnosis.

[0004] The technical means adopted in this utility model are as follows:

[0005] A multi-level diagnostic link status indication device for VHF data exchange systems, comprising:

[0006] The system comprises a multi-level signal acquisition module, a cross-layer correlation diagnostic module, and an intelligent visualization indicator module; the output of the multi-level signal acquisition module is connected to the input of the cross-layer correlation diagnostic module; the output of the cross-layer correlation diagnostic module is connected to the input of the intelligent visualization indicator module; the intelligent visualization indicator module includes a three-dimensional LED dot matrix and a buzzer; the multi-level signal acquisition module includes a physical layer detection unit and a protocol layer parsing unit.

[0007] The physical layer detection unit includes a standing wave ratio (VSWR) detection circuit and a time division multiple access (TDMA) channel load monitoring circuit.

[0008] Furthermore, the standing wave ratio detection circuit includes: a JDC-20-3 directional coupler, an AD8317 logarithmic amplifier I and an AD8317 logarithmic amplifier II, a temperature sensor, and an LTC6912 gain amplifier;

[0009] The input terminal of the JDC-20-3 directional coupler is connected to the feed line of the radio frequency antenna; the output terminal of the JDC-20-3 directional coupler is connected to the input terminal of the AD8317 logarithmic amplifier I.

[0010] The output of the JDC-20-3 directional coupler is connected to the input of the AD8317 logarithmic amplifier II; the output of the AD8317 logarithmic amplifier I is connected to the input of the gain amplifier, and the output of the AD8317 logarithmic amplifier II is connected to the input of the gain amplifier.

[0011] The output of the temperature sensor is connected to the input of the field-programmable gate array (FPGA); the input of the LTC6912 gain amplifier is connected to the output of the FPGA; and the output of the LTC6912 gain amplifier is also connected to the input of the FPGA.

[0012] Furthermore, the temperature sensor is positioned between AD8317 logarithmic amplifier I and AD8317 logarithmic amplifier II.

[0013] Furthermore, the time division multiple access channel load monitoring circuit includes: a coupler, a radio frequency matching network unit, an LTC6406 differential analog-to-digital converter unit, and a fast Fourier transform unit;

[0014] The input terminal of the coupler is connected to the output terminal of the base station transmitter power amplifier; the output terminal of the coupler is connected to the input terminal of the radio frequency matching network unit; the output terminal of the radio frequency matching network unit is connected to the input terminal of the LTC6406 differential analog-to-digital converter unit; and the output terminal of the LTC6406 differential analog-to-digital converter unit is connected to the input terminal of the fast Fourier transform unit.

[0015] Furthermore, the cross-layer correlation diagnosis module includes: a physical layer parameter extraction unit, a protocol layer processing unit, and an LSTM fault decision engine unit;

[0016] The output of the physical layer parameter extraction unit is connected to the input of the LSTM fault decision engine unit via an AXI bus; the output of the protocol layer processing unit is connected to the input of the LSTM fault decision engine unit via an AXI bus.

[0017] Furthermore, the three-dimensional LED dot matrix includes: a WS2812B LED dot matrix and an STM32 driver controller;

[0018] The output of the cross-layer correlation diagnostic module is connected to the input of the STM32 driver controller via a GPIO interface; the output of the STM32 driver controller is connected to the input of the WS2812B LED dot matrix.

[0019] The intelligent visualization indicator module includes an NE555 timer and an auxiliary LED driver circuit; the output of the cross-layer correlation diagnostic module is connected to the input of the NE555 timer via a GPIO interface; the output of the cross-layer correlation diagnostic module is connected to the input of the auxiliary LED driver circuit via a GPIO interface.

[0020] The visible range extension structure includes a housing, light strip, decorative panel, LED, nut, LED cable, 3M double-sided tape, crimp terminal, male connector, female connector, PCB board, screw, and light trough.

[0021] Compared with the prior art, the present invention has the following advantages:

[0022] 1. This utility model utilizes a physical layer detection unit and a protocol layer parsing unit to achieve full-dimensional parameter monitoring from physical layer signal degradation to protocol layer anomalies, eliminating the single-dimensional detection blind spot of traditional solutions.

[0023] 2. This utility model adopts a heterogeneous architecture of FPGA (hardware acceleration) and ARM (intelligent algorithm). It utilizes a physical layer parameter extraction unit, a protocol layer processing unit, and an LSTM fault decision engine unit to deeply integrate physical layer signal characteristics and protocol layer behavioral data, thereby realizing time-series correlation analysis and fault determination of multi-level parameters. It can distinguish between occasional interference and persistent faults, and the misjudgment rate is reduced by more than 70% compared with traditional solutions.

[0024] 3. This utility model utilizes an intelligent visual indication module to achieve rapid location of fault level (physical layer / protocol layer) and severity, reducing the average troubleshooting time by 60% compared to traditional solutions.

[0025] 4. This utility model solves the problem of indicator light status being unobservable through a small viewing window in a cabinet by designing the aforementioned extended visibility structure as the outer shell structure. The viewing angle can be adjusted according to the distance between the indicator light and the light strip. Through calculation, the optimal depth of the light trough in this design is 7.5mm, maximizing the light source scattering effect. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the system structure of this utility model.

[0028] Figure 2 This is a schematic diagram of the standing wave ratio detection circuit of this utility model.

[0029] Figure 3 This is a structural diagram of the present utility model.

[0030] Figure 4 This is an exploded view of the structure of this utility model.

[0031] Among them, 101 is the outer shell; 102 is the light strip; 103 is the decorative panel; 104 is the LED; 105 is the nut; 106 is the LED cable; 107 is the 3M double-sided adhesive; 108 is the crimp terminal; 109 is the male connector; 110 is the female connector; 111 is the PCB board; 112 is the screw; and 113 is the light trough. Detailed Implementation

[0032] It should be noted that, where there is no conflict, the embodiments and features in the embodiments of this utility model can be combined with each other. The present utility model will now be described in detail with reference to the accompanying drawings and embodiments.

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this utility model or its application or use. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0034] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to the present invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0035] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this invention. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0036] In the description of this utility model, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this utility model and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this utility model. The directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0037] For ease of description, spatial relative terms such as "above," "over," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation besides the orientation of the device as described in the figures. For example, if the device in the figures is inverted, a device described as "above" or "above" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0038] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be construed as limiting the scope of protection of this utility model.

[0039] like Figure 1 As shown, this utility model provides a multi-level diagnostic link status indication device for VDES systems, including: a multi-level signal acquisition module, a cross-layer correlation diagnostic module, and an intelligent visualization indication module; the output terminal of the multi-level signal acquisition module is connected to the input terminal of the cross-layer correlation diagnostic module; the output terminal of the cross-layer correlation diagnostic module is connected to the input terminal of the intelligent visualization indication module; the intelligent visualization indication module includes: a three-dimensional LED dot matrix and a buzzer. This application employs a three-dimensional LED dot matrix and an audio-visual composite alarm mechanism to realize the status indication of the multi-level diagnostic link of the VDES device.

[0040] The multi-level signal acquisition module includes a physical layer detection unit and a protocol layer parsing unit, which is the core of the system's front-end data acquisition.

[0041] The physical layer detection unit includes a standing wave ratio (SWR) detection circuit and a time division multiple access (TDMA) channel load monitoring circuit, used to collect antenna SWR and time division multiple access (TDMA) channel load information.

[0042] In a preferred embodiment, the VSWR detection circuit in this application includes: a JDC-20-3 directional coupler, AD8317 logarithmic amplifier I and AD8317 logarithmic amplifier II, a temperature sensor, and an LTC6912 gain amplifier. The input terminal (pin 8) of the JDC-20-3 directional coupler is connected to the feed line of the RF antenna for receiving RF signals from the system; the output terminal (pin 5) of the JDC-20-3 directional coupler is connected to the input terminal (pin 1) of the AD8317 logarithmic amplifier I.

[0043] The output terminal (pin 4) of the JDC-20-3 directional coupler is connected to the input terminal (pin 1) of the AD8317 logarithmic amplifier II, for real-time acquisition of the reflected signal from the antenna feed line and conversion into DC voltage. The output terminal (pin 5) of the AD8317 logarithmic amplifier I is connected to the input terminal (pin 2) of the gain amplifier, and the output terminal (pin 5) of the AD8317 logarithmic amplifier II is connected to the input terminal (pin 4) of the gain amplifier.

[0044] The output terminal (pin 3) of the temperature sensor is connected to the input terminal of the field programmable gate array (FPGA) for real-time monitoring of ambient temperature.

[0045] In a preferred embodiment, the input terminals (pins 6, 7, 8) of the LTC6912 gain amplifier are connected to the output terminals (pins A4, D3, C3) of the FPGA, so that the FPGA can control the LTC6912 gain amplifier through an SPI interface to dynamically adjust the reference voltage according to temperature changes in order to compensate for the temperature drift of the AD8317 logarithmic amplifier.

[0046] Meanwhile, the output terminals (pins 15 and 13) of the LTC6912 gain amplifier are connected to the input terminals (pins J6 and L8) of the FPGA.

[0047] In this application, the temperature sensor is positioned between AD8317 logarithmic amplifier I and AD8317 logarithmic amplifier II.

[0048] In a preferred embodiment, the time division multiple access channel load monitoring circuit in this application includes: a coupler, a radio frequency matching network unit, an LTC6406 differential analog-to-digital converter unit, and a fast Fourier transform unit;

[0049] The input of the coupler is connected to the output of the base station transmitter power amplifier, used to couple a portion of the signal from the main RF link with low insertion loss (typically ≤0.5 dB). The output of the coupler is connected to the input of the RF matching network unit, used to convert the single-ended coupled signal into a differential signal and suppress common-mode noise without affecting the main link communication. The output of the RF matching network unit is connected to the input of the LTC6406 differential analog-to-digital converter unit, used to convert the analog RF signal into digital sampled data, which is transmitted to the FPGA's Fast Fourier Transform module to provide raw data for spectrum analysis. The output of the LTC6406 differential analog-to-digital converter unit is connected to the input of the Fast Fourier Transform unit.

[0050] In this application, the Fast Fourier Transform module is embedded with relevant Fast Fourier Transform algorithms. Specifically, as long as it can decompose the radio frequency signal into spectral components, accurately extract the energy distribution within the target channel (such as the 25 kHz bandwidth of VDES), provide a basis for load rate calculation, and quantify the channel occupancy level in real time, the specific method is a well-known technical solution in this field, and therefore will not be described in detail in this specification.

[0051] Preferably, the cross-layer correlation diagnosis module includes a physical layer parameter extraction unit, a protocol layer processing unit, and an LSTM fault decision engine unit. It is the core of the system's intelligent analysis and adopts a heterogeneous architecture of FPGA (hardware acceleration) and ARM (intelligent algorithm). It deeply integrates physical layer signal characteristics and protocol layer behavioral data to realize time-series correlation analysis and fault determination of multi-level parameters.

[0052] The input of the physical layer parameter extraction unit is to receive the standing wave ratio (VSWR) voltage signal, TDMA channel load spectrum data and temperature sensor data from the physical layer detection unit. After the VSWR is dynamically calculated, the TDMA load rate is calculated and the temperature drift is compensated within the FPGA, a physical layer alarm signal (such as VSWR>2.5, TDMA load rate>70%) is generated, and the processing delay is ≤5us.

[0053] The output of the physical layer parameter extraction unit is connected to the input of the LSTM fault decision engine unit via an AXI bus; the output of the protocol layer processing unit is connected to the input of the LSTM fault decision engine unit via an AXI bus.

[0054] Preferably, the input of the protocol layer processing unit is the AIS / ASM / VDE protocol message transmitted by the base station equipment, including data frames, control frames, and handshake protocol raw data. After processing by the protocol layer unit, key protocol behavior parameters are parsed from the raw message and extracted. Data frames (such as user data), control frames (such as ACK / NACK), and management frames (such as time slot allocation instructions) are distinguished, and then abnormal behavior statistical analysis (such as ACK loss rate, TDMA retransmission count, time slot conflict, etc.) is performed.

[0055] The input of the LSTM fault decision engine unit is the physical layer alarm signal generated by the physical layer parameter extraction unit and the protocol layer alarm signal generated by the protocol layer processing unit. By analyzing the timing correlation between the physical layer and protocol layer parameters, it can accurately determine the fault type and predict the probability. The determination result is connected to the input of the intelligent visualization indication module through the GPIO interface for status indication of the multi-level diagnostic link of the VDES device.

[0056] In a preferred embodiment, the three-dimensional LED dot matrix in this application includes: a WS2812B LED dot matrix and an STM32 driver controller;

[0057] The output of the cross-layer correlation diagnostic module is connected to the input of the STM32 driver controller via a GPIO interface. The output of the STM32 driver controller is connected to the input of the WS2812B LED dot matrix, controlling the LED color and blinking mode via a single-wire serial protocol (such as SPI). The intelligent visualization indicator module includes an NE555 timer and an auxiliary LED driver circuit. The output of the cross-layer correlation diagnostic module is connected to the input of the NE555 timer via a GPIO interface to generate buzzer signals of different frequencies (such as a single 1 kHz beep or a continuous 3 kHz beep). The output of the cross-layer correlation diagnostic module is connected to the input of the auxiliary LED driver circuit via a GPIO interface to control the blinking frequency of the red LED (such as 2 Hz or 10 Hz).

[0058] like Figure 2As shown, the eighth terminal of coupler U57 is connected to the RF antenna feed line, the first terminal is connected to the RF receiving channel, the second and fourth terminals are connected to ground, the fourth terminal is connected to the first terminal of capacitor C79, the fifth terminal is connected to the first terminal of capacitor C78, ​​the second terminal of capacitor C79 is connected to the first and eighth terminals of detector U58 respectively, the second terminal of capacitor C78 is connected to the first and eighth terminals of detector U59 respectively, the second terminal of detector U58 is connected to ground, the third terminal of detector U58 is connected to the first terminal of capacitor C82, the third terminal of detector U59 is connected to the first terminal of capacitor C85, and the capacitor C82... The second terminal of detector U58 and the second terminal of capacitor C85 are connected to ground. The fourth terminal of detector U58 is connected to the first terminal of resistor R135. The fourth terminal of detector U59 is connected to the first terminal of resistor R140. The fifth terminal of detector U58 is connected to the second terminal of resistor R135 and the second terminal of gain amplifier U2. The fifth terminal of detector U59 is connected to the second terminal of resistor R140 and the fourth terminal of gain amplifier U2. The sixth terminal of detector U58 is connected to the first terminal of resistor R134. The sixth terminal of detector U59 is connected to the first terminal of resistor R139. The second terminals of resistors R134 and R139 are connected to ground. The seventh terminal of detector U58 is connected to the first terminals of capacitors C80, C81, and L44, respectively. The seventh terminal of detector U59 is connected to the first terminals of capacitors C83, C84, and L45, respectively. The second terminals of inductors L44 and L45 are connected to a 3.3V power supply, respectively. The third, fifth, and tenth terminals of gain amplifier U2 are connected to ground, respectively. The twelfth terminal of gain amplifier U2 is connected to the first terminal of capacitor C87 and the 3.3V power supply, respectively. The second terminal of capacitor C87 is connected to the fourteenth terminal of gain amplifier U2 and ground, respectively. The sixth terminal of gain amplifier U2 is connected to... The FPGA's C3 pin is connected; the seventh terminal of gain amplifier U2 is connected to the FPGA's D3 pin; the eighth terminal of gain amplifier U2 is connected to the FPGA's A4 pin; the temperature sensor U60 is located between detectors U58 and U59; the first terminal of temperature sensor U60 is connected to ground; the second terminal of temperature sensor U60 is connected to the FPGA's F3 pin; the third terminal of temperature sensor U60 is connected to the first terminals of capacitors C88 and C89, and the first terminal of inductor L46, respectively; the second terminals of capacitors C88 and C89 are connected to ground, respectively; and the second terminal of inductor L46 is connected to a 3.3V power supply.

[0059] The extended visibility structure integrates the aforementioned unit design into the circuit PCB. It is then installed inside the chassis housing. LED 104 is secured to a hole in the housing 101 using nuts 105. The cable end of LED 104 is crimped using crimp terminals 108 and then inserted into a male connector 109, which connects to a female connector 110 on the PCB board 111. LED cable 106 is secured inside the structural housing using fixing blocks 114.

[0060] The light strip 102 is attached to the light groove 113 of the decorative panel 103 using 3M double-sided tape 107. The decorative panel 103 is then fixed to the housing 101 with screws 112. The light strip 102 is made of a milky white frosted semi-transparent PC board, which has a light-scattering effect. The forward circular beam emitted by the LED 104 is diffused into a long strip shape by the light strip 102, increasing the visible range of the LED. The degree of diffusion can be adjusted according to the distance between the LED 104 and the light strip 102. Through calculation, the optimal depth of the light groove 113 in this design is 7.5mm. This maximizes the light scattering effect without affecting adjacent LEDs 104.

[0061] As one embodiment of this application, a method for implementing state monitoring using the device of this application includes the following steps:

[0062] First, the VSWR of the RF signal is measured. A JDC-20-3 directional coupler is connected in series to the base station antenna feeder, ensuring 50Ω impedance matching. The coupling outputs forward (Port 2) and reflected (Port 3) signals. The forward signal (RF1) and reflected signal (RF2) are then input to the AD8317 logarithmic amplifier.

[0063] The AD8317's RF1 and RF2 pins receive forward and reflected signals respectively, configuring its operating mode to "power detection mode". The AD8317 outputs two DC voltages (… , Acquisition via the FPGA's ADC channel. and The voltage was set to a sampling rate of 1 MSPS and a resolution of 12 bits. The VSWR detection results were then linearized using the following calibration formula:

[0064] ;

[0065] A temperature sensor (DS18B20) is deployed near the AD8317 to monitor the ambient temperature in real time. The FPGA controls the LTC6912 gain amplifier via the SPI interface to dynamically adjust the reference voltage according to temperature changes, compensating for the temperature drift of the AD8317. The compensation formula is as follows:

[0066] ;

[0067] In the formula, This represents the uncalibrated raw voltage value directly output from the AD8317 logarithmic amplifier. It is the difference between the current temperature and the reference temperature. The voltage value is dynamically calibrated and then corrected through a compensation circuit (LTC6912 gain adjustment) and algorithm (such as temperature compensation formula) to eliminate [the voltage's inherent characteristics]. By minimizing the error in the measurement, a high-precision power measurement value can be obtained.

[0068] Furthermore, the RF signal is input to the LTC6406 differential ADC from the power amplifier output via a coupler (coupling degree -20 dB), with the ADC sampling rate configured at 1 MSPS and input impedance at 50Ω. An FFT IP core (1024 points, Hamming window, 25% overlap) is deployed inside the FPGA to calculate the spectral power density. The FFT results are divided by frequency band, and the energy percentage within the target channel (e.g., the 25kHz bandwidth of VDES) is extracted. The load factor calculation formula is shown below:

[0069] ;

[0070] in: After performing a Fast Fourier Transform (FFT) on a radio frequency signal, the amplitude values ​​of each frequency component are... The total energy of all frequency points within the target channel bandwidth. The total energy of all frequency points across the entire spectrum.

[0071] Preferably, the FPGA and ARM communicate via an AXI bus. The FPGA is responsible for high-speed extraction of physical layer parameters, including VSWR over-limit alarm, TDMA channel occupancy calculation, and data processing latency. The ARM runs an LSTM fault prediction model, with input parameters including VSWR, ACK loss rate, and TDMA load rate, outputting fault type and probability, and driving the indicator unit. The indicator unit uses WS2812B LEDs to construct an 8×8 dot matrix, and an NE555 timer drives a buzzer to generate an audible and visual alarm.

[0072] This invention achieves full-dimensional monitoring and real-time early warning of physical layer and protocol layer faults through a multi-level signal acquisition module (VSWR detection, TDMA load monitoring, protocol parsing), a cross-layer correlation diagnosis module (FPGA+ARM heterogeneous computing), and an intelligent visualization system (3D LED dot matrix and audible and visual alarms), which significantly improves operation and maintenance efficiency and reduces false alarm rate.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A multi-level diagnostic link status indication device for VHF data exchange systems, characterized in that, include: Multi-level signal acquisition module, cross-layer correlation diagnosis module, visible range extension structure and intelligent visualization indication module; The output of the multi-level signal acquisition module is connected to the input of the cross-level correlation diagnostic module; The output of the cross-layer correlation diagnostic module is connected to the input of the intelligent visualization indication module; The intelligent visualization indicator module includes: a three-dimensional LED dot matrix and a buzzer; The multi-level signal acquisition module includes: a physical layer detection unit and a protocol layer parsing unit; The physical layer detection unit includes: a standing wave ratio (VSWR) detection circuit and a time division multiple access (TDMA) channel load monitoring circuit; The standing wave ratio detection circuit includes: a JDC-20-3 directional coupler, an AD8317 logarithmic amplifier I and an AD8317 logarithmic amplifier II, a temperature sensor, and an LTC6912 gain amplifier; The input terminal of the JDC-20-3 directional coupler is connected to the feed line of the radio frequency antenna; the output terminal of the JDC-20-3 directional coupler is connected to the input terminal of the AD8317 logarithmic amplifier I. The output of the JDC-20-3 directional coupler is connected to the input of the AD8317 logarithmic amplifier II; the output of the AD8317 logarithmic amplifier I is connected to the input of the gain amplifier, and the output of the AD8317 logarithmic amplifier II is connected to the input of the gain amplifier. The output of the temperature sensor is connected to the input of the field-programmable gate array (FPGA); the input of the LTC6912 gain amplifier is connected to the output of the FPGA; and the output of the LTC6912 gain amplifier is also connected to the input of the FPGA.

2. The multi-level diagnostic link status indication device for VHF data exchange systems according to claim 1, characterized in that, The temperature sensor is positioned between AD8317 logarithmic amplifier I and AD8317 logarithmic amplifier II.

3. The multi-level diagnostic link status indication device for VHF data exchange systems according to claim 1, characterized in that, The time division multiple access channel load monitoring circuit includes: a coupler, a radio frequency matching network unit, an LTC6406 differential analog-to-digital converter unit, and a fast Fourier transform unit; The input terminal of the coupler is connected to the output terminal of the base station transmitter power amplifier; the output terminal of the coupler is connected to the input terminal of the radio frequency matching network unit; the output terminal of the radio frequency matching network unit is connected to the input terminal of the LTC6406 differential analog-to-digital converter unit; and the output terminal of the LTC6406 differential analog-to-digital converter unit is connected to the input terminal of the fast Fourier transform unit.

4. The multi-level diagnostic link status indication device for VHF data switching systems according to claim 1, characterized in that, The cross-layer correlation diagnosis module includes: a physical layer parameter extraction unit, a protocol layer processing unit, and an LSTM fault decision engine unit; The output of the physical layer parameter extraction unit is connected to the input of the LSTM fault decision engine unit via an AXI bus; the output of the protocol layer processing unit is connected to the input of the LSTM fault decision engine unit via an AXI bus.

5. The multi-level diagnostic link status indication device for VHF data switching systems according to claim 1, characterized in that, The three-dimensional LED dot matrix includes: a WS2812B LED dot matrix and an STM32 driver controller; The output of the cross-layer correlation diagnostic module is connected to the input of the STM32 driver controller via a GPIO interface; the output of the STM32 driver controller is connected to the input of the WS2812B LED dot matrix; the intelligent visualization indicator module includes an NE555 timer and an auxiliary LED driver circuit; the output of the cross-layer correlation diagnostic module is connected to the input of the NE555 timer via a GPIO interface; the output of the cross-layer correlation diagnostic module is connected to the input of the auxiliary LED driver circuit via a GPIO interface.

6. The multi-level diagnostic link status indication device for VHF data exchange systems according to claim 1, characterized in that, The visible range extension structure includes: a housing (101), a light strip (102), a decorative panel (103), an LED (104), a nut (105), an LED cable (106), 3M double-sided tape (107), a crimp terminal (108), a male connector (109), a female connector (110), a PCB board (111), a screw (112), and a light trough (113).

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