Chip package structure

Abstract

The utility model discloses a chip packaging structure, chip packaging structure includes first encapsulation spare and second encapsulation spare, and first encapsulation spare includes first base plate and first chip, and second encapsulation spare includes second base plate, heat dissipation spare and second chip, and second base plate is stacked in the side of first chip away from first base plate, and second chip sets up in the side of second base plate away from first chip, and heat dissipation spare sets up in the side of first chip away from first base plate. The chip packaging structure provided by the utility model has the advantages of high heat dissipation efficiency of first chip, stable and reliable use performance.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, specifically to a chip packaging structure. Background Technology

[0002] Chip packaging structures typically employ Package on Package (POP) technology, which involves stacking another matching upper-layer package structure on top of a lower-level package structure to form the POP package structure. In this structure, two or more package units are stacked together from bottom to top, with a dielectric layer in between for signal transmission. POP technology increases the integration density of devices, and the lower-level package structure is in direct contact with the PCB board.

[0003] In this design, the lower packaging layer typically houses highly integrated logic chips, while the upper packaging layer houses large-capacity memory chips. However, with the development of AI technology, the scale and computing power of processing units such as CPUs, GPUs, and NPUs within logic chips are increasing, leading to a continuous increase in power consumption. In the POP packaging structure of related technologies, the logic chip is usually located vertically below the memory chip, completely covering it in the height direction. This results in high upward thermal resistance and poor heat dissipation performance, ultimately affecting the performance of the logic chip. Utility Model Content

[0004] This utility model aims to at least partially solve one of the technical problems in the related art.

[0005] Therefore, embodiments of this utility model propose a chip packaging structure. This chip packaging structure avoids a portion of the first chip on the first package by setting a second substrate on the second package and setting the aforementioned portion of the battery cell to be heat exchanged with the heat sink on the second package, thereby effectively reducing the upward thermal resistance of the first chip, resulting in high heat dissipation efficiency of the first chip, and thus making the performance of the first chip stable and reliable.

[0006] The chip packaging structure of this utility model embodiment includes a first packaging component and a second packaging component. The first packaging component includes a first substrate and a first chip. The second packaging component includes a second substrate, a heat sink, and a second chip. The second substrate is stacked on the side of the first chip away from the first substrate, and the second chip is disposed on the side of the second substrate away from the first chip. The heat sink is disposed on the side of the first chip away from the first substrate.

[0007] According to the chip packaging structure of this utility model embodiment, by placing the heat sink on the side of the first chip away from the first substrate, the heat generated by the portion of the first chip located directly below the heat sink is transferred to the heat sink for rapid heat exchange with the heat sink, resulting in higher heat dissipation efficiency of the first chip and stable and reliable performance of the first chip.

[0008] In some embodiments, on a projection plane perpendicular to the thickness direction of the first substrate, the projection of the second substrate and the projection of the heat sink are spaced apart.

[0009] In some embodiments, the first chip integrates a processing module, which includes at least one of a CPU, GPU, NPU, and DSP. On a projection plane perpendicular to the thickness direction of the first substrate, at least a portion of the projection of the processing module coincides with the projection of the heat sink.

[0010] In some embodiments, the first chip includes at least two cores spaced apart on the upper surface of the first substrate, and on a projection plane perpendicular to the thickness direction of the first substrate, at least a portion of the projection of at least one of the cores coincides with the projection of the heat sink.

[0011] In some embodiments, the number of the chips is at least two and includes a first chip and a second chip. The first chip integrates a processing module. On a projection plane perpendicular to the thickness direction of the first substrate, at least a portion of the projection of the first chip coincides with the projection of the heat sink, and the projection of the second chip coincides with the projection of the second chip.

[0012] In some embodiments, the second chip is electrically connected to the second substrate through a UBM layer.

[0013] In some embodiments, the second chip is electrically connected to the second substrate via bonding leads.

[0014] In some embodiments, the heat sink is bonded to the side of the first chip away from the first substrate by thermally conductive adhesive.

[0015] In some embodiments, the heat sink and the second substrate are arranged along a first direction, the length of the heat sink in a second direction is greater than the length of the second chip in the second direction, and the first direction, the second direction and the thickness direction of the first substrate are perpendicular to each other.

[0016] In some embodiments, the heat sink includes at least one of a heat sink, a heat sink block, and heat sink fins.

[0017] In some embodiments, the first package further includes a first molding layer, the first molding layer sealing the first chip, and the first chip being heat-exchangeably connected to the first substrate through the first molding layer;

[0018] The second package further includes a second molding layer that seals the second chip, and / or the second molding layer seals the heat sink. Attached Figure Description

[0019] Figure 1 This is a cross-sectional view of the chip packaging structure according to the first embodiment of the present invention.

[0020] Figure 2 This is another cross-sectional view of the chip packaging structure according to the first embodiment of the present invention.

[0021] Figure 3 This is a top view of the chip packaging structure according to the first embodiment of the present invention.

[0022] Figure 4 This is a cross-sectional view of the chip packaging structure according to the second embodiment of the present invention.

[0023] Figure 5 This is another cross-sectional view of the chip packaging structure according to the second embodiment of the present invention.

[0024] Figure 6 This is a cross-sectional view of the chip packaging structure according to the third embodiment of the present invention.

[0025] Figure 7 This is another cross-sectional view of the chip packaging structure according to the third embodiment of the present utility model.

[0026] Figure label:

[0027] 1. First package; 11. First substrate; 12. First chip; 121. First chip; 122. Second chip; 13. First molding compound; 2. Second package; 21. Second substrate; 22. Second chip; 23. Heat sink; 24. UBM layer; 25. Bonding wire; 26. Second molding compound; 27. Thermal adhesive layer; 3. Circuit board. Detailed Implementation

[0028] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0029] The following is combined with Figures 1-7 The chip packaging structure according to an embodiment of the present utility model is described.

[0030] The chip packaging structure of this utility model embodiment includes a first package 1 and a second package 2. The first package 1 includes a first substrate 11 and a first chip 12. The second package 2 includes a second substrate 21, a heat sink 23, and a second chip 22. The second substrate 21 is stacked on the side of the first chip 12 away from the first substrate 11. The second chip 22 is disposed on the side of the second substrate 21 away from the first chip 12. The heat sink 23 is disposed on the side of the first chip 12 away from the first substrate 11.

[0031] According to the chip packaging structure of this utility model embodiment, by placing the heat sink 23 on the side of the first chip 12 away from the first substrate 11, the heat generated by the portion of the first chip 12 located directly below the heat sink 23 is transferred to the heat sink 23 for rapid heat exchange with the heat sink 23, resulting in higher heat dissipation efficiency of the first chip 12 and stable and reliable performance of the first chip 12.

[0032] It should be noted that the first chip 12 is a logic chip, and the second chip 22 is a memory chip. The first substrate 11 and the second substrate 21 are redistribution layers. The first package 1 also includes a plurality of copper balls or copper pillars disposed at the edge of the upper surface of the first substrate 11. The first substrate 11 is electrically connected to the second substrate 21 through the plurality of copper balls or copper pillars. The diameter of the copper balls or the height of the copper pillars is greater than the thickness of the first chip 12. In this embodiment, the first substrate 11 of the chip package structure is electrically connected to the circuit board 3 by ball bonding. The surface of the first substrate 11 facing the circuit board 3 is provided with DTC capacitors.

[0033] In some embodiments, such as Figure 2 , Figure 5 and Figure 7 As shown, on the projection plane perpendicular to the thickness direction of the first substrate 11, the projection of the second substrate 21 and the projection of the heat sink 23 are separated, that is, the projection of the second substrate 21 and the projection of the heat sink 23 do not overlap.

[0034] By setting a second substrate 21 to avoid a portion of the first chip 12, and by using a heat sink 23 instead of the second substrate 21 to be disposed on the side of the first chip 12 away from the first substrate 11, the heat generated by the portion of the first chip 12 located directly below the heat sink 23 is directly transferred to the heat sink 23 for rapid heat exchange with the heat sink 23. As a result, the heat dissipation efficiency of the first chip 12 is higher, and the performance of the first chip 12 is stable and reliable.

[0035] In some embodiments, the first chip 12 integrates a processing module, which includes at least one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an NPU (Neural Processing Unit), and a DSP (Digital Signal Processor). On a projection surface perpendicular to the thickness direction of the first substrate 11, at least a portion of the projection of the processing module coincides with the projection of the heat sink 23.

[0036] By placing at least a portion of the high-power processing module directly below the heat sink 23, the processing module on the first chip 12 is positioned closer to the heat sink 23 than the other modules, thereby enabling faster heat exchange with the heat sink 23, resulting in higher heat dissipation efficiency for the processing module and more stable and reliable operation of the first chip 12.

[0037] For example, the first chip 12 also integrates an interface module, a power management module, etc., and the other modules, except for the processing module, are preferably located directly below the second chip 22.

[0038] In some embodiments, the first chip 12 includes at least two cores spaced apart on the upper surface of the first substrate 11, and on a projection plane perpendicular to the thickness direction of the first substrate 11, at least a portion of the projection of at least one core coincides with the projection of the heat sink 23.

[0039] By splitting the first chip 12 into at least two non-contact chips, the distribution area of ​​the first chip 12 is larger, and the heat dissipation efficiency of the functional modules on each chip is higher. At the same time, the functional modules on different chips are less likely to interfere with each other, making the performance of the first chip 12 more stable and reliable.

[0040] Taking the heat sink 23 and the second chip 22 arranged along the first direction as an example, all the chips are arranged at intervals along the second direction. The number of chips can be two, three, or four.

[0041] Alternatively, when there are multiple cores, the multiple cores can also be arranged in an array on the first substrate 11.

[0042] In some embodiments, the number of chips is at least two and includes a first chip 121 and a second chip 122. The first chip 121 integrates a processing module. On a projection plane perpendicular to the thickness direction of the first substrate 11, at least a portion of the projection of the first chip 121 coincides with the projection of the heat sink 23, and the projection of the second chip 122 coincides with the projection of the second chip 22.

[0043] By placing at least a portion of the first chip 121, which integrates the processing module, directly below the heat sink 23, the heat generated by the high-power processing module can be quickly dissipated from the heat sink 23 to the outside, effectively ensuring the performance of the processing module. Furthermore, the first chip 12 can be split into only the first chip 121 and the second chip 122, effectively reducing the assembly efficiency of the first chip 12 on the first substrate 11. Simultaneously, arranging the first chip 121 and the second chip 122 alternately effectively prevents the heat from the processing module on the first chip 121 from being transferred to the second chip 122, thus avoiding temperature increases in the functional modules on the second chip 122 that could affect their performance.

[0044] For example, such as Figure 6 and Figure 7 As shown, most of the first chip 121 is offset from the second chip 22 in the height direction and is located directly below the heat sink 23.

[0045] For example, the first core 121 is located directly below the heat sink 23.

[0046] In some embodiments, such as Figure 1 and Figure 2 As shown, the second chip 22 is electrically connected to the second substrate 21 through the UBM layer 24 (Under Bump Metallization), or, as... Figure 4 and Figure 5 As shown, the second chip 22 is electrically connected to the second substrate 21 via bonding leads 25.

[0047] That is, whether the second chip 22 is electrically connected to the second substrate 21 through the UBM layer 24 or through the bonding wire 25, a heat sink 23 can be provided on the side of the second chip 22 to improve the heat dissipation efficiency of the first chip 12, and the chip packaging structure has stronger applicability.

[0048] For example, the electrical connection between the second chip 22 and the second substrate 21 via the UBM layer 24 means that a metallization layer is first formed on the pads of the second chip 22, and then connected to the second substrate 21 via bumps such as solder balls. Specifically, the electrical connection between the second chip 22 and the second substrate 21 via bonding leads 25 means that the pads of the second chip 22 are connected to the pads of the second substrate 21 via metal wires (such as gold wires, aluminum wires, or copper wires), and the metal wires form an arc-shaped lead between the second chip 22 and the second substrate 21.

[0049] In some embodiments, such as Figure 2 , Figure 5 and Figure 7As shown, the heat sink 23 is bonded to the side of the first chip 12 away from the first substrate 11 using thermally conductive adhesive. This ensures that the heat sink 23 is easily and reliably fixed to the first chip 12, and the thermally conductive adhesive effectively improves the thermal conductivity between the heat sink 23 and the first chip 12, thereby making the heat dissipation efficiency of the first chip 12 higher.

[0050] In some embodiments, the heat sink 23 and the second substrate 21 are arranged along a first direction, the length of the heat sink 23 in the second direction is greater than the length of the second chip 22 in the second direction, and the first direction, the second direction and the thickness direction of the first substrate 11 are perpendicular to each other.

[0051] By setting the length of the heat sink 23 in the second direction to be greater than the length of the second chip 22 in the second direction, the heat dissipation area of ​​the heat sink 23 is effectively increased, thereby effectively improving the heat exchange efficiency between the heat sink 23 and the first chip 12. The heat dissipation efficiency of the first chip 12 is higher, and its performance is better.

[0052] For example, such as Figure 3 As shown, the heat sink 23 is generally a rectangular heat sink, and its length is equal to or close to the length of the second substrate 21 in the second direction. At the same time, the edge of the heat sink 23 away from the second chip 22 is adjacent to or coincides with the edge of the second substrate 21.

[0053] In some embodiments, the first package 1 further includes a first molding compound 13, which seals the first chip 12 and the first chip 12 is heat-exchange connected to the first substrate 11 through the first molding compound 13.

[0054] The first molding layer 13 increases the heat exchange area between the first chip 12 and the second substrate 21, thereby further improving the heat dissipation efficiency of the first chip 12. Secondly, the first molding layer 13 supports the second package 2, effectively preventing the first chip 12 from being subjected to excessive pressure from the second package 2, which would affect its service life.

[0055] For example, the overall outer contour of the first molding layer 13 and the first substrate 11 is a cube or cuboid shape.

[0056] Optionally, the second package 2 further includes a second molding compound 26, which seals the second chip 22, and / or seals the heat sink 23.

[0057] That is, the second molding compound 26 can only wrap and seal the second chip 22 to ensure the service life of the second chip 22, or it can wrap the heat sink 23 at the same time, so that the second chip 22 is connected to the heat sink 23 through the second molding compound 26 for heat exchange, thereby further improving the heat dissipation efficiency of the second chip 22 and thus further improving the performance of the second chip 22.

[0058] In some embodiments, the heat sink 23 includes at least one of a heat sink, a heat sink block, and heat sink fins.

[0059] When the heat sink 23 is a heat sink fin, it is easier for the heat sink 23 to be attached to the upper surface of the second substrate 21. When the heat sink 23 is a heat sink block, it has a larger volume and surface area, which makes it have a greater heat absorption efficiency and heat dissipation efficiency. When the heat sink 23 is a heat sink fin, it can have a greater heat dissipation efficiency with a fixed volume, thereby further improving the heat dissipation efficiency of the first chip 12.

[0060] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0061] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0062] In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0063] In this utility model, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0064] In this utility model, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this utility model. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0065] Although the above embodiments have been shown and described, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Any changes, modifications, substitutions and variations made to the above embodiments by those skilled in the art are within the protection scope of the present invention.

Claims

1. A chip packaging structure, characterized in that, include: A first package (1) includes a first substrate (11) and a first chip (12); The second package (2) includes a second substrate (21), a heat sink (23), and a second chip (22). The second substrate (21) is stacked on the side of the first chip (12) away from the first substrate (11). The second chip (22) is disposed on the side of the second substrate (21) away from the first chip (12). The heat sink (23) is disposed on the side of the first chip (12) away from the first substrate (11).

2. The chip packaging structure according to claim 1, characterized in that, On the projection plane perpendicular to the thickness direction of the first substrate (11), the projection of the second substrate (21) and the projection of the heat sink (23) are spaced apart.

3. The chip packaging structure according to claim 1, characterized in that, The first chip (12) integrates a processing module, which includes at least one of a CPU, GPU, NPU and DSP. On a projection surface perpendicular to the thickness direction of the first substrate (11), at least a portion of the projection of the processing module coincides with the projection of the heat sink (23).

4. The chip packaging structure according to claim 1, characterized in that, The first chip (12) includes at least two cores spaced apart on the upper surface of the first substrate (11), and on a projection plane perpendicular to the thickness direction of the first substrate (11), at least a portion of the projection of at least one of the cores coincides with the projection of the heat sink (23).

5. The chip packaging structure according to claim 4, characterized in that, The number of the cores is at least two and includes a first core (121) and a second core (122). The first core (121) integrates a processing module. On the projection surface perpendicular to the thickness direction of the first substrate (11), at least a portion of the projection of the first core (121) coincides with the projection of the heat sink (23), and the projection of the second core (122) coincides with the projection of the second chip (22).

6. The chip packaging structure according to claim 1, characterized in that, The second chip (22) is electrically connected to the second substrate (21) through the UBM layer (24).

7. The chip packaging structure according to claim 1, characterized in that, The second chip (22) is electrically connected to the second substrate (21) via bonding leads (25).

8. The chip packaging structure according to claim 1, characterized in that, The heat sink (23) is bonded to the side of the first chip (12) away from the first substrate (11) by thermally conductive adhesive.

9. The chip packaging structure according to any one of claims 1-8, characterized in that, The heat sink (23) and the second substrate (21) are arranged along a first direction. The length of the heat sink (23) in the second direction is greater than the length of the second chip (22) in the second direction. The first direction, the second direction and the thickness direction of the first substrate (11) are perpendicular to each other.

10. The chip packaging structure according to claim 1, characterized in that, The heat sink (23) includes at least one of a heat sink, a heat sink block, and a heat sink fin.

11. The chip packaging structure according to claim 1, characterized in that, The first package (1) further includes a first molding compound (13), which seals the first chip (12) and the first chip (12) is heat-exchange connected to the first substrate (11) through the first molding compound (13); The second package (2) further includes a second molding compound (26) that seals the second chip (22) and / or the second molding compound (26) that seals the heat sink (23).

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