LVDS circuit, signal transmission system and chip

Abstract

This invention discloses an LVDS circuit, a signal transmission system, and a chip, relating to the field of integrated circuits. The LVDS circuit includes a first current component and a second current component, and an LVDS output circuit connected in series between the first and second current components. The LVDS output circuit is used to generate a target differential signal based on the first and second current components and in response to a single-ended signal. The LVDS output circuit of this invention can directly generate the target differential signal based on the first and second current components and in response to a single-ended signal, without requiring logic conversion through an inverter or transmission gate. This avoids excessive power consumption and delay mismatch issues with inverters and transmission gates, and eliminates overshoot and ringing phenomena.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuits, and in particular to an LVDS circuit, a signal transmission system, and a chip. Background Technology

[0002] Low Voltage Differential Signaling (LVDS) technology is widely used in display interfaces, high-speed data communication, and other fields due to its low power consumption, high noise immunity, and high-speed transmission characteristics. A traditional LVDS circuit typically consists of two parts: a single-ended to differential converter and an LVDS output circuit. The single-ended to differential converter converts the single-ended input signal into a complementary differential signal, while the LVDS output circuit, controlled by the differential signal, outputs the target differential signal. Currently, single-ended to differential converters are often implemented using inverters, transmission gates, and latched inverters. This not only increases power consumption but also, because the delay matching requirements for the inverter and transmission gate are extremely high, any delay deviation can lead to overshoot or ringing in the output signal, affecting signal integrity.

[0003] Therefore, how to provide a solution to the above-mentioned technical problems is a problem that needs to be solved by those skilled in the art. Utility Model Content

[0004] The purpose of this invention is to provide an LVDS circuit, signal transmission system, and chip that can directly drive a switching module to switch the current direction through a single-ended signal, without the need for logic conversion through an inverter or transmission gate. This avoids excessive power consumption and delay mismatch between the inverter and transmission gate, and eliminates overshoot, ringing, and other phenomena.

[0005] To solve the above-mentioned technical problems, this utility model provides an LVDS circuit, including a first current component, a second current component, and an LVDS output circuit connected in series between the first current component and the second current component;

[0006] The LVDS output circuit is used to generate a target differential signal based on the first current component and the second current component and in response to a single-ended signal.

[0007] Optionally, the LVDS output circuit includes a load and at least two sets of switching pairs, which are used to turn on or off according to the single-ended signal to generate the target differential signal on the load.

[0008] Optionally, the LVDS output circuit includes two sets of switch pairs. The control terminals of both sets of switch pairs receive the single-ended signal and control the switching transistors in the two sets of switch pairs to turn on or off according to the single-ended signal to generate the target differential signal on the load.

[0009] Optionally, the two sets of switch pairs include a first switch pair and a second switch pair, wherein both the first switch pair and the second switch pair include two switch transistors with opposite conduction characteristics under the same single-ended signal.

[0010] Optionally, the first switch pair includes a first switch and a second switch, the second switch pair includes a third switch and a fourth switch, the first switch and the third switch are both connected to the first current component, the second switch and the fourth switch are both connected to the second current component, and the first switch and the fourth switch have the same conduction characteristics.

[0011] When the single-ended signal is at the first level, both the first and fourth switches are turned on to generate a first current. When the single-ended signal is at the second level, both the second and third switches are turned on to generate a second current in the opposite direction to the first current. The target differential signal is generated on the load based on the first and second currents, with the first and second levels being in opposite states.

[0012] Optionally, the first and fourth switching transistors are both NMOS transistors, and the second and third switching transistors are both PMOS transistors.

[0013] Optionally, both the first current component and the second current component include a current source.

[0014] Optionally, one end of the first current component is connected to a third level, and the other end of the first current component is connected to the first input terminal of the LVDS output circuit.

[0015] One end of the second current component is connected to the second input terminal of the LVDS output circuit, and the other end of the second current component is connected to a fourth level, wherein the third level is higher than the fourth level.

[0016] To solve the above-mentioned technical problems, this utility model also provides a signal transmission system, including an LVDS circuit as described in any of the above claims, wherein the LVDS circuit is used to generate a target differential signal based on a single-ended signal and transmit it.

[0017] To solve the above-mentioned technical problems, this utility model also provides a chip, including the LVDS circuit as described in any one of the above descriptions.

[0018] This invention provides an LVDS circuit, wherein the LVDS output circuit can directly generate the target differential signal based on the first current component, the second current component, and the single-ended signal response, without the need for logic conversion via an inverter or transmission gate. This avoids excessive power consumption and delay mismatch issues with inverters and transmission gates, and eliminates overshoot and ringing. This invention also provides a signal transmission system and chip, which have the same beneficial effects as the LVDS circuit described above. Attached Figure Description

[0019] To more clearly illustrate the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of the structure of the first LVDS circuit provided by this utility model;

[0021] Figure 2 A schematic diagram of the structure of the second LVDS circuit provided by this utility model;

[0022] Figure 3 A schematic diagram of the third type of LVDS circuit provided by this utility model;

[0023] Figure 4 This is a schematic diagram of the first type of current transmission provided by this utility model;

[0024] Figure 5 This is a schematic diagram of the second type of current transmission provided by this utility model. Detailed Implementation

[0025] The core of this invention is to provide an LVDS circuit, a signal transmission system, and a chip. It can directly drive the switching module to switch the current direction through a single-ended signal, without the need for logic conversion through an inverter or transmission gate. This avoids the delay mismatch problem of inverters and transmission gates and eliminates phenomena such as overshoot and ringing.

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0027] Firstly, please refer to Figure 1 The present invention provides an LVDS circuit, including a first current component 1, a second current component 2, and an LVDS output circuit 3 connected in series between the first current component 1 and the second current component 2.

[0028] The LVDS output circuit 3 is used to generate a target differential signal based on the first current component 1 and the second current component 2 and in response to a single-ended signal.

[0029] In this embodiment, the LVDS circuit mainly includes a first current component 1, a second current component 2, and an LVDS output circuit 3. The LVDS output circuit 3 is connected in series between the first current component 1 and the second current component 2. Both the first current component 1 and the second current component 2 are used to provide bias current to the LVDS output circuit 3. The LVDS output circuit 3 includes an input terminal and two differential output terminals for outputting the target differential signal. Figure 1 The circuit includes a first output terminal A and a second output terminal B. The input terminal receives a single-ended signal, which can be a voltage signal relative to ground or a reference point. For example, when the signal is high, it might be a logic high voltage (such as 3.3V or 1.8V), and when it is low, it might be close to ground (0V). Both the first current component 1 and the second current component 2 are used to output corresponding currents. The LVDS output circuit 3 responds to the single-ended signal, generates a target differential signal based on the current output by the first current component 1 and / or the second current component 2, and outputs it through the first output terminal A and the second output terminal B.

[0030] It is understood that the LVDS output circuit 3 in this embodiment is directly controlled by the single-ended signal, without the need for logic conversion through an inverter or transmission gate. This avoids the delay mismatch problem between the inverter and the transmission gate, and eliminates phenomena such as overshoot and ringing. In addition, coupling the single-ended signal to the output stage reduces intermediate links in the signal path, reduces the risk of signal distortion, improves anti-interference capability, reduces power consumption, and reduces chip footprint, making it suitable for high-density integrated circuit design.

[0031] Please refer to Figure 2 The LVDS circuit is based on the above embodiment:

[0032] In one exemplary embodiment, the LVDS output circuit 3 includes a load 31 and at least two sets of switch pairs 32, which are used to turn on or off according to a single-ended signal to generate the target differential signal on the load 31.

[0033] It is understood that the first ends of at least two sets of switch pairs 32 are interconnected and connected to the first current component 1, and the second ends of at least two sets of switch pairs 32 are interconnected and connected to the second current component 2. The control terminals of both sets of switch pairs 32 are connected to single-ended signals so as to execute corresponding switching actions according to the level state of the connected single-ended signals. Different level states of the single-ended signals can control the switch pairs 32 to execute different switching actions, thereby adjusting the current transmission direction between the first output terminal A and the second output terminal B. For example, under the control of the first single-ended signal (high level state), the current generated by the first current component 1 and / or the second current component 2 flows from the first output terminal A to the second output terminal B through the at least two sets of switch pairs 32. Under the control of the second single-ended signal (low level state), the current generated by the first current component 1 and / or the second current component 2 flows from the second output terminal B to the first output terminal A through the at least two sets of switch pairs 32. That is, at least two sets of switch pairs 32 are used to turn on or off according to the single-ended signals to adjust the direction of the current generated on the load 31 in order to generate the target differential signal. In this embodiment, setting at least two (or even three or more) sets of switch pairs 32 to work in parallel can reduce the total on-resistance, improve the output current driving capability, improve signal integrity and enhance system robustness.

[0034] It is understood that in this embodiment, a load 31 is connected in series between the first output terminal A and the second output terminal B. As an optional embodiment, the load 31 can be a resistor, an inductor, or a combination thereof. The level state of the single-ended signal controls at least two switching pairs 32 to switch the current transmission direction, causing the current flowing through the load 31 to reverse. The different current directions result in opposite voltage polarities across the load 31, thereby forming a voltage difference between the first output terminal A and the second output terminal B, i.e., the target differential signal.

[0035] For example, assuming load 31 includes a resistor, when the single-ended signal is high, if at least two switching pairs 32, under the control of the high-level single-ended signal, cause the current to flow from the first output terminal A to the second output terminal B, the voltage drop across load 31 is V. AB =I×R, the voltage at the first output terminal A is higher than the voltage at the second output terminal B. When the single-ended signal is low, if at least two switching pairs 32, under the control of the high-level single-ended signal, cause the current to flow from the second output terminal B to the first output terminal A, then the voltage drop across the load 31 is V. AB =-I×R, the voltage of the first output terminal A is lower than the voltage of the second output terminal B. In this way, the high and low levels of the single-ended signal control the switching of the current direction, thereby generating the target differential signal on the load 31.

[0036] In one exemplary embodiment, the resistor is an adjustable resistor, or the inductor is a variable inductor.

[0037] In this embodiment, the resistor can be an adjustable resistor, which allows for dynamic adjustment of the impedance value during circuit operation, thereby changing the voltage swing across the load 31. By adjusting the resistor value, the amplitude of the output differential signal can be controlled to adapt to different load 31 requirements. Under different operating conditions (such as different loads 31 or signal frequencies), the circuit performance can be optimized by adjusting the resistor value, ensuring signal stability and integrity. The inductor can be a variable inductor, which can adjust the frequency response of the circuit by changing its inductance value. Changes in the inductance value affect the resonant frequency and bandwidth of the circuit, thereby optimizing the frequency characteristics of subsequent signal transmission. Furthermore, the filtering characteristics of the inductor can remove noise at specific frequencies, improving signal purity. Therefore, by adjusting the inductance value, suppression of noise at different frequencies can be achieved during signal generation and subsequent signal transmission.

[0038] In this embodiment, the switching states of at least two switch pairs 32 are directly controlled by a single-ended signal, switching the direction of current transmission on the load 31, thereby generating target differential signals with equal amplitude and opposite polarity. This eliminates the need for inverters, transmission gates, or other logic circuits to generate complementary signals to drive the differential pairs, solving the signal integrity problem caused by delay mismatch. The signal passes only through at least two switch pairs 32 and the load 31, reducing intermediate steps and improving signal integrity. Simultaneously, it achieves the technical effects of low power consumption, small area, and high reliability.

[0039] In an exemplary embodiment, the LVDS output circuit 3 includes two sets of switch pairs 32. The control terminals of both sets of switch pairs 32 receive single-ended signals and control the switching transistors in the two sets of switch pairs 32 to turn on or off according to the single-ended signals in order to generate a target differential signal on the load 31.

[0040] In this embodiment, each pair of switch tubes 32 includes two switch tubes. The control terminal of each switch tube is connected to the same single-ended signal. Under the control of the single-ended signal, the switch tube is turned on or off, thereby realizing the switching of the current direction so as to generate the target differential signal on the load 31.

[0041] In an exemplary embodiment, the two sets of switch pairs 32 include a first switch pair and a second switch pair, each of which includes two switch transistors with opposite conduction characteristics under the same single-ended signal.

[0042] In this embodiment, the two switches in each switch pair 32 are complementaryly turned on under the control of the same single-ended signal. That is, under the control of the same single-ended signal, one switch is turned on and the other switch is turned off. Taking a pair of switching transistors 32 as an example, a pair of switching transistors 32 may specifically include an NMOS (N-channel Metal-Oxide-Semiconductor) transistor and a PMOS (P-channel Metal-Oxide-Semiconductor) transistor. Under the control of a high-level single-ended signal, the NMOS transistor is turned on and the PMOS transistor is turned off; under the control of a low-level single-ended signal, the NMOS transistor is turned off and the PMOS transistor is turned on. Alternatively, a pair of switching transistors 32 may include an NPN (NPN Bipolar Junction Transistor) transistor and a PNP (PNP Bipolar Junction Transistor) transistor. Under the control of a high-level single-ended signal, the NPN transistor is turned on and the PNP transistor is turned off; under the control of a low-level single-ended signal, the NPN transistor is turned off and the PNP transistor is turned on.

[0043] Of course, in another exemplary embodiment, each switch pair 32 may also include four switch transistors, which may be divided into two groups of complementary conducting switch transistors to control the forward and reverse transmission of current respectively.

[0044] In an exemplary embodiment, the first switch pair includes a first switch and a second switch, the second switch pair includes a third switch and a fourth switch, the first switch and the third switch are both connected to the first current component 1, the second switch and the fourth switch are both connected to the second current component 2, and the first switch and the fourth switch have the same conduction characteristics.

[0045] When the single-ended signal is at the first level, both the first and fourth switches are turned on to generate the first current. When the single-ended signal is at the second level, both the second and third switches are turned on to generate the second current in the opposite direction to the first current. The target differential signal is generated on the load 31 based on the first and second currents, and the first and second levels are in opposite states.

[0046] In this embodiment, the common terminal of the first and third switching transistors is connected to the first current component 1, and the common terminal of the second and fourth switching transistors is connected to the second current component 2. It can be understood that in order to achieve the switching of the current transmission path, the first and fourth switching transistors in this embodiment have the same conduction characteristics, and the second and third switching transistors have the same conduction characteristics. That is, under the control of the same single-ended signal, they perform the same switching action.

[0047] In this embodiment, when the level of the single-ended signal changes from a first level to a second level, or from a second level to a first level, the complementary conducting switch pair 32 switches the direction of current transmission. For example, under the control of the single-ended signal at the first level, the first and fourth switches are turned on, while the second and third switches are turned off, causing the first current generated by the first current component 1 and / or the second current component 2 to flow through the load 31. Under the control of the single-ended signal at the second level, the first and fourth switches are turned off, while the second and third switches are turned on, causing the second current generated by the first current component 1 and / or the second current component 2, which is opposite in direction to the first current, to flow through the load 31, thereby generating the target differential signal on the load 31. For example, it can be assumed that the first level is high and the second level is low, or it can be assumed that the first level is low and the second level is high.

[0048] For example, under the first single-ended signal (high level state), the first and fourth switches are turned on, and the second and third switches are turned off. At this time, the current transmission direction is: first current component 1 → first switch → first output terminal A → load 31 → second output terminal B → fourth switch → second current component 2 → ground. Under the second single-ended signal (low level state), the first and fourth switches are turned off, and the second and third switches are turned on. At this time, the current transmission direction is: first current component 1 → third switch → second output terminal B → load 31 → first output terminal A → second switch → second current component 2 → ground. Under the control of different single-ended signal levels, the voltage polarity across the load 31 is reversed, thereby forming a voltage difference between the two output terminals, i.e., forming the target differential signal.

[0049] As an optional embodiment, the first and fourth switching transistors are both NMOS transistors, and the second and third switching transistors are both PMOS transistors.

[0050] Under high-level control, the NMOS transistor is turned on and the PMOS transistor is turned off, and the current flows from the first output terminal A to the second output terminal B. The voltage across the load 31 is positive. Under low-level control, the NMOS transistor is turned off and the PMOS transistor is turned on, and the voltage across the impedance element is negative. The polarity of the voltage across the impedance element is reversed, thus forming a voltage difference between the two output terminals, which forms the target differential signal.

[0051] Correspondingly, such as Figure 3 As shown, the first switching pair includes a first NMOS transistor N1 and a first PMOS transistor P1, and the second switching pair includes a second NMOS transistor N2 and a second PMOS transistor P2. The drain of the first NMOS transistor N1 is connected to the source of the second PMOS transistor P2, the source of the first NMOS transistor N1 is connected to the source of the first PMOS transistor P1, the drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2, and the drain of the first PMOS transistor P1 is connected to the source of the second NMOS transistor N2. The gates of the first NMOS transistor N1, the second NMOS transistor N2, the first PMOS transistor P1, and the second PMOS transistor P2 are all connected to the same single-ended signal.

[0052] In this embodiment, the gates of all switching transistors are connected to a single-ended signal to ensure synchronous control. The source of the NMOS transistor is grounded, and the source of the PMOS transistor is connected to the power supply, forming a symmetrical pull-up and pull-down structure. The input signal directly controls the gate, ensuring that the current path is completely symmetrical when switching between high and low levels, avoiding signal offset, and thus improving signal stability and consistency. The complementary conduction characteristics of the NMOS and PMOS transistors ensure that the current direction can be switched quickly under the direct control of the single-ended signal, thereby achieving efficient single-ended to differential signal conversion.

[0053] In this embodiment, there is no specific limitation on the number of complementary conducting switch pairs 32 and the number of switching transistors in each switch pair 32. In addition to the MOS transistors and bipolar transistors mentioned above, the switching transistors can also be gallium nitride (GaN) transistors, silicon carbide (SiC) transistors, or tunneling field-effect transistors (TFETs), etc., which can be selected according to the actual engineering needs.

[0054] Reference Figure 4 As shown, when the input single-ended signal IN is high, the first NMOS transistor N1 and the second NMOS transistor N2 are turned on, while the first PMOS transistor P1 and the second PMOS transistor P2 are turned off. Current will flow from point A through load 31 to point B. (Refer to...) Figure 5 As shown, when the input single-ended signal IN is low, the first NMOS transistor N1 and the second NMOS transistor N2 are turned off, and the first PMOS transistor P1 and the second PMOS transistor P2 are turned on. The current will flow from point B through the load 31 to point A, thereby realizing the low-voltage differential signal output.

[0055] As an optional embodiment, one end of the first current component 1 is connected to the third level, and the other end of the first current component 1 is connected to the first input terminal of the LVDS output circuit 3;

[0056] One end of the second current component 2 is connected to the second input terminal of the LVDS output circuit 3, and the other end of the second current component 2 is connected to the fourth level, with the third level being higher than the fourth level.

[0057] In this embodiment, the first current component 1 is directly connected to the third level (high potential), and the second current component 2 is directly connected to the fourth level (low potential), forming a clear current gradient difference. This asymmetric structure allows the current to flow along a unidirectional path, avoiding the uncertainty of the current direction that may occur in the traditional symmetric structure.

[0058] As an optional embodiment, both the first current component 1 and the second current component 2 are current sources, ensuring that sufficient current flows through the load 31 when the LVDS output circuit 3 is working (i.e., when the switching transistor in the switching pair 32 is turned on), thereby generating a stable voltage drop across the load 31, further improving signal transmission quality and enhancing the circuit's anti-interference capability. The current source can be a mirror current source or similar structure to ensure current stability. Considering dynamic adjustment, a programmable current source can also be selected, depending on the actual engineering needs; this embodiment does not impose specific limitations.

[0059] In one exemplary embodiment, it further includes:

[0060] The temperature compensation module is configured to adjust the parameters of load 31 in response to the ambient temperature value.

[0061] In this embodiment, the LVDS circuit may further include a temperature compensation module. This module monitors changes in ambient temperature in real time and automatically adjusts the parameters of the load 31 (such as the resistance value of the adjustable resistor or the inductance value of the adjustable inductor) based on the monitored temperature changes to counteract the impact of temperature on circuit performance. Furthermore, it can also adjust the output current of the current source based on the monitored temperature changes to ensure the stability and consistency of the circuit under different temperatures. In this embodiment, the temperature compensation module compensates for the impact of temperature changes on the load 31 and the current source, ensuring the stability and consistency of the circuit over a wide temperature range.

[0062] In one exemplary embodiment, it further includes:

[0063] The filter module is connected to both ends of the load 31 and is configured to filter out noise from the output differential signal.

[0064] In this embodiment, the filtering module is connected across the load 31 to filter out noise in the differential signal. The filtering module can be an RC filtering module or an operational amplifier filtering circuit. By shaping the output signal through the filtering module, high-frequency glitches and low-frequency drift can be removed, improving signal quality and ensuring the integrity and reliability of the output signal.

[0065] In summary, this invention implements an LVDS circuit with single-ended signal input, avoiding the single-ended to differential circuit required in related technologies, while achieving the functional requirements of a traditional LVDS driver. It features a simple and easy-to-implement structure, reduced power consumption, smaller chip area, and low cost.

[0066] Secondly, this invention also provides a signal transmission system, including an LVDS circuit as described in any of the embodiments above, wherein the LVDS circuit is used to generate a target differential signal based on a single-ended signal and transmit it. Thirdly, this invention also provides a chip, including an LVDS circuit as described in any of the embodiments above.

[0067] For a description of the signal transmission system and chip provided by this utility model, please refer to the above embodiments; this utility model will not be described again here.

[0068] The signal transmission system and chip provided by this utility model have the same beneficial effects as the LVDS circuit described above.

[0069] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0070] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LVDS circuit, comprising a first current component and a second current component, characterized in that, Includes an LVDS output circuit connected in series between the first current component and the second current component; The LVDS output circuit is used to generate a target differential signal based on the first current component and the second current component and in response to a single-ended signal.

2. The LVDS circuit according to claim 1, characterized in that, The LVDS output circuit includes a load and at least two sets of switching pairs, which are used to turn on or off according to the single-ended signal to generate the target differential signal on the load.

3. The LVDS circuit according to claim 2, characterized in that, The LVDS output circuit includes two sets of switch pairs. The control terminals of both sets of switch pairs receive the single-ended signal and control the switching transistors in the two sets of switch pairs to turn on or off according to the single-ended signal to generate the target differential signal on the load.

4. The LVDS circuit according to claim 3, characterized in that, The two sets of switch pairs include a first switch pair and a second switch pair, and both the first switch pair and the second switch pair include two switch transistors with opposite conduction characteristics under the same single-ended signal.

5. The LVDS circuit according to claim 4, characterized in that, The first switch pair includes a first switch and a second switch, the second switch pair includes a third switch and a fourth switch, the first switch and the third switch are both connected to the first current component, the second switch and the fourth switch are both connected to the second current component, and the first switch and the fourth switch have the same conduction characteristics. When the single-ended signal is at the first level, both the first and fourth switches are turned on to generate a first current. When the single-ended signal is at the second level, both the second and third switches are turned on to generate a second current in the opposite direction to the first current. The target differential signal is generated on the load based on the first and second currents, with the first and second levels being in opposite states.

6. The LVDS circuit according to claim 5, characterized in that, The first and fourth switching transistors are both NMOS transistors, while the second and third switching transistors are both PMOS transistors.

7. The LVDS circuit according to claim 2, characterized in that, Both the first current component and the second current component include a current source.

8. The LVDS circuit according to claim 1, characterized in that, One end of the first current component is connected to the third level, and the other end of the first current component is connected to the first input terminal of the LVDS output circuit. One end of the second current component is connected to the second input terminal of the LVDS output circuit, and the other end of the second current component is connected to a fourth level, wherein the third level is higher than the fourth level.

9. A signal transmission system, characterized in that, Includes the LVDS circuit as described in any one of claims 1-8, the LVDS circuit being used to generate and transmit a target differential signal based on a single-ended signal.

10. A chip, characterized in that, Includes the LVDS circuit as described in any one of claims 1-8.

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