A power semiconductor device

Abstract

The application discloses a power semiconductor device, comprising: a first semiconductor body for forming a depletion mode transistor; a second semiconductor body located on a first surface of the first semiconductor body for forming a first enhancement mode transistor and connected in series with the depletion mode transistor; a third semiconductor body located on the first surface of the first semiconductor body for forming a second enhancement mode transistor and electrically connected between a gate of the depletion mode transistor and a first electrode; a layer of resistive material located on the first surface of the first semiconductor body and electrically connected between the gate of the depletion mode transistor and the first electrode; the first electrode is electrically connected with the second semiconductor body, the third semiconductor body and the layer of resistive material; and a second electrode located on a second surface of the first semiconductor body. The technical scheme provided by the application ensures that the device has a faster opening speed while reducing the turn-off speed of the device, thereby reducing dv / dt and improving the electromagnetic interference problem.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power semiconductor device. Background Technology

[0002] Silicon carbide (SiC) power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are widely used in power electronics. Compared to bipolar devices such as IGBTs (Insulated Gate Bipolar Transistors), SiC power MOSFETs have lower switching losses, thus exhibiting significant advantages in high-frequency applications.

[0003] However, silicon carbide power MOSFETs still face several technical challenges. First, their high channel interface state density leads to low effective channel mobility, which in turn increases the specific on-resistance of the device and causes heat concentration on the chip surface. Second, the potential barrier between silicon carbide and silicon dioxide is relatively steep, and silicon dioxide contains many traps, resulting in a large interface tunneling current, which affects the long-term reliability of the device. In addition, silicon carbide MOSFETs typically require high drive voltages and extremely fast switching speeds, making them unable to directly replace existing silicon-based devices.

[0004] To overcome the aforementioned problems, the industry often employs a cascode structure, cascading a silicon carbide JFET (Junction Field-Effect Transistor) with a low-voltage silicon-based MOSFET. In this structure, the high critical breakdown electric field strength and high thermal conductivity of silicon carbide material are utilized, allowing the silicon carbide JFET to withstand high voltage and improve heat dissipation. Simultaneously, the high channel mobility and low Si / SiO2 interface tunneling current of the silicon-based MOSFET are leveraged to control the switching action, thereby reducing the overall on-resistance and improving gate oxide reliability.

[0005] However, this cascode structure is prone to high electromagnetic interference (EMI), mainly due to the high voltage change rate (dv / dt) of the silicon carbide JFET during turn-off. To suppress dv / dt, an external resistor is typically connected to the gate, and a trade-off between dv / dt and switching losses is achieved by selecting an appropriate resistance value. However, the turn-off dv / dt of a silicon carbide JFET is not sensitive to changes in the external resistance, often requiring a large resistance value to reduce it to an acceptable range, which in turn leads to a sharp increase in device turn-on losses. Therefore, how to effectively reduce the device's turn-off speed while maintaining a fast turn-on speed, thereby suppressing dv / dt and improving EMI, has become a pressing technical problem to be solved. Summary of the Invention

[0006] This invention provides a power semiconductor device that ensures a fast turn-on speed while reducing the turn-off speed, thereby reducing dv / dt and improving electromagnetic interference.

[0007] This invention provides a power semiconductor device, comprising:

[0008] A first semiconductor body includes a first surface and a second surface disposed opposite to each other; the first semiconductor body is used to form a depletion-type transistor.

[0009] A second semiconductor body is located on a first surface of the first semiconductor body; the second semiconductor body is used to form a first enhancement-mode transistor; wherein the material of the first semiconductor body is different from the material of the second semiconductor body, and the depletion-mode transistor formed by the first semiconductor body is connected in series with the first enhancement-mode transistor formed by the second semiconductor body.

[0010] A third semiconductor body is located on a first surface of the first semiconductor body; the third semiconductor body is used to form a second enhancement-mode transistor; wherein the second enhancement-mode transistor formed by the third semiconductor body is electrically connected between the gate of the depletion-mode transistor and the first electrode;

[0011] A resistive material layer is located on the first surface of the first semiconductor body; the gate resistor formed by the resistive material layer is electrically connected between the gate of the depletion-type transistor and the first electrode, and is connected in parallel with the second enhancement transistor;

[0012] The first electrode is located on the side of the second semiconductor body, the third semiconductor body, and the resistive material layer away from the first semiconductor body, and is electrically connected to the second semiconductor body, the third semiconductor body, and the resistive material layer;

[0013] The second electrode is located on the second surface.

[0014] Optionally, the power semiconductor device further includes:

[0015] A first gate structure is located on the side of the second semiconductor body away from the first semiconductor body, and the first gate structure is used to control the conduction state of the first enhancement transistor.

[0016] The second gate structure is located on the side of the third semiconductor body away from the first semiconductor body, and the second gate structure is used to control the conduction state of the second enhancement transistor.

[0017] The first gate structure and the second gate structure are used to receive the same gate control signal.

[0018] Optionally, the first semiconductor body includes a first ohmic contact region and a second ohmic contact region with different conductivity types, both located on the first surface, and the first ohmic contact region and the second ohmic contact region are spaced apart; the second ohmic contact region is used as the gate of the depletion-type transistor.

[0019] The first semiconductor body further includes a buried layer located on the side of the first ohmic contact region and the second ohmic contact region near the second surface;

[0020] The buried layer has the same conductivity type as the second ohmic contact region; the depletion-type transistor formed by the first semiconductor body is a depletion-type junction field-effect transistor.

[0021] Optionally, the orthographic projection of the first ohmic contact area on the second surface is located in the orthographic projection of the buried layer on the second surface, and the first ohmic contact area extends from the boundary of the first surface to the second ohmic contact area.

[0022] The partial orthographic projection of the second ohmic contact area on the second surface overlaps with the partial orthographic projection of the buried layer on the second surface.

[0023] Optionally, the second semiconductor body includes a third ohmic contact region and a fourth ohmic contact region, which are spaced apart on the surface of the second semiconductor body away from the first semiconductor body; the conductivity type of the third ohmic contact region and the fourth ohmic contact region are different from the conductivity type of the second semiconductor body; the first enhancement-mode transistor formed by the second semiconductor body is a metal-oxide-semiconductor field-effect transistor.

[0024] The power semiconductor device further includes a first conductive structure located on the side of the second semiconductor body away from the third semiconductor body; the first conductive structure is used to electrically connect a first ohmic contact region in the first semiconductor body and a third ohmic contact region in the second semiconductor body.

[0025] The first electrode is electrically connected to the fourth ohmic contact region in the second semiconductor body.

[0026] Optionally, the third semiconductor body includes a fifth ohmic contact region and a sixth ohmic contact region, which are spaced apart on the surface of the third semiconductor body away from the first semiconductor body; the conductivity type of the fifth ohmic contact region and the sixth ohmic contact region are different from the conductivity type of the third semiconductor body; the second enhancement-mode transistor formed by the third semiconductor body is a metal-oxide-semiconductor field-effect transistor.

[0027] The power semiconductor device further includes a second conductive structure located on the side of the third semiconductor body away from the second semiconductor body; the second conductive structure is used to electrically connect a second ohmic contact region in the first semiconductor body and a fifth ohmic contact region in the third semiconductor body.

[0028] The first electrode is electrically connected to the sixth ohmic contact region in the third semiconductor body.

[0029] Optionally, the power semiconductor device further includes an ohmic contact layer located at at least one of the following:

[0030] Between the first conductive structure and the first ohmic contact area;

[0031] Between the first conductive structure and the third ohmic contact region;

[0032] Between the second conductive structure and the second ohmic contact area;

[0033] Between the second conductive structure and the fifth ohmic contact region;

[0034] Between the first electrode and the fourth ohmic contact area;

[0035] Between the first electrode and the sixth ohmic contact area;

[0036] Between the resistive material layer and the second ohmic contact area.

[0037] Optionally, the resistive material layer is located between the first semiconductor body and the second semiconductor body; the power semiconductor device further includes a sidewall insulating layer located at at least one of the following:

[0038] Between the first conductive structure and the sidewall of the first semiconductor body;

[0039] Between the second conductive structure and the sidewall of the second semiconductor body;

[0040] Between the resistive material layer and the sidewall of the first semiconductor body;

[0041] Between the resistive material layer and the sidewall of the second semiconductor body.

[0042] Optionally, the power semiconductor device further includes:

[0043] The first interlayer insulating layer is located between the first semiconductor body and the second semiconductor body;

[0044] The second interlayer insulating layer is located between the first semiconductor body and the third semiconductor body;

[0045] The third interlayer insulating layer is located on the side of the first gate structure and the second gate structure away from the first semiconductor body;

[0046] The first electrode is located on the side of the third interlayer insulating layer away from the first semiconductor body; the third interlayer insulating layer includes an opening, through which the first electrode is electrically connected to the second semiconductor body, the third semiconductor body, and the resistive material layer.

[0047] Optionally, the material of the first semiconductor body includes silicon carbide, the material of the second semiconductor body includes silicon, and the material of the third semiconductor body includes silicon.

[0048] This invention provides a power semiconductor device, comprising: a first semiconductor body including a first surface and a second surface disposed opposite to each other; the first semiconductor body being used to form a depletion-type transistor; a second semiconductor body located on the first surface of the first semiconductor body; the second semiconductor body being used to form a first enhancement-type transistor; wherein the material of the first semiconductor body is different from the material of the second semiconductor body, and the depletion-type transistor formed by the first semiconductor body and the first enhancement-type transistor formed by the second semiconductor body are connected in series; a third semiconductor body located on the first surface of the first semiconductor body; the third semiconductor body being used to form a second enhancement-type transistor; wherein the second enhancement-type transistor formed by the third semiconductor body is electrically connected between the gate of the depletion-type transistor and a first electrode; a resistive material layer located on the first surface of the first semiconductor body and electrically connected between the gate of the depletion-type transistor and the first electrode; a first electrode located on the side of the second semiconductor body, the third semiconductor body, and the resistive material layer away from the first semiconductor body, and electrically connected to the second semiconductor body, the third semiconductor body, and the resistive material layer; and a second electrode located on the second surface. The technical solution provided by this invention utilizes a second enhancement-mode transistor and a resistive material layer to provide two switchable charging and discharging circuits for the gate of the depletion-mode transistor in a cascode power semiconductor device. This allows the device to reduce its turn-off speed while ensuring a faster turn-on speed, thereby reducing dv / dt and electromagnetic interference.

[0049] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of the structure of a power semiconductor device provided in an embodiment of the present invention;

[0052] Figure 2 yes Figure 1 The equivalent circuit diagram of the structure shown;

[0053] Figure 3 yes Figure 1 The diagram shows the working principle of the structure in the on state. Detailed Implementation

[0054] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0055] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0056] This invention provides a power semiconductor device. Figure 1 This is a schematic diagram of the structure of a power semiconductor device provided in an embodiment of the present invention. Figure 2 yes Figure 1 The equivalent circuit diagram of the structure shown is for reference. Figure 1 and Figure 2 Power semiconductor devices include:

[0057] The first semiconductor body 10 includes a first surface and a second surface disposed opposite to each other; the first semiconductor body 10 is used to form a depletion-type transistor 101.

[0058] The second semiconductor body 20 is located on the first surface of the first semiconductor body 10; the second semiconductor body 20 is used to form the first enhancement transistor 102; wherein the material of the first semiconductor body 10 is different from the material of the second semiconductor body 20, and the depletion transistor 101 formed by the first semiconductor body 10 is connected in series with the first enhancement transistor 102 formed by the second semiconductor body 20.

[0059] A third semiconductor body 30 is located on the first surface of the first semiconductor body 10; the third semiconductor body 30 is used to form a second enhancement-mode transistor 103; wherein the second enhancement-mode transistor 103 formed by the third semiconductor body 30 is electrically connected between the gate c of the depletion-mode transistor 101 and the first electrode 1.

[0060] A resistive material layer 70 is located on the first surface of the first semiconductor body 10 and is electrically connected between the gate c of the depletion-type transistor 101 and the first electrode 1; the resistive material layer 70 is used to form a gate resistor 104; the gate resistor 104 is connected in parallel with the second enhancement transistor 103.

[0061] The first electrode 1 is located on the side of the second semiconductor body 20, the third semiconductor body 30 and the resistive material layer 70 away from the first semiconductor body 10, and is electrically connected to the second semiconductor body 20, the third semiconductor body 30 and the resistive material layer 70.

[0062] The second electrode 2 is located on the second surface.

[0063] Specifically, the first semiconductor body 10 is used to form a first transistor, which is a depletion-type transistor 101 and is normally on. The second semiconductor body 20 is used to form a second transistor, which is an enhancement-type transistor and is normally off. The second transistor can be turned on by a gate control signal. The first transistor and the second transistor are connected in series. Therefore, the on and off states of the entire power semiconductor device are controlled by the second transistor formed by the second semiconductor body 20.

[0064] The third semiconductor body 30 is used to form a third transistor, which is an enhancement-mode transistor and is normally closed. The third transistor can be turned on by a gate control signal. To distinguish it from the enhancement-mode transistor formed by the second semiconductor body 20, this invention refers to the enhancement-mode transistor formed by the second semiconductor body 20 as the first enhancement-mode transistor 102, and the enhancement-mode transistor formed by the third semiconductor body 30 as the second enhancement-mode transistor 103. The second enhancement-mode transistor 103 formed by the third semiconductor body 30 is electrically connected between the gate c of the depletion-mode transistor 101 and the first electrode 1, and the resistive material layer 70 is also electrically connected between the gate c of the depletion-mode transistor 101 and the first electrode 1. When the second enhancement-mode transistor 103 is turned on, the gate c of the depletion-mode transistor 101 can be electrically connected to the first electrode 1 through the second enhancement-mode transistor 103.

[0065] The first enhancement-mode transistor 102 and the second enhancement-mode transistor 103 are synchronously turned on and off. Therefore, the first enhancement-mode transistor 102 and the second enhancement-mode transistor 103 can be controlled by the same gate control signal. Furthermore, the gate of the first enhancement-mode transistor 102 (first gate G1) and the gate of the second enhancement-mode transistor 103 (second gate G2) can be electrically connected, thereby facilitating synchronous control of the first enhancement-mode transistor 102 and the second enhancement-mode transistor 103.

[0066] When a turn-on voltage is applied to the gate of the first enhancement-type transistor 102, the first enhancement-type transistor 102 turns on, and the second enhancement-type transistor 103 also turns on. The depletion-type transistor 101 is in the turn-on state, and the first electrode 1 and the second electrode 2 are connected. The gate c of the depletion-type transistor 101 discharges to the first electrode 1 through the second enhancement-type transistor 103. The circuit through which the charge passes during discharge is a low-resistance circuit, which can ensure that the device turns on quickly and reduce the device's turn-on loss.

[0067] A turn-off voltage is applied to the gate of the first enhancement-mode transistor 102, turning it off. Simultaneously, the second enhancement-mode transistor 103 also turns off. After the first enhancement-mode transistor 102 turns off, the source potential (b) of the depletion-mode transistor 101 increases. The first electrode 1 charges the gate (c) of the depletion-mode transistor 101 through the gate resistor 104 formed by the resistive material layer 70 until the gate-source potential difference of the depletion-mode transistor 101 is less than the threshold voltage, at which point the depletion-mode transistor 101 enters the turn-off state. Because the charging circuit is a high-resistance circuit, the charging speed can be reduced, thereby reducing the turn-off speed of the depletion-mode transistor 101, and consequently reducing its dv / dt, thus mitigating EMI problems. The turn-off speed of the depletion-mode transistor 101 can be adjusted based on the resistance of the gate resistor 104; a higher resistance results in a slower turn-off speed, and a lower resistance results in a slower turn-off speed. Therefore, the resistance of the gate resistor 104 can be determined according to the turn-off speed requirements of the depletion-type transistor 101. The resistive material layer 70 can be made of a high-resistivity material, including but not limited to SIPOS (semi-insulating polysilicon).

[0068] The technical solution provided by the embodiments of the present invention provides two switchable charging and discharging circuits for the gate c of the depletion-type transistor 101 in the cascode power semiconductor device, thereby reducing the turn-off speed of the device while ensuring a fast turn-on speed, thus reducing dv / dt and reducing electromagnetic interference problems.

[0069] The above are the core inventive points of this invention. The structure of the power semiconductor device will be described in detail below with reference to the accompanying drawings.

[0070] refer to Figure 1 The first semiconductor body 10 can be formed by a single epitaxial layer or by multiple epitaxial layers. That is, the first semiconductor body 10 can be a single first semiconductor epitaxial layer 12 or a stacked structure formed by multiple first semiconductor epitaxial layers 12. The first semiconductor body 10 may also include a substrate 11, meaning the first semiconductor body 10 includes a substrate 11 and at least one first semiconductor epitaxial layer 12 formed on one side of the substrate 11. The material of the substrate 11 is the same as the material of the semiconductor epitaxial layer.

[0071] When the first semiconductor body 10 includes only the first semiconductor epitaxial layer 12, the second surface is the surface of the semiconductor body closer to the substrate 11, and the first surface is the surface of the semiconductor body farther from the substrate 11. When the first semiconductor body 10 includes both the substrate 11 and the first semiconductor epitaxial layer 12, the second surface is the surface of the substrate 11 farther from the first semiconductor epitaxial layer 12, and the first surface is the surface of the first semiconductor epitaxial layer 12 furthest from the substrate 11, farther from the substrate 11. Figure 1 The first semiconductor body 10 shown includes a substrate 11 and a first semiconductor epitaxial layer 12 located on one side of the substrate 11. The first surface is the surface of the first semiconductor epitaxial layer 12 away from the substrate 11, and the second surface is the surface of the substrate 11 away from the first semiconductor epitaxial layer 12.

[0072] A second semiconductor body 20 is disposed on the first surface of the first semiconductor body 10. The second semiconductor body 20 can be formed by a single epitaxial layer or by multiple epitaxial layers in the first direction Y. That is, the second semiconductor body 20 may include a single second semiconductor epitaxial layer or a stacked structure formed by multiple second semiconductor epitaxial layers. A third semiconductor body 30 is disposed on the first surface of the first semiconductor body 10. The third semiconductor body 30 can be formed by a single epitaxial layer or by multiple epitaxial layers. That is, the third semiconductor body 30 may include a single third semiconductor epitaxial layer or a stacked structure formed by multiple third semiconductor epitaxial layers. Figure 1 The second semiconductor body 20 shown includes a second semiconductor epitaxial layer, and the third semiconductor body 30 includes a third semiconductor epitaxial layer. Furthermore, the second and third semiconductor epitaxial layers are made of the same material and can be formed simultaneously, thereby reducing the fabrication difficulty of power semiconductor devices and ensuring that the second and third semiconductor epitaxial layers have the same thickness.

[0073] Based on the above embodiments, refer to Figure 1 Optionally, the first semiconductor body 10 includes a first ohmic contact region 121 and a second ohmic contact region 122 with different conductivity types, both located on the first surface, and the first ohmic contact region 121 and the second ohmic contact region 122 are spaced apart; the first semiconductor body 10 also includes a buried layer 123 located on the side of the first ohmic contact region 121 and the second ohmic contact region 122 near the second surface; wherein, the buried layer 123 and the second ohmic contact region 122 are the same and can both have the same conductivity type as the second semiconductor layer; the depletion-type transistor 101 formed by the first semiconductor body 10 is a depletion-type junction field-effect transistor (JFET).

[0074] Specifically, the first semiconductor epitaxial layer 12 includes a first ohmic contact region 121 and a second ohmic contact region 122 with different conductivity types, and a buried layer 123 with the same conductivity type as the second ohmic contact region 122. The buried layer 123 is located on the side of the first ohmic contact region 121 and the second ohmic contact region 122 closest to the substrate 11. The conductivity type of the first ohmic contact region 121 is the same as that of the first semiconductor epitaxial layer 12, both being of the first conductivity type. The doping concentration of the first conductivity type ions in the first ohmic contact region 121 is greater than the doping concentration of the first conductivity type ions in the first semiconductor epitaxial layer 12. The conductivity type of the second ohmic contact region 122 is of the second conductivity type. Both the first ohmic contact region 121 and the second ohmic contact region 122 are heavily doped regions. The second ohmic contact region 122 and the buried layer 123 can be formed by implanting second conductivity type ions in the first semiconductor epitaxial layer 12. The doping concentration of the second conductivity type ions in the second ohmic contact region 122 can be equal to or different from the doping concentration of the second conductivity type ions in the buried layer 123.

[0075] The orthographic projection of the first ohmic contact region 121 on the second surface lies within the orthographic projection of the buried layer 123 on the second surface, and the first ohmic contact region 121 extends from the boundary of the first surface along the second direction X towards the second ohmic contact region 122; the first direction Y and the second direction X can be perpendicular to each other. A portion of the orthographic projection of the second ohmic contact region 122 on the second surface overlaps with a portion of the orthographic projection of the buried layer 123 on the second surface, while a portion of the orthographic projection of the second ohmic contact region 122 on the second surface does not overlap with the orthographic projection of the buried layer 123 on the second surface. The area outside the buried layer 123, the first ohmic contact region 121, and the second ohmic contact region 122 in the first semiconductor epitaxial layer 12 is a drift region. The width between the buried layer 123 and the second ohmic contact region 122 satisfies the condition that after the depletion region is formed between the buried layer 123 and the drift region, and the depletion region is formed between the second ohmic contact region 122 and the drift region, the channel is not interrupted by the depletion region, allowing current to flow between the second electrode 2 and the first ohmic contact region 121. The first ohmic contact region 121 is used to electrically connect with the second semiconductor body 20 to achieve a series connection with the enhancement transistor formed with the second semiconductor body 20.

[0076] The first conductivity type can be N-type, and the second conductivity type can be P-type, meaning the conductivity type of the first ohmic contact region 121 is N-type, and the conductivity type of the second ohmic contact region 122 is P-type. Alternatively, the first conductivity type can be P-type, and the second conductivity type can be N-type, meaning the conductivity type of the first ohmic contact region 121 is P-type, and the conductivity type of the second ohmic contact region 122 is N-type. Figure 1In the structure shown, the first ohmic contact region 121 has an N-type conductivity, and the second ohmic contact region 122 has a P-type conductivity. The first electrode 1 is the source (S) of the power semiconductor device, and the second electrode 2 is the drain (D) of the power semiconductor device.

[0077] Based on the above embodiments, refer to Figure 1 Optionally, the second semiconductor body 20 includes a third ohmic contact region 21 and a fourth ohmic contact region 22, which are spaced apart on the surface of the second semiconductor body 20 away from the first semiconductor body 10; the conductivity types of the third ohmic contact region 21 and the fourth ohmic contact region 22 are different from the conductivity type of the second semiconductor body 20; wherein, the first enhancement-mode transistor 102 formed by the second semiconductor body 20 is an enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET).

[0078] Specifically, the third ohmic contact region 21 and the fourth ohmic contact region 22 can be formed by ion implantation on the surface of the second semiconductor body 20 away from the first semiconductor body 10. The third ohmic contact region 21 and the fourth ohmic contact region 22 have the same conductivity type, and the channel region of the first enhancement-mode transistor 102 formed in the second semiconductor body 20 is located between the third ohmic contact region 21 and the fourth ohmic contact region 22.

[0079] The first enhancement-mode transistor 102 further includes a first gate structure 41 located on the side of the second semiconductor body 20 away from the first semiconductor body 10. The first gate structure 41 is used to control the conduction state of the first enhancement-mode transistor 102. The first gate structure 41 includes a first gate insulating layer 412 and a first gate G1. The first gate insulating layer 412 is located on the surface of the second semiconductor body 20 away from the first semiconductor body 10; the first gate G1 is located on the surface of the first gate insulating layer 412 away from the second semiconductor body 20. The vertical projection of the first gate G1 onto the second semiconductor body 20 covers the channel region of the first enhancement-mode transistor 102. The material of the first gate insulating layer 412 can be silicon oxide, and the material of the first gate G1 can be polysilicon. The first gate G1 is the gate of the first enhancement-mode transistor 102 and is used to control the conduction state of the first enhancement-mode transistor 102.

[0080] In this embodiment of the invention, the first enhancement-mode transistor 102 formed in the second semiconductor body 20 is an enhancement-mode MOSFET. The first electrode 1 is electrically connected to the fourth ohmic contact region 22 in the second semiconductor body 20. The conductivity type of the third ohmic contact region 21 is the same as that of the first ohmic contact region 121, and the third ohmic contact region 21 and the first ohmic contact region 121 are electrically connected through a first conductive structure 51, thereby realizing the series connection between the depletion-mode JFET formed in the first semiconductor body 10 and the enhancement-mode MOSFET formed in the second semiconductor body 20. The first conductive structure 51 is located on the side of the second semiconductor body 20 away from the third semiconductor body 30.

[0081] Furthermore, since the first ohmic contact region 121 has an N-type conductivity, the third ohmic contact region 21 and the fourth ohmic contact region 22 also have N-type conductivity, while the second semiconductor body 20 has a P-type conductivity. The first enhancement-mode transistor 102 formed by the second semiconductor body 20 is an enhancement-mode N-type MOSFET. The third ohmic contact region 21 serves as the drain contact region of the first enhancement-mode transistor 102, and the fourth ohmic contact region 22 serves as the source contact region of the first enhancement-mode transistor 102. The material of the first conductive structure 51 includes a metallic material. Using a metallic conductive structure to electrically connect the first semiconductor body 10 and the second semiconductor body 20 avoids the problem of increased conduction losses caused by the heterojunction barrier, as well as the problem of increased leakage current or decreased breakdown voltage caused by lattice mismatch.

[0082] Based on the above embodiments, refer to Figure 1 Optionally, the third semiconductor body 30 includes a fifth ohmic contact region 31 and a sixth ohmic contact region 32, which are spaced apart on the surface of the third semiconductor body 30 away from the first semiconductor body 10; the conductivity types of the fifth ohmic contact region 31 and the sixth ohmic contact region 32 are different from the conductivity type of the third semiconductor body 30; wherein, the second enhancement-mode transistor 103 formed by the third semiconductor body 30 is an enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET).

[0083] Specifically, the fifth ohmic contact region 31 and the sixth ohmic contact region 32 can be formed by ion implantation on the surface of the third semiconductor body 30 away from the first semiconductor body 10. The fifth ohmic contact region 31 and the sixth ohmic contact region 32 have the same conductivity type, and the channel region of the second enhancement-mode transistor 103 formed in the third semiconductor body 30 is located between the fifth ohmic contact region 31 and the sixth ohmic contact region 32.

[0084] The second enhancement-mode transistor 103 further includes a second gate structure 42 located on the side of the third semiconductor body 30 away from the first semiconductor body 10. The second gate structure 42 is used to control the conduction state of the second enhancement-mode transistor 103. The second gate structure 42 includes a second gate insulating layer 421 and a second gate G2. The second gate insulating layer 421 is located on the surface of the third semiconductor body 30 away from the first semiconductor body 10; the second gate G2 is located on the surface of the second gate insulating layer 421 away from the third semiconductor body 30. The vertical projection of the second gate G2 onto the third semiconductor body 30 covers the channel region of the second enhancement-mode transistor 103. The material of the second gate insulating layer 421 can be silicon oxide, and the material of the second gate G2 can be polysilicon. The second gate G2 is the gate of the second enhancement-mode transistor 103 and is used to control the conduction state of the second enhancement-mode transistor 103.

[0085] In this embodiment of the invention, the second enhancement-mode transistor 103 formed in the third semiconductor body 30 is an enhancement-mode MOSFET. The first electrode 1 is electrically connected to the sixth ohmic contact region 32 in the third semiconductor body 30. The conductivity type of the fifth ohmic contact region 31 is the same as that of the first ohmic contact region 121. The fifth ohmic contact region 31 and the second ohmic contact region 122 are electrically connected through a second conductive structure 52, thereby realizing the electrical connection between the gate c of the depletion-mode JFET formed in the first semiconductor body 10 and the enhancement-mode MOSFET formed in the third semiconductor body 30. The second conductive structure 52 is located on the side of the third semiconductor body 30 away from the third semiconductor body 30.

[0086] Furthermore, since the first ohmic contact region 121 has an N-type conductivity, the fifth ohmic contact region 31 and the sixth ohmic contact region 32 also have N-type conductivity, while the third semiconductor body 30 has a P-type conductivity. Therefore, the second enhancement-mode transistor 103 formed by the third semiconductor body 30 is an enhancement-mode N-type MOSFET. The fifth ohmic contact region 31 serves as the drain contact region of the second enhancement-mode transistor 103, and the sixth ohmic contact region 32 serves as the source contact region of the second enhancement-mode transistor 103. The material of the second conductive structure 52 includes a metallic material.

[0087] Based on the above embodiments, optionally, the material of the first semiconductor body 10 includes silicon carbide (SiC), the material of the second semiconductor body 20 includes silicon (e.g., single crystal silicon), and the material of the third semiconductor body 30 includes silicon (e.g., single crystal silicon).

[0088] Specifically, the depletion-type transistor 101 formed by the first semiconductor body 10 is a depletion-type SiC JFET; the enhancement-type transistor formed by the second semiconductor body 20 is an enhancement-type Si MOSFET, thus the power semiconductor device includes a cascaded high-voltage SiC JFET and a low-voltage Si MOSFET. When the power semiconductor device is in the ON state, reference... Figure 3 Current I DS The voltage flows from the drain D through the SiC JFET channel and the low-voltage Si MOSFET channel to the source S. When the device is in the blocking state, the SiC JFET bears most of the voltage, while the low-voltage Si MOSFET bears a small voltage drop. If the enhancement-mode transistor formed by the third semiconductor body 30 is an enhancement-mode Si MOSFET, then the power semiconductor device also includes a JFET gate loop controlled by the Si MOSFET electrically connected between the source S and the gate of the SiC JFET.

[0089] The technical solution provided in this invention replaces the SiC MOSFET structure in related technologies with a Si MOSFET (first enhancement-mode transistor 102), avoiding the problem of excessively high interface state density of SiC MOSFETs, improving channel mobility, and reducing the specific on-resistance of the device. Furthermore, replacing the SiC MOSFET structure in related technologies with a Si MOSFET can also avoid reliability issues caused by excessive tunneling current between SiC and the gate oxide layer (SiO2 layer). By controlling the Si MOSFET (second enhancement-mode transistor 103) and gate resistor 104 through the JFET gate circuit, two switchable charge / discharge circuits can be provided to the gate c of the depletion-mode SiC JFET, enabling the device to maintain a fast turn-on speed while reducing the turn-off speed, thereby reducing dv / dt and electromagnetic interference.

[0090] In summary, the power semiconductor device provided in this embodiment of the invention can switch between an on state and an off state during operation.

[0091] The drain (D) of the power semiconductor device is connected to a high potential, and the source (S) is connected to a low potential. When a positive voltage is applied to the first gate (G1) of the low-voltage Si MOSFET (first enhancement-mode transistor 102), the gate circuit of the JFET controls the Si MOSFET (second enhancement-mode transistor 103) to turn on as well. The gate of the SiC JFET discharges to the source (S) of the power semiconductor device, and the SiC JFET enters the on state. The current of the power semiconductor device flows from the drain (D) to the source (S), and the current path is as follows: Figure 3 As shown.

[0092] The drain (D) of the power semiconductor device remains at a high potential, and the source (S) is at a low potential. When a negative voltage is applied to the first gate (G1) of the low-voltage SiMOSFET, the gate circuit of the JFET controls the SiMOSFET to turn off. The gate of the SiC JFET is charged through the circuit formed by the gate resistor 104 of the JFET until the potential difference between the gate potential and the source potential of the SiC JFET is less than the threshold voltage. At this time, the device enters the off state, the current is cut off, and most of the blocking voltage is borne by the SiC JFET.

[0093] Specifically, regarding the control of the switching speed of the SiC JFET, as can be seen from the above description, when the device is turned on, the "JFET gate circuit controls the Si MOSFET" turns on, the charge carriers in the gate PN junction of the SiC JFET recombine in the depletion region, the depletion region narrows, and the SiC JFET turns on. During this process, the discharge current of the gate capacitance (the gate-drain capacitance of the SiC JFET, formed by the PN junction between the second ohmic contact region 122 and the drift region in the first semiconductor body 10) is discharged through the "JFET gate circuit controls the Si MOSFET". Since this is a low-resistance circuit, it can ensure that the device turns on quickly and reduce the device's turn-on loss.

[0094] When the device is turned off, the source potential of the SiC JFET increases (up to the breakdown voltage of a low-voltage Si MOSFET), the gate PN junction of the SiC JFET becomes reverse biased, and the depletion region widens. The device turns off when the gate / source potential difference falls below the SiC JFET threshold voltage. During this process, the gate capacitance of the SiC JFET is charged through the "gate resistor 104" circuit. Since this is a high-resistance circuit, and the resistance value of the gate resistor 104 can be adjusted during the design process, the turn-off speed of the SiC JFET can be reduced, thereby reducing its dv / dt and alleviating EMI issues. By switching the gate charging and discharging circuit of the SiC JFET, the turn-on and turn-off speeds can be individually controlled without the need for additional drive to switch the gate circuit, greatly reducing application complexity.

[0095] Based on the above embodiments, refer to Figure 1 The power semiconductor device also includes an ohmic contact layer located at at least one of the following:

[0096] Between the first conductive structure 51 and the first ohmic contact region 121;

[0097] Between the first conductive structure 51 and the third ohmic contact region 21;

[0098] Between the second conductive structure 52 and the second ohmic contact region 122;

[0099] Between the second conductive structure 52 and the fifth ohmic contact region 31;

[0100] Between the first electrode 1 and the fourth ohmic contact region 22;

[0101] Between the first electrode 1 and the sixth ohmic contact region 32;

[0102] Between the resistive material layer 70 and the second ohmic contact area 122.

[0103] Specifically, the power semiconductor device also includes: a first ohmic contact layer 61 located on the surface of the first ohmic contact region 121, and a first conductive structure 51 electrically connected to the first ohmic contact region 121 through the first ohmic contact layer 61, thereby reducing the contact resistance between the first conductive structure 51 and the first ohmic contact region 121.

[0104] And / or, the third ohmic contact layer 63 is located on the surface of the third ohmic contact area 21, and the first conductive structure 51 is electrically connected to the third ohmic contact area 21 through the third ohmic contact layer 63, thereby reducing the contact resistance between the first conductive structure 51 and the third ohmic contact area 21.

[0105] And / or, the second ohmic contact layer 62 is located on the surface of the second ohmic contact area 122, and the second conductive structure 52 is electrically connected to the second ohmic contact area 122 through the second ohmic contact layer 62, thereby reducing the contact resistance between the second conductive structure 52 and the second ohmic contact area 122.

[0106] And / or, the fifth ohmic contact layer 65 is located on the surface of the fifth ohmic contact area 31, and the second conductive structure 52 is electrically connected to the fifth ohmic contact area 31 through the fifth ohmic contact layer 65, thereby reducing the contact resistance between the second conductive structure 52 and the fifth ohmic contact area 31.

[0107] And / or, the fourth ohmic contact layer 64 is located on the surface of the fourth ohmic contact area 22, and the first electrode 1 is electrically connected to the fourth ohmic contact area 22 through the fourth ohmic contact layer 64, thereby reducing the contact resistance between the first electrode 1 and the fourth ohmic contact area 22.

[0108] And / or, the sixth ohmic contact layer 66 is located on the surface of the sixth ohmic contact area 32, and the first electrode 1 is electrically connected to the sixth ohmic contact area 32 through the sixth ohmic contact layer 66, thereby reducing the contact resistance between the first electrode 1 and the sixth ohmic contact area 32.

[0109] And / or, the seventh ohmic contact layer 67 is located on the surface of the second ohmic contact area 122, and the resistive material layer 70 is electrically connected to the seventh ohmic contact area through the seventh ohmic contact layer 67, thereby reducing the contact resistance between the resistive material layer 70 and the second ohmic contact area 122.

[0110] Based on the above embodiments, optionally, the resistive material layer 70 is located between the first semiconductor body 10 and the second semiconductor body 20; the power semiconductor device further includes a sidewall insulating layer located at at least one of the following locations:

[0111] Between the first conductive structure 51 and the sidewall of the first semiconductor body 10;

[0112] Between the second conductive structure 52 and the sidewall of the second semiconductor body 20;

[0113] Between the resistive material layer 70 and the sidewall of the first semiconductor body 10;

[0114] Between the resistive material layer 70 and the sidewall of the second semiconductor body 20.

[0115] Specifically, the power semiconductor device also includes a first sidewall insulating layer 81, located on the sidewall surface of the first semiconductor body 10 near the first conductive structure 51. The first sidewall insulating layer 81 is used to electrically isolate the first conductive structure 51 from the sidewall of the first semiconductor body 10.

[0116] And / or, the second sidewall insulating layer 82 is located on the sidewall surface of the second semiconductor body 20 near the second conductive structure 52, and the second sidewall insulating layer 82 is used to electrically isolate the second conductive structure 52 from the sidewall of the second semiconductor body 20.

[0117] And / or, a third sidewall insulating layer 83 is located on the sidewall surface of the first semiconductor body 10 near the resistive material layer 70, and the third sidewall insulating layer 83 is used to electrically isolate the resistive material layer 70 from the sidewall of the first semiconductor body 10.

[0118] And / or, a fourth sidewall insulating layer 84 is located on the sidewall surface of the second semiconductor body 20 near the resistive material layer 70, and the fourth sidewall insulating layer 84 is used to electrically isolate the resistive material layer 70 from the sidewall of the second semiconductor body 20.

[0119] Optionally, the materials of the first sidewall insulation layer 81, the second sidewall insulation layer 82, the third sidewall insulation layer 83, and the fourth sidewall insulation layer 84 can be the same, different, or partially the same and partially different. This can be configured according to actual needs.

[0120] Based on the above embodiments, please continue to refer to Figure 1 Optionally, power semiconductor devices also include:

[0121] The first interlayer insulating layer 91 is located between the first semiconductor body 10 and the second semiconductor body 20. The first interlayer insulating layer 91 is disposed on the first surface of the first semiconductor body 10, and the second semiconductor body 20 is disposed on the surface of the first interlayer insulating layer 91 away from the first semiconductor body 10. The first interlayer insulating layer 91 is used to electrically isolate the first semiconductor body 10 and the second semiconductor body 20.

[0122] The second interlayer insulating layer 92 is located between the first semiconductor body 10 and the third semiconductor body 30. The second interlayer insulating layer 92 is disposed on the first surface of the first semiconductor body 10, and the third semiconductor body 30 is disposed on the surface of the second interlayer insulating layer 92 away from the first semiconductor body 10. The second interlayer insulating layer 92 is used to electrically isolate the first semiconductor body 10 and the third semiconductor body 30.

[0123] A third interlayer insulating layer 93 is located on the side of the first gate structure 41 and the second gate structure 42 away from the first semiconductor body 10; the first electrode 1 is located on the side of the third interlayer insulating layer 93 away from the first semiconductor body 10; the third interlayer insulating layer 93 includes an opening, through which the first electrode 1 is electrically connected to the second semiconductor body 20, the third semiconductor body 30, and the resistive material layer 70. The third interlayer insulating layer 93 is used to electrically isolate the first conductive structure 51 from the first electrode 1, electrically isolate the second conductive structure 52 from the first electrode 1, electrically isolate the first electrode 1 from the first gate G1, and electrically isolate the first electrode 1 from the second gate G2.

[0124] Optionally, the materials of the first interlayer insulation layer 91, the second interlayer insulation layer 92, and the third interlayer insulation layer 93 can be the same, different, or partially the same and partially different. This can be configured according to actual needs.

[0125] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A power semiconductor device, characterized in that, include: A first semiconductor body includes a first surface and a second surface disposed opposite to each other; the first semiconductor body is used to form a depletion-type transistor. A second semiconductor body is located on a first surface of the first semiconductor body; the second semiconductor body is used to form a first enhancement-mode transistor; wherein the material of the first semiconductor body is different from the material of the second semiconductor body, and the depletion-mode transistor formed by the first semiconductor body is connected in series with the first enhancement-mode transistor formed by the second semiconductor body. A third semiconductor body is located on a first surface of the first semiconductor body; the third semiconductor body is used to form a second enhancement-mode transistor; wherein the second enhancement-mode transistor formed by the third semiconductor body is electrically connected between the gate of the depletion-mode transistor and the first electrode; the first enhancement-mode transistor and the second enhancement-mode transistor are controlled by the same gate control signal; A resistive material layer is located on the first surface of the first semiconductor body; the gate resistor formed by the resistive material layer is electrically connected between the gate of the depletion-type transistor and the first electrode, and is connected in parallel with the second enhancement transistor; The first electrode is located on the side of the second semiconductor body, the third semiconductor body, and the resistive material layer away from the first semiconductor body, and is electrically connected to the second semiconductor body, the third semiconductor body, and the resistive material layer; The second electrode is located on the second surface.

2. The power semiconductor device according to claim 1, characterized in that, Also includes: A first gate structure is located on the side of the second semiconductor body away from the first semiconductor body, and the first gate structure is used to control the conduction state of the first enhancement transistor. The second gate structure is located on the side of the third semiconductor body away from the first semiconductor body, and the second gate structure is used to control the conduction state of the second enhancement transistor. The first gate structure and the second gate structure receive the same gate control signal.

3. The power semiconductor device according to claim 1, characterized in that, The first semiconductor body includes a first ohmic contact region and a second ohmic contact region with different conductivity types, both located on the first surface, and the first ohmic contact region and the second ohmic contact region are spaced apart; the second ohmic contact region is used as the gate of the depletion-type transistor. The first semiconductor body further includes a buried layer located on the side of the first ohmic contact region and the second ohmic contact region near the second surface; The buried layer has the same conductivity type as the second ohmic contact region; the depletion-type transistor formed by the first semiconductor body is a depletion-type junction field-effect transistor.

4. The power semiconductor device according to claim 3, characterized in that, The orthographic projection of the first ohmic contact area on the second surface lies in the orthographic projection of the buried layer on the second surface, and the first ohmic contact area extends from the boundary of the first surface to the second ohmic contact area. The partial orthographic projection of the second ohmic contact area on the second surface overlaps with the partial orthographic projection of the buried layer on the second surface.

5. The power semiconductor device according to claim 3, characterized in that, The second semiconductor body includes a third ohmic contact region and a fourth ohmic contact region, which are spaced apart on the surface of the second semiconductor body away from the first semiconductor body; the conductivity type of the third ohmic contact region and the fourth ohmic contact region are different from the conductivity type of the second semiconductor body; the first enhancement-mode transistor formed by the second semiconductor body is a metal-oxide-semiconductor field-effect transistor. The power semiconductor device further includes a first conductive structure located on the side of the second semiconductor body away from the third semiconductor body; the first conductive structure is used to electrically connect a first ohmic contact region in the first semiconductor body and a third ohmic contact region in the second semiconductor body. The first electrode is electrically connected to the fourth ohmic contact region in the second semiconductor body.

6. The power semiconductor device according to claim 5, characterized in that, The third semiconductor body includes a fifth ohmic contact region and a sixth ohmic contact region, which are spaced apart on the surface of the third semiconductor body away from the first semiconductor body; the conductivity types of the fifth ohmic contact region and the sixth ohmic contact region are different from the conductivity type of the third semiconductor body; the second enhancement-mode transistor formed by the third semiconductor body is a metal-oxide-semiconductor field-effect transistor. The power semiconductor device further includes a second conductive structure located on the side of the third semiconductor body away from the second semiconductor body; the second conductive structure is used to electrically connect a second ohmic contact region in the first semiconductor body and a fifth ohmic contact region in the third semiconductor body. The first electrode is electrically connected to the sixth ohmic contact region in the third semiconductor body.

7. The power semiconductor device according to claim 6, characterized in that, It also includes an ohmic contact layer located at at least one of the following: Between the first conductive structure and the first ohmic contact area; Between the first conductive structure and the third ohmic contact region; Between the second conductive structure and the second ohmic contact area; Between the second conductive structure and the fifth ohmic contact region; Between the first electrode and the fourth ohmic contact area; Between the first electrode and the sixth ohmic contact area; Between the resistive material layer and the second ohmic contact area.

8. The power semiconductor device according to claim 6, characterized in that, The resistive material layer is located between the first semiconductor body and the second semiconductor body; the power semiconductor device further includes a sidewall insulating layer located at at least one of the following locations: Between the first conductive structure and the sidewall of the first semiconductor body; Between the second conductive structure and the sidewall of the second semiconductor body; Between the resistive material layer and the sidewall of the first semiconductor body; Between the resistive material layer and the sidewall of the second semiconductor body.

9. The power semiconductor device according to claim 2, characterized in that, Also includes: The first interlayer insulating layer is located between the first semiconductor body and the second semiconductor body; The second interlayer insulating layer is located between the first semiconductor body and the third semiconductor body; The third interlayer insulating layer is located on the side of the first gate structure and the second gate structure away from the first semiconductor body; The first electrode is located on the side of the third interlayer insulating layer away from the first semiconductor body; the third interlayer insulating layer includes an opening, through which the first electrode is electrically connected to the second semiconductor body, the third semiconductor body, and the resistive material layer.

10. The power semiconductor device according to claim 1, characterized in that, The material of the first semiconductor body includes silicon carbide, the material of the second semiconductor body includes silicon, and the material of the third semiconductor body includes silicon.

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