High power semiconductor device packaging

Abstract

Method of forming semiconductor die module or package 600 comprising attaching semiconductor die 605 between first leadframe 601 and second leadframe 400 (Figure 4). The second leadframe comprises int

Description

Field of the Disclosure The present disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices. Particularly, but not exclusively, the disclosure relates to the packaging of power semiconductor devices such as a hetero-structure AIGaN / GaN high electron mobility transistor. Background of the Disclosure Gallium Nitride (GaN) is a wide band gap material suitable for power and RF semiconductor devices. GaN technology facilitates the design of transistors with high electron mobility and a high saturation velocity, both of which are, generally, useful traits in the field of power and Radio-Frequency (RF) electronics. The use of GaN material has additional advantages in power devices. For example, the wide band gap of the material (Eg=3.39eV) results in high critical electric field (Ec=3.3MV / cm), which allows the design of devices with a shorter drift region (and therefore a lower on-state resistance) compared to silicon-based devices with the same breakdown voltage. The use of an Aluminium Gallium Nitride (AIGaN) / GaN heterostructure also allows the formation of a two-dimensional electron gas (2DEG) at the hetero-interface, where carriers can reach very high carrier mobility values (e.g. p=2000cm2 / (Vs)). In addition, the piezopolarization charge present at the AIGaN / GaN heterostructure can result in a high electron density in the 2DEG layer (e.g. 1e13 cm-2). These properties facilitate the development of High Electron Mobility Transistors (HEMTs) and Schottky barrier diodes with very competitive performance parameters. With the increasing adoption of power devices in various applications, the demand for higher current carrying capability, reliability and thermal efficiency of the power devices has increased, and a corresponding boom in advanced packaging technologies. Integrated circuit packages may be made by placing the semiconductor chip on a lead frame, wire bonding the chip to the metal leads of that lead frame, and then covering the chip with plastic. This simple and usually low-cost packaging is still the best solution for many applications. A lead frame may act as a thin layer of metal that connects the wiring from tiny electrical terminals on the semiconductor surface to the large-scale circuitry on electrical devices and circuit boards. Typically, lead frames are produced in a long strip, which allows them to be quickly processed on assembly machines. Amongst others, lead frames are used to manufacture a quad flat no-leads package (QFN), a dual flat no-leads (DFN), a quad flat package (QFP), a dual in-line package (DIP), a small outline package (SO), etc. For some applications, copper clips have been introduced as a favourable replacement for traditional wire bond interconnections used for high performance power semiconductor switches. Copper clips provide significant performance advantages over traditional wire bonds, for example allowing for higher current, higher frequency and an improved overall system efficiency through lower interconnect resistances and inductances. Copper clips may also facilitate a lower spreading resistance, improved current handling capability, and improved transient and steady state thermal performances. For high volume packaging, where multiple packages need to be processed, the throughput efficiency of copper clip packaging is a challenge. This is because current copper clip technology involves placing individual clips in each package one by one. In addition, in lateral power devices such as GaN based devices, the drain and source leads may be positioned in close proximity to each other, thereby requiring very high placement accuracy. A pick-and-place tool is generally used attach each clip to any region of the die. However, when mounting two or more separate clips to a die, there can be inconsistencies when aligning the clips to the source / gate / drain regions in the semiconductor die. Further, individual placement of copper clips can also lead to variations across multiple packages, and corresponding variations in the performance between the packages. Various additional alignment techniques have been attempted to provide better placement accuracy. However, these generally require multiple additional manufacturing steps, and / or the requirement of additional tools / components. Examples of such techniques may be found in US20230005846A1, US7768105B2, US8058107B2 and US11676934B2. The Applicant has therefore recognised a need for an improved packaging technique that can provide low parasitic, thermally enhanced packages for power devices with a higher throughput, without requiring additional equipment or infrastructure. Summary It is an object of the present invention to provide a power semiconductor device package or module and a method of packaging power devices using copper clips in a strip format. Processes according to the present disclosure may provide a copper clip array in a leadframe strip format. A semiconductor die may be placed on the die attach pad of a bottom leadframe. The copper clip leadframe is placed on top of the semiconductor die. This combination of the two leadframes with a die in between may then be overmolded to encapsulate the die and leadframes, for example using conventional transfer mold, compression mold, mold underfill or film assisted mold processes. The top leadframe may be separated along with the bottom leadframe, for example during the conventional package singulation process. According to a first aspect of the present disclosure there is provided a method of forming a semiconductor die module, the method comprising: attaching a semiconductor die to a first leadframe; and attaching a second leadframe to the semiconductor die such that the semiconductor die is positioned between the second leadframe and the first leadframe; wherein the second leadframe comprises an interconnection clip such that attaching the second leadframe to the semiconductor die comprises attaching the interconnection clip to the semiconductor die. By forming the interconnection clip as part of the second (e.g. top) leadframe, and then attaching to the semiconductor die and the first (e.g. bottom) leadframe, this method may facilitate improved placement accuracy of the interconnection clip. This may in turn both enhance the operational characteristics of the semiconductor die package, and reduce a variation in semiconductor die packages. This method may therefore be particularly advantageous for lateral power devices with close source and drain leads. It will be understood that relative positional terms such as “top” and “bottom” are provided to assist in the conceptual understanding of the disclosure, and are not intended to be limiting in nature. In implementations, the method comprises forming the second leadframe. Forming the second leadframe may comprise stamping or etching a sheet of leadframe material to form one or more interconnection clips. The leadframe material may be e.g. copper or any other suitable material, such as other metals and electrically conductive materials. The second leadframe may comprise the interconnection clip(s) and a support frame, such that the support frame assists in the placement of the interconnection clips relative to the second leadframe (and therefore also relative to the semiconductor die). Advantageously, the provision of a support frame may therefore further increase the accuracy and security of the placement of the interconnection clips. The support frame may form a perimeter of the second leadframe. The interconnection clip may be connected to the support frame by one or more deformable connections or tether points, for example a lateral spring structure in the plane of the clip structures. The deformable connections may facilitate the adjustment of the positioning of the interconnection clip relative to the support frame and / or second leadframe. For example, a height or angle of the interconnection clip may be adjusted based on the structure of the semiconductor die and the first leadframe. Thus, the method may comprise deforming the one or more deformable connections to adjust a positioning of the interconnection clip prior to attaching the interconnection clip to the semiconductor die and the first leadframe. Additionally or alternatively, a height profile of the clips may be adjusted via e.g. bending or etching of the clips. In implementations, the second leadframe comprises a plurality of interconnection clips, which may form an array of clips. The method comprises attaching the plurality of interconnection clips to the semiconductor die and / or the first leadframe. The method may therefore facilitate the accurate attachment of multiple clips to the semiconductor die and the first leadframe in a single manufacturing process step. This may reduce the number of manufacturing steps required to produce each semiconductor die package, and increase throughput. In implementations, the support frame may be removed after attaching the interconnection clip to the semiconductor die. The method may comprise one or more other process steps, for example encapsulating the semiconductor die, e.g. in a moulding compound such as epoxy resin. Additionally or alternatively the method may comprise providing interconnections between the semiconductor die and the first (e.g. bottom) leadframe, for example to one or more control terminals provided on the bottom leadframe. These interconnections may be e.g. wire bonds or any other suitable interconnection technology, and may be provided at any time during or after attaching the semiconductor die to the first leadframe. The connections of the interconnection clips of the second leadframe may be combined with wire bonding for smaller semiconductor die geometries or for connections that are less susceptible to parasitic performance issues, such as for providing control lines. The entire structure may be capped with a conductive layer or heat slug to further enhance thermal performance. The conductive layer may comprise e.g.. copper or aluminium, and / or may comprise an electrically insulating material such as ceramic to provide or improve electrical isolation, while still maintaining thermal performance. For example, the conductive layer may be a thermally conductive layer formed from or comprising a ceramic heatsink. A conductive layer or heat slug may be incorporated into a module or package in various ways. For example, a film-assisted molding process may be used for overmolding the semiconductor die, to retain a portion of the copper clip that extends out of the mold compound, or is otherwise not covered by the mold compound (e.g. by being level with a surface of the mold compound). The film may then be removed to expose the copper clip (e.g. from top of the package), for attachment to a copper pad or any other conductive pad, such as a heat slug. Alternatively, the copper pad may be attached to e.g. a heatsink such as a ceramic heatsink. As another example, the interconnection clip structure may be formed with a preformed pad on top of the clips, with the preformed pad configured to act as a heat slug. Another method may comprise providing a pin in the mold case, the pin corresponding to the space which will be occupied by the top heat slug so that this space remains free of the mold compound during an overmolding process. Alternatively, other conventional methods of molding / grinding may be used to connect a conductive layer or heat slug to the interconnection clip structure, to facilitate or enhance top side cooling capabilities. This can be beneficial over conventional methods of manufacturing dual-side cooled packages, where traditionally multiple layers of copper and molding compound may be formed over the semiconductor die to enable cooling from the top side of the package. This traditional process leads to a complex design and long lead times of manufacturing. In contrast, methods according to the present disclosure may comprise attaching a heat slug directly to an interconnection clip, to thereby provide a package with a simpler construction and that can be molded in a single step. The interconnection clip may be a copper clip, and may be attached to the semiconductor die and / or first leadframe via any suitable means, such as solder or a conductive epoxy. In implementations, attaching the semiconductor die to the first leadframe comprises attaching a plurality of semiconductor dies to the first lead frame, wherein each of the plurality of interconnection clips corresponds to at least one of the plurality of semiconductor dies; and attaching the interconnection clip to the semiconductor die comprises attaching each interconnection clip to the respective semiconductor die in the same process step. In such implementations, it will be understood that the second leadframe comprises a plurality of interconnection clips. For example, the second leadframe may comprise an array of clip structures, each clip structure comprising one or more interconnection clips fora given semiconductor die. In such an array, any support frame may form a perimeter around each clip structure in the array, and / or a perimeter around the second leadframe as a whole. In other words, in various implementations the second leadframe may comprise just a single clip per die, multiple clips per die, or multiple clips for multiple dies. Optionally, each such interconnection clip or clip structure may be formed in the second leadframe in the same manufacturing step, e.g. as part of a stamping or etching process. The method may therefore provide a means for increasing the throughput of bulk semiconductor die package manufacturing, by facilitating the placement and attachment of interconnection clips to multiple semiconductor dies in a single process step. The method may further advantageously result in a lower manufacturing costs, material costs and tooling costs than existing methods due to a simpler leadframe manufacturing process and compatibility with existing equipment infrastructure. The method may comprise singulating each of the plurality of semiconductor dies into a separate semiconductor die package. Singulating the semiconductor dies may comprise singulating the first and second leadframes, for example by removing any support frame(s). The proposed packaging methodology may therefore provide higher placement accuracy, higher throughput, less waste, lower manufacturing cost, lower tooling cost, lower inventory cost, lower parasitics, and higher thermal conductivity. The proposed method of packaging power devices may be used in conjunction with any semiconductor device or any combination of semiconductor power devices, for example but not limited to GaN power devices. For example, bulk manufacturing techniques according to the present disclosure may be used to package multiple different types of semiconductor dies in the same process steps. Optionally, the method may comprise forming a package for subsequent attachment to a printed circuit board (PCB) to create a power supply. Alternatively, the method may comprise forming a module, such as an intelligent power module, which may include surface mount components directly attached or attachable to the module or connectors for further integration. According to a second aspect of the invention, there is provided a semiconductor die package or module manufactured according to the method of the first aspect. Brief Description of the Drawings The present disclosure will be understood more fully from the accompanying drawings, which however, should not be taken to limit the disclosure to the specific embodiments shown, but are for explanation and understanding only. Figure 1 shows an example method for forming a semiconductor die package according to the present disclosure. Figures 2a-c show example components of a semiconductor package at various stages of a method according to the present disclosure. Figures 3a and b show an example semiconductor package according to the present disclosure. Figure 4 shows an example leadframe comprising an interconnection clip according to the present disclosure. Figure 5 shows an example leadframe comprising a plurality of interconnection clips in a strip array according to the present disclosure. Figure 6 shows a further example semiconductor package according to the present disclosure. Detailed Description of the Preferred Embodiments Figure 1 depicts a flow diagram 1000 for an implementation of a method of forming a semiconductor die package using a clip assembly packaging technique according to the present disclosure. In step 2001, a semiconductor die is attached to a first or bottom leadframe. The semiconductor die may be attached to the bottom leadframe via any suitable means, for example via a solder or any other known die attach technology. The bottom leadframe may comprise a conductive material such as (but not limited to) copper, and may be e.g. stamped, etched or otherwise patterned for attachment to the semiconductor die. In step 2002, a second leadframe is formed. The second or top leadframe comprises an array of interconnection clips such as copper clips. For bulk manufacturing, the clips may be formed in a leadframe strip format or other suitable array. However, it will be understood that implementations of the disclosure may be suitable for the manufacture of individual semiconductor die module or packages, for example utilising a top leadframe comprising one or more clips for a single semiconductor die (e.g. one source connection clip and one drain connection clip). The top leadframe may comprise a sheet of conductive material, e.g. copper or other suitable material. Forming the second leadframe may comprise stamping, etching or otherwise forming shapes in the conductive material to act as interconnection clips. In step 2003, the interconnection clips may be formed to shapes suitable for attachment to the semiconductor dies, for example by accounting for height differences in the structures of the semiconductor dies. For example, the interconnection clips forming the second leadframe may be bent or etched (e.g. half-etched to remove a portion of the thickness) to account for the (height) profile of a semiconductor die. It will be understood that this step is optional. For example semiconductor dies, may be configured with all structures provided at an approximately uniform height. Step 2003 may occur simultaneously with the forming of the second leadframe in step 2002, for example in the same stamping or etching process, or may be performed as a separate step after the leadframe is formed. In step 2004, the top leadframe structure including the clip(s) or clip array is attached to the semiconductor dies, such that the semiconductor die are positioned between the top leadframe and the bottom leadframe. The top leadframe is positioned such that each clip is suitably aligned to a given semiconductor die. For example, the top leadframe may comprise a source connection clip and a drain connection clip for each semiconductor die, and the top leadframe may be positioned to align the source connection clip and drain connection clip with the respective source and drain terminals of the semiconductor die. It will be understood that clips for other connections may also be provided, as required or desired for any given semiconductor die design or application. This process therefore facilitates the attachment of all of the interconnection clips to a semiconductor die in a single step, as part of the top leadframe. Moreover, in bulk manufacturing processes the clips for each semiconductor die may be attached to their respective semiconductor dies in the same single step process. Optionally, in steps 2005 and 2006, the semiconductor die module or packages may be overmolded (for example with an epoxy resin or other suitable material) and singulated, to separate the individual die modules or packages. Step 2005 may comprise any suitable conventional transfer mold, compression mold, mold underfill or film assisted mold processes. Similarly, step 2006 may comprise any conventional die singulation process, and may include removing a support frame from the top leadframe and / or a support frame from the bottom leadframe. As such, the singulation step may include cutting, slicing or otherwise separating the top and / or bottom leadframes into sections corresponding to the semiconductor die module or packages. It will be understood that no singulation step may be necessary for example in implementations for manufacturing a single semiconductor die modules or package. By forming a clip or an array of clips on the top leadframe in predetermined locations, the process 1000 may facilitate the consistent placement of interconnection clips in both individual and bulk semiconductor modules or package manufacturing processes, and thereby reduce variations in performances between individual modules or packages while simultaneously improving the throughput of bulk manufacturing processes. Figure 2a illustrates an example semiconductor die 200 attached to a first or bottom leadframe, 202 for example as part of step 2001 of process 1000. In this example, bottom leadframe 202 has been processed (e.g. by stamping, etching, or any other suitable technique) prior to attachment to the semiconductor die. However, it will be understood that the bottom leadframe may not require any such processing. Figure 2b illustrates an example interconnection clips 204a,b formed as part of a second or top leadframe 203, for example formed as part of step 2002 of process 1000. It will be understood that the clip structures may be selected or designed based on the desired or intended semiconductor die for attachment. For example, the clips 204a,b may comprise e.g. a source connection clip, a drain connection clip, and / or any other desired or required interconnection clips. The second leadframe 203 may be formed from e.g. a sheet of copper, or any other suitable material, for example via stamping or etching processes. A “clip structure” may refer to the shape and number of clips formed as part of the top leadframe for a given semiconductor die. Each of the top and and / or bottom leadframes may comprise a support frame such as support frame 206. The support frame may assist in the accurate positioning of the interconnection clips to a semiconductor die, and / or with the accurate positioning of the top and bottom leadframes relative to one another. Figure 2c illustrates a semiconductor die modules or package comprising a top leadframe 203, a bottom leadframe 202 and a semiconductor die 200 positioned between the bottom leadframe 202 and the top leadframe 203. The top leadframe 203 may be attached to the top of the semiconductor die 200 and the bottom leadframe, for example as part of step 2004 of process 1000. The top leadframe 203 is attached to the semiconductor die such that each clip 204a,b is suitably aligned with a respective portion of the semiconductor die 200. The clips may be attached to the semiconductor die via any suitable means, for example but not limited to solder or a conductive epoxy. Figure 3a illustrates an example final semiconductor die modules or package 300a comprising semiconductor die 305, bottom leadframe 301 and interconnection clips 304a. It will be understood that the modules or package 300a may further comprise a mold compound (for example provided as part of step 2005 of process 1000). However, the mold compound is not shown in Figure 3 for improved visibility and clarity. Any support frames for the top and bottom lead frames (such as support frame 206) may be removed, for example during a singulation process or as a further process step. If required, additional die interconnections such as wire bonds 302 may be attached to the die, for example to provide connections between the die and any control pads. In implementations however, all necessary die interconnections may be by clips forming the top leadframe, such that no additional die interconnections are required. It will be understood that any such further die interconnections between the semiconductor die and bottom leadframe (such as wire bonds 302) may also be provided prior to attaching the clip structure to the top of the semiconductor die, for example as part of step 2001 of process 1000. Figure 3b illustrates a cross-section of an example final semiconductor die module or package 300b. The cross-section shows an encapsulation layer 307 comprising a mold compound, provided inside the package 300b. The semiconductor die 305 is attached to the bottom leadframe 301 through a die attach 303. The interconnection clip 304b can be seen attached to the die 305 through a clip attach 306. Example interconnection clip 304b includes connections 308 to bottom leadframe 301, e.g. to provide connections between the semiconductor die 305 and control terminals provided on the bottom leadframe 301. It will be understood that interconnection clip 304b may comprise multiple clips. The die and clip attach layers may comprise any suitable attachment means, for example solder or a conductive epoxy. Figure 4 illustrates a further example top leadframe 400. Leadframe 400 comprises a similar structure to leadframe 203, including a support frame 402 and one or more interconnection clips 404a, 404b. In leadframe 400, connections to the support frame 402 are provided via deformable connections such as tether points 406. Tether points 406 may be designed to be pliable or flexible such that the positioning of the clips 404a, 404b may be adjusted or formed to account for height differences, e.g. between bottom leadframe and the top of semiconductor die or any other parts of the semiconductor die structure. Tether point 406 is depicted as a lateral spring type structure, however it will be understood that any other compliant structures may also be used for tether point 406. The heights and / or positioning of the clips 404a, 404b may be adjusted for example as part of step 2003 of process 1000. Optionally, each clip may include only one tether point, i.e. connecting a single side of the clip to the support structure. In implementations, the single tether point may be the only connection between a clip and the support frame. Alternatively, additional non-compliant connections may also be provided. More generally, it will be understood that clip structure may comprise any number of tether points 406 for each clip, including one, two, three or more tether points. The more tether points that are provided, the more securely and accurately the clip may be positioned relative the support frame. However, a larger number of tether points may increase costs and manufacturing requirements for the clip. Tether points 406 and / or any other connections between the interconnection clips 404a,b and the support frame 402 may be formed in the same process step, for example via stamping or etching. Figure 5 depicts an example leadframe 500 comprising an array of clip structures. The leadframe 500 is provided with a clip array in a strip format, however it will be understood that the clip structures may be provided in other array formats based on the manufacturing needs of a particular use case. For example, hexagonal semiconductor dies may utilise a honeycomb array structure. The array may comprise a plurality of clip structures such as those depicted in leadframes 203 or 400, or any other clip structure design. The leadframe 500 may be a (top) leadframe to facilitate the bulk manufacturing of semiconductor dies. As depicted in Figure 5, a single support frame may be provided for all clip structures, to assist in maintaining the relative positioning of the entire array of clips. Using an array such as that shown in leadframe 500, interconnection clips such as copper clips may be attached to the top of multiple semiconductor dies in a single step, resulting in an improved throughput without reducing the accuracy in the placement of clips. The array of clips may include registration features such as locating holes for jigs and fixtures to improve placement accuracy and throughput. Figure 6 illustrates a cross-section of another example final semiconductor die module or package 600, e.g. after a singulation step is performed to separate each semiconductor package. Here, a conductive layer 608 such as a heat slug 608 is attached on top of the interconnection clip 604, to provide or enhance heat dissipation from the top of the semiconductor module or package. The heat slug may be attached to the interconnection clip 604 through a solder layer 609, or may be attached through any other suitable methods, such as low pressure sintering etc. The conductive layer or heat slug 608 may be formed of any conductive material such as copper, aluminium, or any other material (e.g. metal) that may assist in thermal dissipation and enhance the thermal performance of the package. The heat slug may also be called a heat conducting plate or a heat spreader. A heatsink of a suitable material may further be attached to the top of heat slug of the final package to further increase the thermal performance. Alternatively, the conductive layer 608 be a thermally conductive layer such as a ceramic heatsink or other ceramic layer, to provide electrical isolation in addition to improved thermal performance. This may facilitate cooling from the top surface, e.g. as a dual-side cooled package. The cross-section further shows an encapsulation layer 607 inside the package. The semiconductor die 605 is attached to the bottom leadframe 601 through a die attach 603. The interconnection clip 604 can be seen attached to the die 605 through a clip attach 606. Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and 5 that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein. 10 It will be understood that directional terms such as “top” and “bottom” are provided to assist in the conceptualisation of the invention of the present disclosure, and are not intended to be limiting in nature. 15 Many other effective alternatives will occur to the person skilled in the art. It will be understood that the disclosure is not limited to the described embodiments, but encompasses all the modifications which fall within the spirit and scope of the disclosure.

Claims

1. A method of forming a semiconductor die module, the method comprising: attaching a semiconductor die to a first leadframe; and attaching a second leadframe to the semiconductor die such that the semiconductor die is positioned between the second leadframe and the first leadframe;wherein the second leadframe comprises an interconnection clip such that attaching the second leadframe to the semiconductor die comprises attaching the interconnection clip to the semiconductor die.

2. The method of claim 1, wherein the second leadframe comprises the interconnection clip and a support frame.

3. The method of claim 2, wherein the support frame forms a perimeter of the second leadframe.

4. The method of claim 2 or 3, wherein the interconnection clip is connected to the support frame by one or more deformable connections.

5. The method of claim 4, wherein the one or more deformable connections comprises a lateral spring structure in the plane of the clip structure.

6. The method of claim 4 or 5, comprising deforming the one or more deformable connections to adjust a positioning or profile of the interconnection clip prior to attaching the interconnection clip to the semiconductor die.

7. The method of any preceding claims, comprising bending or etching the interconnection clip based on a profile of the semiconductor die.

8. The method of any one of claims 2 to 7, comprising removing the support frame after attaching the interconnection clip to the semiconductor die.

9. The method of any preceding claim, wherein the second leadframe comprises a plurality of interconnection clips, and attaching the second leadframe to the semiconductor die comprises attaching each of plurality of interconnection clips to the semiconductor die in a single step.

10. The method of claim 9, wherein:attaching the semiconductor die to the first leadframe comprises attaching a plurality of semiconductor dies to the first lead frame, wherein each of the plurality of interconnection clips corresponds to at least one of the plurality of semiconductor dies; andattaching the second leadframe to the semiconductor die comprises attaching each interconnection clip to its respective semiconductor die in a single step.

11. The method of claim 10, comprising singulating each of the plurality of semiconductor dies.

12. The method of any preceding claim, comprising forming an encapsulation layer to encapsulate the semiconductor die after attaching the interconnection clip to the semiconductor die.

13. The method of claim 12, wherein at least part of the interconnection clip extends beyond the encapsulation layer.

14. The method of any preceding claim, wherein the interconnection clip is a copper clip.

15. The method of any preceding claim, wherein the interconnection clip is attached to the semiconductor die comprises with solder or a conductive epoxy.

16. The method of any preceding claim, wherein the interconnection clip is attached to the first leadframe comprises with solder or a conductive epoxy.

17. The method of any preceding claim, wherein the first leadframe comprises one or more control terminals, and wherein attaching the semiconductor die to the first leadframe comprises providing interconnections between the semiconductor die and the one or more control terminals.

18. The method of claim 17, wherein the interconnections are wire bonds.

19. The method of any preceding claim, comprising capping the semiconductor die module with a thermally conductive layer, optionally wherein the thermally conductive layer comprises copper, aluminium or ceramic.

20. The method of claim 19, wherein the thermally conductive layer is attached to the interconnection clip.

21. The method of claim 19 or 20, wherein the thermally conductive layer is a heatsink or is attached to a heat sink.

22. The method of any preceding claim, further comprising forming a semiconductor die package comprising the semiconductor die module, the semiconductor die package configured for attachment to a printed circuit board.

23. The method of any preceding claim, comprising forming the second leadframe, wherein forming the second leadframe comprises stamping or etching a sheet of leadframe material to form one or more interconnection clips.

24. The method of claim 23, wherein the leadframe material is copper.

25. A semiconductor die package or module manufactured according to any preceding claim.

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