Power semiconductor device and method for manufacturing the same
The power semiconductor device optimizes current distribution and reduces on-resistance through a specialized layer structure with differential doping concentrations, addressing the challenge of achieving both low specific on-resistance and high reliability in SiC-based MOSFETs.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- SICHAIN SEMICONDUCTORS (NINGBO) CO LTD
- Filing Date
- 2024-05-29
- Publication Date
- 2026-06-03
AI Technical Summary
Existing SiC-based power MOSFETs face challenges in achieving both low specific on-resistance and high reliability due to the distribution of resistances in channel, JFET, and drift regions, with reliability issues when reducing JFET region resistance.
The power semiconductor device incorporates a semiconductor substrate with a drift layer, a first lateral current diffusion layer, and a device layer, featuring active doping regions and a second lateral current diffusion layer with specific doping concentrations and configurations to optimize current distribution and reduce on-resistance while maintaining reliability.
The solution enhances forward conduction characteristics, reduces on-resistance, and suppresses electric field effects, thereby improving the reliability and performance of the power semiconductor device.
Smart Images
Figure 2026518017000001_ABST
Abstract
Description
Technical Field
[0001] This application claims the priority of Chinese Patent Application CN202310639333.8 titled "Power Semiconductor Device and Manufacturing Method Thereof" filed on May 31, 2023, and all of its contents are incorporated herein by reference.
[0002] The present invention relates to the field of semiconductor technology, and particularly to power semiconductor devices and manufacturing methods thereof.
Background Art
[0003] As a unipolar power switch device, SiC-based power MOSFET plays an important role in the electrical energy conversion of systems such as power supplies and power processing. SiC-based power devices can achieve higher breakdown voltage, lower energy loss, faster switching frequency, and higher operating temperature compared to conventional Si-based power devices. Therefore, they are almost completely compatible with conventional Si-based power devices in the manufacturing process and are highly pursued by the market. Currently, an important parameter restricting the further improvement of the cost price and performance of SiC-based power MOSFET is the specific on-resistance (on-resistance per unit area) during device operation. It is composed of multiple distributed resistances connected in series, with different ratios in each part, and the ratios of the three parts of channel region resistance, JFET region resistance, and drift region resistance are large. Since there are reliability problems when reducing the resistance of the JFET region by improving the quality of gate oxygen on the SiC base or increasing the doping concentration of the JFET region, it is difficult to achieve both low specific on-resistance and high reliability.
Summary of the Invention
Problems to be Solved by the Invention
[0004] Therefore, the technical problem to be solved by the present invention is to overcome the drawback in the prior art that it is difficult to achieve both low specific on-resistance and high reliability, and to provide a power semiconductor device and its manufacturing method. [Means for solving the problem]
[0005] The present invention Semiconductor substrate layer, A drift layer located on one side of the semiconductor substrate layer, A first lateral current diffusion layer is located on the surface opposite to the semiconductor substrate layer of the drift layer, has the same conductivity type as the drift layer, and has a doping concentration greater than that of the drift layer. The first lateral current diffusion layer includes a drift layer and a device layer located on the opposite surface, The aforementioned device layer is Multiple active doping regions are provided at intervals in the lateral direction, It includes a second lateral current diffusion layer located between the active doping region and a portion of the first lateral current diffusion layer, The device layer between the second lateral current diffusion layer and the adjacent active doping region does not have superimposed projection in a direction perpendicular to the surface of the semiconductor substrate layer. The conductivity type of the second lateral current diffusion layer is the same as that of the first lateral current diffusion layer. The doping concentration of the second lateral current diffusion layer is greater than that of the drift layer, providing a power semiconductor device.
[0006] The doping concentration of the first lateral current diffusion layer may be less than the doping concentration of the second lateral current diffusion layer, or the doping concentration of the first lateral current diffusion layer may be greater than or equal to the doping concentration of the second lateral current diffusion layer.
[0007] The doping concentration of the first lateral current diffusion layer may be 0.01 to 1 times the doping concentration of the second lateral current diffusion layer.
[0008] The doping concentration of the first lateral current diffusion layer may be 2 to 5000 times that of the drift layer, and the doping concentration of the second lateral current diffusion layer may also be 2 to 5000 times that of the drift layer.
[0009] The thickness of the second lateral current diffusion layer may be less than the thickness of the first lateral current diffusion layer, or the thickness of the second lateral current diffusion layer may be greater than or equal to the thickness of the first lateral current diffusion layer.
[0010] The thickness of the second lateral current diffusion layer may be 0.2 to 5 times the thickness of the first lateral current diffusion layer.
[0011] The thickness of the first lateral current diffusion layer may be 0.1 μm to 10 μm.
[0012] The thickness of the second lateral current diffusion layer may be 0.1 μm to 10 μm.
[0013] The first lateral current diffusion layer may have a plurality of first lateral current sub-diffusion layers in the thickness direction of the first lateral current diffusion layer.
[0014] The doping concentration of the first lateral current subdiffusion layer may increase along the direction from the side of the first lateral current subdiffusion layer opposite to the semiconductor substrate layer toward the side of the first lateral current subdiffusion layer facing the semiconductor substrate layer.
[0015] The thickness of the first lateral current subdiffusion layer may decrease along the direction from the side of the first lateral current subdiffusion layer opposite to the semiconductor substrate layer toward the side of the first lateral current subdiffusion layer facing the semiconductor substrate layer.
[0016] The second lateral current diffusion layer may have a plurality of second lateral current sub-diffusion layers in the thickness direction of the second lateral current diffusion layer.
[0017] The doping concentration of the second lateral current sub-diffusion layer may decrease along the direction from the side opposite to the semiconductor substrate layer of the second lateral current sub-diffusion layer to the side facing the semiconductor substrate layer of the second lateral current sub-diffusion layer.
[0018] The thickness of the second lateral current sub-diffusion layer may decrease along the direction from the side opposite to the semiconductor substrate layer of the second lateral current sub-diffusion layer to the side facing the semiconductor substrate layer of the second lateral current sub-diffusion layer.
[0019] The power semiconductor device is a vertical metal-oxide semiconductor field-effect transistor. The power semiconductor device further includes a gate structure having the active doping regions on both sides and taking the active doping regions as well regions, and a source region located in the well region and having the same conductivity type as that of the drift layer. The gate structure is located on the upper surface of some of the device layers, or the gate structure may be located in the device layers between adjacent active doping regions and between adjacent second lateral current diffusion layers.
[0020] The power semiconductor device is an insulated-gate bipolar transistor. Taking the active doping region as a well region, the power semiconductor device further includes an emitter region located in the well region, and the conductivity type of the emitter region may be the same as that of the drift layer.
[0021] The present invention further provides a method for manufacturing a power semiconductor device, comprising the steps of: providing a semiconductor substrate layer; and forming a stacked drift layer, a first lateral current diffusion layer, and a device layer on the semiconductor substrate layer from bottom to top, wherein the conductivity type of the first lateral current diffusion layer is the same as that of the drift layer, the doping concentration of the first lateral current diffusion layer is greater than that of the drift layer, and the device layer includes a plurality of active doping regions spaced apart in the lateral direction, and a second lateral current diffusion layer located between the active doping regions and a portion of the first lateral current diffusion layer, wherein there is no superimposed projection between the device layer between the second lateral current diffusion layer and adjacent active doping regions in a direction perpendicular to the surface of the semiconductor substrate layer, the conductivity type of the second lateral current diffusion layer is the same as that of the first lateral current diffusion layer, and the doping concentration of the second lateral current diffusion layer is greater than that of the drift layer.
[0022] The step of forming a stacked drift layer, a first lateral current diffusion layer, and a device layer on the semiconductor substrate layer from bottom to top may include the steps of forming a stacked drift layer, a first lateral current diffusion layer, and an initial device layer on the semiconductor substrate layer from bottom to top; forming a plurality of active doping regions provided at lateral intervals in a portion of the initial device layer; and forming a second lateral current diffusion layer in the initial device layer between the active doping regions and a portion of the first lateral current diffusion layer, thereby forming the initial device layer into a device layer.
[0023] Before forming the active doping region, a mask layer is formed on the surface of a part of the initial device layer, and with the mask layer as a mask, an active doping region is formed in the initial device layer. After forming the active doping region with the mask layer as a mask, a sidewall covering a part of the surface of the active doping region is formed on the sidewall surface of the mask layer. With the sidewall and the mask layer as a mask, a second lateral current diffusion layer is formed between the active doping region and a part of the first lateral current diffusion layer. After forming the second lateral current diffusion layer, the mask layer and the sidewall may be removed.
[0024] The active doping region may be used as a well region, and further include forming a source region in the active doping region with the sidewall and the mask layer as a mask before removing the mask layer and the sidewall.
[0025] The width of the sidewall may be 0.1 μm to 2 μm.
[0026] The step of forming a stacked drift layer, a first lateral current diffusion layer, and an initial device layer on the semiconductor substrate layer from bottom to top includes the steps of epitaxially forming the drift layer on the semiconductor substrate layer, epitaxially forming the first lateral current diffusion layer on the surface of the drift layer opposite to the semiconductor substrate layer, and epitaxially forming the initial device layer on the surface of the first lateral current diffusion layer opposite to the drift layer, or forming a stacked drift layer, a first lateral current diffusion layer, and an initial device layer on the semiconductor substrate layer from bottom to top The step of forming the device layer includes the steps of epitaxially forming an initial drift layer on the semiconductor substrate layer, forming a first lateral current diffusion layer on the initial drift layer of a certain thickness using an ion implantation process, wherein the initial drift layer below the first lateral current diffusion layer constitutes a drift layer, and epitaxially forming an initial device layer on the surface of the first lateral current diffusion layer opposite to the drift layer, or forming a stacked drift layer, a first lateral current diffusion layer and an initial device layer on the semiconductor substrate layer from bottom to top. The steps of forming a semiconductor layer include: epitaxially forming an initial drift layer on the semiconductor substrate layer; forming a first initial lateral current diffusion layer on the initial drift layer of a certain thickness using an ion implantation process; and forming an initial device layer on the first initial lateral current diffusion layer of a certain thickness using an ion implantation process, wherein the first initial lateral current diffusion layer below the initial device layer constitutes a first lateral current diffusion layer, and the initial drift layer below the first lateral current diffusion layer constitutes a drift layer, or the semiconductor The steps of forming a stacked drift layer, a first lateral current diffusion layer, and an initial device layer on a semiconductor substrate layer from bottom to top may include: epitaxially forming a drift layer on the semiconductor substrate layer; epitaxially forming a first initial lateral current diffusion layer on the side of the drift layer opposite to the semiconductor substrate layer; and forming an initial device layer on a first initial lateral current diffusion layer of a certain thickness using an ion implantation process, wherein the first initial lateral current diffusion layer below the initial device layer constitutes the first lateral current diffusion layer.
[0027] The technical proposal of the present invention has the following advantages. In the power semiconductor device according to the proposed technology of the present invention, when forward conduction occurs, current flows along the edge of the active doping region and the device layer adjacent to the active doping region to the bottom of the active doping region and the second lateral current diffusion layer adjacent to the active doping region, and then conducts in the direction of the first lateral current diffusion layer and the semiconductor substrate layer. Since the second lateral current diffusion layer is provided at the bottom of the active doping region and the doping concentration of the second lateral current diffusion layer is greater than the doping concentration of the drift layer, the width of the depletion layer formed by the active doping region and the second lateral current diffusion layer is narrowed, a depletion layer is formed in a part of the second lateral current diffusion layer, and the doping concentration in the region located at the bottom of the depletion layer in the second lateral current diffusion layer is relatively large, so the current can rapidly diffuse along the edge of the active doping region toward the second lateral current diffusion layer, thereby improving the forward conduction characteristics and contributing to a reduction in forward conduction resistance. A first lateral current diffusion layer is provided, and since the doping concentration of the first lateral current diffusion layer is greater than that of the drift layer, the first lateral current diffusion layer can further diverte the current flowing through the second lateral current diffusion layer, making the current distribution more uniform, maximizing compensation for the degree of current congestion at the top of the spaced-out second lateral current diffusion layer, and contributing to a reduction in forward conduction resistance, thereby effectively reducing relative on-resistance. Since there is no superimposed projection of the device layer between the second lateral current diffusion layer and the adjacent active doping region in the direction perpendicular to the surface of the semiconductor substrate layer, the second lateral current diffusion layer contributes to reducing the electric field on the surface of the device layer between adjacent active doping regions. Since the distance from the first lateral current diffusion layer to the surface of the device layer is greater than the distance from the second lateral current diffusion layer to the surface of the device layer, the influence of the first lateral current diffusion layer on the electric field on the surface of the device layer between adjacent active doping regions is small, and the decrease in reverse breakdown voltage is suppressed. Reliability is improved. [Brief explanation of the drawing]
[0028] To more clearly describe specific embodiments of the present invention or technical concepts in the prior art, the drawings that may be used to describe specific embodiments or the prior art will be briefly described below. Clearly, the drawings in the following description are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these without any creative work. [Figure 1] Figure 1 is a schematic diagram of the structure of a power semiconductor device according to one embodiment of the present invention. [Figure 2] Figure 2 is a schematic diagram of the structure of a power semiconductor device according to another embodiment of the present invention. [Figure 3] Figure 3 is a schematic diagram of the manufacturing process of a power semiconductor device according to one embodiment of the present invention. [Figure 4] Figure 4 is a schematic diagram of the manufacturing process of a power semiconductor device according to one embodiment of the present invention. [Figure 5] Figure 5 is a schematic diagram of the manufacturing process of a power semiconductor device according to one embodiment of the present invention. [Figure 6] Figure 6 is a schematic diagram of the manufacturing process of a power semiconductor device according to one embodiment of the present invention. [Figure 7] Figure 7 is a schematic diagram of the manufacturing process of a power semiconductor device according to one embodiment of the present invention. [Figure 8] Figure 8 is a schematic diagram of the manufacturing process of a power semiconductor device according to one embodiment of the present invention. [Figure 9] Figure 9 is a schematic diagram of the manufacturing process of a power semiconductor device according to one embodiment of the present invention. [Figure 10] Figure 10 is a schematic diagram of the manufacturing process of a power semiconductor device according to one embodiment of the present invention. [Figure 11] Figure 11 is a schematic diagram of the manufacturing process of a power semiconductor device according to one embodiment of the present invention. [Figure 12] Figure 12 is a schematic diagram of the manufacturing process of a power semiconductor device according to another embodiment of the present invention. [Modes for carrying out the invention]
[0029] The technical aspects of the present invention will be described clearly and completely below with reference to the drawings, and it is clear that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments obtained by those skilled in the art without creative work based on the embodiments of the present invention are within the scope of the protection of the present invention.
[0030] In the description of this invention, directions or positional relationships indicated by terms such as "center," "top," "bottom," "left," "right," "vertical," "horizontal," "inside," and "outside" are based on the directions or positional relationships shown in the drawings and are merely for the convenience and simplification of the description of this invention. They do not indicate or imply that the shown devices or elements have a specific direction or must be configured and operated in a specific direction, and should not be understood as limiting the invention. Furthermore, the terms "first," "second," and "third" are merely for descriptive purposes and should not be understood as indicating or implying relative importance.
[0031] In the description of this invention, unless otherwise specifically defined or limited, the terms "attachment," "connection," and "connection" should be understood in a broad sense. For example, they may be fixed connections, removable connections, integral connections, mechanical connections, electrical connections, direct connections, indirect connections via an intermediate medium, or internal communication between two elements. Those skilled in the art will be able to specifically understand the concrete meaning of the above terms in this invention.
[0032] Furthermore, the technical features of the different embodiments of the present invention described below can be combined with each other, as long as they do not contradict each other.
[0033] One embodiment of the present invention provides a power semiconductor device. Referring to Figure 1, Semiconductor substrate layer 100, A drift layer 110 located on one side of the semiconductor substrate layer 100, A first lateral current diffusion layer 120 is located on the surface of the drift layer 110 opposite to the semiconductor substrate layer 100, has the same conductivity type as the drift layer 110, and has a doping concentration greater than the doping concentration of the drift layer 110, The first lateral current diffusion layer 120 includes a device layer 130 located on the surface opposite to the drift layer 110, The device layer 130 is Multiple active doping regions 1302 are provided at intervals in the lateral direction, It includes a second lateral current diffusion layer 1301 located between the active doping region 1302 and a portion of the first lateral current diffusion layer 120, The device layer 130 between the second lateral current diffusion layer 1301 and the adjacent active doping region 1302 does not have superimposed projection in a direction perpendicular to the surface of the semiconductor substrate layer 100. The conductivity type of the second lateral current diffusion layer 1301 is the same as that of the first lateral current diffusion layer 120, and the doping concentration of the second lateral current diffusion layer 1301 is greater than the doping concentration of the drift layer 110.
[0034] In this embodiment, during forward conduction, the current flows along the edge of the active doping region and the device layer adjacent to the active doping region to the bottom of the active doping region and the second lateral current diffusion layer adjacent to the active doping region, and then conducts in the direction of the first lateral current diffusion layer and the semiconductor substrate layer. Since the second lateral current diffusion layer is provided at the bottom of the active doping region and the doping concentration of the second lateral current diffusion layer is greater than the doping concentration of the drift layer, the width of the depletion layer formed by the active doping region and the second lateral current diffusion layer is narrowed, a depletion layer is formed in part of the second lateral current diffusion layer, and the doping concentration in the region located at the bottom of the depletion layer in the second lateral current diffusion layer is relatively large, so the current can rapidly diffuse along the edge of the active doping region toward the second lateral current diffusion layer, thereby improving the forward conduction characteristics and contributing to a reduction in forward conduction resistance. A first lateral current diffusion layer is provided, and since the doping concentration of the first lateral current diffusion layer is greater than that of the drift layer, the first lateral current diffusion layer can further diverte the current flowing through the second lateral current diffusion layer, making the current distribution more uniform, maximizing compensation for the degree of current congestion at the top of the spaced-out second lateral current diffusion layer, and contributing to a reduction in forward conduction resistance, thereby effectively reducing relative on-resistance. Since there is no superimposed projection of the device layer between the second lateral current diffusion layer and the adjacent active doping region in the direction perpendicular to the surface of the semiconductor substrate layer, the second lateral current diffusion layer contributes to reducing the electric field on the surface of the device layer between adjacent active doping regions. Since the distance from the first lateral current diffusion layer to the surface of the device layer is greater than the distance from the second lateral current diffusion layer to the surface of the device layer, the first lateral current diffusion layer also does not significantly affect the electric field on the surface of the device layer between adjacent active doping regions, suppressing a decrease in reverse breakdown voltage. This improves reliability.
[0035] As shown in the cross-sectional view in Figure 1, the second lateral current diffusion layer 1301 does not extend below the region between adjacent active doping regions 1302; in other words, the second lateral current diffusion layer 1301 does not extend to a position directly opposite the region between adjacent active doping regions 1302 and the surface of the semiconductor substrate layer 100 in a direction perpendicular to it.
[0036] In one embodiment, the doping concentration of the first lateral current diffusion layer 120 is lower than that of the second lateral current diffusion layer 1301. The advantages of this are that, because the doping concentration of the second lateral current diffusion layer 1301 is higher than that of the first lateral current diffusion layer 120, the second lateral current diffusion layer 1301 with a higher doping concentration contributes to a reduction in relative on-resistance. Furthermore, the doping concentration of the second lateral current diffusion layer 1301 is high, and the second lateral current diffusion layer 1301 is located below the active doping region, that is, the second lateral current diffusion layer 1301 is located below the active doping region 1302 of the semiconductor substrate layer. The second lateral current diffusion layer 1301 is located on the side facing 100, and its influence on the electric field on the surface of the device layer between adjacent active doping regions is low, suppressing problems such as a decrease in breakdown voltage. Furthermore, because the doping concentration of the first lateral current diffusion layer 120 is low, the doping concentration of the first lateral current diffusion layer 120 located in the lower region between adjacent active doping regions is low, avoiding an increase in the electric field on the surface of the device layer. In addition, because the distance from the first lateral current diffusion layer 120 to the surface of the device layer is large, the influence on the electric field on the surface of the device layer between adjacent active doping regions can be further reduced.
[0037] In one embodiment, the doping concentration of the first lateral current diffusion layer 120 is 0.01 to 1 times the doping concentration of the second lateral current diffusion layer 1301, for example, 0.01 times, 0.02 times, 0.05 times, 0.08 times, 0.1 times, 0.5 times, 0.8 times, or 1 time.
[0038] In one embodiment, the doping concentration of the first lateral current diffusion layer 120 is 2 to 5000 times the doping concentration of the drift layer 110, for example, 2, 10, 100, 500, 1000, 2000, or 5000 times, and the doping concentration of the second lateral current diffusion layer 1301 is 2 to 5000 times the doping concentration of the drift layer 110, for example, 2, 10, 100, 500, 1000, 2000, or 5000 times.
[0039] In other embodiments, the doping concentration of the first lateral current diffusion layer is equal to or greater than the doping concentration of the second lateral current diffusion layer.
[0040] In one embodiment, the thickness of the second lateral current diffusion layer 1301 is smaller than the thickness of the first lateral current diffusion layer 120. The advantages of this are that the smaller thickness of the second lateral current diffusion layer 1301 contributes to improving the reverse breakdown voltage, and the smaller thickness of the second lateral current diffusion layer 1301 reduces the distance from the first lateral current diffusion layer 120 to the bottom surface of the active doping region, allowing the current to diffuse more quickly and reducing the relative on-resistance. Furthermore, if the thickness of the first lateral current diffusion layer 120 is large and the doping concentration of the first lateral current diffusion layer 120 is small, the larger thickness of the first lateral current diffusion layer 120 can further enhance the effect of the small doping concentration on the reverse breakdown voltage, thereby improving the reverse breakdown voltage.
[0041] In one embodiment, the thickness direction of the second lateral current diffusion layer 1301 is perpendicular to the surface of the semiconductor substrate layer 100, or in other words, the thickness direction of the second lateral current diffusion layer 1301 is parallel to the direction from the side of the second lateral current diffusion layer 1301 opposite to the semiconductor substrate layer 100 to the side of the second lateral current diffusion layer 1301 facing the semiconductor substrate layer 100.
[0042] In other embodiments, the thickness of the second lateral current diffusion layer is less than or equal to the thickness of the first lateral current diffusion layer.
[0043] In one embodiment, the thickness of the second lateral current diffusion layer 1301 is 0.2 to 5 times, 0.2 times, 0.5 times, 0.8 times, 1 time, 2 times, 3 times, 4 times, or 5 times the thickness of the first lateral current diffusion layer 120.
[0044] In one embodiment, the thickness of the first lateral current diffusion layer 120 is 0.1 μm to 10 μm, and in one embodiment, the thickness of the second lateral current diffusion layer 1301 is 0.1 μm to 10 μm.
[0045] In one embodiment, the thickness direction of the first lateral current diffusion layer 120 is perpendicular to the surface of the semiconductor substrate layer 100; in other words, the thickness direction of the first lateral current diffusion layer 120 is parallel to the direction from the side of the first lateral current diffusion layer 120 opposite to the semiconductor substrate layer 100 to the side of the first lateral current diffusion layer 120 facing the semiconductor substrate layer 100.
[0046] In one embodiment, the doping concentration of the first lateral current diffusion layer 120 is smaller than the doping concentration of the second lateral current diffusion layer 1301, and the thickness of the second lateral current diffusion layer 1301 is smaller than the thickness of the first lateral current diffusion layer.
[0047] In this embodiment, the first lateral current diffusion layer 120 has a single-layer structure, and the second lateral current diffusion layer 1301 has a single-layer structure.
[0048] In other embodiments, the first lateral current diffusion layer 120 has a plurality of first lateral current sub-diffusion layers in the thickness direction of the first lateral current diffusion layer 120, and in this way, the doping concentration of the first lateral current diffusion layer 120 can be divided into sections. Preferably, the doping concentration of the first lateral current sub-diffusion layer increases along the direction from the side of the first lateral current sub-diffusion layer opposite the semiconductor substrate layer 100 to the side of the first lateral current sub-diffusion layer facing the semiconductor substrate layer 100, that is, in the cross-sectional view shown in Figure 1, the advantage of the doping concentration of the first lateral current sub-diffusion layer increasing from top to bottom is that the doping concentration of the upper first lateral current sub-diffusion layer is low, and the influence on the electric field of the device layer surface between adjacent active doping regions by the upper first lateral current sub-diffusion layer with a low doping concentration is lower. Preferably, the thickness of the first lateral current subdiffusion layer decreases along the direction from the side of the first lateral current subdiffusion layer opposite the semiconductor substrate layer 100 toward the side of the first lateral current subdiffusion layer facing the semiconductor substrate layer 100. That is, in the cross-sectional view shown in Figure 1, the thickness of the first lateral current subdiffusion layer decreases from top to bottom, and the upper first lateral current subdiffusion layer, which is thicker, contributes to improving the reverse breakdown voltage.
[0049] In other embodiments, the second lateral current diffusion layer 1301 has a plurality of second lateral current sub-diffusion layers in the thickness direction of the second lateral current diffusion layer 1301, and in this way, the doping concentration of the second lateral current diffusion layer 1301 can be divided into sections. Preferably, the doping concentration of the second lateral current sub-diffusion layer decreases along the direction from the side of the second lateral current sub-diffusion layer opposite to the semiconductor substrate layer 100 toward the side of the second lateral current sub-diffusion layer facing the semiconductor substrate layer 100, that is, in the cross-sectional view shown in Figure 1, the doping concentration of the second lateral current sub-diffusion layer decreases from top to bottom, and the upper second lateral current sub-diffusion layer with a higher doping concentration contributes to the reduction of relative on-resistance. Preferably, the thickness of the second lateral current subdiffusion layer decreases along the direction from the side of the second lateral current subdiffusion layer opposite to the semiconductor substrate layer 100 toward the side of the second lateral current subdiffusion layer facing the semiconductor substrate layer 100. That is, in the cross-sectional view shown in Figure 1, the thickness of the second lateral current subdiffusion layer decreases from top to bottom, and the upper second lateral current subdiffusion layer, which is thicker, contributes to reducing the relative on-resistance.
[0050] In this embodiment, the second lateral current diffusion layer 1301 is adjacent to the bottom surface of the active doping region 1302, that is, the second lateral current diffusion layer 1301 is adjacent to the surface of the active doping region 1302 facing the semiconductor substrate layer, and the first lateral current diffusion layer 120 is adjacent to the bottom surface of the second lateral current diffusion layer 1301, that is, the first lateral current diffusion layer 120 is adjacent to the surface of the second lateral current diffusion layer 1301 facing the semiconductor substrate layer.
[0051] In other embodiments, a certain distance is provided between the second lateral current diffusion layer and the bottom surface of the active doping region, for example, the distance between the second lateral current diffusion layer and the active doping region is 2 μm or less. A certain distance is maintained between the first lateral current diffusion layer and the second lateral current diffusion layer, for example, the distance between the first lateral current diffusion layer and the second lateral current diffusion layer is 2 μm or less.
[0052] In this embodiment, the power semiconductor device is a vertical metal oxide semiconductor field-effect transistor, and the power semiconductor device further includes a gate structure 140, the gate structure 140 is located on the upper surface of a portion of the device layer 130, and the gate structure 140 has active doping regions 1302 on both sides, the active doping regions 1302 are well regions, and the source region 1303 located in the well region has a conductivity type that is the same as the conductivity type of the drift layer 110. The gate structure 140 includes a gate dielectric layer 1401 and a gate electrode layer 1402.
[0053] Referring to Figure 1, the device layer 130 further includes an ohmic contact layer 1304 located in a portion of the active doping region 1302, and a JFET region 1305 located at the bottom of the gate structure 140 and between adjacent active doping regions 1302 and between adjacent second lateral current diffusion layers 1301. The first lateral current diffusion layer 120 is located below the second lateral current diffusion layer 1301 and the JFET region 1305.
[0054] In another embodiment, referring to Figure 2, the power semiconductor device is a vertical metal oxide semiconductor field-effect transistor, the power semiconductor device further includes a gate structure 170, the active doping regions 1302 on both sides of the gate structure 170, the active doping regions 1302 are well regions, the source region 1303 located in the well region has a conductivity type that is the same as the conductivity type of the drift layer, the difference between the power semiconductor device of Figure 2 and the power semiconductor device of Figure 1 is that the gate structure 170 is located in the device layer between adjacent active doping regions 1302 and adjacent second lateral current diffusion layers 1301. The gate structure 170 includes a gate dielectric layer 1702 and a gate electrode layer 1701.
[0055] Referring to Figure 2, the power semiconductor device further includes an additional doping region 1306 between the gate structure 170 and the first lateral current diffusion layer 120, wherein the conductivity type of the additional doping region 1306 is opposite to that of the first lateral current diffusion layer 120, and the doping concentration of the additional doping region 1306 is greater than that of the drift layer 110. If the conductivity type of the first lateral current diffusion layer 120 is N-type, then the conductivity type of the additional doping region 1306 is P-type.
[0056] The additional doping region 1306 and the first lateral current diffusion layer 120, and the additional doping region 1306 and the second lateral current diffusion layer 1301, all form space charge regions. When there are multiple gate structures 170, the space charge regions below different gate structures 170 overlap, shielding the electric field strength at the location of the gate dielectric layer 1702 and reducing the electric field strength at the location of the gate dielectric layer 1702.
[0057] In another embodiment, the power semiconductor device is an insulated gate bipolar transistor, the active doping region is a well region, the power semiconductor device further includes an emitter region located in the well region, and the conductivity type of the emitter region is the same as the conductivity type of the drift layer.
[0058] Another embodiment of the present invention provides a method for manufacturing a power semiconductor device comprising the steps of providing a semiconductor substrate layer and forming a laminated drift layer, a first lateral current diffusion layer, and a device layer on the semiconductor substrate layer from bottom to top, wherein the conductivity type of the first lateral current diffusion layer is the same as that of the drift layer, the doping concentration of the first lateral current diffusion layer is greater than that of the drift layer, and the device layer includes a plurality of active doping regions spaced apart in the lateral direction and a second lateral current diffusion layer located between the active doping regions and a portion of the first lateral current diffusion layer, wherein there is no superimposed projection between the device layer and the adjacent active doping region in a direction perpendicular to the surface of the semiconductor substrate layer, the conductivity type of the second lateral current diffusion layer is the same as that of the first lateral current diffusion layer, and the doping concentration of the second lateral current diffusion layer is greater than that of the drift layer.
[0059] In one embodiment, the step of forming a stacked drift layer, a first lateral current diffusion layer, and a device layer on the semiconductor substrate layer from bottom to top includes the steps of forming a stacked drift layer, a first lateral current diffusion layer, and an initial device layer on the semiconductor substrate layer from bottom to top; forming a plurality of active doping regions provided at lateral intervals in a portion of the initial device layer; and forming a second lateral current diffusion layer in the initial device layer between the active doping regions and a portion of the first lateral current diffusion layer, thereby forming the initial device layer into a device layer.
[0060] The manufacturing process for power semiconductor devices will be explained below with reference to Figures 3 through 11.
[0061] Referring to Figures 3 to 5, a drift layer 110, a first lateral current diffusion layer 120, and an initial device layer 130a are formed on the semiconductor substrate layer 100 from bottom to top.
[0062] The conductivity type of the initial device layer 130a is the same as that of the drift layer 110. In one embodiment, the conductivity type of the drift layer 110 is N-type, and the conductivity type of the initial device layer 130a is N-type.
[0063] The doping concentration of the initial device layer 130a is lower than the doping concentration of the first lateral current diffusion layer and lower than the doping concentration of the second lateral current diffusion layer.
[0064] In one embodiment, the doping concentration of the initial device layer 130a is 1 × 10⁻⁶ 15 atom / cm 3 ~1 × 10 17 atom / cm 3 The doping concentration of the drift layer 110 is 1 × 10⁻⁶. 15 atom / cm 3 ~1 × 10 17 atom / cm 3 That is the case.
[0065] In this embodiment, the steps of forming a stacked drift layer 110, a first lateral current diffusion layer 120, and an initial device layer 130a on the semiconductor substrate layer 100 from bottom to top include, with reference to Figures 3 to 5, the steps of epitaxially forming the drift layer 110 on the semiconductor substrate layer 100, epitaxially forming the first lateral current diffusion layer 120 on the surface of the drift layer 110 opposite to the semiconductor substrate layer 100, and epitaxially forming the initial device layer 130a on the surface of the first lateral current diffusion layer 120 opposite to the drift layer 110.
[0066] In other embodiments, the steps of forming a stacked drift layer, a first lateral current diffusion layer, and an initial device layer on the semiconductor substrate layer from bottom to top include: epitaxially forming an initial drift layer on the semiconductor substrate layer; forming a first lateral current diffusion layer on the initial drift layer to a certain thickness using an ion implantation process, wherein the initial drift layer below the first lateral current diffusion layer constitutes a drift layer; and epitaxially forming an initial device layer on the surface of the first lateral current diffusion layer opposite to the drift layer.
[0067] In another embodiment, the step of forming a stacked drift layer, a first lateral current diffusion layer, and an initial device layer on the semiconductor substrate layer from bottom to top includes the steps of epitaxially forming the initial drift layer on the semiconductor substrate layer, forming a first initial lateral current diffusion layer on the initial drift layer of a certain thickness using an ion implantation process, and forming an initial device layer on the first initial lateral current diffusion layer of a certain thickness using an ion implantation process, wherein the first initial lateral current diffusion layer below the initial device layer constitutes the first lateral current diffusion layer. In this case, the initial drift layer below the first lateral current diffusion layer constitutes the drift layer, and the conductivity type of the conductive ions injected when forming the initial device layer in the first initial lateral current diffusion layer of a certain thickness is opposite to the conductivity type of the conductive ions injected when forming the first initial lateral current diffusion layer in the initial drift layer of a certain thickness, and the conductive ions injected when forming the initial device layer in the first initial lateral current diffusion layer of a certain thickness neutralize a portion of the conductive ions injected when forming the first initial lateral current diffusion layer in the initial drift layer of a certain thickness.
[0068] In another embodiment, the step of forming a stacked drift layer, a first lateral current diffusion layer, and an initial device layer on the semiconductor substrate layer from bottom to top includes the steps of epitaxially forming the drift layer on the semiconductor substrate layer, epitaxially forming the first initial lateral current diffusion layer on the side of the drift layer opposite to the semiconductor substrate layer, and forming an initial device layer on the first initial lateral current diffusion layer of a certain thickness using an ion implantation process, wherein the first initial lateral current diffusion layer below the initial device layer constitutes the first lateral current diffusion layer. In this case, the conductive ions implanted in the initial device layer formed on the first initial lateral current diffusion layer of a certain thickness have opposite conductivity types to the conductive ions formed on the first initial lateral current diffusion layer, and the conductive ions implanted in the initial device layer formed on the first initial lateral current diffusion layer of a certain thickness neutralize some of the conductive ions in the first initial lateral current diffusion layer.
[0069] Referring to Figure 7, a plurality of active doping regions 1302 are formed in a portion of the initial device layer 130a, spaced apart in the lateral direction.
[0070] There is a constant vertical distance between the active doping region 1302 and the first lateral current diffusion layer 120, and the active doping region 1302 and the first lateral current diffusion layer 120 are spaced apart. The conductivity type of the active doping region 1302 is opposite to that of the initial device layer 130a and opposite to that of the drift layer.
[0071] The initial device layer 130a exposes the top surface of the initial device layer 130a. The top surface of the initial device layer 130a and the top surface of the active doping region 1302 are flush.
[0072] In this embodiment, before forming the active doping region 1302, a mask layer 150 is formed on a portion of the initial device layer 130a, as shown in Figure 6, and the active doping region 1302 is formed on the initial device layer 130a using the mask layer 150 as a mask, as shown in Figure 7.
[0073] Referring to Figure 8, after forming the active doping region 1302 on the initial device layer 130a using the mask layer 150 as a mask, a sidewall 160 is formed on the side surface of the mask layer 150, and the sidewall 160 covers a portion of the surface of the active doping region 1302.
[0074] The material of the sidewall 160 includes silicon oxide or silicon nitride.
[0075] In one embodiment, the width of the sidewall 160 is 0.1 μm to 2 μm, 0.1 μm, 0.5 μm, 0.8 μm, 1 μm, 1.5 μm, or 2 μm.
[0076] Referring to Figure 9, a second lateral current diffusion layer 1301 is formed in the initial device layer 130a between the active doping region 1302 and a portion of the first lateral current diffusion layer 120.
[0077] Specifically, the sidewall 160 and the mask layer 150 are used as a mask to form a second lateral current diffusion layer 1301 between the active doping region 1302 and a portion of the first lateral current diffusion layer 120.
[0078] The process of forming a second lateral current diffusion layer 1301 in the initial device layer 130a between the active doping region 1302 and a portion of the first lateral current diffusion layer 120 is an ion implantation process.
[0079] The sidewall 160 and mask layer 150 are used to define the position of the second lateral current diffusion layer 1301. The sidewall 160 enables self-aligned ion implantation of the second lateral current diffusion layer 1301, and because the second lateral current diffusion layer 1301 is located directly beneath the active doping region 1302 and does not affect the JFET region, the electric field strength on the surface of the JFET region can still be kept low, thus avoiding an impact on the reverse breakdown voltage and reliability of the power semiconductor device.
[0080] The sidewall 160 enables self-aligned ion implantation of the second lateral current diffusion layer 1301, which does not increase the doping concentration in the JFET region. As a result, the pinch-off effect in the JFET region is not affected by the second lateral current diffusion layer 1301, allowing for a low pinch-off voltage, further reducing gate leakage capacitance, and lowering switching losses.
[0081] Making the active doping region 1302 a well region further includes forming a source region 1303 in the active doping region 1302 using the sidewall 160 and the mask layer 150 as a mask. The conductivity type of the source region 1303 is opposite to that of the active doping region 1302.
[0082] In this embodiment, the spacing between adjacent second lateral current diffusion layers 1301 is greater than the spacing between adjacent active doping regions 1302, and the lateral dimensions of the second lateral current diffusion layer 1301 are smaller than the lateral dimensions of the active doping regions 1302.
[0083] In other embodiments, masks of different dimensions may be used such that the lateral dimensions of the second lateral current diffusion layer are equal to the lateral dimensions of the active doping region.
[0084] Referring to Figure 10, after forming the second lateral current diffusion layer 1301 and the source region 1303, the mask layer 150 and the sidewall 160 are removed.
[0085] Referring to Figure 10, the invention further includes forming an ohmic contact layer 1304 in a portion of the active doping region 1302, wherein the conductivity type of the ohmic contact layer 1304 is the same as that of the active doping region 1302, and the doping concentration of the ohmic contact layer 1304 is greater than that of the active doping region 1302.
[0086] The device layer located at the bottom of the gate structure 140 and between adjacent active doping regions 1302 and adjacent second lateral current diffusion layers 1301 is the JFET region 1305. The first lateral current diffusion layer 120 is located below the second lateral current diffusion layer 1301 and the JFET region 1305.
[0087] Referring to Figure 11, a gate structure 170 is formed on a portion of the surface of the device layer, and the active doping regions 1302 are located on both sides of the gate structure 170, with the active doping regions 1302 serving as well regions.
[0088] In this embodiment, the active doping region is formed first, followed by the formation of the second lateral current diffusion layer. In other embodiments, the active doping region is formed after the formation of the second lateral current diffusion layer.
[0089] Another embodiment of the present invention further provides a method for manufacturing a power semiconductor device, referring to Figure 12, which is a schematic diagram based on Figure 10, wherein a gate structure 170 is formed in a device layer between adjacent active doping regions 1302 and between adjacent second lateral current diffusion layers 1301. The gate structure 170 includes a gate dielectric layer 1702 and a gate electrode layer 1701. The source region 1303 and the gate structure 170 are adjacent.
[0090] In conventional drift region resistance, electrons do not enter the drift region and distribute uniformly after flowing out of the JFET region; instead, the electron flow becomes congested in the apex region, causing an increase in on-resistance. This invention is an optimization technique that optimizes this region to suppress problems such as a decrease in breakdown voltage and an increase in leakage current in other device parameters, while ensuring that other main performance parameters and reliability are not affected, thereby reducing the relative on-resistance as much as possible.
[0091] Clearly, the embodiments described above are merely illustrative for clarity and do not limit the embodiments. Those skilled in the art can make other different forms of changes or variations based on the above description. It is not necessary, nor is it possible, to cover all embodiments. The obvious changes or variations thus derived still fall within the scope of the invention.
Claims
1. Semiconductor substrate layer, A drift layer located on one side of the semiconductor substrate layer, A first lateral current diffusion layer is located on the surface opposite to the semiconductor substrate layer of the drift layer, has the same conductivity type as the drift layer, and has a doping concentration greater than that of the drift layer. The first lateral current diffusion layer includes a drift layer and a device layer located on the opposite surface, The aforementioned device layer is Multiple active doping regions are provided at intervals in the lateral direction, It includes a second lateral current diffusion layer located between the active doping region and a portion of the first lateral current diffusion layer, The device layer between the second lateral current diffusion layer and the adjacent active doping region does not have superimposed projection in a direction perpendicular to the surface of the semiconductor substrate layer. The conductivity type of the second lateral current diffusion layer is the same as that of the first lateral current diffusion layer. A power semiconductor device characterized in that the doping concentration of the second lateral current diffusion layer is greater than the doping concentration of the drift layer.
2. The doping concentration of the first lateral current diffusion layer is less than the doping concentration of the second lateral current diffusion layer, or the doping concentration of the first lateral current diffusion layer is greater than or equal to the doping concentration of the second lateral current diffusion layer. Preferably, the doping concentration of the first lateral current diffusion layer is 0.01 to 1 times the doping concentration of the second lateral current diffusion layer. Preferably, the doping concentration of the first lateral current diffusion layer is 2 to 5000 times that of the drift layer, and the doping concentration of the second lateral current diffusion layer is 2 to 5000 times that of the drift layer, characterized in that the power semiconductor device according to claim 1.
3. The thickness of the second lateral current diffusion layer is less than the thickness of the first lateral current diffusion layer, or the thickness of the second lateral current diffusion layer is greater than or equal to the thickness of the first lateral current diffusion layer. Preferably, the thickness of the second lateral current diffusion layer is 0.2 to 5 times the thickness of the first lateral current diffusion layer. Preferably, the thickness of the first lateral current diffusion layer is 0.1 μm to 10 μm. Preferably, the power semiconductor device according to claim 1 or 2, characterized in that the thickness of the second lateral current diffusion layer is 0.1 μm to 10 μm.
4. The first lateral current diffusion layer has a plurality of first lateral current sub-diffusion layers in the thickness direction of the first lateral current diffusion layer, Preferably, the doping concentration of the first lateral current subdiffusion layer increases progressively along the direction from the side of the first lateral current subdiffusion layer opposite the semiconductor substrate layer to the side of the first lateral current subdiffusion layer facing the semiconductor substrate layer. Preferably, the power semiconductor device according to claim 1, characterized in that the thickness of the first lateral current subdiffusion layer decreases along the direction from the side of the first lateral current subdiffusion layer opposite to the semiconductor substrate layer toward the side of the first lateral current subdiffusion layer facing the semiconductor substrate layer.
5. The second lateral current diffusion layer has a plurality of second lateral current sub-diffusion layers in the thickness direction of the second lateral current diffusion layer, Preferably, the doping concentration of the second lateral current subdiffusion layer decreases along the direction from the side of the second lateral current subdiffusion layer opposite the semiconductor substrate layer to the side of the second lateral current subdiffusion layer facing the semiconductor substrate layer. Preferably, the power semiconductor device according to claim 1, characterized in that the thickness of the second lateral current subdiffusion layer decreases along the direction from the side of the second lateral current subdiffusion layer opposite to the semiconductor substrate layer toward the side of the second lateral current subdiffusion layer facing the semiconductor substrate layer.
6. The power semiconductor device is a vertical metal oxide semiconductor field-effect transistor, and the power semiconductor device further includes a gate structure having the active doping regions on both sides and the active doping regions being well regions, and a source region located in the well region and having the same conductivity type as the drift layer, The power semiconductor device according to claim 1, characterized in that the gate structure is located on the upper surface of a portion of the device layer, or the gate structure is located in a device layer between adjacent active doping regions and between adjacent second lateral current diffusion layers.
7. The power semiconductor device according to claim 1, wherein the power semiconductor device is an insulated gate bipolar transistor, the active doping region is a well region, the power semiconductor device further includes an emitter region located in the well region, and the conductivity type of the emitter region is the same as the conductivity type of the drift layer.
8. The steps include providing a semiconductor substrate layer, The step includes forming a drift layer, a first lateral current diffusion layer, and a device layer stacked from bottom to top on the semiconductor substrate layer, The conductivity type of the first lateral current diffusion layer is the same as that of the drift layer. The doping concentration of the first lateral current diffusion layer is greater than the doping concentration of the drift layer. The device layer includes a plurality of active doping regions spaced apart in the lateral direction, and a second lateral current diffusion layer located between the active doping regions and a portion of the first lateral current diffusion layer. The device layer between the second lateral current diffusion layer and the adjacent active doping region does not have superimposed projection in a direction perpendicular to the surface of the semiconductor substrate layer. The conductivity type of the second lateral current diffusion layer is the same as that of the first lateral current diffusion layer. A method for manufacturing a power semiconductor device, characterized in that the doping concentration of the second lateral current diffusion layer is greater than the doping concentration of the drift layer.
9. The method for manufacturing a power semiconductor device according to claim 8, comprising the steps of forming a stacked drift layer, a first lateral current diffusion layer, and a device layer on the semiconductor substrate layer from bottom to top, the steps of forming a stacked drift layer, a first lateral current diffusion layer, and an initial device layer on the semiconductor substrate layer from bottom to top, the steps of forming a plurality of active doping regions provided at lateral intervals in a part of the initial device layer, and forming a second lateral current diffusion layer in the initial device layer between the active doping regions and a part of the first lateral current diffusion layer, thereby forming the initial device layer into a device layer.
10. A method for manufacturing a power semiconductor device according to claim 9, characterized in that, before forming the active doping region, a mask layer is formed on the surface of a portion of the initial device layer; the mask layer is used as a mask to form the active doping region on the initial device layer; after forming the active doping region on the initial device layer using the mask layer as a mask, a sidewall is formed on the sidewall surface of the mask layer to cover a portion of the surface of the active doping region; a second lateral current diffusion layer is formed between the active doping region and a portion of the first lateral current diffusion layer using the sidewall and the mask layer as a mask; and after forming the second lateral current diffusion layer, the mask layer and the sidewall are removed.
11. The method for manufacturing a power semiconductor device according to claim 10, further comprising using the active doping region as a well region, and forming a source region in the active doping region using the sidewall and the mask layer as a mask before removing the mask layer and the sidewall.
12. The method for manufacturing a power semiconductor device according to claim 10, characterized in that the width of the sidewall is 0.1 μm to 2 μm.
13. The step of forming a stacked drift layer, a first lateral current diffusion layer, and an initial device layer on the semiconductor substrate layer from bottom to top includes the steps of epitaxially forming the drift layer on the semiconductor substrate layer, epitaxially forming the first lateral current diffusion layer on the surface of the drift layer opposite to the semiconductor substrate layer, and epitaxially forming the initial device layer on the surface of the first lateral current diffusion layer opposite to the drift layer. Alternatively, the step of forming a stacked drift layer, a first lateral current diffusion layer, and an initial device layer on the semiconductor substrate layer from bottom to top includes the steps of epitaxially forming an initial drift layer on the semiconductor substrate layer, forming a first lateral current diffusion layer on the initial drift layer of a certain thickness using an ion implantation process, wherein the initial drift layer below the first lateral current diffusion layer constitutes a drift layer, and epitaxially forming an initial device layer on the surface of the first lateral current diffusion layer opposite to the drift layer. Alternatively, the step of forming a stacked drift layer, a first lateral current diffusion layer, and an initial device layer on the semiconductor substrate layer from bottom to top includes the steps of epitaxially forming an initial drift layer on the semiconductor substrate layer, forming a first initial lateral current diffusion layer on the initial drift layer of a certain thickness using an ion implantation process, and forming an initial device layer on the first initial lateral current diffusion layer of a certain thickness using an ion implantation process, wherein the first initial lateral current diffusion layer below the initial device layer constitutes the first lateral current diffusion layer, and the initial drift layer below the first lateral current diffusion layer constitutes the drift layer. Alternatively, the method for manufacturing a power semiconductor device according to claim 9, comprising the steps of forming a stacked drift layer, a first lateral current diffusion layer, and an initial device layer on the semiconductor substrate layer from bottom to top, the steps of epitaxially forming a drift layer on the semiconductor substrate layer, epitaxially forming a first initial lateral current diffusion layer on the side of the drift layer opposite to the semiconductor substrate layer, and forming an initial device layer on a first initial lateral current diffusion layer of a certain thickness using an ion implantation process, wherein the first initial lateral current diffusion layer below the initial device layer constitutes the first lateral current diffusion layer.