Semiconductor structure

Abstract

Some embodiments of the present disclosure provide a semiconductor structure including a plurality of nanosheets disposed above a substrate, a gate structure disposed above a channel region of the nanosheets, a plurality of source / drain features disposed on opposite sides of the channel region, and a plurality of shallow trench isolation features disposed on the substrate, wherein a bottom layer of the nanosheets enters a metal depth of the shallow trench isolation features less than or equal to 4 nanometers.

Description

Technical Field

[0001] This disclosure pertains to semiconductor structures. Background Technology

[0002] Semiconductor devices are used in a variety of electronic products, such as personal computers, mobile phones, digital cameras, and other electronic devices. The manufacture of semiconductor devices typically involves depositing insulating or dielectric layers, conductive layers, and semiconductor layers sequentially on a semiconductor substrate, and using lithography to pattern the multiple material layers to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly shrinking the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems need to be addressed. Utility Model Content

[0004] According to some embodiments of the present disclosure, a semiconductor structure includes a plurality of nanosheets disposed above a substrate, a gate structure disposed above a channel region of the nanosheets, a plurality of source / drain features disposed on opposite sides of the channel region, and a plurality of shallow trench isolation features disposed on the substrate, wherein the metal depth of the bottom nanosheets in the nanosheets into the shallow trench isolation features is less than or equal to 4 nanometers.

[0005] According to some embodiments of this disclosure, a semiconductor structure includes fins disposed on a substrate and comprising a plurality of nanosheets, shallow trench isolation features disposed adjacent to the fins, a dielectric layer disposed above the shallow trench isolation features, a gate structure disposed above a channel region of the nanosheets, a contact etch stop layer disposed on the sidewalls of the gate structure and above the shallow trench isolation features, and a plurality of source / drain features disposed on opposite sides of the channel region, wherein the height measured from the bottom of the bottommost nanosheet among the nanosheets to the bottom of the contact etch stop layer is between 4 nanometers and 6 nanometers.

[0006] According to some embodiments of this disclosure, a semiconductor structure includes a plurality of shallow trench isolation features disposed between a first fin and a second fin on a substrate, a dielectric layer disposed above the shallow trench isolation features and having a thickness between 1 nanometer and 4 nanometers, a gate structure disposed on a plurality of channel regions of the first fin, a plurality of gate spacers disposed on the sidewalls of the gate structure, a plurality of source / drain features disposed on opposite sides of the gate structure, and a plurality of inner spacers separating the source / drain features and the gate structure. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A flowchart illustrating an example method 100 for manufacturing a semiconductor is shown according to some embodiments;

[0009] Figures 2 to 3 , Figures 4A to 4B , Figures 5A to 5C , Figures 6A to 6C , Figures 7A to 7C , Figures 8A to 8C , Figures 9A to 9D , Figures 10A to 10B , Figures 11 to 12 , Figures 13A to 13B , Figures 14 to 15 and Figures 16A to 16B Schematic diagrams illustrating multiple manufacturing stages of an example semiconductor device structure are provided according to some embodiments;

[0010] Figure 17A and Figure 17B This is a schematic diagram of the manufacturing stage of an example semiconductor device according to some embodiments, after the formation of a stop layer;

[0011] Figure 18A and Figure 18B This is a schematic diagram of the manufacturing stage of an example semiconductor device according to some embodiments, after the patterning of a virtual gate.

[0012] Figure 19A and Figure 19B This is a schematic diagram of another example semiconductor device according to some embodiments, after the fabrication stages of depositing spacers, etching source / drain electrodes, and depositing and etching inner spacers;

[0013] Figure 20A and Figure 20B This is a schematic diagram of an example semiconductor device according to some embodiments during the manufacturing stage after the metal gate is replaced.

[0014] Figure 21A and Figure 21B This is a schematic diagram of an example semiconductor device according to several embodiments.

[0015] [Symbol Explanation]

[0016] 100: Method

[0017] 102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136: Squares

[0018] 200: Device

[0019] 202:Substrate

[0020] 212: Epitaxial Stacking

[0021] 214: Sacrificial epitaxial layer

[0022] 216: Channel epitaxial layer / nanofacial sheet

[0023] 218: Shallow trench isolation features

[0024] 220: Fins

[0025] 221: Dielectric layer

[0026] 222: Stopping Layer

[0027] 224: Sacrificial gate structure

[0028] 228: Sacrificial gate electrode layer

[0029] 232: Gate sidewall spacer

[0030] 234: Groove

[0031] 238: Inner spacer

[0032] 240: Epitaxial Source / Drain Characteristics

[0033] 242: Contact Etching Stop Layer

[0034] 244: Interlayer dielectric layer

[0035] 254: Gate Trench

[0036] 260: Gate structure

[0037] 320: Semiconductor device

[0038] 322: Fins

[0039] 324: Channel epitaxial layer

[0040] 326: Sacrificial epitaxial layer

[0041] 328: Shallow trench isolation features

[0042] 330:Substrate

[0043] 332: Stopping Layer

[0044] 334: Corner

[0045] 336: Dielectric materials

[0046] 440: Semiconductor Device

[0047] 442: Virtual Gate

[0048] 444: Shallow trench isolation features

[0049] 446:Substrate

[0050] 448: Stopping Layer

[0051] 462: Fins

[0052] 464: Channel epitaxial layer

[0053] 466: Sacrificial epitaxial layer

[0054] 468: Corner

[0055] 470: Dielectric

[0056] 600: Semiconductor Devices

[0057] 602: Fins

[0058] 604: Channel epitaxial layer

[0059] 606: Sacrificial epitaxial layer

[0060] 608: Shallow trench isolation features

[0061] 610:Substrate

[0062] 612: Stop Layer

[0063] 800: Semiconductor Device

[0064] 802: Fins

[0065] 804: Nanosheets

[0066] 806: Metal gate layer

[0067] 808: Shallow trench isolation features

[0068] 810:Substrate

[0069] 902: Shallow trench isolation features

[0070] 904: Dielectric material

[0071] 906: High dielectric constant metal gate

[0072] 908: Interlayer dielectric layer

[0073] 910: Contact Etching Stop Layer

[0074] 912: Gate spacer

[0075] 914: Channel

[0076] 916: Source / Drain

[0077] 918: Inner spacer

[0078] F′: Height

[0079] Ha′,Hb′: Height

[0080] M′: Thickness

[0081] M1′, M2′, M3′, M4′: Height

[0082] N′: Height

[0083] P′: Distance

[0084] R′: Height

[0085] S′: Height

[0086] W′: Height

[0087] X, Y, Z: Axes

[0088] X1-X1′, X2-X2′, Y1-Y1′: Line Detailed Implementation

[0089] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting.

[0090] For the sake of brevity, the known techniques associated with the manufacture of conventional semiconductor devices may not be described in detail herein. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive procedures or processes with additional functionality not described in detail herein. Specifically, the various processes for manufacturing semiconductor devices are well known; therefore, for the sake of brevity, many known processes will only be briefly mentioned herein or will be omitted entirely without providing details of the well-known processes. As will be readily apparent to those skilled in the art upon a full reading of this disclosure, the structures disclosed herein can be employed with various techniques and incorporated into various semiconductor devices and products. Additionally, it should be noted that semiconductor device structures include varying numbers of elements, and a single element shown in the description may represent multiple elements.

[0091] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, parts, and / or sections, these elements, components, regions, layers, parts, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, part, or section from another. Therefore, the first element, component, region, layer, part, or section discussed below may be referred to as the second element, component, region, layer, part, or section without departing from the teachings of this document.

[0092] In addition, this document may use spatial relative terms such as “above,” “overlapping,” “above,” “upper,” “top,” “below,” “subordinate,” “below,” “lower,” “bottom,” and the like to describe the relationship of one element or feature to another element or feature as shown in the figures. Besides the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly. When spatial relative terms such as those listed above are used to describe the relationship of a first component relative to a second component, the first component may be directly on top of the other component, or there may be an intermediate component or layer. When a component or layer is referred to as being “on” another component or layer, the component or layer may be directly on top of and in contact with the other component or layer.

[0093] Additionally, reference numerals and / or letters may be repeated in various examples within this disclosure. This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0094] It should be noted that the description of an embodiment, such as "an embodiment," "an example embodiment," "exemplary," "model," or "example," indicates that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, incorporating other embodiments to affect that feature, structure, or characteristic is within the knowledge of those skilled in the art.

[0095] In specific embodiments herein, a "material layer" is a layer comprising at least 50 weight percent of an identification material, such as at least 60 weight percent, at least 75 weight percent, at least 90 weight percent, at least 95 weight percent, or at least 99 weight percent of an identification material, while a "material" layer comprises at least 50 weight percent of an identification material, such as at least 60 weight percent, at least 75 weight percent, at least 90 weight percent, at least 95 weight percent, or at least 99 weight percent of an identification material. For example, in specific embodiments, an aluminum layer and a layer of aluminum are each a layer of aluminum comprising at least 50 weight percent, at least 60 weight percent, at least 75 weight percent, at least 90 weight percent, at least 95 weight percent, or at least 99 weight percent.

[0096] It should be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes, and that the terminology or terminology used herein shall be interpreted by one skilled in the art in light of the teachings herein.

[0097] To achieve the various features of the mentioned subject matter, the following disclosure provides numerous different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. In the description herein, unless otherwise specified, the same reference numerals in the different figures represent the same or similar components formed using the same or similar materials and in the same or similar methods.

[0098] The embodiments discussed herein are specific examples of semiconductor structures forming fin-like field-effect transistor (FinFET) devices. For example, the semiconductor structure may be a complementary metal-oxide-semiconductor (CMOS) device, including P-type metal-oxide-semiconductor (PMOS) and N-type metal-oxide-semiconductor (NMOS) finFET devices. The embodiments will be described in a manner that includes specific examples of finFET fabrication processes. However, the embodiments are not limited to the examples provided herein, and the ideas herein can be implemented in a wide range of embodiments. Therefore, many embodiments can be applied to other semiconductor devices / processes, such as planar transistors and the like. Furthermore, some embodiments discussed herein are described in a manner that uses a gate-last process to form the device. In other embodiments, a gate-first process may be used.

[0099] The accompanying drawings illustrate several embodiments of a semiconductor device, but additional features may be added to the semiconductor device shown in the drawings, and some of the features described below may be replaced, modified, or deleted in other embodiments of the semiconductor device.

[0100] Additional steps may be provided before, during, and / or after the stages described in the embodiments. Some stages may be replaced or omitted in different embodiments. Additional features may be added to the semiconductor device structure. Some features described below may be replaced or omitted in different embodiments. Although the steps discussed in some embodiments are performed in a specific order, these steps may be performed in other logical orders.

[0101] As used herein, a “layer” is a region, such as an area encompassing arbitrary boundaries, and need not be of uniform thickness. For example, a layer can be a region whose thickness includes at least some variation.

[0102] The embodiments of this disclosure are generally related to semiconductor devices and their fabrication processes, and more specifically to multi-gate devices. Multi-gate devices include transistors in which gate structures are formed on at least two sides of a channel region. These multi-gate devices may include n-type metal-oxide-semiconductor devices or p-type metal-oxide-semiconductor multi-gate devices. Specific examples herein may be presented as multi-gate transistor types referred to as gate-all-around (GAA) devices. A gate-all-around device includes any device in which a gate structure or a portion of a gate structure is formed on all four sides of a channel region (e.g., surrounding a portion of the channel region). The devices presented herein also include embodiments having channel regions disposed in nanosheet channels, nanowire channels, strip channels, and / or other suitable channel configurations. The device embodiments presented herein may have one or more channel regions (e.g., nanosheets) associated with a single continuous gate structure. However, those skilled in the art will understand that the teachings herein can be applied to a single channel or any number of channels, such as fin field-effect transistor devices attributable to fin structures. Those skilled in the art will understand that other examples of semiconductor devices may gain advantages from the embodiments of this disclosure.

[0103] According to the various forms disclosed herein, Figure 1 A flowchart illustrating an example method 100 for manufacturing a semiconductor, including a multi-gate device, is provided. As used herein, the term "multi-gate device" is used to describe a device (e.g., a semiconductor transistor) having at least some gate material disposed on multiple sides of at least one channel of the device. In some examples, a multi-gate device may refer to a gate-surrounded device having gate material disposed on all four sides of at least one channel of the device. The channel composition may refer to "nanostructure" or "nanosheet," which herein is used to specify any material portion having a nanoscale or even microscale and having an extended shape in the cross-sectional shape of this portion. Thus, the term "nanostructure" or "nanosheet" as used herein refers to both extended material portions with circular and substantially circular cross-sections and bundled or strip-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections.

[0104] According to some embodiments, Figure 1 Combination Figures 2 to 3 , Figures 4A to 4B , Figures 5A to 5C , Figures 6A to 6C , Figures 7A to 7C , Figures 8A to 8C , Figures 9A to 9D , Figures 10A to 10B , Figures 11 to 12 , Figures 13A to 13B , Figures 14 to 15 and Figures 16A to 16BThe accompanying drawings illustrate a semiconductor device 200 or its structure at multiple manufacturing stages. Method 100 is merely an example and is not intended to limit the scope of the claims. Additional steps may be provided before, during, and after method 100, and other embodiments of method 100 may move, replace, or omit some of the described steps. Additional features may be added to the semiconductor device 200 in the drawings, and some features described below may be replaced, modified, or omitted in other embodiments.

[0105] Regarding other method embodiments and example apparatuses discussed herein, it should be understood that some semiconductor devices can be manufactured using semiconductor technology processes; therefore, only some processes are described briefly herein. Furthermore, example semiconductor devices may include a variety of other devices and features, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic devices, but these are simplified herein to better understand the concepts of this disclosure. In some embodiments, example apparatuses include multiple semiconductor devices (e.g., transistors), including p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), etc., wherein these semiconductor devices may be interconnected. Furthermore, it should be noted that any descriptions given with reference to the accompanying drawings and the process steps of method 100 provided in the embodiments of this disclosure and the example drawings are merely illustrative and are not intended to limit the scope of the claims.

[0106] According to some embodiments, Figures 2 to 3 , Figures 4A to 4B , Figures 5A to 5C , Figures 6A to 6C , Figures 7A to 7C , Figures 8A to 8C , Figures 9A to 9D , Figures 10A to 10B , Figures 11 to 12 , Figures 13A to 13B , Figures 14 to 15 and Figures 16A to 16B Schematic diagrams illustrating example semiconductor device structures across multiple manufacturing stages are provided. In some figures, reference numerals for components or features illustrated herein may be omitted for ease of illustration to avoid obscuring other components or features.

[0107] In block 102, example method 100 includes providing a substrate. (Reference) Figure 2For example, in one embodiment of block 102, a substrate 202 is provided to form a multi-gate device 200. In some embodiments, the substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. In some embodiments, the substrate 202 includes a single-crystal semiconductor layer at least on a surface portion of the substrate 202. The substrate 202 may include a single-crystal semiconductor material, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, the substrate 202 may include compound semiconductors and / or alloy semiconductors. The substrate 202 may include multiple layers, including conductive or insulating layers formed on the semiconductor substrate. The substrate 202 may include various doping configurations depending on design requirements. For example, different doping profiles (e.g., n-wells, p-wells) may be formed in regions of the substrate 202 designed for different device types (e.g., n-type field-effect transistors, p-type field-effect transistors). Suitable doping may include ion implantation and / or diffusion processes of dopants. The substrate 202 has isolation features (e.g., shallow trench isolation (STI) features) intervening to provide areas between different device types. Furthermore, the substrate 202 may be strained to improve performance and may include a silicon-on-insulator (SOI) structure and / or may have other suitable reinforcement features.

[0108] In block 104, example method 100 then includes forming an epitaxial stack comprising multiple epitaxial layers over a substrate. (Reference) Figure 3 For example, in one embodiment of block 104, an epitaxial stack 212 is formed over substrate 202. The epitaxial stack 212 includes a plurality of sacrificial epitaxial layers 214 of a first composition and channel epitaxial layers 216 of a second composition interposed between the sacrificial epitaxial layers 214. The first and second compositions can be different. In one embodiment, the sacrificial epitaxial layers 214 are formed of SiGe and the channel epitaxial layers 216 are formed of silicon (Si). However, other embodiments may include a first and second composition with different oxidation rates and / or etch selectivity. In some embodiments, the sacrificial epitaxial layer 214 comprises SiGe and the channel epitaxial layer 216 comprises silicon (Si). However, other embodiments may include a first and second composition with different oxidation rates and / or etch selectivity. In some embodiments, the sacrificial epitaxial layer 214 comprises SiGe and the channel epitaxial layer 216 comprises Si, wherein the Si oxidation rate of the channel epitaxial layer 216 is lower than the SiGe oxidation rate of the sacrificial epitaxial layer 214. It should be noted that... Figure 3The illustration shows three sacrificial epitaxial layers 214 and three channel epitaxial layers 216, but this is for illustrative purposes only and is not intended to limit the scope of the claims. In various embodiments, any number of epitaxial layers may be formed in the epitaxial stack 212, depending on the desired number of channel regions for the device 200. In some embodiments, the number of channel epitaxial layers 216 is between 2 and 10, such as 3, 4, or 5.

[0109] In some embodiments, the sacrificial epitaxial layer 214 has a thickness ranging from about 4 nanometers to about 12 nanometers. The sacrificial epitaxial layer 214 may have a substantially uniform thickness. In some embodiments, the channel epitaxial layer 216 has a thickness ranging from about 3 nanometers to about 6 nanometers. In some embodiments, the stacked channel epitaxial layers 216 have a substantially uniform thickness.

[0110] As described in more detail below, the channel epitaxial layer 216 can serve as the channel region for a subsequently formed multi-gate device, and the thickness of the channel epitaxial layer 216 can be selected based on device performance considerations. The sacrificial epitaxial layer 214 can serve as a gap (which may be referred to as a void) between adjacent channel regions of a subsequently formed multi-gate device, and the thickness of the sacrificial epitaxial layer 214 can be selected based on device performance considerations.

[0111] As an example, the epitaxial growth of the epitaxial stack 212 can be performed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, for example, the epitaxial growth layer of the channel epitaxial layer 216 comprises the same material as the substrate 202, such as silicon (Si). In some embodiments, the sacrificial epitaxial layer 214 and the channel epitaxial layer 216 comprise materials different from the substrate 202. As described above, in at least some examples, the sacrificial epitaxial layer 214 comprises epitaxially grown Si. 1-x Ge xThe sacrificial epitaxial layer 214 (e.g., x is about 25% to 55%) and the channel epitaxial layer 216 comprise an epitaxially grown Si layer. Alternatively, in some embodiments, either the sacrificial epitaxial layer 214 and the channel epitaxial layer 216 may comprise other materials, such as germanium, compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP), or combinations thereof. As described above, the material selection for the sacrificial epitaxial layer 214 and the channel epitaxial layer 216 may be based on the purpose of different oxidation and etching selectivity. In several embodiments, the sacrificial epitaxial layer 214 and the channel epitaxial layer 216 are substantially free of dopants (i.e., having about 0 cm⁻¹). -3 To approximately 1×10 17 cm -3 (Foreign dopant concentration), for example, intentional doping not performed during the epitaxial growth process.

[0112] In block 106, example method 100 includes patterning epitaxial stacks to form semiconductor fins (also known as fins). Reference Figure 4A and Figure 4B For example, in one embodiment of block 106, a plurality of fins 220 are formed extending from substrate 202. In various embodiments, each fin 220 includes an upper portion formed by interleaved sacrificial epitaxial layers 214 and channel epitaxial layers 216, and a bottom portion protruding from substrate 202.

[0113] Fabricating the fins 220 can be performed using suitable processes, including photolithography and etching. The photolithography process may include forming a photoresist layer over the substrate 202 (e.g., over the epitaxial stack 212), exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a mask element including the photoresist. In some embodiments, patterning the photoresist to form the mask element can be performed using an electron beam lithography process. The mask element can then be used to protect areas of the substrate 202 and the epitaxial stack 212 formed on those areas, while the etching process forms trenches in the unprotected areas through a mask layer, such as a hard mask, thereby leaving multiple extended fins. The etched trenches can be formed using dry etching (e.g., reactive-ion etching, RIE), wet etching, and / or other suitable processes. The trenches may be filled with a dielectric material to form, for example, shallow trench isolation features intervening between the fins.

[0114] In block 108, example method 100 includes forming a shallow trench isolation feature on a substrate. In various embodiments, forming the shallow trench isolation feature is achieved by filling trenches between adjacent fins with a dielectric material to form the isolation feature. (See reference...) Figure 5A , Figure 5B and Figure 5C For example, in one embodiment of block 108, a shallow trench isolation feature 218 is deposited between adjacent fins 220. The shallow trench isolation feature may include one or more dielectric layers. Suitable dielectric materials for the shallow trench isolation feature may include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low dielectric constant dielectric materials, and / or other suitable dielectric materials. The dielectric material can be deposited using any suitable technique, including thermal growth, chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDP-CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or spin coating. The deposited shallow trench isolation feature is then recessed to form the shallow trench isolation feature. Any suitable etching technique can be used for recessed isolation features, including dry etching, wet etching, reactive ion etching and / or other etching methods, and in one example embodiment, anisotropic dry etching is used to selectively remove the dielectric material of the isolation feature without etching the fins.

[0115] In block 110, example method 100 includes depositing a dielectric layer over a substrate feature. (Reference) Figure 6A , Figure 6B and Figure 6C For example, in one embodiment of block 110, dielectric layer 221 is deposited over substrate 202. In various embodiments, dielectric layer 221 is formed of a silicon-based material, such as SiO, SiN, SiCN, SiON, SiOCN, and others like these. Using these materials allows for adjustment of the etch selectivity during the metal gate replacement step, resulting in less material loss during etching (e.g., less shallow trench isolation loss). When the metal fills locations with less loss, the capacitance effect of the metal can be reduced. In various embodiments, dielectric layer 221 can be deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes, including low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD).

[0116] In block 112, example method 100 includes etching back the dielectric layer until the dielectric layer above the shallow trench isolation feature has a suitable thickness. (Reference) Figure 7A , Figure 7B and Figure 7C For example, in one embodiment of block 112, the dielectric layer 221 has a suitable thickness above the shallow trench isolation feature 218 after being etched back. In various embodiments, the etched-back dielectric layer 221 can be achieved using a variety of etching techniques, such as wet etching and dry etching. In various embodiments, the remaining dielectric layer 221 has a thickness of approximately 4 nanometers to approximately 7 nanometers. In various embodiments, if the remaining dielectric layer 221 has a thickness of less than 4 nanometers, it may result in unnecessary material loss and capacitance effects. In various embodiments, if the remaining dielectric layer 221 has a thickness greater than 7 nanometers, it may cause problems with the growth of the third silicon epitaxial layer (low epitaxial density).

[0117] In block 114, example method 100 includes forming a stop layer over the fins and substrate. In several embodiments, the stop layer is blanket-deposited over the fins 220 and the shallow trench isolation feature 218. In several embodiments, the stop layer 222 (shown in...) Figure 9A The thickness of the stop layer 222 is in the range of about 1 nanometer to about 5 nanometers. In several embodiments, the stop layer 222 undergoes a planarization step. In several embodiments, the stop layer 222 can be deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes, including low-pressure chemical vapor deposition and plasma-enhanced chemical vapor deposition.

[0118] In block 116, example method 100 includes forming one or more sacrificial layers / features over the substrate. (Reference) Figure 8A , Figure 8B and Figure 8C For example, in one embodiment of block 116, a sacrificial gate dielectric layer (not shown) is blanket-deposited over a stop layer 222, wherein the stop layer 222 is formed over a substrate 202. Next, a sacrificial gate electrode layer 228 is blanket-deposited over the sacrificial gate dielectric layer and over the substrate 202. The sacrificial gate electrode layer 228 comprises silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer is in the range of about 1 nanometer to about 5 nanometers. In some embodiments, the thickness of the sacrificial gate electrode layer is in the range of about 100 nanometers to about 200 nanometers. In some embodiments, the sacrificial gate electrode layer undergoes a planarization step. The deposition of the sacrificial gate dielectric layer and the sacrificial gate electrode layer 228 can be performed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes, including low-pressure chemical vapor deposition and plasma-enhanced chemical vapor deposition.

[0119] In block 118, example method 100 includes patterning one or more sacrificial layers / features to form a virtual gate structure on the channel region of the fin. Reference Figure 9A , Figure 9B , Figure 9C and Figure 9D In one embodiment of block 118, a sacrificial gate structure 224 is formed over a portion of the fin 220 that is intended to become a channel region. The sacrificial gate structure 224 defines the channel region of the gate full-around device. The sacrificial gate structure 224 includes a sacrificial gate dielectric layer (not shown) and a sacrificial gate electrode layer 228. Forming the sacrificial gate structure 224 can be achieved by forming a mask layer over the sacrificial gate electrode layer. The mask layer may include a pad silicon oxide layer and a silicon nitride mask layer. Subsequently, a patterning step is performed on the mask layer, and the sacrificial gate dielectric and sacrificial gate electrode layer are patterned into the sacrificial gate structure 224. After patterning the sacrificial gate structure 224, the fin 220 is partially exposed on opposite sides of the sacrificial gate structure 224, thereby defining a source / drain (S / D) region. In embodiments of this disclosure, the source and drain can be used interchangeably, and the source and drain structures are substantially identical. Dielectric layer 221 avoids or substantially reduces the loss of shallow trench isolation features 218 during the virtual gate patterning step.

[0120] Referring to block 130 of method 100, the sacrificial gate structure 224 is subsequently removed and replaced by the final gate stack in a later process stage of device 200. Specifically, the sacrificial gate structure 224 is replaced in a later process stage by a high-k dielectric (HK) layer and a metal gate (MG) electrode, as described below.

[0121] In block 120, example method 100 includes forming gate sidewall spacers on the sidewalls of the dummy gate stack. Gate sidewall spacers 232 (shown in...) Figure 11The gate sidewall spacer 232 may include dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, the gate sidewall spacer 232 includes multiple layers, such as a primary spacer wall, an inner liner, and the like. As an example, the gate sidewall spacer 232 may be formed using, for example, chemical vapor deposition, sub-atmospheric chemical vapor deposition (SACVD), flowable chemical vapor deposition (FCVD), atomic layer deposition, physical vapor deposition, or other suitable processes to deposit a dielectric material layer over the sacrificial gate structure 224. In some embodiments, an etch-back (e.g., anisotropic) process may follow the deposition of the dielectric material layer to expose portions of the fins 220 adjacent to and not covered by the sacrificial gate structure 224 (e.g., source / drain regions). A dielectric material layer may be retained on the sidewalls of the sacrificial gate structure 224 as a gate sidewall spacer 232. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof. The gate sidewall spacer 232 may have a thickness ranging from about 5 nanometers to about 20 nanometers.

[0122] In block 122, the example method includes fins in the recessed source / drain regions. (Reference) Figure 10A and Figure 10B For example, in one embodiment of block 122, the fins in the source / drain regions are recessed. The stacked sacrificial epitaxial layer 214 and channel epitaxial layer 216 in the source / drain regions are etched down to form a recess 234. In several embodiments, the recessing step is to perform a suitable etching process, such as a dry etching process, a wet etching process, or a reactive ion etching process. Dry etching can be performed using etchants including bromine-containing gases (e.g., HBr and / or CHBr3), fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), other suitable gases, or combinations thereof.

[0123] In block 124, example method 100 includes forming inner spacers. Forming inner spacers may include a recessed sacrificial epitaxial layer (e.g., SiGe), deposited inner spacer material, and etched-back inner spacer material. Reference Figure 11For example, in one embodiment of block 124, gate sidewall spacers 232 and inner spacers 238 are illustrated. The sacrificial epitaxial layer 214 is etched back. The sacrificial epitaxial layer 214 can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution. Alternatively, in block 124, the sacrificial epitaxial layer 214 can be selectively oxidized to expose the lateral ends in the recess 234 to increase the etch selectivity between the sacrificial epitaxial layer 214 and the channel epitaxial layer 216. In some examples, the oxidation process can be performed by exposing the device 200 to a wet oxidation process, a dry oxidation process, or a combination thereof.

[0124] The inner spacer 238 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonoxylate, silicon carbonitride, and / or other suitable dielectric materials. In some embodiments, the inner spacer material layer is deposited as a conformal layer. The inner spacer material layer can be formed by atomic layer deposition or any other suitable method. After the inner spacer material layer is formed, an etching step may be performed to partially remove the inner spacer material layer.

[0125] In block 126, example method 100 includes forming source / drain characteristics. (Reference) Figure 12 For example, in one embodiment of block 126, an epitaxial source / drain feature 240 is formed in a recess 234. In some embodiments, the epitaxial source / drain feature 240 comprises silicon for an n-type field-effect transistor or SiGe for a p-type field-effect transistor. In some embodiments, the epitaxial source / drain feature 240 is formed by an epitaxial growth method using chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy (MBE). The formed epitaxial source / drain feature 240 contacts the channel epitaxial layer 216, and an inner spacer 238 separates the epitaxial source / drain feature 240 from the sacrificial epitaxial layer 214.

[0126] In block 128, example method 100 includes forming a contact etch stop layer (CESL) and an interlayer dielectric layer. (Reference) Figure 13A and Figure 13BFor example, in one embodiment of block 128, a contact etch stop layer 242 is formed over the epitaxial source / drain feature 240, and an interlayer dielectric (ILD) layer 244 is formed over the contact etch stop layer 242. The contact etch stop layer 242 may include silicon nitride, silicon oxynitride, silicon nitride having oxygen (O) or carbon (C) elements, and / or other materials, and the contact etch stop layer 242 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable methods. The interlayer dielectric layer 244 may include tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG)) and / or other suitable dielectric materials. Forming the interlayer dielectric layer 244 can be achieved by plasma-enhanced chemical vapor deposition, flow-through chemical vapor deposition, or other suitable methods. In some embodiments, forming the interlayer dielectric layer 244 further includes performing a chemical mechanical polishing (CMP) process to planarize the top surface of the device 200, thereby exposing the top surface of the sacrificial gate structure 224.

[0127] In block 130, example method 100 includes removing the dummy gate stack to form a gate trench. (Reference) Figure 14 In one embodiment of block 130, as an example, the sacrificial gate structure 224 is removed to form a gate trench 254. The gate trench 254 exposes the fins 220 in the channel region. During the removal of the sacrificial gate structure 224, the interlayer dielectric layer 244 and the contact etch stop layer 242 protect the epitaxial source / drain features 240. The sacrificial gate structure 224 can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer is polysilicon and the interlayer dielectric layer 244 is an oxide, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode layer. Subsequently, the sacrificial gate dielectric layer is removed using plasma dry etching and / or wet etching.

[0128] In block 132, example method 100 includes removing the sacrificial epitaxial layer to form nanosheets. (Reference) Figure 15For example, in one embodiment of block 132, the sacrificial epitaxial layer 214 is removed, thereby releasing the channel composition of the channel region of the gate-all-around device. In the illustrated embodiment, the channel composition is a channel epitaxial layer 216 in the form of a nanosheet. In several embodiments, the channel epitaxial layer 216 comprises silicon, and the sacrificial epitaxial layer 214 comprises silicon-germanium. In several embodiments, multiple sacrificial epitaxial layers 214 are selectively removed by a selective removal process, wherein the selective removal process includes oxidizing multiple sacrificial epitaxial layers 214 using a suitable oxidant such as ozone. Subsequently, the oxidized sacrificial epitaxial layers 214 are selectively removed by a dry etching process, for example, by applying hydrochloric acid gas at a temperature of about 500 degrees Celsius to about 700 degrees Celsius, or by applying a mixture of CF4, SF6, and CHF3.

[0129] In block 134, example method 100 includes forming a high-dielectric-constant metal gate structure. (Reference) Figure 16A and Figure 16BFor example, in one embodiment of block 134, a gate structure 260 is formed. In several embodiments, the gate structure is the gate of a multi-gate transistor. In several embodiments, the gate structure is a high-dielectric-constant metal gate stack; however, other compositions are also feasible. In several embodiments, the high-dielectric-constant metal gate stack includes a gate dielectric layer, wherein the gate dielectric layer includes an interfacial layer and a high-dielectric-constant dielectric layer. The high-dielectric-constant dielectric layer surrounds each nanosheet 216, and the interfacial layer intervenes between the high-dielectric-constant dielectric layer and the nanosheet 216. The interfacial layer may include a dielectric material such as silicon oxide (SiO2) or silicon oxynitride (SiON), and the interfacial layer can be formed by chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, and / or other suitable methods. High dielectric constant dielectric layers may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HMO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), other suitable high dielectric constant dielectric materials, and / or combinations thereof. High dielectric constant materials may be further selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable materials, and / or combinations thereof. High-dielectric-constant dielectric layers can be formed using any suitable process, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, remote plasma chemical vapor deposition (RPCVD), plasma-enhanced chemical vapor deposition, metal-organic chemical vapor deposition, sputtering, electroplating, other suitable processes, and / or combinations thereof. In one embodiment, a highly conformal deposition process, such as atomic layer deposition, is used to form the gate dielectric layer to ensure that the formed gate dielectric layer has a uniform thickness around the respective channel layers. The high-dielectric-constant metal gate structure may include additional material layers.

[0130] In block 136, example method 100 includes performing further processing steps. The semiconductor device may be further processed to form multiple features and regions known in the art. For example, subsequent processes may form contact openings, contact metals, and multiple contacts / vias / wires and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate, these elements configured to connect multiple features to form a functional circuit that may include one or more multi-gate devices. In a further example, the multilayer interconnect may include, for example, vertical interconnects of vias or contacts and horizontal interconnects of, for example, metal wires. Multiple interconnect features may use a variety of conductive materials, including copper, tungsten, and / or silicides. In one example, damascene and / or dual damascene processes are used to form a copper-associated multilayer interconnect structure. Furthermore, according to various embodiments of method 100, additional process steps may be performed before, during, and after method 100, and some of the process steps described above may be replaced or omitted.

[0131] Figure 17A and Figure 17B This is a schematic diagram of the fabrication stage of the example semiconductor device 320 after the formation of the stop layer. The figure illustrates a fin 322 including alternating channel epitaxial layers 324 and sacrificial epitaxial layers 326, a shallow trench isolation feature 328 deposited over a substrate 330 on the opposite side of the fin 322, a dielectric material 336 deposited over the shallow trench isolation feature 328, and a stop layer 332 deposited over the fin 322 and the dielectric material 336. The example semiconductor device 320 includes a height R′ measured from the bottom of the sacrificial epitaxial layer 326 to the bottom of the stop layer 332, and a thickness M′ of the dielectric material 336. Because the dielectric layer intervenes between the shallow trench isolation and the stop layer, less shallow trench isolation loss can be achieved during the virtual gate patterning step compared to when the dielectric layer is not intervened between the shallow trench isolation and the stop layer. In several embodiments, the height R′ is between about 2 nanometers and about 4 nanometers, and the thickness M′ is between about 4 nanometers and about 7 nanometers. Figure 17B As illustrated, the stop layer 332 has a near-right angle shape at corner 334, where corner 334 is the location where the stop layer 332 encounters the shallow trench isolation feature 328. If no dielectric layer is interposed between the shallow trench isolation and the stop layer, the height R measured from the bottom of the sacrificial epitaxial layer to the bottom of the stop layer may be in the range of approximately 10 nanometers to approximately 15 nanometers, and the corner where the stop layer encounters the shallow trench isolation feature may have a rounded shape.

[0132] Figure 18A and Figure 18B This is a schematic diagram of the manufacturing stage of the example semiconductor device 440 after virtual gate patterning. Figure 18AThis is a schematic cross-sectional view of an example semiconductor device 440 along the X-axis on a shallow trench isolation (outer gate). The figure illustrates a dummy gate 442 and a shallow trench isolation feature 444 deposited over a substrate 446. A height S′ is defined between the top of the inner gate stop layer 448 and the outer gate dielectric 470. As illustrated in the figure, the stop layer 448 has a near-right-angled shape around the top of the shallow trench isolation feature 444.

[0133] Figure 18B This is a schematic cross-sectional view of an example semiconductor device 440 along the Y-axis on a nanosheet. The figure illustrates a fin 462 including alternating channel epitaxial layers 464 and sacrificial epitaxial layers 466, a shallow trench isolation feature 444 deposited over a substrate 446 on the opposite side of the fins 462, and a gate dielectric 470 deposited over the shallow trench isolation feature 444. A height W′ is defined between the bottom of the sacrificial epitaxial layer 466 and the top of the outer gate dielectric 470. As illustrated in the figure, a stop layer 448 has a near-right-angle shape at a corner 468, where the corner 468 is the location where the stop layer 448 encounters the shallow trench isolation feature 444. A height N′ is defined as the height of the dielectric 470 retained after the dummy gate patterning step. The dielectric 470 avoids shallow trench isolation losses during the dummy gate patterning step. Because the dielectric layer intervenes between the shallow trench isolation and the stop layer, less shallow trench isolation loss is generated during the dummy gate patterning step. In several embodiments, the height S′ is from 0 nm to approximately 2 nm. In several embodiments, the height W′ is from approximately 7 nm to approximately 12 nm. In several embodiments, the height N′ is from approximately 1 nm to approximately 4 nm. If no dielectric layer is interposed between the shallow trench isolation and the stop layer, the stop layer may have a rounded corner where it encounters the shallow trench isolation feature. The height S, defined between the inner gate stop layer and the top of the outer gate shallow trench isolation, may be from approximately 3 nm to approximately 6 nm, and the height W, defined between the bottom of the sacrificial epitaxial layer and the top of the outer gate shallow trench isolation, may be from approximately 16 nm to approximately 21 nm.

[0134] Figure 19A and Figure 19B This is a schematic diagram of another example semiconductor device 600 in the manufacturing stages after depositing spacers, etching source / drain electrodes, and depositing and etching inner spacers. Figure 19A The diagram illustrates a cross-section of an example semiconductor device 600 along the X-axis on a nanosheet. Figure 19BThe illustration depicts a cross-section of an example semiconductor device 600 along the X-axis on a shallow trench isolation (outer gate). The figure illustrates a fin 602 comprising alternating channel epitaxial layers 604 and sacrificial epitaxial layers 606, and a shallow trench isolation feature 608 deposited over a substrate 610. The example semiconductor device 600 includes a height F′ measured from an inner gate stop layer 612 to the top of the outer gate shallow trench isolation feature 608. Because a dielectric layer intervenes between the shallow trench isolation and the stop layer, less shallow trench isolation loss occurs during the dummy gate patterning step. In several embodiments, the height F′ is between about 3 nanometers and about 10 nanometers. If no dielectric layer intervenes between the shallow trench isolation and the stop layer, the height F measured from the inner gate stop layer to the top of the outer gate shallow trench isolation may be between about 16 nanometers and about 30 nanometers.

[0135] Figure 20A and Figure 20B This is a schematic diagram of the manufacturing stage of the example semiconductor device 800 after the metal gate with a high dielectric constant has been replaced. Figure 20A The diagram illustrates a cross-section of the fin 802 of an example semiconductor device 800 along the X-axis of the nanosheet. Figure 20B The illustration shows a cross-section of an example semiconductor device 800 along the X-axis on a shallow trench isolation (outer gate). The figure also shows alternating nanosheets 804 and a metal gate layer 806 above a substrate 810, and a shallow trench isolation feature 808 deposited above the substrate 810.

[0136] Example semiconductor device 800 includes heights M1′ measured from the bottom of the bottommost nanosheet to the bottom of the contact etch stop layer, heights M2′ measured from the bottom of the second bottom nanosheet to the bottom of the contact etch stop layer, heights M3′ measured from the bottom of the third bottom nanosheet to the bottom of the contact etch stop layer, and heights M4′ measured from the bottom of the fourth bottom nanosheet to the bottom of the contact etch stop layer. Example semiconductor device 800 includes height Ha′ (or metal depth) measured from the top of the shallow trench isolation to the third-level silicon channel as shown by an X-section on the nanosheet, height Hb′ (or metal depth) measured from the top of the shallow trench isolation to the bottom of the metal as shown by an X-section on the shallow trench isolation from an outer gate view, the shortest distance P′ between a point in the source / drain epitaxy (S / D EPI) and a point in the bottom of the metal, and a near-right-angle shape at the corner where the stop layer encounters the shallow trench isolation feature.

[0137] Because the dielectric layer intervenes between the shallow trench isolation and the stop layer, less shallow trench isolation loss is generated during the metal gate replacement step. In several embodiments, the height M1′ is between about 4 nm and about 6 nm, the height M2′ is between about 19 nm and about 21 nm, the height M3′ is between about 34 nm and about 36 nm, the height M4′ is between about 49 nm and about 51 nm, the height Ha′ is between about 2 nm and about 4 nm, the height Hb′ is between about 2 nm and about 4 nm, and the shortest distance P′ is between about 9 nm and about 12 nm. When the height Ha′, height Hb′, and / or distance P′ are shortened, the distance between the metal gate and the source / drain epitaxial layer is greater. The greater the distance, the less capacitance effect. Because the dielectric layer intervenes between the shallow trench isolation and the stop layer, the distance P′ between the metal gate and the source / drain epitaxial layer is longer, thus reducing the capacitance between the metal gate and the metal drain.

[0138] Without a dielectric layer between the shallow trench isolation and the stop layer, an example semiconductor device might include a height M1 between about 16 nm and about 30 nm from the bottom of the bottom nanosheet to the bottom of the contact etch stop layer, a height M2 between about 31 nm and about 35 nm from the bottom of the second bottom nanosheet to the bottom of the contact etch stop layer, a height M3 between about 45 nm and about 50 nm from the bottom of the third bottom nanosheet to the bottom of the contact etch stop layer, a height M4 between about 61 nm and about 65 nm from the bottom of the fourth bottom nanosheet to the bottom of the contact etch stop layer, and additional nanosheets could each increase the distance by about 15 nm. Furthermore, without a dielectric layer between the shallow trench isolation and the stop layer, the height Ha might be between about 14 nm and about 18 nm, the height Hb might be between about 14 nm and about 18 nm, and the distance P might be between about 3 nm and about 8 nm.

[0139] According to several embodiments, Figure 21A and Figure 21B This is a schematic diagram of an example semiconductor device. Figure 21B It is a three-dimensional part of an example semiconductor device, and Figure 21A This is a cross-section of an example semiconductor device along the inner gate and along the X-axis. The figure illustrates a shallow trench isolation feature 902, a dielectric material 904, a high-dielectric-constant metal gate 906, an interlayer dielectric layer 908, a contact etch stop layer 910, a gate spacer 912, a channel 914, a source / drain 916, and an inner spacer 918.

[0140] This document describes improved systems, manufacturing methods, manufacturing techniques, and articles. The systems, methods, techniques, and articles described herein can be used with a wide range of semiconductor devices, including gate-all-around field-effect transistors (GAAFETs), nano-sheet field-effect transistors (NSFETs), fork-sheet transistors, complementary field-effect transistors (CFETs), vertical field-effect transistors (VFETs), and metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0141] In some embodiments, the technology described herein relates to a method of fabricating a semiconductor structure, including depositing a dielectric layer over a shallow trench isolation feature, wherein the shallow trench isolation feature is formed between a first fin and a second fin on a substrate, each of the first and second fins comprising an epitaxial stack having at least one sacrificial epitaxial layer and at least one channel epitaxial layer, wherein the dielectric layer reduces the loss of the shallow trench isolation feature during a subsequent etching step. The method includes patterning a sacrificial gate stack on a channel region of the first fin, forming gate spacers, performing source / drain etching steps on opposite sides of the sacrificial gate stack, forming inner gate spacers, forming source / drain regions, forming a contact etch stop layer, and replacing the sacrificial gate stack with a metal gate.

[0142] In some cases, the technique described herein is about a method in which a dielectric layer formed over a shallow trench isolation feature has a thickness between 4 nanometers and 7 nanometers.

[0143] In some cases, the techniques described herein relate to a method in which the dielectric layer is formed from a silicon-based dielectric material including at least one of SiN, SiCN, SiON, or SiOCN.

[0144] In some cases, the technique described herein relates to a method in which, after the step of patterning the sacrificial gate stack, a height S′ defined between the top of the inner gate stop layer and the outer gate dielectric is about 2 nanometers or less.

[0145] In some cases, the technique described herein relates to a method in which, after the step of patterning the sacrificial gate stack, a height W′ defined between the bottom of the sacrificial epitaxial layer and the top of the outer gate dielectric is approximately 7 nanometers to approximately 12 nanometers.

[0146] In some cases, the technique described herein is about a method in which, after the step of patterning the sacrificial gate stack, the height N′ of the retained dielectric layer is about 1 nanometer to about 4 nanometers.

[0147] In some cases, the technique described herein relates to a method in which, after a source / drain etching step, a height F′ is defined between the top of the inner gate stop layer and the outer gate shallow trench isolation, ranging from approximately 3 nanometers to approximately 10 nanometers.

[0148] In some embodiments, the technology described herein relates to a semiconductor structure comprising fins, the fins comprising a plurality of nanosheets disposed above a substrate. The semiconductor structure includes a gate structure disposed above a channel region of the plurality of nanosheets, source / drain features disposed on opposite sides of the channel region, and shallow trench isolation features disposed on opposite sides of the fins, wherein the bottom nanosheet among the plurality of nanosheets penetrates the shallow trench isolation features to a metal depth of less than or equal to 4 nanometers.

[0149] In some cases, the technology described herein relates to a semiconductor structure in which the metal depth is between 2 nanometers and 4 nanometers.

[0150] In some cases, the technique described herein relates to a semiconductor structure in which the shortest distance between the bottom of the underlying nanosheet and the source / drain features is greater than 8 nanometers.

[0151] In some cases, the technology described herein relates to a semiconductor structure in which the shortest distance between the bottom of the underlying nanosheet and the source / drain features is between 9 nanometers and 12 nanometers.

[0152] In some embodiments, the technology described herein relates to a semiconductor structure that further includes a contact etch stop layer disposed on the sidewall of a gate structure, on the sidewall of an adjacent gate structure, and over a shallow trench isolation feature between the gate structure and the adjacent gate structure, wherein a first height measured from the bottom of the underlying nanosheet to the bottom of the contact etch stop layer is 4 nanometers to 6 nanometers.

[0153] In some embodiments, the technology described herein relates to a semiconductor structure that further includes a contact etch stop layer disposed on the sidewall of a gate structure, on the sidewall of an adjacent gate structure, and over a shallow trench isolation feature between the gate structure and the adjacent gate structure, wherein a second height, measured from the bottom of the second bottom nanosheet to the bottom of the contact etch stop layer, is 19 nanometers to 21 nanometers.

[0154] In some embodiments, the techniques described herein relate to a method of fabricating a semiconductor structure, including depositing a dielectric layer over a shallow trench isolation feature, wherein the shallow trench isolation feature is formed between a first fin and a second fin on a substrate, each of the first and second fins comprising an epitaxial stack having at least one sacrificial epitaxial layer and at least one channel epitaxial layer, the dielectric layer reducing the loss of the shallow trench isolation feature during a subsequent etching step. The method includes patterning a sacrificial gate stack on a channel region of the first fin, forming source / drain regions, forming a contact etch stop layer, and performing a metal gate replacement step to form a metal gate comprising multiple nanosheets.

[0155] In some cases, the technique described herein is about a method in which the shortest distance P′ between a point in the source / drain region and a point on the underlying nanosheet of the metal gate is between about 9 nanometers and about 12 nanometers after the metal gate replacement step.

[0156] In some cases, the technique described herein relates to a method in which, after a metal gate replacement step, the height Ha′ from the top of the shallow trench isolation feature to the bottom of the metal is measured on a plane intersecting with the nanosheet in the range of about 2 nanometers to about 4 nanometers.

[0157] In some cases, the technique described herein relates to a method in which, after a metal gate replacement step, the height Hb′ from the top of the shallow trench isolation feature to the bottom of the metal is measured on a plane outside the nanosheet in the range of about 2 nanometers to about 4 nanometers.

[0158] In some cases, the technique described herein is about a method in which, after the metal gate replacement step, the height M1′ from the bottom of the bottommost nanosheet to the bottom of the contact etch stop layer is between about 4 nanometers and about 6 nanometers.

[0159] In some cases, the technique described herein relates to a method in which, after the metal gate replacement step, the height M2′ from the bottom of the second bottom nanosheet to the bottom of the contact etch stop layer is between about 19 nanometers and about 21 nanometers.

[0160] In some cases, the technique described herein relates to a method in which, after the metal gate replacement step, the height M3′ from the bottom of the third bottom nanosheet to the bottom of the contact etch stop layer is between approximately 34 nm and approximately 36 nm.

[0161] In some embodiments, the technology described herein relates to a semiconductor structure comprising fins comprising multiple nanosheets disposed on a substrate, shallow trench isolation features disposed adjacent to the fins, a dielectric layer disposed above the shallow trench isolation features, a gate structure disposed above a channel region of the nanosheets, a contact etch stop layer disposed on the sidewalls of the gate structure and above the shallow trench isolation features, and multiple source / drain features disposed on opposite sides of the channel region, wherein the height measured from the bottom of the bottommost nanosheet among the nanosheets to the bottom of the contact etch stop layer is between 4 nanometers and 6 nanometers.

[0162] In some cases, the technique described herein relates to a semiconductor structure in which the height measured from the bottom of the second bottom nanosheet within the nanosheet to the bottom of the contact etch stop layer is between 19 nanometers and 21 nanometers.

[0163] In some cases, the technique described herein relates to a semiconductor structure in which the height measured from the bottom of the third bottom nanosheet among the nanosheets to the bottom of the contact etch stop layer is between 34 nanometers and 36 nanometers.

[0164] In some embodiments, the technology described herein relates to a semiconductor structure, wherein the semiconductor structure includes a plurality of shallow trench isolation features disposed between a first fin and a second fin on a substrate, a dielectric layer disposed above the shallow trench isolation features and having a thickness between 1 nanometer and 4 nanometers, a gate structure disposed on a plurality of channel regions of the first fin, a plurality of gate spacers disposed on the sidewalls of the gate structure, a plurality of source / drain features disposed on opposite sides of the gate structure, and a plurality of inner spacers separating the source / drain features and the gate structure.

[0165] In some cases, the technology described herein relates to a semiconductor structure in which the height between the top of the outer gate shallow trench isolation, defined within the inner gate stop layer and the shallow trench isolation feature, is between 3 nanometers and 10 nanometers.

[0166] While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist in the embodiments. It should also be understood that one or more exemplary embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of this disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with convenient planning for implementing exemplary embodiments of this disclosure. It should be understood that various changes may be made to the function and configuration of the components described in the exemplary embodiments without departing from the scope of this disclosure as set forth in the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Multiple nanosheets are disposed on a substrate; A gate structure is disposed above a channel region of the plurality of nanosheets; Multiple source / drain features are positioned on opposite sides of this channel region; as well as Multiple shallow trench isolation features are disposed on the substrate; The bottom nanosheet of the plurality of nanosheets enters a metal depth of less than or equal to 4 nanometers into the plurality of shallow trench isolation features.

2. The semiconductor structure as described in claim 1, characterized in that, The depth of the metal is between 2 nanometers and 4 nanometers.

3. The semiconductor structure as described in claim 1, characterized in that, The shortest distance between the bottom of the underlying nanosheet and the plurality of source / drain features is greater than 8 nanometers.

4. The semiconductor structure as described in claim 1, characterized in that, The shortest distance between the bottom of the underlying nanosheet and the plurality of source / drain features is between 9 nanometers and 12 nanometers.

5. The semiconductor structure as described in claim 1, characterized in that, The device further includes a contact etch stop layer disposed on the sidewall of the gate structure, on the sidewall of an adjacent gate structure, and above the plurality of shallow trench isolation features between the gate structure and the adjacent gate structure, wherein a first height measured from a bottom of the underlying nanosheet to a bottom of the contact etch stop layer is 4 nanometers to 6 nanometers.

6. A semiconductor structure, characterized in that, include: A fin is disposed on a substrate, wherein the fin comprises multiple nanosheets; A shallow groove isolation feature is provided adjacent to the fin; A dielectric layer is disposed above the shallow trench isolation feature; A gate structure is disposed above a channel region of the plurality of nanosheets; A contact etch stop layer is disposed on the sidewall of the gate structure and above the shallow trench isolation feature, wherein the height measured from a bottom of the bottommost nanosheet among the plurality of nanosheets to a bottom of the contact etch stop layer is between 4 nanometers and 6 nanometers; and Multiple source / drain features are located on opposite sides of this channel region.

7. The semiconductor structure as described in claim 6, characterized in that, The height of the contact etch stop layer, measured from the bottom of a second bottom layer nanosheet among the plurality of nanosheets, is between 19 nanometers and 21 nanometers.

8. The semiconductor structure as described in claim 6, characterized in that, The height of the contact etch stop layer, measured from the bottom of a third bottom layer nanosheet among the plurality of nanosheets, is between 34 nanometers and 36 nanometers.

9. A semiconductor structure, characterized in that, include: Multiple shallow trench isolation features are disposed between a first fin and a second fin on a substrate; A dielectric layer is disposed above the plurality of shallow trench isolation features, wherein the dielectric layer has a thickness between 1 nanometer and 4 nanometers; A gate structure is disposed on multiple channel regions of the first fin; Multiple gate spacers are disposed on the sidewalls of the gate structure; Multiple source / drain features are disposed on opposite sides of the gate structure; as well as Multiple inner spacers separate the multiple source / drain features from the gate structure.

10. The semiconductor structure as described in claim 9, characterized in that, The height between the top of an outer gate shallow trench isolation layer and the plurality of shallow trench isolation features is between 3 nanometers and 10 nanometers.

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