Liquid crystal initialization timing control circuit

Abstract

This application relates to a liquid crystal initialization timing control circuit, comprising: a delayed turn-on module and a delayed turn-off module. The delayed turn-on module includes a first input terminal, a capacitor C1, a resistor R3, and a MOSFET Q1. The first end of capacitor C1 is electrically connected to both the first input terminal and the first end of resistor R3. The second end of capacitor C1 is electrically connected to the second end of resistor R3. The first end of resistor R3 is electrically connected to MOSFET Q1. The delayed turn-off module includes a second input terminal, a capacitor C2, a resistor R8, and a MOSFET Q2. The first end of capacitor C2 is grounded. The second end of capacitor C2 is electrically connected to the first end of resistor R8. The second end of resistor R8 is electrically connected to the second input terminal. The first end of resistor R8 is electrically connected to MOSFET Q2. The second input terminal is also electrically connected to MOSFET Q2. The solution provided by this application can forcibly pull down the VGH voltage to the VGL voltage, thereby eliminating residual charge on the TFTs of the preceding circuit.

Description

Technical Field

[0001] This utility model relates to the field of liquid crystal display technology, and in particular to a liquid crystal initialization timing control circuit. Background Technology

[0002] Currently, oxide semiconductor TFTs are being used instead of traditional amorphous silicon TFTs because oxide semiconductor TFTs have higher electron mobility, making them suitable for high-resolution and high-refresh-rate displays.

[0003] In related technologies, VGH and VGL voltages are two crucial voltages in gate driving. VGH is a high-level voltage used to turn on the TFTs, while VGL is a low-level voltage used to turn off the TFTs. The timing and level control of these voltages are critical in the array substrate row driving circuit to ensure correct transmission of the scan signal. The array substrate row driving circuit turns on the gate lines row by row through a cascaded structure, with the output of each stage depending on the trigger signal of the previous stage. However, if the VGH voltage is not reset to the VGL voltage upon power-up, residual charge may remain on the TFTs of the preceding stage, leading to false triggering or cascade timing errors, resulting in flickering or horizontal line defects on the display panel. Utility Model Content

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a liquid crystal initialization timing control circuit that can force the VGH voltage down to the VGL voltage, thereby eliminating the residual charge of the TFT in the front-end circuit and thus avoiding the problem of flickering or horizontal line defects on the display panel.

[0005] The objective of this utility model is achieved through the following technical solution:

[0006] The first aspect of this application provides a liquid crystal initialization timing control circuit, comprising: a delay-on module, including a first input terminal, a capacitor C1, a resistor R3, and a MOSFET Q1, wherein the first end of the capacitor C1 is electrically connected to the first input terminal and the first end of the resistor R3, the second end of the capacitor C1 is electrically connected to the second end of the resistor R3, and the first end of the resistor R3 is electrically connected to the MOSFET Q1; and a delay-off module, including a second input terminal, a capacitor C2, a resistor R8, and a MOSFET Q2, wherein the first end of the capacitor C2 is grounded, the second end of the capacitor C2 is electrically connected to the first end of the resistor R8, the second end of the resistor R8 is electrically connected to the second input terminal, the first end of the resistor R8 is electrically connected to the MOSFET Q2, and the second input terminal is electrically connected to the MOSFET Q2.

[0007] The first input terminal is the VGH voltage input terminal.

[0008] The second input terminal is the VGL voltage input terminal.

[0009] The delay-on module also includes resistors R1 and R2. The first end of resistor R1 is electrically connected to the MOS transistor Q1, and the second end of resistor R1 is electrically connected to the first end of resistor R2.

[0010] The delay-on module also includes a first output terminal, which is electrically connected to the second terminal of the resistor R2.

[0011] The delay conduction module also includes resistors R4 and R5. The first end of resistor R4 is electrically connected to the first end of resistor R2, the first end of resistor R5 is electrically connected to MOS transistor Q1, and the second end of resistor R5 is grounded.

[0012] The delay shutdown module also includes a resistor R7, the first end of which is electrically connected to the second end of the resistor R4.

[0013] The delay shutdown module also includes a second output terminal, which is electrically connected to the second end of the resistor R7.

[0014] The delay shutdown module also includes a resistor R6, with the first end of the resistor R6 grounded and the second end of the resistor R6 electrically connected to the MOS transistor Q2.

[0015] The resistance value of resistor R8 is different from that of resistor R3.

[0016] Compared with the prior art, the present invention has at least the following advantages:

[0017] By setting up a delay network using capacitor C2 and resistor R8, the turn-off of MOSFET Q2 is delayed, ensuring that the OVGL signal is turned off only after a certain time has elapsed since the VGL voltage drops. Similarly, by setting up a delay network using capacitor C1 and resistor R3, the turn-on of MOSFET Q1 is delayed, ensuring that the VGHD signal is turned on only after a certain time has elapsed since the VGH voltage rises. Thus, by adjusting these two delay networks, the VGL voltage is turned off before the VGH voltage turns on. This achieves the goal of forcibly pulling the VGH voltage down to the VGL voltage at power-on, eliminating display flickering or horizontal line defects caused by residual charge. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings used in the embodiments will be briefly described below.

[0019] Figure 1 This is a functional block diagram of the liquid crystal initialization timing control circuit in one embodiment of the present invention;

[0020] Figure 2 This is a circuit diagram of the liquid crystal initialization timing control circuit in one embodiment of the present invention. Detailed Implementation

[0021] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While embodiments of this application are shown in the drawings, it should be understood that this application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to make this application more thorough and complete, and to fully convey the scope of this application to those skilled in the art.

[0022] It should be understood that although the terms "first," "second," "third," etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0023] Unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0024] VGH and VGL voltages are two crucial voltages in gate driving. VGH is a high-level voltage used to turn on the TFTs, while VGL is a low-level voltage used to turn off the TFTs. In the array substrate row driving circuit, the timing and level control of these voltages are critical to ensure correct transmission of the scan signal. The array substrate row driving circuit turns on the gate lines row by row through a cascaded structure, with the output of each stage depending on the trigger signal of the previous stage. However, if the VGH voltage is not reset to the VGL voltage upon power-up, residual charge may remain on the TFTs of the preceding stage, leading to false triggering or cascade timing errors, resulting in flickering or horizontal line defects on the display panel.

[0025] To address the aforementioned issues, this application provides a liquid crystal initialization timing control circuit that can forcibly pull down the VGH voltage to the VGL voltage, thereby eliminating residual charge on the TFTs of the preceding circuit and thus avoiding the problem of flickering or horizontal line defects on the display panel.

[0026] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0027] Please see Figure 1 and Figure 2 A liquid crystal initialization timing control circuit includes: a delay-on module 100 and a delay-off module 200. The delay-on module 100 includes a first input terminal, a capacitor C1, a resistor R3, and a MOSFET Q1. The first end of the capacitor C1 is electrically connected to the first input terminal and the first end of the resistor R3. The second end of the capacitor C1 is electrically connected to the second end of the resistor R3. The first end of the resistor R3 is electrically connected to the MOSFET Q1. The delay-off module 200 includes a second input terminal, a capacitor C2, a resistor R8, and a MOSFET Q2. The first end of the capacitor C2 is grounded. The second end of the capacitor C2 is electrically connected to the first end of the resistor R8. The second end of the resistor R8 is electrically connected to the second input terminal. The first end of the resistor R8 is electrically connected to the MOSFET Q2. The second input terminal is electrically connected to the MOSFET Q2.

[0028] It should be noted that the first input terminal is the VGH voltage input terminal, and the second input terminal is the VGL voltage input terminal, where VGH voltage is positive and VGL voltage is negative. A delay network is formed by capacitor C2 and resistor R8, thereby delaying the turn-off of MOSFET Q2 and ensuring that the OVGL signal is turned off only after a certain time following the drop in VGL voltage. Similarly, a delay network is formed by capacitor C1 and resistor R3, thereby delaying the turn-on of MOSFET Q1 and ensuring that the VGHD signal is turned on only after a certain time following the rise in VGH voltage. In this way, by adjusting the two delay networks, the VGL voltage is turned off before the VGH voltage turns on. This achieves the goal of forcibly pulling the VGH voltage down to the VGL voltage at power-on, eliminating problems such as display flickering or horizontal line defects caused by residual charge.

[0029] It should also be noted that, in order to ensure that the turn-on delay of MOSFET Q1 is greater than the turn-off delay of MOSFET Q2, the resistance value of resistor R8 is different from that of resistor R3.

[0030] Please see Figure 2 In one embodiment, the delay-on module 100 further includes resistors R1 and R2, with the first end of resistor R1 electrically connected to MOSFET Q1 and the second end of resistor R1 electrically connected to the first end of resistor R2.

[0031] It should be noted that resistors R1 and R2 serve to limit current and divide voltage.

[0032] Please see Figure 2 In one embodiment, the delay-on module 100 further includes a first output terminal, which is electrically connected to the second terminal of the resistor R2.

[0033] It should be noted that the first output terminal is used to output the VGHD signal.

[0034] Please see Figure 2 In one embodiment, the delay conduction module 100 further includes resistors R4 and R5. The first end of resistor R4 is electrically connected to the first end of resistor R2, the first end of resistor R5 is electrically connected to MOSFET Q1, and the second end of resistor R5 is grounded.

[0035] It should be noted that resistors R4 and R5 serve to limit current and divide voltage.

[0036] Please see Figure 2 In one embodiment, the delay shutdown module 200 further includes a resistor R7, the first end of which is electrically connected to the second end of the resistor R4. The resistor R7 serves as a current limiter and voltage divider.

[0037] Please see Figure 2 In one embodiment, the delay shutdown module 200 further includes a second output terminal, which is electrically connected to the second end of the resistor R7. The second output terminal is used to output the VGL signal.

[0038] Please see Figure 2 In one embodiment, the delay shutdown module 200 further includes a resistor R6, with its first end grounded and its second end electrically connected to the MOSFET Q2. The resistor R6 serves as a current limiter and voltage divider.

[0039] The circuit principle of this application is explained below:

[0040] The VGH voltage enters from the first input terminal. When the VGH voltage rises, capacitor C1 charges through resistor R3, thus delaying the rise of the gate voltage of MOSFET Q1. Because the turn-on of MOSFET Q1 is delayed, the VGHD signal is delayed. The second terminal of resistor R5 is grounded to ensure that MOSFET Q1 remains off when there is no input signal. The VGL voltage enters from the second input terminal. When the VGL voltage drops, capacitor C2 discharges through resistor R6, thus delaying the drop of the gate voltage of MOSFET Q2. This delays the turn-off of MOSFET Q2, thus delaying the VGL signal. Resistor R6 is grounded to ensure that MOSFET Q2 remains on when there is no input signal.

[0041] The solution of this application has been described in detail above with reference to the accompanying drawings. In the above embodiments, the descriptions of each embodiment have different focuses; for parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Those skilled in the art should also understand that the actions and modules involved in the specification are not necessarily essential to this application. Furthermore, it is understood that the steps in the method of this application embodiment can be adjusted, combined, and deleted according to actual needs, and the modules in the device of this application embodiment can be combined, divided, and deleted according to actual needs.

[0042] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A liquid crystal initialization timing control circuit, characterized in that, include: The delayed conduction module includes a first input terminal, a capacitor C1, a resistor R3, and a MOSFET Q1. The first end of the capacitor C1 is electrically connected to the first input terminal and the first end of the resistor R3, the second end of the capacitor C1 is electrically connected to the second end of the resistor R3, and the first end of the resistor R3 is electrically connected to the MOSFET Q1. The delayed shutdown module includes a second input terminal, a capacitor C2, a resistor R8, and a MOSFET Q2. The first terminal of the capacitor C2 is grounded, the second terminal of the capacitor C2 is electrically connected to the first terminal of the resistor R8, the second terminal of the resistor R8 is electrically connected to the second input terminal, the first terminal of the resistor R8 is electrically connected to the MOSFET Q2, and the second input terminal is electrically connected to the MOSFET Q2.

2. The liquid crystal initialization timing control circuit according to claim 1, characterized in that, The first input terminal is the VGH voltage input terminal.

3. The liquid crystal initialization timing control circuit according to claim 1, characterized in that, The second input terminal is the VGL voltage input terminal.

4. The liquid crystal initialization timing control circuit according to claim 2, characterized in that, The delay-on module also includes resistors R1 and R2. The first end of resistor R1 is electrically connected to the MOS transistor Q1, and the second end of resistor R1 is electrically connected to the first end of resistor R2.

5. The liquid crystal initialization timing control circuit according to claim 4, characterized in that, The delay-on module also includes a first output terminal, which is electrically connected to the second terminal of the resistor R2.

6. The liquid crystal initialization timing control circuit according to claim 4, characterized in that, The delay conduction module also includes resistors R4 and R5. The first end of resistor R4 is electrically connected to the first end of resistor R2, the first end of resistor R5 is electrically connected to MOS transistor Q1, and the second end of resistor R5 is grounded.

7. The liquid crystal initialization timing control circuit according to claim 6, characterized in that, The delay shutdown module also includes a resistor R7, the first end of which is electrically connected to the second end of the resistor R4.

8. The liquid crystal initialization timing control circuit according to claim 7, characterized in that, The delay shutdown module also includes a second output terminal, which is electrically connected to the second end of the resistor R7.

9. The liquid crystal initialization timing control circuit according to claim 8, characterized in that, The delay shutdown module also includes a resistor R6, with the first end of the resistor R6 grounded and the second end of the resistor R6 electrically connected to the MOS transistor Q2.

10. The liquid crystal initialization timing control circuit according to claim 1, characterized in that, The resistance value of resistor R8 is different from that of resistor R3.

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