A data anomaly detection alarm circuit

Abstract

The utility model relates to data detection technical field, concretely, relate to a kind of data anomaly detection alarm circuit, including the sensor that is electrically connected in turn, amplification module, filter module, comparison module, timing module, main control module and alarm module, main control module includes processor U6, amplification module is amplified based on operational amplifier circuit to signal processing, filter module is based on low-pass filter circuit and filters interference signal, comparison module is based on window comparison circuit and detects signal anomaly, timing module is based on timer circuit and detects the duration of abnormal signal, comparison module is also electrically connected with main control module.The utility model in the present application, window comparison circuit can quickly detect whether signal exceeds normal range by preset upper and lower threshold, timing module can quantify the duration of abnormal signal, avoid to misjudge as abnormal for instantaneous fluctuation, greatly reduce false alarm rate, make detection result more close to actual scene demand.

Description

Technical Field

[0001] This utility model relates to the field of data detection technology, and more specifically, to a data anomaly detection and alarm circuit. Background Technology

[0002] In the field of data detection technology, real-time monitoring and early warning of anomalies for various physical quantities are key to ensuring industrial production, equipment operation and environmental safety. In existing data anomaly detection solutions, some circuits have insufficient signal processing accuracy: the raw signals output by sensors are often weak and mixed with high-frequency noise, which can easily lead to misjudgment of anomalies if detected directly; at the same time, most detection circuits can only identify whether the signal exceeds the threshold, but it is difficult to distinguish between fluctuations caused by instantaneous interference and real continuous anomalies, resulting in frequent false alarms and missed alarms.

[0003] The utility model patent with announcement number CN221485808U discloses a data center intelligent data acquisition circuit, including a main control circuit, a data detection circuit, an alarm circuit, a control circuit, and a host computer. The data detection circuit is used to detect various types of data in the computer room, the main control circuit is used to process various types of data transmitted by the data detection circuit, the alarm circuit and the control circuit are both controlled by the main control circuit, and the control circuit is used to control the on / off state of the data detection circuit.

[0004] Although the data detection circuit in this utility model monitors various data in the data center computer room and transmits the data to the main control chip, and provides real-time feedback to the host computer, which then sends corresponding instructions, the control circuit can operate and disconnect the data detection circuit when monitoring is not required, thus saving resources. Furthermore, it can provide audible and visual alarms through the alarm circuit in case of abnormalities, making it more practical. However, it can only identify whether the signal exceeds the threshold, but it is difficult to distinguish between fluctuations caused by instantaneous interference and real continuous abnormalities, leading to false alarms and missed alarms. Utility Model Content

[0005] The purpose of this invention is to provide a data anomaly detection and alarm circuit to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, this utility model provides the following technical solution:

[0007] A data anomaly detection and alarm circuit includes a sensor, an amplification module, a filtering module, a comparison module, a timing module, a main control module, and an alarm module connected in sequence. The main control module includes a processor U6. The amplification module amplifies the signal based on an operational amplifier circuit. The filtering module filters out interference signals based on a low-pass filter circuit. The comparison module detects signal anomalies based on a window comparison circuit. The timing module detects the duration of the abnormal signal based on a timer circuit. The comparison module is also electrically connected to the main control module. The main control module controls the alarm module to issue an audible and visual alarm according to a preset program and the data output by the comparison module and the timing module.

[0008] Preferably, the amplification module includes resistors R1, R2, R3, R4, R5 and operational amplifier U1;

[0009] The first ends of resistors R1 and R2 are respectively connected to the two output terminals of the sensor. The second end of resistor R1 is connected to the non-inverting input terminal of operational amplifier U1, and the second end of resistor R2 is connected to the inverting input terminal of operational amplifier U1. The first end of resistor R3 is grounded, and the second end of resistor R3 is connected to the non-inverting input terminal of operational amplifier U1. The first end of resistor R4 is connected to the inverting input terminal of operational amplifier U1, and the second end of resistor R4 is connected to the output terminal of operational amplifier U1. The first end of resistor R5 is connected to the output terminal of operational amplifier U1.

[0010] Preferably, the filtering module includes resistor R6, resistor R7, capacitor C1, capacitor C2, resistor R8, resistor R9, and operational amplifier U2;

[0011] The first terminal of resistor R6 is connected to the output terminal of operational amplifier U1. The second terminal of resistor R6 is connected to the first terminal of resistor R7. The second terminal of resistor R7 is connected to the non-inverting input terminal of operational amplifier U2. The first terminal of capacitor C1 is connected to the second terminal of resistor R6. The second terminal of capacitor C1 is connected to the output terminal of operational amplifier U2. The first terminal of capacitor C2 is connected to the second terminal of resistor R7. The second terminal of capacitor C2 is grounded. The first terminal of resistor R8 is connected to the inverting input terminal of operational amplifier U2. The second terminal of resistor R8 is connected to the output terminal of operational amplifier U2. The first terminal of resistor R9 is connected to the inverting input terminal of operational amplifier U2. The second terminal of resistor R9 is grounded.

[0012] In these two settings, the amplification module amplifies the weak signal output by the sensor through an operational amplifier circuit, enhancing the signal strength and facilitating subsequent circuit processing; the low-pass filter circuit of the filtering module can filter out high-frequency interference, making the signal more stable and providing good conditions for accurate anomaly detection.

[0013] Preferably, the comparison module includes power supply VCC, resistor R10, resistor R11, operational amplifier U3, diode D1, resistor R12, resistor R13, operational amplifier U4, and diode D2;

[0014] The first terminal of resistor R10 is connected to the power supply VCC, the second terminal of resistor R10 is connected to the first terminal of resistor R11, the second terminal of resistor R11 is grounded, the inverting input terminal of operational amplifier U3 is connected to the second terminal of resistor R10, and the non-inverting input terminal of operational amplifier U3 is connected to the output terminal of operational amplifier U2.

[0015] The first terminal of resistor R12 is connected to the power supply VCC, the second terminal of resistor R12 is connected to the first terminal of resistor R13, the second terminal of resistor R13 is grounded, the non-inverting input terminal of operational amplifier U4 is connected to the second terminal of resistor R12, and the inverting input terminal of operational amplifier U4 is connected to the output terminal of operational amplifier U2.

[0016] The positive terminal of diode D1 is connected to the output terminal of operational amplifier U3, the positive terminal of diode D2 is connected to the output terminal of operational amplifier U4, the negative terminal of diode D1 is connected to the negative terminal of diode D2, and the negative terminal of diode D2 is also connected to the input port of processor U6.

[0017] Preferably, the timing module includes two cascaded counter chips U5. The ENP and ENT pins of the first-stage counter chip U5 are connected to the negative terminal of diode D2. The RCO pin of the first-stage counter chip U5 is connected to the ENP and ENT pins of the second-stage counter chip U5. The Q0, Q1, Q2, and Q3 pins of the two counter chips U5 are respectively connected to different input ports of the processor U6. The CLK pin of the two counter chips U5 is connected to an external clock signal. The CLR pin of the two counter chips U5 is connected to the control port of the processor U6.

[0018] In these two settings, the window comparison circuit of the comparison module can quickly identify whether the signal exceeds the normal range by using preset upper and lower thresholds, thus realizing the preliminary judgment of abnormal signals; the timing module detects the duration of abnormal signals through the cascaded counter chip U5, which can distinguish between instantaneous fluctuations and continuous abnormalities, reduce false judgments, and make the detection more in line with the actual situation.

[0019] Preferably, the alarm module includes resistor R14, resistor R15, transistor Q1, resistor R16, indicator light L, resistor R17, resistor R18, transistor Q2, resistor R19 and buzzer BL, wherein transistors Q1 and Q2 are both PNP type transistors.

[0020] The first terminals of resistors R14 and R17 are respectively connected to different control pins of processor U6;

[0021] The second terminal of resistor R14 is connected to the base of transistor Q1, the first terminal of resistor R15 is connected to power supply VCC, the second terminal of resistor R15 is connected to the second terminal of resistor R14, the emitter of transistor Q1 is connected to power supply VCC, the collector of transistor Q1 is connected to the first terminal of resistor R16, the second terminal of resistor R16 is connected to the first terminal of indicator light L, and the second terminal of indicator light L is grounded.

[0022] The second terminal of resistor R17 is connected to the base of transistor Q2. The first terminal of resistor R18 is connected to power supply VCC. The second terminal of resistor R18 is connected to the second terminal of resistor R17. The emitter of transistor Q2 is connected to power supply VCC. The collector of transistor Q2 is connected to the first terminal of resistor R19. The second terminal of resistor R19 is connected to the first terminal of buzzer BL. The second terminal of buzzer BL is grounded.

[0023] This setting uses a combination of sound and light alarms to ensure that abnormal situations can be detected in a timely manner in different environments, thus improving the effectiveness of the alarm.

[0024] Compared with the prior art, the beneficial effects of this utility model are:

[0025] 1. This utility model significantly improves signal quality by setting up an amplification module and a filtering module. The amplification module uses an operational amplifier circuit to accurately amplify weak signals, ensuring the sensitivity of subsequent detection stages to signal changes. The filtering module uses a low-pass filter circuit, which can effectively filter out high-frequency interference signals, reduce the impact of noise on anomaly detection, and improve detection accuracy from the source.

[0026] 2. This utility model achieves accurate identification and duration judgment of abnormal signals by setting a collaborative structure of a window comparison module and a timing module. The window comparison circuit can quickly detect whether the signal exceeds the normal range by setting upper and lower thresholds. The timing module is based on a cascaded counter chip U5, which can quantify the duration of abnormal signals, avoid misjudging instantaneous fluctuations as abnormalities, greatly reduce the false alarm rate, and make the detection results more in line with the actual needs of the scenario.

[0027] 3. This utility model improves the effectiveness and flexibility of alarms by setting up a linkage mechanism between the main control module and the sound and light alarm module. The main control module can flexibly control the indicator light and buzzer to work according to the preset program and abnormal data, so as to realize the synchronous sound and light alarm. It can remind people with sound in well-lit environments and warn people with light in noisy environments, ensuring that abnormal information is captured in time. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the overall structure of the utility model;

[0029] Figure 2 This is a circuit diagram of the amplification module in the utility model.

[0030] Figure 3 This is a circuit diagram of the filter module in the utility model.

[0031] Figure 4 This is a circuit diagram of the comparison module in the utility model;

[0032] Figure 5This is a schematic diagram showing the connection between the timing module and the main control module in the utility model.

[0033] Figure 6 This is a circuit diagram of the alarm module in the utility model.

[0034] In the picture:

[0035] 100. Sensor; 200. Amplification module; 300. Filtering module; 400. Comparison module; 500. Timing module; 600. Main control module; 700. Alarm module. Detailed Implementation

[0036] The technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0037] Please see Figure 1 Figure 6 The present invention provides the following technical solution:

[0038] A data anomaly detection and alarm circuit includes a sensor 100, an amplification module 200, a filtering module 300, a comparison module 400, a timing module 500, a main control module 600, and an alarm module 700, which are electrically connected in sequence. The main control module 600 includes a processor U6. The amplification module 200 amplifies the signal based on an operational amplifier circuit. The filtering module 300 filters out interference signals based on a low-pass filter circuit. The comparison module 400 detects signal anomalies based on a window comparison circuit. The timing module 500 detects the duration of the abnormal signal based on a timer circuit. The comparison module 400 is also electrically connected to the main control module 600. The system controls the alarm module 700 to issue an audible and visual alarm based on the data output from the preset program, comparison module 400, and timing module 500. Through the sequential collaborative work of each module, a complete process from signal acquisition and processing to anomaly judgment and alarm is realized. The amplification module 200 and the filtering module 300 improve signal quality, providing a reliable foundation for subsequent detection. The combination of comparison module 400 and timing module 500 can quickly identify anomalies and distinguish between instantaneous fluctuations and continuous anomalies, reducing the false alarm rate. The linkage between the main control module 600 and the alarm module 700 ensures that abnormal information can be transmitted in a timely manner in the form of sound and light, adapting to the early warning needs of different scenarios.

[0039] In this embodiment, please refer to Figures 1-3 The amplification module 200 includes resistors R1, R2, R3, R4, R5 and operational amplifier U1;

[0040] The first terminals of resistors R1 and R2 are connected to the two output terminals of sensor 100, respectively. The second terminal of resistor R1 is connected to the non-inverting input terminal of operational amplifier U1, and the second terminal of resistor R2 is connected to the inverting input terminal of operational amplifier U1. The first terminal of resistor R3 is grounded, and the second terminal of resistor R3 is connected to the non-inverting input terminal of operational amplifier U1. The first terminal of resistor R4 is connected to the inverting input terminal of operational amplifier U1, and the second terminal of resistor R4 is connected to the output terminal of operational amplifier U1. The first terminal of resistor R5 is connected to the output terminal of operational amplifier U1. The amplification circuit in amplification module 200 is a differential amplifier circuit. Generally, the amplification factor is determined by the resistance values ​​of resistors R2 and R4. The differential amplifier circuit can specifically amplify the weak differential signal output by sensor 100, while effectively suppressing common-mode interference and significantly improving the signal-to-noise ratio. By accurately amplifying the weak signal, it ensures that the subsequent filtering module 300 and comparison module 400 can clearly identify signal changes, providing more reliable raw data for anomaly detection.

[0041] Specifically, the filter module 300 includes resistors R6 and R7, capacitors C1 and C2, resistors R8 and R9, and operational amplifier U2.

[0042] Resistor R6 is connected to the output of operational amplifier U1. Its second terminal is connected to the first terminal of resistor R7, and the second terminal of resistor R7 is connected to the non-inverting input of operational amplifier U2. Capacitor C1 is connected to the second terminal of resistor R6, and the second terminal of capacitor C1 is connected to the output of operational amplifier U2. Capacitor C2 is connected to the second terminal of resistor R7, and the second terminal of capacitor C2 is grounded. Resistor R8 is connected to the inverting input of operational amplifier U2, and the second terminal of resistor R8 is connected to the output of operational amplifier U2. Resistor R9 is connected to the inverting input of operational amplifier U2, and the second terminal of resistor R9 is grounded. The filtering circuit in filter module 300 is a second-order active low-pass filter circuit. This second-order active low-pass filter circuit can effectively filter out high-frequency interference noise mixed in the amplified signal, preventing noise signals from interfering with the threshold judgment of subsequent comparison module 400. By purifying the signal, the stability and accuracy of the signal are further improved, providing a cleaner input signal for anomaly detection.

[0043] In this embodiment, please refer to Figures 1-5 The comparator module 400 includes power supply VCC, resistor R10, resistor R11, operational amplifier U3, diode D1, resistor R12, resistor R13, operational amplifier U4, and diode D2.

[0044] The first terminal of resistor R10 is connected to the power supply VCC, the second terminal of resistor R10 is connected to the first terminal of resistor R11, the second terminal of resistor R11 is grounded, the inverting input terminal of operational amplifier U3 is connected to the second terminal of resistor R10, and the non-inverting input terminal of operational amplifier U3 is connected to the output terminal of operational amplifier U2.

[0045] The first terminal of resistor R12 is connected to the power supply VCC, the second terminal of resistor R12 is connected to the first terminal of resistor R13, the second terminal of resistor R13 is grounded, the non-inverting input terminal of operational amplifier U4 is connected to the second terminal of resistor R12, and the inverting input terminal of operational amplifier U4 is connected to the output terminal of operational amplifier U2.

[0046] The anode of diode D1 is connected to the output terminal of operational amplifier U3, the anode of diode D2 is connected to the output terminal of operational amplifier U4, the cathode of diode D1 is connected to the cathode of diode D2, and the cathode of diode D2 is also connected to the input port of processor U6. The reference voltage at the inverting input terminal of operational amplifier U3 is the upper threshold of the window comparator circuit, and the reference voltage at the non-inverting input terminal of operational amplifier U4 is the lower threshold of the window comparator circuit. When the signal output by filter module 300 is a normal signal, i.e., between the upper and lower thresholds, the window comparator circuit will output a low level. A pull-down resistor can be connected to the cathode of diode D2 to make the low level output more stable. When the signal output by filter module 300 is an abnormal signal, i.e., not between the upper and lower thresholds, the window comparator circuit will output a high level, which can quickly determine whether the signal is within the normal range and achieve preliminary screening of abnormal signals.

[0047] Specifically, the timing module 500 includes two synchronously cascaded counter chips U5. The ENP and ENT pins of the front-stage counter chip U5 are connected to the negative terminal of diode D2, and the RCO pin of the front-stage counter chip U5 is connected to the ENP and ENT pins of the rear-stage counter chip U5. The Q0, Q1, Q2, and Q3 pins of the two counter chips U5 are respectively connected to different input ports of the processor U6. The CLK pins of the two counter chips U5 are connected to an external clock signal, and the CLR pins of the two counter chips U5 are connected to the control port of the processor U6. When the comparator module 400 detects a signal abnormality, it outputs a high level. This signal is transmitted to the ENP and ENT pins of the front-stage counter, causing the front-stage counter chip U5 to enter the counting state. The external clock signal is input to the front-stage counter chip U5 through the CLK pin. For each clock pulse received, the front-stage counter chip U5 increments its count by 1. The counting begins. When the maximum range is reached, the RCO pin outputs a high level, triggering the subsequent counter chip U5 to start counting. By cascading two stages, the counting range is expanded to meet the timing requirements for longer durations. For even longer timing, more counter chips U5 can be cascaded later. When the abnormal signal ends, the ENP and ENT pins of the preceding counter chip U5 become inactive, stopping the counting. If timing needs to be restarted, the processor U6 sends a reset signal via the CLR pin, resetting the count to zero. The cascaded counter chip U5 can quantify the duration of the abnormal signal, achieving accurate timing through an external clock signal, avoiding misjudging instantaneous fluctuations as real abnormalities, and significantly reducing the false alarm rate. The two-stage cascading expands the counting range, meeting the detection requirements for abnormal duration in different scenarios. The processor U6 controls the reset via the CLR pin, allowing the timing module 500 to flexibly adapt to multiple abnormal detection cycles, improving the circuit's practicality.

[0048] In this embodiment, please refer to Figure 1 and Figure 6 The alarm module 700 includes resistors R14 and R15, transistor Q1, resistor R16, indicator light L, resistors R17 and R18, transistor Q2, resistor R19, and buzzer BL. Transistors Q1 and Q2 are both PNP transistors. PNP transistors conduct when their base is low and are cut off when their base is high. The combination of sound and light alarms ensures that abnormal information can be effectively captured in well-lit or noisy environments, improving the reliability and scene adaptability of the alarm.

[0049] The first terminals of resistors R14 and R17 are respectively connected to different control pins of processor U6;

[0050] The second terminal of resistor R14 is connected to the base of transistor Q1, the first terminal of resistor R15 is connected to power supply VCC, the second terminal of resistor R15 is connected to the second terminal of resistor R14, the emitter of transistor Q1 is connected to power supply VCC, the collector of transistor Q1 is connected to the first terminal of resistor R16, the second terminal of resistor R16 is connected to the first terminal of indicator light L, and the second terminal of indicator light L is grounded.

[0051] The second terminal of resistor R17 is connected to the base of transistor Q2. The first terminal of resistor R18 is connected to power supply VCC. The second terminal of resistor R18 is connected to the second terminal of resistor R17. The emitter of transistor Q2 is connected to power supply VCC. The collector of transistor Q2 is connected to the first terminal of resistor R19. The second terminal of resistor R19 is connected to the first terminal of buzzer BL. The second terminal of buzzer BL is grounded.

[0052] When the data anomaly detection alarm circuit of this utility model is in use, the sensor 100 monitors the target physical quantity in real time, converts the physical quantity into an electrical signal and outputs it to the amplification module 200.

[0053] The amplification module 200 amplifies the weak electrical signal output by the sensor 100 through the differential amplifier circuit composed of the operational amplifier U1, and improves the signal strength to meet the detection requirements of the subsequent circuit. The amplified signal is output to the filter module 300 through the resistor R5.

[0054] The filter module 300 uses a second-order active low-pass filter circuit composed of operational amplifier U2 to process the amplified signal, filter out high-frequency interference noise, and transmit the purified signal to the comparison module 400.

[0055] The window comparison circuit of the comparison module 400 sets the upper threshold and lower threshold through operational amplifiers U3 and U4 respectively, compares the filtered signal with the upper and lower thresholds, and outputs a high level if the signal is not within the threshold range, and synchronously transmits the abnormal signal to the timing module 500 and the main control module 600.

[0056] When the timing module 500 receives a high-level abnormal signal from the comparator module 400, the ENP and ENT pins of the front-end counter chip U5 are activated, and it begins counting the duration of the abnormal signal based on the external clock signal. When the front-end counter reaches its full range, its RCO pin outputs a high level, triggering the rear-end counter chip U5 to start counting and extend the timing range. The Q0, Q1, Q2, and Q3 pins of the rear-end counter chip U5 transmit the counting result to the processor U6, realizing the quantization of the abnormal duration.

[0057] The processor U6 of the main control module 600 receives the abnormal signal from the comparison module 400 and the duration data from the timing module 500, and makes a judgment based on the preset program. For example, if an abnormal duration threshold is set, and the duration of the abnormal signal reaches the preset threshold, the processor U6 outputs a control signal to the alarm module 700.

[0058] After receiving the control signal from the processor U6, the alarm module 700 turns on transistors Q1 and Q2. Transistor Q1 turns on to power on the indicator light L, realizing a visual alarm; transistor Q2 turns on to power on the buzzer BL, realizing an audible alarm, thus completing the timely warning of data anomalies.

[0059] The foregoing has shown and described the basic principles, main features, and advantages of this utility model. Those skilled in the art should understand that this utility model is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the utility model. Various changes and modifications can be made to this utility model without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed utility model. The scope of protection of this utility model is defined by the appended claims and their equivalents.

Claims

1. A data anomaly detection and alarm circuit, comprising a sensor (100), an amplification module (200), a filtering module (300), a comparison module (400), a timing module (500), a main control module (600), and an alarm module (700) connected in sequence, characterized in that: The main control module (600) includes a processor U6. The amplification module (200) amplifies the signal based on an operational amplifier circuit. The filtering module (300) filters out interference signals based on a low-pass filter circuit. The comparison module (400) detects signal abnormalities based on a window comparison circuit. The timing module (500) detects the duration of the abnormal signal based on a timer circuit. The comparison module (400) is also electrically connected to the main control module (600). The main control module (600) controls the alarm module (700) to issue an audible and visual alarm based on the data output by the comparison module (400) and the timing module (500) according to a preset program.

2. The data anomaly detection alerting circuit of claim 1, wherein: The amplification module (200) includes resistors R1, R2, R3, R4, R5 and operational amplifier U1; The first ends of resistors R1 and R2 are respectively connected to the two output terminals of the sensor (100). The second end of resistor R1 is connected to the non-inverting input terminal of operational amplifier U1, the second end of resistor R2 is connected to the inverting input terminal of operational amplifier U1, the first end of resistor R3 is grounded, the second end of resistor R3 is connected to the non-inverting input terminal of operational amplifier U1, the first end of resistor R4 is connected to the inverting input terminal of operational amplifier U1, the second end of resistor R4 is connected to the output terminal of operational amplifier U1, and the first end of resistor R5 is connected to the output terminal of operational amplifier U1.

3. The data anomaly detection alerting circuit of claim 2, wherein: The filtering module (300) includes resistors R6 and R7, capacitors C1 and C2, resistors R8 and R9, and operational amplifier U2; The first terminal of resistor R6 is connected to the output terminal of operational amplifier U1. The second terminal of resistor R6 is connected to the first terminal of resistor R7. The second terminal of resistor R7 is connected to the non-inverting input terminal of operational amplifier U2. The first terminal of capacitor C1 is connected to the second terminal of resistor R6. The second terminal of capacitor C1 is connected to the output terminal of operational amplifier U2. The first terminal of capacitor C2 is connected to the second terminal of resistor R7. The second terminal of capacitor C2 is grounded. The first terminal of resistor R8 is connected to the inverting input terminal of operational amplifier U2. The second terminal of resistor R8 is connected to the output terminal of operational amplifier U2. The first terminal of resistor R9 is connected to the inverting input terminal of operational amplifier U2. The second terminal of resistor R9 is grounded.

4. The data anomaly detection and alarm circuit according to claim 3, characterized in that: The comparison module (400) includes power supply VCC, resistor R10, resistor R11, operational amplifier U3, diode D1, resistor R12, resistor R13, operational amplifier U4 and diode D2; The first terminal of resistor R10 is connected to the power supply VCC, the second terminal of resistor R10 is connected to the first terminal of resistor R11, the second terminal of resistor R11 is grounded, the inverting input terminal of operational amplifier U3 is connected to the second terminal of resistor R10, and the non-inverting input terminal of operational amplifier U3 is connected to the output terminal of operational amplifier U2. The first terminal of resistor R12 is connected to the power supply VCC, the second terminal of resistor R12 is connected to the first terminal of resistor R13, the second terminal of resistor R13 is grounded, the non-inverting input terminal of operational amplifier U4 is connected to the second terminal of resistor R12, and the inverting input terminal of operational amplifier U4 is connected to the output terminal of operational amplifier U2. The positive terminal of diode D1 is connected to the output terminal of operational amplifier U3, the positive terminal of diode D2 is connected to the output terminal of operational amplifier U4, the negative terminal of diode D1 is connected to the negative terminal of diode D2, and the negative terminal of diode D2 is also connected to the input port of processor U6.

5. The data anomaly detection alerting circuit of claim 4, wherein: The timing module (500) includes two synchronously cascaded counter chips U5. The ENP and ENT pins of the first-stage counter chip U5 are connected to the negative terminal of diode D2. The RCO pin of the first-stage counter chip U5 is connected to the ENP and ENT pins of the second-stage counter chip U5. The Q0, Q1, Q2 and Q3 pins of the two counter chips U5 are respectively connected to different input ports of the processor U6. The CLK pin of the two counter chips U5 is connected to an external clock signal. The CLR pin of the two counter chips U5 is connected to the control port of the processor U6.

6. The data anomaly detection and alarm circuit according to claim 1, characterized in that: The alarm module (700) includes resistor R14, resistor R15, transistor Q1, resistor R16, indicator light L, resistor R17, resistor R18, transistor Q2, resistor R19 and buzzer BL. Transistors Q1 and Q2 are both PNP type transistors. The first terminals of resistors R14 and R17 are respectively connected to different control pins of processor U6; The second terminal of resistor R14 is connected to the base of transistor Q1, the first terminal of resistor R15 is connected to power supply VCC, the second terminal of resistor R15 is connected to the second terminal of resistor R14, the emitter of transistor Q1 is connected to power supply VCC, the collector of transistor Q1 is connected to the first terminal of resistor R16, the second terminal of resistor R16 is connected to the first terminal of indicator light L, and the second terminal of indicator light L is grounded. The second terminal of resistor R17 is connected to the base of transistor Q2. The first terminal of resistor R18 is connected to power supply VCC. The second terminal of resistor R18 is connected to the second terminal of resistor R17. The emitter of transistor Q2 is connected to power supply VCC. The collector of transistor Q2 is connected to the first terminal of resistor R19. The second terminal of resistor R19 is connected to the first terminal of buzzer BL. The second terminal of buzzer BL is grounded.

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