Wide range AD scanning data acquisition card

Abstract

The utility model discloses a wide range AD scanning data acquisition card belongs to signal acquisition technical field. The utility model acquisition card's front end signal conditioning circuit includes 64 way signal conditioning branch, and signal conditioning branch includes two -way voltage stabilizing diode, voltage division branch, first operational amplifier, RC filter circuit and second operational amplifier. First operational amplifier realizes voltage follow -up and isolates input signal with subsequent circuit, and RC filter circuit filters high -frequency ripple and noise, and second operational amplifier further isolates signal, and two -way voltage stabilizing diode and voltage division branch are in parallel, avoid high -voltage impact and step -down, break through the limitation of traditional acquisition card + 10V. Analog switch selection circuit switches 64 way signals through 8 piece first level multiplexer chip, and realizes difference or single -end mode switching through second level multiplexer chip. Zero -setting circuit is used for eliminating signal's zero point deviation. The accuracy and stability of acquisition card acquisition signal are guaranteed.

Description

Technical Field

[0001] This utility model belongs to the field of signal acquisition technology, specifically relating to a wide-range AD scanning data acquisition card. Background Technology

[0002] Data acquisition cards, with their advanced signal acquisition principles and wide applicability, have become essential data acquisition devices in numerous fields. However, existing data acquisition cards have many limitations in their acquisition range. Most acquisition cards are limited to ±10V, a limitation that makes acquisition extremely complex when dealing with high-voltage signal sources. For example, in some industrial production processes, the signal output by sensors may far exceed ±10V. In such cases, directly using a conventional acquisition card will not only fail to accurately acquire the signal but may also damage the acquisition card.

[0003] In summary, the input range of existing data acquisition cards is relatively narrow. Utility Model Content

[0004] The technical problem to be solved by this utility model is to provide a wide range AD scanning data acquisition card that addresses the shortcomings of the prior art. The card has a simple design structure and practical functions, and achieves wide range, high precision and high sampling rate functions on the board. The board layout is neat and the structure is compact.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows:

[0006] A wide-range AD scanning data acquisition card includes a connector, a front-end signal conditioning circuit, an analog switch selection circuit, a zeroing circuit, an AD converter, an FPGA module, and a memory.

[0007] Connectors are used to acquire analog signals and send them to the front-end signal conditioning circuit;

[0008] The front-end signal conditioning circuit includes 64 signal conditioning branches for processing the input signal and outputting the conditioned signal. Each signal conditioning branch includes a bidirectional Zener diode, a voltage divider branch, a first operational amplifier, an RC filter circuit, and a second operational amplifier. The input signal is connected to the non-inverting input of the first operational amplifier through a series first resistor and a second resistor. The bidirectional Zener diode and the voltage divider branch are connected in parallel between the output of the second resistor and ground. The output of the first operational amplifier is connected to the inverting input of the first operational amplifier. The output of the first operational amplifier is also connected to the input of the RC filter circuit. The output of the RC filter circuit is connected to the non-inverting input of the second operational amplifier. The output of the second operational amplifier outputs the conditioned signal.

[0009] The analog switch selection circuit includes eight first-stage multiplexer chips and one second-stage multiplexer chip. The input of the first-stage multiplexer chip is connected to the output of the front-end signal conditioning circuit, and the outputs of the eight first-stage multiplexer chips converge to a common output. According to the control of the FPGA module, one or more signals are selected for output. The input of the second-stage multiplexer chip is connected to the common output of the eight first-stage multiplexer chips, and the output of the second-stage multiplexer chip selects differential mode or single-ended mode according to the input signal.

[0010] The input terminal of the adder is connected to the output terminal of the analog switch selection circuit, which is used to superimpose the input signal and the gain reference signal to obtain the composite signal.

[0011] The integrated signal is connected to the input terminal of the zero-adjustment circuit to eliminate the zero-point offset of the integrated signal;

[0012] The AD converter is used to convert analog signals into data signals. The zeroed signal is connected to the input terminal of the AD converter, and the output terminal of the AD converter is connected to the input terminal of the FPGA module.

[0013] The memory is used to store the digital signals input to the FPGA module.

[0014] Furthermore, the adder includes a third operational amplifier and a fourth operational amplifier; the input signal is connected to the non-inverting input terminal of the third operational amplifier, and the output terminal of the third operational amplifier is connected to the branch formed by the third resistor and the gain reference signal through the fourth resistor. At the junction, the signals are superimposed through a resistor network, and the combined signal after addition is connected to the non-inverting input terminal of the fourth operational amplifier.

[0015] The zero-adjustment circuit includes a fifth operational amplifier and a sixth operational amplifier. The output of the fourth operational amplifier is connected to the inverting input of the fifth operational amplifier through the fifth resistor. The integrated signal is connected to the inverting input of the sixth operational amplifier through the output of the fifth operational amplifier. The non-inverting input of the sixth operational amplifier is connected to the zero-adjustment signal. The sixth operational amplifier performs differential processing on the amplified integrated signal and the zero-adjustment signal and outputs the zero-adjusted signal.

[0016] Furthermore, the third, fourth, fifth, and sixth operational amplifiers all use the AD8066 operational amplifier.

[0017] Furthermore, the RC filter circuit is used to filter out high-frequency noise in the signal; it includes a sixth resistor, a seventh resistor, an eighth resistor, and a capacitor.

[0018] The sixth and seventh resistors are connected in series between the output of the first operational amplifier and the non-inverting input of the second operational amplifier. One end of the eighth resistor is connected to the output of the sixth resistor, and the other end is grounded, forming a voltage divider. One end of the capacitor is connected to the output of the seventh resistor, and the other end is grounded, forming a low-pass filter.

[0019] Furthermore, the voltage divider branch consists of two voltage divider resistors connected in series.

[0020] Furthermore, both the first and second operational amplifiers use the ADA4622 operational amplifier.

[0021] Furthermore, both the first-stage multiplexer chip and the second-stage multiplexer chip use the ADG759BCPZ chip.

[0022] Furthermore, the AD converter uses the AD4000 analog converter.

[0023] Furthermore, the FPGA module uses the XC7A100T-2FGG676I chip.

[0024] This utility model has the following advantages compared with the prior art:

[0025] The front-end signal conditioning circuit of this utility model includes 64 signal conditioning branches for processing the input signal and outputting the conditioned signal. The signal conditioning branch includes a bidirectional Zener diode, a voltage divider branch, a first operational amplifier, an RC filter circuit, and a second operational amplifier. The output terminal of the first operational amplifier is connected to the inverting input terminal of the first operational amplifier to ensure that the output voltage follows the input voltage change, thus completing voltage following and isolation between the input signal and subsequent circuits. An RC filter circuit removes high-frequency ripple and noise, improving signal purity. A second operational amplifier isolates the input signal from subsequent circuits. A bidirectional Zener diode and a voltage divider branch are connected in parallel between the output of the second resistor and ground. The bidirectional Zener diode prevents the circuit from being subjected to high-voltage surges, while the voltage divider branch reduces the input signal voltage to a range suitable for the data acquisition card, thus overcoming the traditional ±10V acquisition range limitation. A front-end signal conditioning circuit avoids the structural complexity and cumbersome cabling issues associated with adding conditioning circuits in traditional methods. An analog switch selection circuit uses eight first-stage multiplexer chips to switch between 64 signals, and a second-stage multiplexer chip to switch between differential and single-ended modes. A zero-adjustment circuit is used to eliminate signal zero-point offset.

[0026] The technical solution of this utility model will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0027] Figure 1This is a front-end signal conditioning circuit diagram of an embodiment of the wide-range AD scanning data acquisition card of this utility model;

[0028] Figure 2 This is a schematic diagram of the first-stage multiplexer chip in an embodiment of the wide-range AD scanning data acquisition card of this utility model;

[0029] Figure 3 This is a schematic diagram of the second-stage multiplexer chip in an embodiment of the wide-range AD scanning data acquisition card of this utility model;

[0030] Figure 4 This is a circuit diagram of the adder and zero-adjustment circuit of an embodiment of the wide-range AD scanning data acquisition card of this utility model;

[0031] Figure 5 This is a schematic diagram of the structure of an embodiment of the wide-range AD scanning data acquisition card of this utility model. Detailed Implementation

[0032] Example of a wide-range AD scanning data acquisition card:

[0033] like Figure 5 As shown, the wide-range AD scanning data acquisition card includes a connector front-end signal conditioning circuit, an analog switch selection circuit, an adder, a zeroing circuit, an AD converter, an FPGA module, a memory, and a power supply module.

[0034] The FPGA module is connected to the control terminals of the front-end signal conditioning circuit, analog switch selection circuit, zero-adjustment circuit, AD converter, memory, and power supply module. The FPGA module uses the Xilinx Artix-7 series XC7A100T-2FGG676I chip. The FPGA module communicates with each part through a bus system. The memory stores the digital signals input to the FPGA module. A bus buffer circuit is also included to ensure stable signal transmission and compatibility.

[0035] The power supply module is connected to the front-end signal conditioning circuit, analog switch selection circuit, zeroing circuit, AD converter, FPGA module, and memory for power supply. This module includes nine power supplies, with an external 5V power supply and the board converting the other eight power supplies via the power supply module. The 3.3V, 2.5V, and 1.2V power supplies required by the digital circuitry are converted by the LTM4644; the 1.5V power supply required by the digital circuitry is converted from the 5V power supply by the ISL88550A; the AD conversion circuitry requires ±12V, 1.8V, and 5.5V power supplies from the board, which are converted to ±12V by the wide-voltage input power chips MIW3017, ADP7142AUJZ, and ADP7182AUJZ; the +12V power supply is converted to an analog 5.5V power supply by the ADP7142AUJZ; and the 5.5V power supply is converted to an analog 1.8V power supply by the LT1963AEST-1.8.

[0036] The connector is used to acquire analog signals and send them to the front-end signal conditioning circuit; this connector is a J30J-100ZKWP7 connector. This connector is also used for inputting and outputting digital signals to the FPGA module.

[0037] like Figure 1 As shown, the front-end signal conditioning circuit includes 64 signal conditioning branches, used to process the input signal and output the conditioned signal. This acquisition card supports 32-channel differential or 64-channel single-ended analog input. The maximum sampling rate can reach 1Msps for a single channel and 500Ksps for multiple channels.

[0038] The signal conditioning branch includes a bidirectional Zener diode, a voltage divider branch, a first operational amplifier, an RC filter circuit, and a second operational amplifier. Both the first and second operational amplifiers are ADA4622 operational amplifiers. The voltage divider branch consists of two series-connected voltage divider resistors. Figure 1 In this embodiment, the voltage divider resistors are R948 and R950, the first operational amplifier is U26A, the second operational amplifier is U26D, and the bidirectional Zener diode is D82. All resistors involved in this embodiment are surface-mount resistors.

[0039] The input signal is connected to the non-inverting input of the first operational amplifier (op-amp) via a series first and second resistors. A bidirectional Zener diode and a voltage divider branch are connected in parallel between the output of the second resistor and ground. The output of the first op-amp is connected to its inverting input and also to the input of an RC filter circuit. The output of the RC filter circuit is connected to the non-inverting input of the second op-amp. The output of the second op-amp outputs the conditioned signal. Figure 1 Above, the first resistor and the second resistor refer to R947 and R949, respectively.

[0040] An RC filter circuit is used to filter out high-frequency noise in a signal; it includes a sixth resistor, a seventh resistor, an eighth resistor, and a capacitor. The sixth and seventh resistors are connected in series between the output of the first operational amplifier and the non-inverting input of the second operational amplifier. One end of the eighth resistor is connected to the output of the sixth resistor, and the other end is grounded, forming a voltage divider. One end of the capacitor is connected to the output of the seventh resistor, and the other end is grounded, forming a low-pass filter. Figure 1 Above, the sixth, seventh, and eighth resistors and the capacitor are R440, R441, R444, and C222, respectively.

[0041] The analog switch selection circuit includes eight first-stage multiplexer chips and one second-stage multiplexer chip. Both the first-stage and second-stage multiplexer chips use the ADG759BCPZ chip.

[0042] like Figure 2 The input terminal of the first-stage multiplexer chip shown is connected to the output terminal of the front-end signal conditioning circuit. The output terminals of the eight first-stage multiplexer chips converge to a common output terminal, and one or more signals are selected for output according to the control of the FPGA module.

[0043] like Figure 3 As shown, the input terminal of the second-stage multiplexer chip is connected to the common output terminal of eight first-stage multiplexer chips. The output terminal of the second-stage multiplexer chip selects differential mode or single-ended mode according to the input signal.

[0044] like Figure 4 As shown, the input of the adder is connected to the output of the analog switch selection circuit, used to superimpose the input signal and the gain reference signal to obtain the synthesized signal. The synthesized signal is connected to the input of the zero-adjustment circuit to eliminate the zero-point offset of the synthesized signal. The zero-adjustment circuit is a circuit used to adjust the zero point of the circuit's output signal. Its function is to eliminate the DC bias in the circuit, ensuring that the circuit output is zero when there is no input signal.

[0045] The adder includes a third operational amplifier and a fourth operational amplifier. The input signal is connected to the non-inverting input of the third operational amplifier. The output of the third operational amplifier is connected to the branch formed by the third resistor and the gain reference signal through the fourth resistor. The signals are superimposed at the junction through a resistor network. The combined signal after addition is connected to the non-inverting input of the fourth operational amplifier.

[0046] The zero-adjustment circuit includes a fifth operational amplifier and a sixth operational amplifier. The output of the fourth operational amplifier is connected to the inverting input of the fifth operational amplifier through the fifth resistor. The integrated signal is connected to the inverting input of the sixth operational amplifier through the output of the fifth operational amplifier. The non-inverting input of the sixth operational amplifier is connected to the zero-adjustment signal. The sixth operational amplifier performs differential processing on the amplified integrated signal and the zero-adjustment signal and outputs the zero-adjusted signal.

[0047] The third, fourth, fifth, and sixth operational amplifiers all use the AD8066 operational amplifier. This amplifier boosts the input voltage to the range of the ADC chip input; zeroing ensures that the value acquired is 0 when the board input is grounded.

[0048] exist Figure 4 In the circuit, the third, fourth, fifth, and sixth operational amplifiers are U84A, U84B, U85A, and U85B, respectively; the third, fourth, and fifth resistors are R1000, R1001, and R1003, respectively.

[0049] The analog-to-digital converter (ADC) is used to convert analog signals into data signals. The zeroed signal is connected to the input terminal of the ADC, and the output terminal of the ADC is connected to the input terminal of the FPGA module. The ADC uses the AD4000 analog-to-digital converter. This chip has a maximum acquisition rate of 2Msps, which meets the design acquisition rate of 1Msps(max); the chip has an offset error of 4.5LSB(max) and a gain error of 20LSB(max), which meets the error requirements of each range in the design.

[0050] The working principle of this data acquisition card is to realize the digital acquisition and transmission of multi-channel analog signals through the collaboration of multiple modules. When an external signal enters the card, it first undergoes preprocessing such as filtering, amplification, and impedance adjustment by analog circuits. Then, it selects a channel through an analog switch and converts the analog signal into a digital signal through ADC sampling. After one channel is converted, the analog switch can be switched to the next channel for ADC sampling and conversion. The converted data signal is stored in the DDR of the card and can be read, processed, and analyzed by a computer.

[0051] The above description is merely a preferred embodiment of the present utility model and does not constitute any limitation on the present utility model. Any simple modifications, alterations, or equivalent structural changes made to the above embodiments based on the technical essence of the present utility model shall still fall within the protection scope of the present utility model.

Claims

1. A wide-range AD scanning data acquisition card, characterized in that: It includes connectors, front-end signal conditioning circuits, analog switch selection circuits, adders, zero-adjustment circuits, AD converters, FPGA modules, and memory; Connectors are used to acquire analog signals and send them to the front-end signal conditioning circuit; The front-end signal conditioning circuit includes 64 signal conditioning branches for processing the input signal and outputting the conditioned signal. Each signal conditioning branch includes a bidirectional Zener diode, a voltage divider branch, a first operational amplifier, an RC filter circuit, and a second operational amplifier. The input signal is connected to the non-inverting input of the first operational amplifier through a series first resistor and a second resistor. The bidirectional Zener diode and the voltage divider branch are connected in parallel between the output of the second resistor and ground. The output of the first operational amplifier is connected to the inverting input of the first operational amplifier. The output of the first operational amplifier is also connected to the input of the RC filter circuit. The output of the RC filter circuit is connected to the non-inverting input of the second operational amplifier. The output of the second operational amplifier outputs the conditioned signal. The analog switch selection circuit includes eight first-stage multiplexer chips and one second-stage multiplexer chip. The input of the first-stage multiplexer chip is connected to the output of the front-end signal conditioning circuit, and the outputs of the eight first-stage multiplexer chips converge to a common output. According to the control of the FPGA module, one or more signals are selected for output. The input of the second-stage multiplexer chip is connected to the common output of the eight first-stage multiplexer chips, and the output of the second-stage multiplexer chip selects differential mode or single-ended mode according to the input signal. The input terminal of the adder is connected to the output terminal of the analog switch selection circuit, which is used to superimpose the input signal and the gain reference signal to obtain the composite signal. The integrated signal is connected to the input terminal of the zero-adjustment circuit to eliminate the zero-point offset of the integrated signal; The AD converter is used to convert analog signals into data signals. The zeroed signal is connected to the input terminal of the AD converter, and the output terminal of the AD converter is connected to the input terminal of the FPGA module. The memory is used to store the digital signals input to the FPGA module.

2. A wide-range AD scanning data acquisition card according to claim 1, characterized in that: The adder includes a third operational amplifier and a fourth operational amplifier; the input signal is connected to the non-inverting input of the third operational amplifier, and the output of the third operational amplifier is connected to the branch formed by the third resistor and the gain reference signal through the fourth resistor. The signals are superimposed at the junction through a resistor network, and the combined signal after addition is connected to the non-inverting input of the fourth operational amplifier. The zero-adjustment circuit includes a fifth operational amplifier and a sixth operational amplifier. The output of the fourth operational amplifier is connected to the inverting input of the fifth operational amplifier through the fifth resistor. The integrated signal is connected to the inverting input of the sixth operational amplifier through the output of the fifth operational amplifier. The non-inverting input of the sixth operational amplifier is connected to the zero-adjustment signal. The sixth operational amplifier performs differential processing on the amplified integrated signal and the zero-adjustment signal and outputs the zero-adjusted signal.

3. A wide-range AD scanning data acquisition card according to claim 1, characterized in that: The third, fourth, fifth, and sixth op-amps all use the AD8066 operational amplifier.

4. A wide-range AD scanning data acquisition card according to claim 1, characterized in that: The RC filter circuit is used to filter out high-frequency noise in the signal; it includes a sixth resistor, a seventh resistor, an eighth resistor, and a capacitor. The sixth and seventh resistors are connected in series between the output of the first operational amplifier and the non-inverting input of the second operational amplifier. One end of the eighth resistor is connected to the output of the sixth resistor, and the other end is grounded, forming a voltage divider. One end of the capacitor is connected to the output of the seventh resistor, and the other end is grounded, forming a low-pass filter.

5. A wide-range AD scanning data acquisition card according to claim 1, characterized in that: The voltage divider branch consists of two voltage divider resistors connected in series.

6. A wide-range AD scanning data acquisition card according to claim 1, characterized in that: Both the first and second op-amps use the ADA4622 operational amplifier.

7. A wide-range AD scanning data acquisition card according to claim 1, characterized in that: Both the first-stage multiplexer chip and the second-stage multiplexer chip use the ADG759BCPZ chip.

8. A wide-range AD scanning data acquisition card according to claim 1, characterized in that: The AD converter is an AD4000 analog converter.

9. A wide-range AD scanning data acquisition card according to claim 1, characterized in that: The FPGA module uses the XC7A100T-2FGG676I chip.

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