Electronic device and amplifier device

Abstract

An electronic device and an amplifier device, the electronic device including an amplifier having an input and an output. The amplifier includes a gain stage, and an output impedance matching circuit coupled to the gain stage and the output. The output impedance matching circuit includes a plurality of metal-oxide-metal (MOM) capacitors in parallel with one another.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to an electronic device and amplifier device utilizing metal-oxide-metal (MOM) capacitors, as well as a method for manufacturing the amplifier. Background Technology

[0002] Generally, amplifiers amplify both the power and noise of the input signal and introduce additional noise into the output signal. A low-noise amplifier (LNA) is a circuit designed to amplify an input signal (e.g., a very low-power input signal) without attenuating the signal-to-noise ratio (SNA) of the input / output signal. Through the selection of specific components, operating points, and circuit layout, LNAs are designed to minimize additional noise, while balancing other design considerations such as power gain and impedance matching.

[0003] LNAs can be used in radio frequency (RF) communication systems, medical instruments, and electronic test equipment. While LNAs primarily focus on weak signals slightly above the noise floor, they must also account for the presence of larger signals. Furthermore, the high cost of wafers for advanced complementary metal-oxide-semiconductor (CMOS) technology necessitates improvements in power, performance, and area (PPA) to make costs more reasonable. Utility Model Content

[0004] The purpose of this invention is to provide an electronic device and an amplifier device to solve at least one of the above-mentioned problems.

[0005] According to some embodiments, an electronic device includes an amplifier having an input terminal and an output terminal. The amplifier includes a gain stage and an output impedance matching network connected to the gain stage and the output terminal. The output impedance matching network includes a plurality of MOM capacitors connected in parallel with each other.

[0006] According to one embodiment of the present invention, the output impedance matching network includes a capacitor having a first terminal connected to the gain stage and a second terminal connected to the output terminal, and the capacitor includes a plurality of metal-oxide-metal capacitors connected in parallel with each other.

[0007] According to one embodiment of the present invention, it further includes a gain stage output path and an output path, wherein the gain stage output path is connected to one side of the gain stage and each of the plurality of metal-oxide-metal capacitors, and the output path is connected to the other side of each of the plurality of metal-oxide-metal capacitors and the output terminal, wherein the plurality of metal-oxide-metal capacitors connected in parallel with each other include one or more lower metal layers, and the lower metal layers are lower than the gain stage output path and the output path.

[0008] According to one embodiment of the present invention, it further includes a gain stage output path and an output path, wherein the gain stage output path is connected to one side of each of the gain stage and each of the plurality of metal-oxide-metal capacitors, and the output path is connected to the other side of each of the plurality of metal-oxide-metal capacitors and the output terminal, wherein the gain stage output path and the output path include one or more higher metal layers, and the higher metal layers are higher than the plurality of metal-oxide-metal capacitors, wherein the gain stage output path and the output path include a plurality of metal lines, and at least a portion of the gain stage output path is disposed on at least a portion of each of the plurality of metal-oxide-metal capacitors, and at least a portion of the output path is disposed on at least a portion of each of the plurality of metal-oxide-metal capacitors.

[0009] According to one embodiment of the present invention, the output impedance matching network includes an inductor having a first terminal connected to a power supply terminal and a second terminal connected to the gain stage and the capacitor.

[0010] According to one embodiment of the present invention, the output impedance matching network includes a capacitor having a first end connected to the output terminal and a second end connected to a reference terminal, and the capacitor includes a plurality of metal-oxide-semiconductor (MODS) capacitors connected in parallel with each other; or the gain stage includes at least two metal-oxide-semiconductor (MODS) field-effect transistors, and the at least two MODS field-effect transistors have a plurality of drain / source paths connected in series.

[0011] According to one embodiment of the present invention, it further includes: an input impedance matching network having a first terminal connected to the input terminal and a second terminal connected to the gain stage; or a source decay circuit having a first terminal connected to the gain stage and a second terminal connected to a reference terminal.

[0012] According to one embodiment of the present invention, it includes: an input terminal and an output terminal; an input impedance matching network connected to the input terminal; a gain stage connected to the input impedance matching network; and an output impedance matching network connected to the gain stage and the output terminal, wherein the output impedance matching network includes a first capacitor having a first terminal connected to the gain stage and a second terminal connected to the output terminal, and the first capacitor includes a plurality of first metal-oxide-metal capacitors connected in parallel with each other.

[0013] According to further embodiments, an amplifier device includes an input terminal, an output terminal, an input impedance matching network connected to the input terminal, a gain stage connected to the input impedance matching network, and an output impedance matching network connected to the gain stage and the output terminal. The output impedance matching network includes a first capacitor having a first terminal connected to the gain stage and a second terminal connected to the output terminal, and the first capacitor includes a plurality of first MOM capacitors connected in parallel with each other.

[0014] According to one embodiment of the present invention, it further includes a gain stage output path and an output path, wherein the gain stage output path is connected to one side of each of the gain stage and each of the plurality of first metal-oxide-metal capacitors, and the output path is connected to the other side of each of the plurality of first metal-oxide-metal capacitors and the output terminal, wherein the plurality of first metal-oxide-metal capacitors connected in parallel with each other include one or more lower metal layers, and the lower metal layers are lower than the gain stage output path and the output path, and wherein the gain stage output path and the output path include one or more higher metal layers, and the higher metal layers are higher than the plurality of metal-oxide-metal capacitors.

[0015] According to one embodiment of the present invention, the output impedance matching network includes a second capacitor having a first terminal connected to the output terminal and a second terminal connected to a reference terminal, and the second capacitor includes a plurality of second metal-oxide-metal capacitors connected in parallel with each other; wherein the output impedance matching network includes an inductor having a first terminal connected to a power supply terminal and a second terminal connected to the gain stage and the first capacitor; or wherein the input impedance matching network includes an inductor having a first terminal connected to the input terminal and a second terminal connected to the gain stage. Attached Figure Description

[0016] The complete disclosure is based on the following detailed description and the accompanying drawings. It should be noted that, in accordance with the general practice of the industry, the illustrations are not necessarily drawn to scale. In fact, the dimensions of components may be arbitrarily enlarged or reduced for clarity.

[0017] Figure 1 This is a block diagram of a low noise amplifier (LNA) device described according to some embodiments.

[0018] Figure 2 This is a circuit diagram of an LNA device described according to some embodiments.

[0019] Figure 3 The present invention is a schematic diagram of a semiconductor device described according to some embodiments, the semiconductor device including a second capacitor C2 and a third capacitor C3, wherein the second capacitor C2 is connected to a gain stage through a gain stage output path, and the third capacitor C3 is connected to an output terminal through an output path.

[0020] Figure 4 This is a schematic diagram of a semiconductor device described according to some embodiments, having multiple metal layers, multiple vias, an active region layer, a polysilicon layer, and a via extending from the polysilicon layer to the metal layer 0.

[0021] Figure 5 For the semiconductor device described according to some embodiments along Figure 3 A schematic diagram of the cross section of the tangent A-A.

[0022] Figure 6 This is a graph of the Q factor versus frequency of a first capacitor and a second capacitor as described in some embodiments, wherein the first capacitor is formed by a large MOM capacitor, and the second capacitor is formed by a plurality of smaller MOM capacitors connected in parallel with each other.

[0023] Figure 7 A route reuse technique in a semiconductor device described according to some embodiments is used for a second capacitor C2 formed by multiple MOM capacitors.

[0024] Figure 8 For the semiconductor device described according to some embodiments along Figure 7 A schematic diagram of the cross section of the tangent line B-B.

[0025] Figure 9 The diagram illustrates multiple experimental results of an LNA described according to some embodiments, wherein the LNA includes a second capacitor C2 formed by the original large MOM capacitor and a third capacitor C3 formed by smaller MOM capacitors connected in parallel with each other, wherein the smaller MOM capacitors connected in parallel with each other provide an enhanced MOM Q factor.

[0026] Figure 10 This is a flowchart of a method for manufacturing an amplifier according to some embodiments.

[0027] Figure 11 This is a flowchart of another method for manufacturing an amplifier according to some embodiments.

[0028] Figure 12 This is a block diagram of an example of a computer system described according to some embodiments, configured to provide electronic devices, semiconductor devices, and methods of the present invention.

[0029] Figure 13 This is a block diagram of a semiconductor device manufacturing system and a related semiconductor device process described according to some embodiments.

[0030] 20,40: Low-noise amplifiers

[0031] 22,42: Input terminals

[0032] 24, 44: Output terminals

[0033] 26,46: Input impedance matching network

[0034] 28, 48: Gain Stage

[0035] 30, 50: Output impedance matching network

[0036] 32, 34: Communication paths

[0037] 52: First Inductor

[0038] 54: First capacitor

[0039] 56: Second Inductor

[0040] 58,76: Reference End

[0041] 60: First MOSFET

[0042] 62: Second MOSFET

[0043] 64: Third Inductor

[0044] 66: Second capacitor

[0045] 68: Third capacitor

[0046] 70: Power supply end

[0047] 72,114: Gain stage output path

[0048] 74,116: Output path

[0049] 80,110: Semiconductor devices

[0050] 82a~82h, 84a~84h, 112a~112e: MOM capacitors

[0051] 86a~86k: Metallic layer

[0052] 88a~88j,94: Through holes

[0053] 90: Active Layer

[0054] 92: Polycrystalline silicon layer

[0055] 100: Chart

[0056] 102L, 104L: Curve

[0057] 106: x-axis

[0058] 108: y-axis

[0059] 120: Experimental Results

[0060] 122, 124, 126: lines

[0061] 128, 130, 132, 134: Columns

[0062] 140, 142, 144, 150, 152, 154, 156: Operations

[0063] 200: Computer System

[0064] 202: Processor

[0065] 204: Computer-readable storage media

[0066] 206: Instruction

[0067] 208: Technique Tools

[0068] 210: Busbar

[0069] 212: Input / Output (I / O) Interface

[0070] 214: Web Interface

[0071] 216: Network

[0072] 218: Database

[0073] 220: User Interface (UI)

[0074] 222: Semiconductor Device Manufacturing System

[0075] 224: Design Company

[0076] 226: Photomask Company

[0077] 228: Semiconductor device manufacturer

[0078] 230: Semiconductor Device Design Layout Diagram

[0079] 232: Data Preparation Procedure

[0080] 234: Photomask Manufacturing Process

[0081] 236: Photomask

[0082] 238: Semiconductor wafers

[0083] 240: Wafer Process

[0084] 242: Semiconductor structure or semiconductor device

[0085] V b Bias voltage

[0086] A─A, B─B: Tangents

[0087] W1, W2, W3: Width Detailed Implementation

[0088] The following disclosure provides numerous different embodiments or examples to implement the various features of this application. The following disclosure describes specific examples of the various components and their arrangements for simplification. Of course, these specific examples are not intended to be limiting. For example, if this disclosure describes a first feature formed on or above a second feature, it indicates that it may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the same reference numerals and / or designations may be repeated in different examples of the following disclosure. These repetitions are for simplification and clarity and are not intended to limit any specific relationship between the different embodiments and / or structures discussed.

[0089] Furthermore, spatially related terms, such as "below," "below," "lower," "above," "higher," and similar terms, are used to facilitate the description of the relationship between one element or feature and another(s) in the illustration. In addition to the orientations shown in the accompanying drawings, these spatially related terms are intended to encompass different orientations of the device in use or operation. The device may be rotated to different orientations (90 degrees or other orientations), and the spatially related terms used herein can be interpreted in the same way.

[0090] Some low-noise amplifiers (LNAs) include metal-oxide-metal (MOM) capacitors for impedance matching, alternating current (AC) coupling, and / or bypass capacitors. Impedance matching networks can include inductors and MOM capacitors, such as conductive finger MOM (CFMOM) capacitors and conductive spiral MOM (CRTMOM) capacitors. MOM capacitors are implemented in lower metal layers within the semiconductor device, and the thickness of these lower metal layers is reduced due to lithography limitations at advanced complementary metal-oxide-semiconductor (CMOS) technology nodes. This reduction in lower metal layer thickness leads to a decrease in the Q-factor of MOM capacitors in advanced CMOS nodes, which in turn affects the gain and noise factor of the LNA.

[0091] Furthermore, some LNAs operate at frequencies exceeding billions of hertz (GHz) using large capacitors (e.g., 1 pF capacitor operating at 2.4 GHz). To provide these large capacitors, longer metal is used to form the MOM capacitor, resulting in greater parasitic resistance and a reduced Q factor of the MOM capacitor (especially in advanced CMOS nodes, such as the 6 nanometer (nm) node). A reduced Q factor of the MOM capacitor further affects the LNA's gain and noise factor.

[0092] The disclosed embodiments provide an LNA including MOM capacitors, wherein the MOM capacitors have an enhanced Q factor to improve the LNA's gain and noise. In some embodiments, at least one larger capacitor is formed by connecting multiple smaller MOM capacitors in parallel to achieve a larger capacitance value. This reduces the parasitic resistance of the capacitor and increases the Q factor of at least one capacitor. This is particularly advantageous for advanced CMOS nodes and can contribute to an enhanced Q factor and better gain and noise factor in the LNA.

[0093] The disclosed embodiments also include a route reuse technique, wherein the aforementioned plurality of smaller MOM capacitors connected in parallel are configured under a signal path, such as a signal path from the gain stage of the LNA to the output of the LNA. This can mitigate power loss in the connection lines of the signal path and improve the LNA's performance in terms of gain and noise factor.

[0094] The benefits of enhanced MOM Q factors in these LNAs (such as radio frequency (RF) LNAs) include enhanced gain and noise at advanced nodes (such as 6nm CMOS nodes), resulting in better performance and justifying the increased cost.

[0095] Figure 1 This is a schematic diagram of an LNA (or LNA device) 20 described according to some embodiments. The LNA 20 has an input terminal 22 and an output terminal 24, and includes an input impedance matching network 26, a gain stage 28, and an output impedance matching network 30. The input terminal 22 is electrically connected to the input impedance matching network 26, which is electrically connected to the gain stage 28 via a communication path 32. The gain stage 28 is electrically connected to the output impedance matching circuit 30 via a communication path 34, and the output terminal 24 is electrically connected to the output impedance matching circuit 30.

[0096] Input terminal 22 receives an input signal, such as an RF input signal, and transmits it to input impedance matching network 26, where impedance matching exists between input impedance matching network 26 and the signal path transmitting the input signal. Gain stage 28 amplifies the received input signal and provides the amplified signal to output impedance matching network 30, which in turn provides an amplified output signal (e.g., an amplified RF output signal) to output terminal 24. Impedance matching exists between output impedance matching network 30 and the signal path transmitting the amplified output signal.

[0097] In some embodiments, the output impedance matching network 30 includes at least one capacitor comprising a plurality of MOM capacitors connected in parallel to provide a large capacitance value in the output impedance matching network 30. In some embodiments, the output impedance matching network 30 includes a capacitor comprising a plurality of MOM capacitors connected in parallel to provide the aforementioned capacitance with a large capacitance value, wherein the smaller MOM capacitors have shorter metal lengths and lower parasitic resistances, thus enhancing the Q factor of the larger capacitance.

[0098] In some embodiments, the output impedance matching network 30 includes a capacitor comprising a plurality of MOM capacitors connected in parallel, wherein the capacitor has a first terminal connected to the gain stage 28 and a second terminal connected to the output stage 24. In some embodiments, the output impedance matching network 30 includes a capacitor comprising a plurality of MOM capacitors connected in parallel, wherein the capacitor has a first terminal connected to the output stage 24 and a second terminal connected to a reference terminal (e.g., ground). In some embodiments, the output impedance matching network 30 includes a capacitor comprising a plurality of MOM capacitors connected in parallel, wherein all or at least a portion of the capacitor is configured under one or more signal paths configured between the gain stage 28 and the output stage 24. In some embodiments, the output impedance matching network 30 includes a capacitor comprising a plurality of MOM capacitors connected in parallel, wherein the capacitor has a first terminal connected to the gain stage 28 and a second terminal connected to the output stage 24, and all or at least a portion of the capacitor is configured under one or more signal paths configured between the gain stage 28 and the output stage 24.

[0099] Figure 2 This is a schematic diagram of an LNA (or LNA device) 40 described according to some embodiments. The LNA 40 includes an input (IN) 42, an output (OUT) 44, an input impedance matching network 46, a gain stage 48, and an output impedance matching network 50. The LNA 40 is... Figure 1 An example of an LNA 20. Input (IN) 42 is similar to input 22, and output (OUT) 44 is similar to output 24. Furthermore, input impedance matching network 46 is similar to input impedance matching network 26, gain stage 48 is similar to gain stage 28, and output impedance matching network 50 is similar to output impedance matching network 30.

[0100] Input terminal (IN) 42 is electrically connected to input impedance matching network 46, which in turn is electrically connected to gain stage 48, and gain stage 48 is electrically connected to output impedance matching network 50. Output terminal (OUT) 44 is electrically connected to output impedance matching network 50.

[0101] Input terminal (IN) 42 receives an input signal (e.g., an RF input signal) and transmits it to input impedance matching network 46, where impedance matching exists between input impedance matching network 46 and the signal path transmitting the input signal. Input impedance matching network 46 provides a matching network signal to gain stage 48.

[0102] The input impedance matching network 46 includes a first inductor (L1) 52 and a first capacitor (C1) 54, and a second inductor (L2) 56, also referred to as a source decay circuit. The input terminal (IN) 42 is electrically connected to one end of the first inductor (L1) 52, and the other end of the first inductor (L1) 52 is electrically connected to one end of the first capacitor (C1) 54 and the gain stage 48. The other end of the first capacitor (C1) 54 is electrically connected to one end of the second inductor (L2) 56 and the gain stage 48. The other end of the second inductor (L2) 56 is electrically connected to a reference terminal 58 (e.g., ground).

[0103] Gain stage 48 receives and amplifies the signal from the matching network and provides the amplified signal to output impedance matching network 50. Gain stage 48 includes at least two metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein the MOSFETs have series drain / source paths. Gain stage 48 includes a first MOSFET (M1) 60 and a second MOSFET (M2) 62. The second MOSFET (M2) 62 includes a drain / source terminal electrically connected to the output impedance matching network 50, and also includes another drain / source terminal electrically connected to a drain / source terminal of the first MOSFET (M1) 60. The other drain / source terminal of the first MOSFET (M1) 60 is electrically connected to the other end of the first capacitor (C1) 54 and one end of the second inductor (L2) 56. The gate of the first MOSFET (M1) 60 is electrically connected to the other end of the first inductor (L1) 52 and one end of the first capacitor (C1) 54. The gate of the second MOSFET (M2) 62 is electrically connected to a bias voltage V. b .

[0104] The output impedance matching network 50 and the gain stage 48 receive the amplified signal and provide an amplified output signal (e.g., an amplified RF output signal) to the output terminal 44. The output impedance matching network 50 and the signal path that transmits the amplified output signal are impedance matched.

[0105] The output impedance matching network 50 includes a third inductor (L3) 64, a second capacitor (C2) 66, and a third capacitor (C3) 68. The third inductor (L... 3- One end of 64 is electrically connected to a power supply terminal (V). DD )70, Third Inductor (L 3-The other end of MOSFET 64 is electrically connected via a gain stage output path 72 to one drain / source terminal of the second MOSFET (M2) 62 and one end of the second capacitor (C2) 66. The other end of the second capacitor (C2) 66 is electrically connected via an output path 74 to one end of the third capacitor (C3) 68 and the output terminal 44. The other end of the third capacitor (C3) 68 is electrically connected to a reference terminal 76 (e.g., ground). The output terminal 44 is configured to provide an amplified output signal.

[0106] In some embodiments, the second capacitor (C2) 66 includes a plurality of MOM capacitors connected in parallel to provide a larger capacitance value for the second capacitor (C2) 66 in the output impedance matching network 50. In some embodiments, the third capacitor (C3) 68 includes a plurality of MOM capacitors connected in parallel to provide a larger capacitance value for the third capacitor (C3) 68 in the output impedance matching network 50. In some embodiments, at least one of the second capacitor (C2) 66 and the third capacitor (C3) 68 includes a plurality of MOM capacitors connected in parallel to each other, and all or at least a portion of at least one of the second capacitor (C2) 66 and the third capacitor (C3) 68 is configured under one or more signal paths, wherein the signal paths are located between the gain stage 48 and the output terminal 44.

[0107] Figure 3 This is a schematic diagram of a semiconductor device 80 described according to some embodiments, wherein the semiconductor device 80 includes a second capacitor (C2) 66 connected to a gain stage 48 via a gain stage output path 72 and a third capacitor (C3) 68 connected to the second capacitor (C2) 66 and an output terminal 44 via an output path 74. Furthermore, the third capacitor (C3) 68 is connected to a reference terminal 76. The semiconductor device 80 includes a plurality of MOM capacitors connected in parallel to each other to provide a large capacitance value for the second capacitor (C2) 66 and the third capacitor (C3) 68.

[0108] The second capacitor (C2) 66 comprises eight MOM capacitors 82a to 82h connected in parallel with each other. Each of the eight MOM capacitors 82a to 82h can be of any suitable shape, such as a square, a rectangle, or finger-shaped. The resulting second capacitor (C2) 66 has a capacitance value equivalent to the sum of the capacitance values ​​of the eight MOM capacitors 82a to 82h. This avoids the use of a single large MOM capacitor with a long metal strip, and the Q factor of the second capacitor (C2) 66 is enhanced compared to a single large MOM capacitor because each of the eight smaller MOM capacitors has a shorter metal length and lower parasitic resistance.

[0109] Furthermore, the third capacitor (C3) 68 comprises eight MOM capacitors 84a to 84h connected in parallel with each other. Each of the eight MOM capacitors 84a to 84h can be of any suitable shape, such as a square, a rectangle, or finger-shaped. The resulting third capacitor (C3) 68 has a capacitance value equivalent to the sum of the capacitance values ​​of the eight MOM capacitors 84a to 84h. This avoids the use of a single large MOM capacitor with a long metal strip, and the Q factor of the third capacitor (C3) 68 is enhanced compared to a single large MOM capacitor because each of the eight smaller MOM capacitors has a shorter metal length and lower parasitic resistance.

[0110] The gain stage output path 72 includes multiple metal lines connecting from the gain stage 48 to one end of each of the eight MOM capacitors 82a to 82h of the second capacitor (C2) 66. The output path 74 includes multiple metal lines connecting the other end of each of the eight MOM capacitors 82a to 82h of the second capacitor (C2) 66 to one end of the output terminal 44 and one end of each of the eight MOM capacitors 84a to 84h of the third capacitor (C3) 68. Furthermore, the other end of each of the eight MOM capacitors 84a to 84h of the third capacitor (C3) 68 is connected to the reference terminal 76.

[0111] In some embodiments, the semiconductor device 80 includes a plurality of metal layers, such as metal layers 0 to 9. In some embodiments, each of the eight MOM capacitors 82a to 82h of the second capacitor (C2) 66 is formed by one or more of metal layers 1 to 7. In some embodiments, each of the eight MOM capacitors 84a to 84h of the third capacitor (C3) 68 is formed by one or more of metal layers 1 to 7. In some embodiments, a plurality of metal lines of the gain stage output path 72 are formed by one or more of metal layers 8 and 9. In some embodiments, a plurality of metal lines of the output path 74 are formed by one or more of metal layers 8 and 9. In some embodiments, one or more of metal layers 8 and 9 are used to connect to the reference terminal 76.

[0112] Figure 4 The semiconductor device 80 comprises multiple metal layers 86a to 86k, vias 88a to 88j, an active region layer 90, a polysilicon layer 92, and a via 94, as described in some embodiments. The via 94 extends from the polysilicon layer 92 to the metal layer 86a (or metal layer 94) in the semiconductor device 80. The active region layer 90 of the semiconductor device 80 includes multiple elements (e.g., transistors). The polysilicon layer 92 is disposed over the active region layer 90, and the via 94 extends from the polysilicon layer 92 to the metal layer 86a. The metal layers 86a to 86k are connected by vias 88a to 88j.

[0113] Each of metal layers 86b to 86h (or metal layers 1 to 7) has a width W1, wherein the width W1 is smaller than a width W2 of metal layer 8, and the width W2 is smaller than a width W3 of metal layer 9. Each of the eight MOM capacitors 82a to 82h of the second capacitor (C2) 66 is formed by one or more of metal layers 86b to 86h. Furthermore, each of the eight MOM capacitors 84a to 84h of the third capacitor (C3) 68 is formed by one or more of metal layers 86b to 86h. Additionally, each of the metal lines in the gain stage output path 72, each of the metal lines in the output path 74, and each of the connection paths of the reference terminal 76 is formed by one or more of metal layers 86i and 86j (or metal layers 8 and 9).

[0114] Figure 5 For the semiconductor device 80 described according to some embodiments along Figure 3 A schematic diagram of a cross-section along tangent A-A. The metal lines in the gain stage output path 72, the metal lines in the output path 74, and the connection path of the reference terminal 76 are formed by one or more of metal layers 86i and 86j. Furthermore, the MOM capacitance 82d of the second capacitor (C2) 66 is formed by one or more of metal layers 86b to 86h, while the MOM capacitance 84d of the third capacitor (C3) 68 is formed by one or more of metal layers 86b to 86h.

[0115] Figure 6 The diagram below is a schematic representation of a graph 100 as described in some embodiments, wherein graph 100 shows the Q factor versus frequency curves, including a curve 102L of a first capacitor 102 formed by a single large MOM capacitor and a curve 104L of a second capacitor 104 formed by multiple smaller MOM capacitors connected in parallel. The frequency is plotted in GHz on the x-axis 106, while the Q factor is plotted on the y-axis 108.

[0116] When the frequency range is 1 GHz to 5 GHz, the second capacitor 104 has a higher Q factor than the first capacitor 102. When the frequency range is 1 GHz to 5 GHz, the Q factor of the first capacitor 102 ranges from about 35 to less than 10, while the Q factor of the second capacitor 104 ranges from about 140 to 30.

[0117] Figure 7This is a schematic diagram of a routing reuse technique in a semiconductor device 110 according to some embodiments, wherein the routing reuse technique is used in a second capacitor (C2) 66 in the semiconductor device 110, wherein the second capacitor (C2) 66 is formed by multiple MOM capacitors 112a to 112e connected in parallel with each other. The MOM capacitors 112a to 112e connected in parallel with each other provide an enhanced Q factor. Through the smaller MOM capacitors 112a to 112e, the second capacitor (C2) 66 is configured such that at least a portion of it lies below a gain stage output path 114, wherein the gain stage output path 114 is connected by a gain stage 48 to one end of each of the MOM capacitors 112a to 112e, and the second capacitor (C2) 66 is configured such that at least a portion of it lies below an output path 116, wherein the output path 116 is connected by the other end of each of the MOM capacitors 112a to 112e to an output terminal 44. This avoids the additional losses in the connection lines of MOM capacitors 112a to 112e, as well as the additional losses in the connection lines extending from the self-gain stage 48 and output terminal 44 through the gain stage output paths 114 and 116. Furthermore, the gain stage output paths 114 and 116 are formed by multiple metal lines. Based on the above routing reuse technique, the additional losses in the connection lines of MOM capacitors 112a to 112e, as well as the additional losses in the connection lines extending from the self-gain stage 48 and output terminal 44 through the gain stage output paths 114 and 116 are mitigated, thus improving the performance of the LNA 40 in advanced CMOS nodes.

[0118] Figure 8 For the semiconductor device 110 described according to some embodiments along Figure 7 A schematic diagram of the cross-section of all lines B-B in the diagram. Multiple metal lines in the gain stage output paths 114 and 116 are formed by one or more of metal layers 86i and 86j. The MOM capacitor 112c of the second capacitor (C2) 66 is formed by one or more of metal layers 86b to 86h.

[0119] Figure 9 The following are some experimental results 120 of the LNA 40 described according to some embodiments, including experimental results of the second capacitor (C2) 66 and the third capacitor (C3) 68 formed by the original large MOM capacitor (as shown in line 122), and experimental results of the Q factor provided by the smaller MOM capacitors connected in parallel to provide MOM capacitor enhancement (as shown in line 124).

[0120] As shown in line 126, experimental result 120 corresponds to an LNA40 operating at 2.4 GHz in an advanced node N6 (e.g., a 6nm node). Experimental result 120 includes the power supply (V... DD)70 voltage (in volts (V), as shown in column 128), direct current (dc) power P dc (in milliwatts (mW), as shown in column 130), gain (in decibels (dB), as shown in column 132), and noise figure (NF) (in decibels (dB), as shown in column 134). In the LNA 40, the power supply terminal of the original MOM large capacitor (V DD The voltage of 70 is 0.75V, and the DC power P dc The value is 3.2mW (as shown in line 122), while the smaller MOM capacitors connected in parallel to each other provide an enhanced MOM Q factor, as shown in line 124.

[0121] The gain increased from 16.96 dB for the LNA 40 with the original large MOM capacitance (as shown in line 122) to 18.51 dB for the LNA 40 with the smaller MOM capacitance (as shown in line 124). Furthermore, the noise figure decreased from 1.65 dB for the LNA 40 with the original large MOM capacitance (as shown in line 122) to 1.58 dB for the LNA 40 with the smaller MOM capacitance (as shown in line 124). Based on these results, the gain and noise figure of the LNA 40 operating at 2.4 GHz in node N6 (N6 2.4 GHz LNA 40) can be improved by 43.0% and 2.0%, respectively.

[0122] Figure 10 This is a flowchart of a method for manufacturing an amplifier according to some embodiments. The amplifier may be an LNA with an enhanced MOM Q factor, including at least one MOM capacitor with an enhanced Q factor, thereby improving the gain and noise of the LNA. In some embodiments, at least one larger capacitor is formed by a plurality of smaller MOM capacitors connected in parallel to achieve the capacitance value of the at least one larger capacitor. This reduces the parasitic resistance of the capacitor and increases the Q factor of the capacitor. In some embodiments, the amplifier is similar to... Figure 1 LNA 20 in the example. In some embodiments, the amplifier described above is similar to... Figure 2 LNA 40 in the middle.

[0123] In operation 140, the method includes forming a gain stage of an amplifier, while in operation 142, the method includes forming an output impedance matching network, wherein the output impedance matching network is connected to the gain stage and an output terminal of the amplifier. In some embodiments, the gain stage is similar to Figure 2 Gain stage 48 in the above. In some embodiments, the output impedance matching network described above is similar to... Figure 2The output impedance matching network 50 is described above. In some embodiments, the output terminal is similar to... Figure 2 Output terminal 44.

[0124] In one operation 144, forming the output impedance matching network includes forming a plurality of MOM capacitors connected in parallel with each other. This can provide a larger capacitance value in the output impedance matching network. In some embodiments, the method includes forming an input impedance matching network, wherein the input impedance matching network is connected to an input terminal of the gain stage and the amplifier.

[0125] In some embodiments, forming a plurality of MOM capacitors includes forming MOM capacitors connected in parallel below a signal path, wherein the signal path extends from the gain stage to the output. In some embodiments, the method includes forming a first capacitor having a first terminal connected to the gain stage and a second terminal connected to the output, wherein forming the first capacitor includes forming a plurality of first MOM capacitors connected in parallel. In some embodiments, the method includes forming a second capacitor having a first terminal connected to the output and a second terminal connected to a reference terminal, wherein forming the second capacitor includes forming a plurality of second MOM capacitors connected in parallel. In some embodiments, forming the output impedance matching network includes providing an inductor having a first terminal connected to a power supply and a second terminal connected to the gain stage.

[0126] Figure 11 This is a flowchart of another method of manufacturing an amplifier according to some embodiments. The amplifier described above may be an LNA with an enhanced MOM Q factor, including at least one MOM capacitor with an enhanced Q factor, thereby improving the gain and noise of the LNA. In some embodiments, at least one larger capacitor is formed by a plurality of smaller MOM capacitors connected in parallel to achieve the capacitance value of the at least one larger capacitor. This reduces the parasitic resistance of the capacitor and increases the Q factor of the capacitor. In some embodiments, the amplifier described above is similar to... Figure 1 LNA 20 in the example. In some embodiments, the amplifier described above is similar to... Figure 2 LNA 40 in the middle.

[0127] In one operation 150, the method includes forming a plurality of transistors in an active region layer to form a gain stage of an amplifier. In some embodiments, the active region layer is similar to Figure 4 The active layer 90.

[0128] In one operation 152, the method includes forming a plurality of first MOM capacitors in one or more lower metal layers to form a first capacitor in an impedance matching network, wherein the lower metal layers have a small width. In some embodiments, the lower metal layers are similar to Figure 4 Metal layers 86b to 86h are present in the middle.

[0129] In one operation 154, the method includes forming a plurality of first electrical connection paths in one or more higher metal layers and connecting them to one side of the gain stage and the first MOM capacitor, wherein the higher metal layers have a large width. In some embodiments, the higher metal layers are similar to Figure 4 Metal layers 8 and 9 are present. In some embodiments, forming the first electrical connection path includes forming the first electrical connection path directly on at least a portion of the first MOM capacitor, wherein the first MOM capacitor is located in the lower metal layer and the first electrical connection path is located in the higher metal layer.

[0130] In one operation 156, the method includes forming a plurality of second electrical connection paths in one or more higher metal layers and connecting them to the other side of the first MOM capacitor and an output pad, wherein the one or more higher metal layers have a large width, and the one or more lower metal layers are lower than the first electrical connection paths and the second electrical connection paths, and the one or more higher metal layers are higher than the first MOM capacitor. In some embodiments, the higher metal layers are similar to Figure 4 The metal layers 86i and 86j are described above. In some embodiments, forming the second electrical connection path includes forming the second electrical connection path directly on at least a portion of the first MOM capacitor, wherein the first MOM capacitor is located in the lower metal layer and the second electrical connection path is located in the higher metal layer.

[0131] In some embodiments, the method includes forming a plurality of second MOM capacitors in one or more lower metal layers to form a second capacitor in the impedance matching network, wherein the lower metal layers have a smaller width and are lower than the first electrical connection path and the second electrical connection path. In some embodiments, forming the second electrical connection path includes forming the second electrical connection path in one or more higher metal layers and connecting it to one side of the second MOM capacitor, the other side of the first MOM capacitor, and the output pad, wherein the higher metal layers have a larger width and are higher than the first MOM capacitor.

[0132] Figure 12This is a block diagram of an example of a computer system 200 described according to some embodiments, wherein the computer system 200 is configured to provide a plurality of electronic devices, semiconductor devices, and methods of the present invention. Some or all of the semiconductor devices (also referred to as semiconductor circuits) can be designed, laid out, and manufactured with the assistance of, or through, the computer system 200. Furthermore, some or all of the electronic devices can also be designed, laid out, and manufactured with the assistance of, or through, the computer system 200. In some embodiments, the computer system 200 includes an electronic design automation (EDA) system. In some embodiments, the aforementioned semiconductor devices are integrated circuits (ICs).

[0133] In some embodiments, computer system 200 is a general-purpose computing device including a processor 202 and a non-transitory computer-readable storage medium 204. The computer-readable storage medium 204 can be encoded (e.g., stored) by computer program code (e.g., a plurality of executable instructions 206). The processor 202 executes the instructions 206 to provide at least a portion of a design tool to implement some or all of the functions of computer system 200, such as pre-layout simulation, post-layout simulation, routing, rerouting, and final layout for manufacturing. Furthermore, a plurality of fabrication tools 208 are incorporated to further perform layout and actually implement the design and manufacture of the semiconductor device. In some embodiments, the processor 202 executes the instructions 206 to provide at least a portion of a design tool to implement some or all of the functions of computer system 200. In some embodiments, computer system 200 includes a commercial router. In some embodiments, computer system 200 includes an automatic place and route (APR) system.

[0134] Processor 202 is electrically coupled to computer-readable storage medium 204 via bus 210 and to an input / output (I / O) interface 212 via bus 210. A network interface 214 is also electrically connected to processor 202 via bus 210. Network interface 214 is connected to a network 216, allowing processor 202 and computer-readable storage medium 204 to connect to external components via network 216. Processor 202 is configured to execute computer program code or instructions 206 encoded in computer-readable storage medium 204 to enable computer system 200 to perform some or all of its functions, such as providing the semiconductor device and method of this invention, and other functions of computer system 200. In some embodiments, processor 202 is a central processing unit (CPU), a multi-core processor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0135] In some embodiments, the computer-readable storage medium 204 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system, device, or apparatus. For example, the computer-readable storage medium 204 may include a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, a random-access memory (RAM), a read-only memory (ROM), a hard disk, and / or an optical disc. In some embodiments utilizing an optical disc, the computer-readable storage medium 204 includes a compact disk ROM (CD-ROM), a CD read / write memory (CD-R / W), and / or a digital video disc (DVD).

[0136] In some embodiments, the computer-readable storage medium 204 stores computer program code or instructions 206, wherein the computer program code or instructions 206 are configured to cause the computer system 200 to perform some or all of its functions. In some embodiments, the computer-readable storage medium 204 also stores information that helps the computer system 200 perform some or all of its functions. In some embodiments, the computer-readable storage medium 204 stores a database 218, wherein the database 218 includes one or more component libraries, digital circuit unit libraries, and databases.

[0137] Computer system 200 includes an I / O interface 212 coupled to external circuitry. In some embodiments, the I / O interface 212 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or directional keys for communicating information and commands with processor 202.

[0138] Network interface 214 is coupled to processor 202 and allows computer system 200 to communicate with network 216, wherein network 216 is connected to one or more other computer systems. Network interface 214 may include: a wireless network interface, such as Bluetooth, wireless fidelity (WIFI), worldwide interoperability for microwave access (WIMAX), general packet radio service (GPRS), or wideband code division multiple access (WCDMA); or a wired network interface, such as Ethernet, universal serial bus (USB), or IEEE-1364. In some embodiments, some or all of the functions of computer system 200 may be performed in two or more systems similar to computer system 200.

[0139] Computer system 200 is configured to receive information via I / O interface 212. The information received via I / O interface 212 includes one or more instructions, data, design rules, component and unit program libraries, and / or other parameters that can be processed by processor 202. This information is transmitted to processor 202 via bus 210. Furthermore, computer system 200 is configured to receive information about a user interface (UI) via I / O interface 212. This UI information can be stored as a UI 220 in computer-readable storage medium 204.

[0140] In some embodiments, some or all of the functions of the computer system 200 are implemented by a standalone software application, wherein the standalone software application is executed by a processor. In some embodiments, some or all of the functions of the computer system 200 are implemented by a software application, wherein the software application is part of an additional software application. In some embodiments, some or all of the functions of the computer system 200 are implemented as a plug-in to a software application. In some embodiments, at least one function of the computer system 200 is implemented as a software application, wherein the software application is part of an EDA tool. In some embodiments, some or all of the functions of the computer system 200 are implemented as a software application utilized by the computer system 200. In some embodiments, a tool is used to generate a layout diagram, wherein the tool may be VIRTUOSO provided by CADENCEDESIGN SYSTEMS (Inc.), or other suitable layout generation tools.

[0141] In some embodiments, winding, layout, and other procedures are implemented as functions of a program, wherein the aforementioned programs are stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include (but are not limited to) external / removable and / or internal / built-in storage or memory units, such as one or more optical discs (e.g., a digital versatile disc or DVD), a magnetic disk (e.g., a hard disk), a semiconductor memory (e.g., ROM and RAM), and a memory card or other similar devices.

[0142] As described above, various embodiments of the computer system 200 include a process tool 208 for fabricating the computer system 200. For example, based on a final layout, a lithography photomask can be generated for fabricating a semiconductor device using the process tool 208.

[0143] Combination Figure 13 To further disclose several examples of the device process, among which Figure 13 This describes a semiconductor device manufacturing system 222 and related semiconductor processes according to some embodiments. In some embodiments, based on a layout diagram, the semiconductor device manufacturing system 222 is used to manufacture one or more semiconductor photomasks and / or at least one element in a layer of a semiconductor device.

[0144] exist Figure 13In this semiconductor device manufacturing system 222, multiple entities, such as a design company 224, a photomask company 226, and a semiconductor device manufacturer (also referred to as a "Fab") 228, interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacture of semiconductor devices (such as those described herein). The entities in the semiconductor device manufacturing system 222 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is multiple different networks, such as intranets and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design company 224, photomask company 226, and semiconductor device manufacturer 228 are owned by a single large corporation. In some embodiments, two or more of the design company 224, photomask company 226, and semiconductor device manufacturer 228 coexist in a shared facility and share resources.

[0145] Design company (or design team) 224 generates a semiconductor device design layout 230. The semiconductor device design layout 230 includes various geometric patterns, or multiple semiconductor device layouts designed for use in a semiconductor device. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers forming various elements of the manufactured semiconductor structure. Multiple layers are combined to form various semiconductor device features. For example, a portion of the semiconductor device design layout 230 includes various semiconductor device features to be formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers located above the semiconductor substrate, such as diagonal vias, active regions or active areas, gate electrodes, source electrodes, drain electrodes, metal lines, partial vias, and openings as bond pads. Design company 224 implements a design process to generate the semiconductor device design layout 230. The semiconductor device design layout 230 is presented in one or more data files having the aforementioned geometric patterns. For example, the semiconductor device design layout 230 can be represented in GDSII or DFII file format. In some embodiments, the above design process includes one or more of the following: analog circuit design, digital circuit design, logic circuit design, standard cell circuit design, power distribution network (PDN) design (e.g., including power via design), supply voltage route design, reference voltage route design, placement and routing, and actual layout design.

[0146] Photomask company 226 includes a data preparation process 232 and a photomask fabrication process 234. Photomask company 226 uses a semiconductor device design layout 230 to fabricate one or more photomasks 236 for multiple layers of a semiconductor device or semiconductor structure. Photomask company 226 performs the photomask data preparation process 232, in which the semiconductor device design layout 230 is translated into a representative data file (RDF). The photomask data preparation process 232 provides the RDF to the photomask fabrication process 234. The photomask fabrication process 234 includes a photomask writer for converting the RDF into a pattern on a substrate, which may be a photomask (or reticle) 236 or a semiconductor wafer 238. The semiconductor device design layout 230 is manipulated through the photomask data preparation process 232 to conform to the standards of the photomask writer and / or the semiconductor device manufacturer 228. Figure 13 In this document, the photomask data preparation process 232 and the photomask manufacturing process 234 are described as separate elements. In some embodiments, the photomask data preparation process 232 and the photomask manufacturing process 234 may be considered as a single photomask data preparation process.

[0147] In some embodiments, the photomask data preparation procedure 232 includes an optical proximity correction (OPC) to compensate for pattern errors (e.g., those possibly caused by diffraction, interference, other process effects, and the like) using lithography techniques. The OPC adjusts the semiconductor device design layout 230. In some embodiments, the photomask data preparation procedure 232 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift photomasks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography techniques (ILT) can also be used to treat the OPC as an inverse imaging problem.

[0148] In some embodiments, the photomask data preparation procedure 232 includes a photomask rule checker (MRC) to check the semiconductor device design layout 230, which has undergone an OPC procedure using a set of photomask generation rules, wherein the photomask generation rules have specific geometric and / or conductivity constraints to ensure sufficient margin to account for variables in the semiconductor process. In some embodiments, the MRC adjusts the semiconductor device design layout 230 to compensate for the constraints of the photomask fabrication procedure 234, and may therefore revert the adjustments made by the OPC to conform to the photomask generation rules.

[0149] In some embodiments, the photomask data preparation procedure 232 includes lithography process checking (LPC) to simulate the procedures implemented by the semiconductor device manufacturer 228. Based on the semiconductor device design layout 230, the LPC simulates the aforementioned procedures to generate a simulated manufactured device. In the LPC simulation, the parameters of the aforementioned procedures may be related to the procedures of the semiconductor device manufacturing cycle, the tools used to manufacture the semiconductor device, and / or other process paradigms. The LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like or combinations thereof. In some embodiments, after the LPC generates a simulated manufactured device, if the simulated device is not close enough to meeting the design rules, the OPC and / or MRC will repeat the simulation to further improve the semiconductor device design layout 230.

[0150] The photomask data preparation procedure 232 described above has been simplified for clarity. In some embodiments, the data preparation procedure 232 includes additional features, such as a logic operation (LOP), to adjust the semiconductor device design layout 230 according to process rules. Furthermore, the above procedures can be performed on the semiconductor device design layout 230 in different sequences during the data preparation procedure 232.

[0151] Following the photomask data preparation procedure 232 and in the photomask fabrication procedure 234, a photomask 236 or a set of photomasks 236 is fabricated based on the adjusted semiconductor device design layout 230. In some embodiments, the photomask fabrication procedure 234 includes performing one or more photolithography exposures based on the semiconductor device design layout 230. In some embodiments, based on the adjusted semiconductor device design layout 230, an electron beam (e-beam) or multiple electron beam mechanisms are used to form a pattern on the photomask 236. Different techniques can be used to form the photomask 236. In some embodiments, a binary technique is used to form the photomask 236. In some embodiments, the photomask pattern includes opaque regions and transparent regions. A radiation beam (e.g., an ultraviolet (UV) beam) is used to expose an imaging-sensitive material layer (e.g., a photoresist layer), wherein the radiation beam is blocked by the opaque regions and penetrates the transparent regions. In one example, the photomask 236 of a binary photomask version includes a transparent substrate (e.g., synthetic quartz) and an opaque material (e.g., chromium) attached to an opaque region of the binary photomask. In another example, the photomask 236 is formed using a phase-shifting technique. In a phase-shift mask (PSM) version of the photomask 236, multiple features of the pattern formed on the phase-shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In several examples, the phase-shift mask may be an attenuated PSM or an alternating PSM. One or more photomasks manufactured by photomask fabrication process 234 are used in a variety of processes. For example, one or more photomasks are used in an ion implantation process to form multiple doped regions in a semiconductor wafer 238, in an etching process to form multiple etched regions in a semiconductor wafer 238, and / or in other suitable processes.

[0152] Semiconductor device manufacturer 228 includes wafer process 240. Semiconductor device manufacturer 228 is a semiconductor device manufacturing company, including one or more manufacturing facilities for manufacturing various semiconductor device products. In some embodiments, semiconductor device manufacturer 228 is a semiconductor plant. For example, it may have a manufacturing facility for producing semiconductor device products manufactured using front-end of line (FEOL) processes, a second manufacturing facility for providing back-end of line (BEOL) manufacturing for interconnecting and packaging semiconductor device products, and a third manufacturing facility for providing other services for the semiconductor industry.

[0153] Semiconductor device manufacturer 228 uses one or more photomasks 236 manufactured by a photomask company to fabricate the semiconductor structure or semiconductor device 242 of this invention. Therefore, semiconductor device manufacturer 228 at least indirectly utilizes semiconductor device design layout 230 to fabricate the semiconductor structure or semiconductor device 242 of this invention. Furthermore, semiconductor wafer 238 includes a silicon substrate or other suitable substrate having a material layer formed thereon, and semiconductor wafer 238 also includes one or more different doped regions, dielectric features, multilayer interconnect structures, and the like (formed in subsequent process operations). In some embodiments, semiconductor device manufacturer 228 uses one or more photomasks 236 to fabricate semiconductor wafer 238 to form the semiconductor structure or semiconductor device 242 of this invention. In some embodiments, the semiconductor device process includes one or more photolithography exposures based at least indirectly on semiconductor device design layout 230.

[0154] Therefore, the disclosed embodiments include multiple LNAs with one or more MOM capacitors that enhance the Q factor, thereby improving the gain and noise of the LNAs. In some embodiments, a capacitor is formed by multiple smaller MOM capacitors connected in parallel to achieve the capacitance value of the capacitor. The smaller MOM capacitors reduce the parasitic resistance of the capacitor and increase the Q factor of the capacitor.

[0155] The disclosed embodiments also include a routing reuse technique, wherein the aforementioned MOM capacitors, connected in parallel, are configured under a signal path (e.g., a signal path from the LNA output to the gain stage). This reduces power loss in the signal path and improves the efficiency of the LNA's gain and noise factor.

[0156] The benefits of enhanced MOM Q factor technology include increased gain and reduced noise in advanced nodes, thus contributing to improved LNA performance and justifying the increased cost of advanced nodes.

[0157] According to some embodiments, an electronic device includes an amplifier having an input terminal and an output terminal. The amplifier includes a gain stage and an output impedance matching network connected to the gain stage and the output terminal. The output impedance matching network includes a plurality of MOM capacitors connected in parallel with each other.

[0158] In some embodiments, the output impedance matching network includes a capacitor having a first terminal connected to the gain stage and a second terminal connected to the output terminal, and the capacitor includes a plurality of MOM capacitors connected in parallel with each other. In some embodiments, the electronic device further includes a gain stage output path and an output path, the gain stage output path being connected to one side of each of the gain stage and each of the plurality of MOM capacitors, and the output path being connected to the other side of each of the plurality of MOM capacitors and the output terminal, wherein the plurality of MOM capacitors connected in parallel with each other include one or more lower metal layers, and the lower metal layers are lower than the gain stage output path and the output path.

[0159] In some embodiments, the electronic device further includes a gain stage output path and an output path. The gain stage output path is connected to one side of each of the gain stage and each of the plurality of MOM capacitors, and the output path is connected to the other side of each of the plurality of MOM capacitors and the output terminal. The gain stage output path and the output path include one or more higher metal layers, and the higher metal layers are higher than the plurality of MOM capacitors. The gain stage output path and the output path include multiple metal lines, and at least a portion of the gain stage output path is disposed on at least a portion of each of the plurality of MOM capacitors, and at least a portion of the output path is disposed on at least a portion of each of the plurality of MOM capacitors.

[0160] In some embodiments, the output impedance matching network includes an inductor having a first terminal connected to a power supply and a second terminal connected to the gain stage and the capacitor. In some embodiments, the gain stage includes at least two metal-oxide-semiconductor field-effect transistors (MOSFETs) having multiple drain / source paths connected in series. In some embodiments, the electronic device further includes an input impedance matching network having a first terminal connected to the input and a second terminal connected to the gain stage. In some embodiments, the electronic device further includes a source decay circuit having a first terminal connected to the gain stage and a second terminal connected to a reference terminal.

[0161] According to further embodiments, an amplifier device includes an input terminal, an output terminal, an input impedance matching network connected to the input terminal, a gain stage connected to the input impedance matching network, and an output impedance matching network connected to the gain stage and the output terminal. The output impedance matching network includes a first capacitor having a first terminal connected to the gain stage and a second terminal connected to the output terminal, and the first capacitor includes a plurality of first MOM capacitors connected in parallel with each other.

[0162] In some embodiments, the amplifier device further includes a gain stage output path and an output path, the gain stage output path being connected to one side of each of the gain stage and each of the plurality of first MOM capacitors, and the output path being connected to the other side of each of the plurality of first MOM capacitors and the output terminal, wherein the plurality of first MOM capacitors connected in parallel with each other include one or more lower metal layers, the lower metal layers being lower than the gain stage output path and the output path, and wherein the gain stage output path and the output path include one or more higher metal layers, the higher metal layers being higher than the plurality of MOM capacitors.

[0163] In some embodiments, the output impedance matching network includes a second capacitor having a first terminal connected to the output terminal and a second terminal connected to a reference terminal, and the second capacitor includes a plurality of second MOM capacitors connected in parallel with each other. In some embodiments, the output impedance matching network includes an inductor having a first terminal connected to a power supply terminal and a second terminal connected to the gain stage and the first capacitor. In some embodiments, the input impedance matching network includes an inductor having a first terminal connected to the input terminal and a second terminal connected to the gain stage.

[0164] According to several disclosed examples, a method for manufacturing an amplifier is provided. The method includes forming a plurality of transistors in an active region layer to form a gain stage of the amplifier; forming a plurality of first MOM capacitors in one or more lower metal layers to form a first capacitor in an input impedance matching network, wherein the lower metal layers have a smaller width; forming a plurality of first electrical connection paths in one or more higher metal layers and connecting them to one side of the gain stage and the first MOM capacitors, wherein the higher metal layers have a larger width; and forming a plurality of second electrical connection paths in one or more of the higher metal layers and connecting them to the other end of the first MOM capacitors and an output pad, wherein the higher metal layers have a larger width.

[0165] In some embodiments, forming the first electrical connection path includes forming the first electrical connection path directly over at least a portion of the first MOM capacitor in the lower metal layer, wherein the first electrical connection path is located within the higher metal layer. Similarly, forming the second electrical connection path includes forming the second electrical connection path directly over at least a portion of the first MOM capacitor in the lower metal layer, wherein the second electrical connection path is located within the higher metal layer.

[0166] In some embodiments, the method of manufacturing the amplifier further includes forming a plurality of second MOM capacitors in the lower metal layer to form a second capacitor in the impedance matching circuit, wherein the one or more lower metal layers have a small width and are lower than the first electrical connection path and the second electrical connection path. The operation of forming the second electrical connection path includes forming the second electrical connection path in the higher metal layer and connecting it to one side of the second MOM capacitor, the other side of the first MOM capacitor, and the output pad, wherein the higher metal layer has a larger width and is higher than the first MOM capacitor.

[0167] This utility model outlines numerous embodiments to enable those skilled in the art to better understand the utility model from various aspects. Those skilled in the art will understand and readily be able to design or modify other processes and structures based on this utility model to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive spirit and scope of this utility model. Various changes, substitutions, or modifications can be made to this utility model without departing from the inventive spirit and scope of this utility model.

Claims

1. An electronic device, characterized in that, include: An amplifier having an input terminal and an output terminal, and including: One gain stage; as well as An output impedance matching network is connected to the gain stage and the output terminal described above. The aforementioned output impedance matching network includes multiple metal-oxide-metal capacitors connected in parallel with each other.

2. The electronic device as claimed in claim 1, characterized in that, The aforementioned output impedance matching network includes a capacitor having a first terminal connected to the aforementioned gain stage and a second terminal connected to the aforementioned output stage, and the aforementioned capacitor includes a plurality of metal-oxide-metal capacitors connected in parallel with each other.

3. The electronic device as claimed in claim 2, characterized in that, It also includes a gain stage output path and an output path, wherein the gain stage output path is connected to one side of the gain stage and each of the plurality of metal-oxide-metal capacitors, and the output path is connected to the other side of each of the plurality of metal-oxide-metal capacitors and the output terminal, wherein the plurality of metal-oxide-metal capacitors connected in parallel with each other include one or more lower metal layers, and the lower metal layers are lower than the gain stage output path and the output path.

4. The electronic device as claimed in claim 2, characterized in that, It also includes a gain stage output path and an output path, wherein the gain stage output path is connected to one side of each of the gain stage and each of the plurality of metal-oxide-metal capacitors, and the output path is connected to the other side of each of the plurality of metal-oxide-metal capacitors and the output terminal, wherein the gain stage output path and the output path include one or more higher metal layers, and the higher metal layers are higher than the plurality of metal-oxide-metal capacitors. The aforementioned gain stage output path and the aforementioned output path include multiple metal lines, and at least a portion of the aforementioned gain stage output path is configured on at least a portion of each of the aforementioned multiple metal-oxide-metal capacitors, and at least a portion of the aforementioned output path is configured on at least a portion of each of the aforementioned multiple metal-oxide-metal capacitors.

5. The electronic device as claimed in claim 2, characterized in that, The aforementioned output impedance matching network includes an inductor having a first terminal connected to a power supply and a second terminal connected to the aforementioned gain stage and the aforementioned capacitor.

6. The electronic device as claimed in claim 1, characterized in that, The aforementioned output impedance matching network includes a capacitor having a first terminal connected to the aforementioned output terminal and a second terminal connected to a reference terminal, and the capacitor includes a plurality of metal-oxide-metal capacitors connected in parallel with each other; or The aforementioned gain stage includes at least two metal-oxide-semiconductor field-effect transistors, which have multiple drain / source paths connected in series.

7. The electronic device as claimed in claim 1, characterized in that, Also includes: An input impedance matching network having a first terminal connected to the aforementioned input terminal and a second terminal connected to the aforementioned gain stage; or A source decay circuit has a first terminal connected to the aforementioned gain stage and a second terminal connected to a reference terminal.

8. An amplifier device, characterized in that, include: One input terminal and one output terminal; An input impedance matching network is connected to the aforementioned input terminal; A gain stage is connected to the aforementioned input impedance matching network; and An output impedance matching network is connected to the gain stage and the output terminal described above. The aforementioned output impedance matching network includes a first capacitor having a first terminal connected to the aforementioned gain stage and a second terminal connected to the aforementioned output terminal, and the aforementioned first capacitor includes a plurality of first metal-oxide-metal capacitors connected in parallel with each other.

9. The amplifier device as claimed in claim 8, characterized in that, It also includes a gain stage output path and an output path, wherein the gain stage output path is connected to one side of each of the gain stage and each of the plurality of first metal-oxide-metal capacitors, and the output path is connected to the other side of each of the plurality of first metal-oxide-metal capacitors and the output terminal, wherein the plurality of first metal-oxide-metal capacitors connected in parallel with each other include one or more lower metal layers, and the lower metal layers are lower than the gain stage output path and the output path, and wherein the gain stage output path and the output path include one or more higher metal layers, and the higher metal layers are higher than the plurality of metal-oxide-metal capacitors.

10. The amplifier device as claimed in claim 8, characterized in that, The aforementioned output impedance matching network includes a second capacitor having a first terminal connected to the aforementioned output terminal and a second terminal connected to a reference terminal, and the aforementioned second capacitor includes a plurality of second metal-oxide-metal capacitors connected in parallel with each other; The aforementioned output impedance matching network includes an inductor having a first terminal connected to a power supply and a second terminal connected to the aforementioned gain stage and the aforementioned first capacitor; or The aforementioned input impedance matching network includes an inductor having a first terminal connected to the aforementioned input terminal and a second terminal connected to the aforementioned gain stage.

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