Isolated integrated circuit and carrier frequency control circuit
By controlling the carrier frequency generation circuit to stop outputting signals during the input signal disable period through the carrier frequency control circuit, the problem of increased power consumption in the prior art is solved, and the circuit energy efficiency is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- POWERX SEMICONDUCTOR CORPORATION
- Filing Date
- 2025-06-30
- Publication Date
- 2026-06-26
Smart Images
Figure CN224418787U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a carrier frequency control circuit, and more particularly to a carrier frequency control circuit applied to isolated integrated circuits. Background Technology
[0002] In the field of signal modulation generation, some techniques generate modulated signals by modulating a signal based on a high-frequency signal output by an oscillator. However, even when a high-frequency signal is not needed, these techniques still cause the oscillator to continuously output a high-frequency signal, leading to an increase in the overall circuit power consumption. Utility Model Content
[0003] One embodiment of this utility model is an isolated integrated circuit. The isolated integrated circuit includes a primary-side circuit, an isolation circuit, and a secondary-side circuit. The primary-side circuit includes a carrier frequency generation circuit, a carrier frequency control circuit, and a modulation circuit. The carrier frequency generation circuit generates a carrier frequency signal. The carrier frequency control circuit is electrically coupled to the carrier frequency generation circuit and is used to detect at least one active period and at least one inactive period of the input signal, generate at least one timing pulse during the at least one inactive period, and control the carrier frequency generation circuit to stop outputting the carrier frequency signal based on the at least one timing pulse. If one of the at least one timing pulses fails to increase to a preset voltage level before entering the at least one active period, the level rise slope of the next timing pulse will be adjusted, and the next active pulse will be directly following the previous active pulse. The modulation circuit is electrically coupled to the carrier frequency generation circuit and is used to receive the input signal and the carrier frequency signal, and output a modulated signal based on the input signal and the carrier frequency signal. The isolation circuit is coupled to the primary circuit and is used to transmit the modulated signal. The secondary circuit is coupled to the isolation circuit and is used to generate an output signal based on the modulated signal, wherein the waveform of the output signal is substantially the same as the waveform of the input signal.
[0004] In one embodiment, the carrier frequency control circuit includes an edge detection circuit, a timing pulse generation circuit, a switch control circuit, and a judgment circuit. The edge detection circuit outputs at least one rising signal during the at least one enable period and at least one falling signal during the at least one disable period. The timing pulse generation circuit is electrically coupled to the edge detection circuit and outputs a frequency filtering signal, and adjusts the voltage level of the frequency filtering signal according to the at least one falling signal to generate the at least one timing pulse. The switch control circuit is electrically coupled to the carrier frequency generation circuit, the edge detection circuit, and the timing pulse generation circuit, and controls the carrier frequency generation circuit to output the carrier frequency signal according to the at least one rising signal, and controls the carrier frequency generation circuit to stop outputting the carrier frequency signal during the output period of the at least one timing pulse. The judgment circuit is electrically coupled to the edge detection circuit and the timing pulse generation circuit, and outputs a judgment signal to control the timing pulse generation circuit based on the frequency filtering signal, the at least one rising signal, and the at least one falling signal.
[0005] In one embodiment, the at least one rising signal includes a first rising signal corresponding to the one in the at least one timing pulse, wherein, upon receiving the first rising signal and before the one in the at least one timing pulse is detected to increase to the preset voltage level, the determination circuit adjusts the voltage level of the determination signal to generate an adjustment pulse to control the timing pulse generating circuit to increase the level rise slope of the next one in the at least one timing pulse.
[0006] In one embodiment, the at least one timing pulse is configured to take a first time length to increase to the preset voltage level, and the next timing pulse is configured to take a second time length to increase to the preset voltage level, wherein the second time length is the first time length minus the preset time length.
[0007] In one embodiment, if the voltage level of the device increases to the preset voltage level before the device enters the at least one consistent energy period in the at least one timing pulse, the carrier frequency control circuit is further configured to count the number of pulses of the carrier frequency signal between the time point in the at least one timing pulse when the device has the preset voltage level and the time point when the device enters the at least one consistent energy period, wherein when the number of pulses is greater than a threshold number, the level rise slope of the next device in the at least one timing pulse will be adjusted.
[0008] In one embodiment, the carrier frequency control circuit includes an edge detection circuit, a timing pulse generation circuit, a switch control circuit, a judgment circuit, and a clock counting circuit. The edge detection circuit outputs at least one rising signal during the at least one enable period and at least one falling signal during the at least one disable period. The timing pulse generation circuit is electrically coupled to the edge detection circuit and outputs a frequency filtering signal, and adjusts the voltage level of the frequency filtering signal according to the at least one falling signal to generate the at least one timing pulse. The switch control circuit is electrically coupled to the carrier frequency generation circuit, the edge detection circuit, and the timing pulse generation circuit, and controls the carrier frequency generation circuit to output the carrier frequency signal according to the at least one rising signal, and controls the carrier frequency generation circuit to stop outputting the carrier frequency signal during the output period of the at least one timing pulse. The judgment circuit is electrically coupled to the edge detection circuit and the timing pulse generation circuit, and outputs a judgment signal to control the timing pulse generation circuit according to the frequency filtering signal, the at least one rising signal, and the at least one falling signal. The clock counting circuit is electrically coupled to the carrier frequency generation circuit, the edge detection circuit, and the timing pulse generation circuit, and is used to output an increasing signal to control the timing pulse generation circuit based on the carrier frequency signal, the frequency filtering signal, the at least one rising signal, and the at least one falling signal.
[0009] In one embodiment, at least one rising signal includes a first rising signal corresponding to the one in the at least one timing period, wherein when the one in the at least one timing pulse is detected to increase to the preset voltage level before the first rising signal is received, in response to the number of pulses being greater than the threshold number, the clock counting circuit adjusts the voltage level of the increasing signal to generate an adjustment pulse to control the timing pulse generating circuit to reduce the level rise slope of the next one in the at least one timing pulse.
[0010] In one embodiment, the at least one timing pulse is configured to take a first time length to increase to the preset voltage level, and the next timing pulse is configured to take a second time length to increase to the preset voltage level, wherein the second time length is the first time length plus the preset time length.
[0011] In one embodiment, during the at least one disabled period, the carrier frequency control circuit is used to generate at least one buffer pulse and the at least one timing pulse, and to control the carrier frequency generation circuit to output the carrier frequency signal according to the at least one buffer pulse.
[0012] One embodiment of this utility model is a carrier frequency control circuit. The carrier frequency control circuit is electrically coupled to a carrier frequency generation circuit for receiving an input signal and includes an edge detection circuit, a timing pulse generation circuit, a switch control circuit, and a judgment circuit. The edge detection circuit outputs at least a rising signal during at least one active period of the input signal and outputs at least a falling signal during at least one inactive period of the input signal. The timing pulse generation circuit is electrically coupled to the edge detection circuit for outputting a frequency filtering signal and adjusting the voltage level of the frequency filtering signal according to the at least one falling signal to generate at least one timing pulse. The switch control circuit is electrically coupled to the carrier frequency generation circuit, the edge detection circuit, and the timing pulse generation circuit, controlling the carrier frequency generation circuit to output a carrier frequency signal according to the at least one rising signal, and controlling the carrier frequency generation circuit to stop outputting the carrier frequency signal during the output period of the at least one timing pulse. The judgment circuit is electrically coupled to the edge detection circuit and the timing pulse generation circuit, and is used to output a judgment signal to control the timing pulse generation circuit based on the frequency filtering signal, the at least one rising signal, and the at least one falling signal. If one of the at least one timing pulses fails to increase to a preset voltage level before entering the time point of the at least one consistent energy period, the level rise slope of the next of the at least one timing pulses will be adjusted, and the next pulse in the at least one consistent energy period will be directly after the previous pulse in the at least one timing pulse.
[0013] In summary, the carrier frequency control circuit of this invention detects the enable and disable periods of the input signal, and controls the carrier frequency generation circuit to stop outputting the carrier frequency signal during the timing pulse output period during the disable period of the input signal. Therefore, the isolated integrated circuit of this invention has advantages such as lower overall circuit power consumption. Attached Figure Description
[0014] Figure 1 A block diagram illustrating an isolated integrated circuit according to some embodiments of the present invention.
[0015] Figure 2 The illustrations are based on some embodiments of the present invention. Figure 1 Timing diagrams of some signals related to the operation of isolated integrated circuits.
[0016] Figure 3 A block diagram illustrating an isolated integrated circuit according to some embodiments of the present invention.
[0017] Figure 4 The illustrations are based on some embodiments of the present invention. Figure 3 Timing diagrams of some signals related to the operation of isolated integrated circuits.
[0018] Figure 5 The flowchart illustrates a modulation signal generation method according to some embodiments of the present invention. Detailed Implementation
[0019] The following detailed description of embodiments, in conjunction with the accompanying drawings, is provided. However, the specific embodiments described are only for explaining the present invention and are not intended to limit the present invention. The description of the structural operations is not intended to limit the order of their execution. Any structure resulting from the recombination of elements and producing a device with equivalent functionality is within the scope of the present invention.
[0020] Unless otherwise specified, the terms used throughout the specification and claims generally have their ordinary meaning in the context of the art, the content disclosed herein, and the specific content.
[0021] The terms "coupled" or "connected" as used in this article can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or to two or more components operating or moving together.
[0022] Please see Figure 1 , Figure 1 This is a block diagram illustrating an isolated integrated circuit 100 according to some embodiments of the present invention. In some embodiments, the isolated integrated circuit 100 includes a primary-side circuit 10, an isolation circuit 20, and a secondary-side circuit 30. Specifically, the isolated integrated circuit 100 can be implemented using a gate driver.
[0023] In some embodiments, such as Figure 1 As shown, one end of the isolation circuit 20 is coupled to the output of the primary circuit 10, while the other end is coupled to the input of the secondary circuit 30, to provide electrical insulation between the primary circuit 10 and the secondary circuit 30 in the isolated integrated circuit 100 according to system requirements. Accordingly, the primary circuit 10 can use a first power supply voltage VCC1 and a first ground voltage GND1 as its operating voltage, and the secondary circuit 30 can use a second power supply voltage VCC2, different from the first power supply voltage VCC1, and a second ground voltage GND2, different from the first ground voltage GND1, as its operating voltage. Specifically, the isolation circuit 20 can be implemented using insulating components such as transformers or capacitors.
[0024] In some embodiments, while ensuring voltage isolation (i.e., the aforementioned electrical insulation) between the primary side circuit 10 and the secondary side circuit 30, the isolation circuit 20 can also serve as a communication interface between the primary side circuit 10 and the secondary side circuit 30, so that data, signals and / or information can be transmitted from the primary side circuit 10 to the secondary side circuit 30, thereby enabling the isolated integrated circuit 100 to operate normally.
[0025] In some embodiments, such as Figure 1 As shown, the primary side circuit 10 includes a carrier frequency generation circuit 11, a carrier frequency control circuit 13, a modulation circuit 15, a buffer circuit 17, and a transmitting circuit 19. Specifically, the modulation circuit 15 is electrically coupled to the carrier frequency generation circuit 11, the buffer circuit 17, and the transmitting circuit 19, while the carrier frequency control circuit 13 is electrically coupled to the carrier frequency generation circuit 11. The transmitting circuit 19 is coupled to one end of the isolation circuit 20 through the output terminal of the primary side circuit 10. Furthermore, the secondary side circuit 30 includes a receiving circuit 31 and a demodulation circuit 33. The receiving circuit 31 is coupled to the other end of the isolation circuit 20 through the input terminal of the secondary side circuit 30, while the demodulation circuit 33 is electrically coupled to the receiving circuit 31.
[0026] Then, at the same time, pair Figure 1 and Figure 2 The operation of the primary circuit 10 will be further explained. Figure 2 The illustrations are based on some embodiments of the present invention. Figure 1 Timing diagram of some signals related to the operation of the primary side circuit 10.
[0027] In some embodiments, such as Figure 1 As shown, the primary side circuit 10 is used to receive the input signal Vin. Also, as... Figure 2 As shown, the input signal Vin can be a periodic signal, such as a pulse width modulation (PWM) signal, and has a period TC. Specifically, the frequency of the input signal Vin can be 100 to 1 MHz, and the reciprocal of the frequency of the input signal Vin is the period TC.
[0028] As mentioned above, in each cycle TC, the input signal Vin is at an enabled level for a period of time (e.g., corresponding to logic "1" or the voltage level of the first power supply voltage VCC1), and at a disabled level for another period of time (e.g., corresponding to logic "0" or the voltage level of the first ground voltage GND1). In other words, as... Figure 2 As shown, each period TC of the input signal Vin has an enable period EA (corresponding to the enable level of the input signal Vin) and a disable period DA (corresponding to the disable level of the input signal Vin).
[0029] For clarity and ease of explanation, Figure 2In this context, the number indexes [1] to [4] are used to refer to individual elements or signals, but this is not intended to limit the number of elements or signals to a specific number. If only the element or signal symbol is used without specifying the index of the element or signal symbol, it means that the element or signal symbol refers to any unspecified one in the group of elements or signals to which it belongs. For example, period TC refers to any unspecified one in periods TC[1] to TC[4].
[0030] For example Figure 1 As shown, the carrier frequency generation circuit 11 is used to generate the carrier frequency signal Vosi. The carrier frequency signal Vosi can also be a periodic signal. For example, the frequency of the carrier frequency signal Vosi can be approximately 500 MHz. Therefore, the frequency of the carrier frequency signal Vosi is higher than the frequency of the input signal Vin. Specifically, the carrier frequency generation circuit 11 can be implemented using an oscillator.
[0031] Modulation circuit 15 receives the input signal Vin and carrier frequency signal Vosi, which have been buffered by buffer circuit 17, and outputs a modulation signal Vmod based on the input signal Vin and carrier frequency signal Vosi, so that the transmitting circuit 19 couples the modulation signal Vmod to the isolation circuit 20. Specifically, modulation circuit 15 can use the carrier frequency signal Vosi to modulate the input signal Vin to generate the modulation signal Vmod. Figure 2 As shown, during the enable period EA of the input signal Vin, the modulation circuit 15 controls the modulation signal Vmod to oscillate at the frequency of the carrier frequency signal Vosi according to the enable level of the input signal Vin. During the disable period DA of the input signal Vin, the modulation circuit 15 controls the modulation signal Vmod to stop oscillating according to the disable level of the input signal Vin.
[0032] As described above, the isolation circuit 20 couples the modulated signal Vmod from the primary circuit 10 to the secondary circuit 30, so that the secondary circuit 30 can generate the output signal Vout. Specifically, the receiving circuit 31 receives and transmits a signal (not shown) that is substantially the same as the modulated signal Vmod to the demodulation circuit 33, and the demodulation circuit 33 demodulates the signal that is substantially the same as the modulated signal Vmod to generate the output signal Vout. Therefore, it can be seen that the secondary circuit 30 generates the output signal Vout based on the modulated signal Vmod. Furthermore, as... Figure 2 As shown, the waveform of the output signal Vout is essentially the same as the waveform of the input signal Vin.
[0033] As can be seen from the above description of generating the modulation signal Vmod, when the input signal Vin is at a disabled level, the carrier frequency signal Vosi generated by the carrier frequency generation circuit 11 has virtually no effect on the generation of the modulation signal Vmod. Therefore, this invention utilizes the carrier frequency control circuit 13 to control the modulation signal Vmod when the input signal Vin is at a disabled level (i.e., when...). Figure 2 During the disabled period (DA), the carrier frequency generation circuit 11 stops outputting the carrier frequency signal Vosi within an adjustable time period.
[0034] At Figure 1 In this embodiment, the carrier frequency control circuit 13 includes an edge detection circuit 131, a timing pulse generation circuit 133, a switch control circuit 135, and a judgment circuit 137. The edge detection circuit 131 is electrically coupled to the input terminal of the primary side circuit 10 and is used to generate a rising signal Vris or a falling signal Vfal based on the input signal Vin. The timing pulse generation circuit 133 and the judgment circuit 137 are both electrically coupled to the edge detection circuit 131 and to each other to generate a frequency filtering signal Vtpl and a judgment signal Vjud, respectively. The switch control circuit 135 is electrically coupled to the carrier frequency generation circuit 11, the edge detection circuit 131, and the timing pulse generation circuit 133, and is used to control the carrier frequency generation circuit 11 based on the rising signal Vris and the frequency filtering signal Vtpl.
[0035] Next, the pairing Figure 1 and Figure 2 The operation of the carrier frequency control circuit 13 is described in detail when the input signal Vin is at the enable or disable level (i.e., during the enable period EA or the disable period DA).
[0036] Edge detection circuit 131 is used to detect the rising edge or falling edge of input signal Vin to determine whether input signal Vin is in an enabled or disabled period. In some embodiments, when edge detection circuit 131 detects the rising edge of input signal Vin, it outputs a rising signal Vris (e.g., ...). Figure 1 As shown, the edge detection circuit 131 outputs a rising signal Vris during the enable period of the input signal Vin.
[0037] The timing pulse generation circuit 133 receives the rising signal Vris and controls the frequency filtering signal Vtpl to be at the reference voltage level (e.g., the first ground voltage GND1). That is, as... Figure 2 As shown, during the enable period EA, the timing pulse generation circuit 133 controls the frequency filtering signal Vtpl to be at the reference voltage level according to the enable level input signal Vin.
[0038] The switch control circuit 135 receives the rising signal Vris and the frequency filtering signal Vtpl of the reference voltage level, and controls the carrier frequency generation circuit 11 to output the carrier frequency signal Vosi based on the rising signal Vris. Specifically, after receiving the rising signal Vris, the switch control circuit 135 can generate an enable signal (not shown) to the carrier frequency generation circuit 11. Then, after receiving the enable signal, the carrier frequency generation circuit 11 outputs the carrier frequency signal Vosi. Therefore, as... Figure 2 As shown, during the enable period EA, the carrier frequency generation circuit 11 outputs the carrier frequency signal Vosi, which is used by the modulation circuit 15 to control the modulation signal Vmod to oscillate at the frequency of the carrier frequency signal Vosi.
[0039] As further explained above, the frequency filtering signal Vtpl of the reference voltage level will not affect the operation of the switch control circuit 135 in controlling the carrier frequency generation circuit 11 to output the carrier frequency signal Vosi.
[0040] In addition, the judgment circuit 137 also receives the rising signal Vris and the frequency filtering signal Vtpl of the reference voltage level, and can determine whether to change or adjust the voltage level of the judgment signal Vjud based on the time when it starts receiving the rising signal Vris, which will be explained in detail in the following paragraphs.
[0041] In some embodiments, when the edge detection circuit 131 detects the falling edge of the input signal Vin, it outputs a falling signal Vfal (e.g., ...). Figure 1 As shown, the edge detection circuit 131 outputs a falling signal Vfal during the disabled period of the input signal Vin.
[0042] The timing pulse generation circuit 133 receives the falling signal Vfal and adjusts the voltage level of the frequency filtering signal Vtpl to sequentially generate the buffer pulse Ton and the timing pulse Toff. Specifically, during the disabled period DA, the timing pulse generation circuit 133 raises the voltage level of the frequency filtering signal Vtpl from the reference voltage level to the preset voltage level Ref with a fixed slope (or a preset time length), and then immediately lowers the voltage level of the frequency filtering signal Vtpl back from the preset voltage level Ref to the reference voltage level to generate the buffer pulse Ton. Therefore, the output period of the buffer pulse Ton corresponds to or has a preset time length.
[0043] After the buffer pulse Ton is generated, the timing pulse generation circuit 133 raises the voltage level of the frequency filtering signal Vtpl from the reference voltage level with an adjustable slope until the voltage level of the frequency filtering signal Vtpl reaches the preset voltage level Ref or until the timing pulse generation circuit 133 receives the rising signal Vris corresponding to the next enable period EA, thereby generating the timing pulse Toff. Therefore, the output period Pb of the timing pulse Toff is adjustable.
[0044] As further explained above, if the voltage level of the frequency filtering signal Vtpl has not yet reached the preset voltage level Ref when the timing pulse generation circuit 133 receives the rising signal Vris corresponding to the next enable period EA (e.g., in...), Figure 2 During the disabled period DA[1] or DA[2], the falling edge of the timing pulse Toff will be generated when the timing pulse generation circuit 133 receives the rising signal Vris corresponding to the next enabled period EA. If the voltage level of the frequency filter signal Vtpl has already reached the preset voltage level Ref (e.g., before the timing pulse generation circuit 133 receives the rising signal Vris corresponding to the next enabled period EA), the falling edge of the timing pulse Toff will be generated when the timing pulse generation circuit 133 receives the rising signal Vris corresponding to the next enabled period EA. Figure 2 During the disabled period DA[3] or DA[4], the timing pulse generation circuit 133 will switch the voltage level of the frequency filtering signal Vtpl from the preset voltage level Ref to the reference voltage level, that is, the falling edge of the timing pulse Toff will be generated before the next enabled period EA arrives.
[0045] The switch control circuit 135 receives the frequency filtering signal Vtpl and controls the carrier frequency generation circuit 11 to output or not output the carrier frequency signal Vosi based on the buffer pulse Ton and the timing pulse Toff in the frequency filtering signal Vtpl. Specifically, the switch control circuit 135 controls the carrier frequency generation circuit 11 to output the carrier frequency signal Vosi based on the buffer pulse Ton, and controls the carrier frequency generation circuit 11 to stop outputting the carrier frequency signal Vosi based on the timing pulse Toff. Accordingly, as Figure 2 As shown, during the disabled period DA of the input signal Vin, the carrier frequency signal Vosi maintains its output during the output of the buffer pulse Ton, and stops outputting during the output of the timing pulse Toff.
[0046] As further explained above, when the output period of the timing pulse Toff[3] or Toff[4] ends and the disable period of the input signal Vin, DA[3] or DA[4], has not yet ended (that is, the switch control circuit 135 has completed the reception of the timing pulse Toff[3] or Toff[4] but has not yet received the rising signal Vris corresponding to the enable period EA[3] or EA[4]), the carrier frequency signal Vosi resumes output.
[0047] Furthermore, the determination circuit 137 receives the falling signal Vfal and the frequency filtering signal Vtpl, and determines whether to change or adjust the voltage level of the determination signal Vjud based on the voltage level of the timing pulse Toff in the frequency filtering signal Vtpl at the end of the disabled period DA (or the start of the next enabled period EA), so as to control the timing pulse generation circuit 133 accordingly, which will be described in more detail in the following paragraphs. It should be understood that the determination circuit 137 can determine whether the disabled period DA has ended (or whether the next enabled period EA has started) in one of a variety of ways. In some embodiments, the determination circuit 137 can detect the moment when the edge detection circuit 131 stops outputting the falling signal Vfal (i.e., the moment when it stops receiving the falling signal Vfal) or the moment when the edge detection circuit 131 starts outputting the rising signal Vris (i.e., the moment when it starts receiving the rising signal Vris). In short, the determination circuit 137 is used to output the determination signal Vjud based on the frequency filtering signal Vtpl, at least one rising signal Vris, and at least one falling signal Vfal to control the timing pulse generation circuit 133.
[0048] Specifically, at time point A1 when the disabled period DA[1] ends, the timing pulse Toff[1] has not yet reached the preset voltage level Ref. That is, the judgment circuit 137 receives the rising signal Vris corresponding to the enabled period EA[1], but has not yet detected that the timing pulse Toff[1] has increased to the preset voltage level Ref. Therefore, the judgment circuit 137 determines that the voltage level of the judgment signal Vjud needs to be changed or adjusted. In some embodiments, the judgment circuit 137 adjusts the voltage level of the judgment signal Vjud, for example, by switching the judgment signal Vjud from the disabled level to the enabled level, to generate an adjustment pulse (not shown in the figure).
[0049] During the enable period EA[1] immediately following the disable period DA[1], the timing pulse generation circuit 133 receives the adjustment pulse generated by the judgment circuit 137 and adjusts the timing pulse Toff[2] to be generated during the disable period DA[2] according to the adjustment pulse. Specifically, the timing pulse generation circuit 133 increases the level rise slope (i.e., adjustable slope) of the timing pulse Toff[2]. Therefore, if the timing pulse Toff[1] is set to take a first time length to increase from the reference voltage level to the preset voltage level Ref, then the second time length required for the timing pulse Toff[2] to increase from the reference voltage level to the preset voltage level Ref will be shorter than the first time length. In some embodiments, the second time length is the first time length minus the preset time length.
[0050] When the enable period EA[1] ends or the disable period DA[2] begins, the judgment circuit 137 starts to receive the falling signal Vfal corresponding to the disable period DA[2], and resets the voltage level of the judgment signal Vjud according to the falling signal Vfal, so that the adjustment pulse disappears or the voltage level of the judgment signal Vjud is at the disable level or the reference voltage level.
[0051] At time A2, when the disabled period DA[2] ends, the timing pulse Toff[2] has not yet reached the preset voltage level Ref (that is, the judgment circuit 137 receives the rising signal Vris corresponding to the enabled period EA[2], but has not yet detected that the timing pulse Toff[2] has increased to the preset voltage level Ref). Therefore, the judgment circuit 137 adjusts the voltage level of the judgment signal Vjud again to generate an adjustment pulse. It should be understood that the output period Pb[1] of the timing pulse Toff[1] and the output period Pb[2] of the timing pulse Toff[2] are the same in length.
[0052] During the enable period EA[2] immediately following the disable period DA[2], the timing pulse generation circuit 133 again increases the level rise slope of the timing pulse Toff[3] generated during the disable period DA[3] according to the adjustment pulse. Therefore, if the timing pulse Toff[2] is set to take a second time length to increase from the reference voltage level to the preset voltage level Ref, then the third time length required for the timing pulse Toff[3] to increase from the reference voltage level to the preset voltage level Ref will be shorter than the second time length. In some embodiments, the third time length is the second time length minus the preset time length.
[0053] When the enable period EA[2] ends or the disable period DA[3] begins, the judgment circuit 137 starts to receive the falling signal Vfal corresponding to the disable period DA[3], and resets the judgment signal Vjud according to the falling signal Vfal so that the adjustment pulse disappears or the voltage level of the control judgment signal Vjud is at the disable level or the reference voltage level.
[0054] Before the end of the disabled period DA[3] at time point A3, the timing pulse Toff[3] has reached the preset voltage level Ref (that is, the judgment circuit 137 has detected that the timing pulse Toff[3] has increased to the preset voltage level Ref before receiving the rising signal Vris corresponding to the enabled period EA[3]), so the judgment circuit 137 determines that there is no need to change or adjust the voltage level of the judgment signal Vjud, that is, the voltage level of the judgment signal Vjud will be maintained at the disabled level or the reference voltage level. It should be understood that the output period Pb[3] of the timing pulse Toff[3] will be shorter than the output period Pb[2] of the timing pulse Toff[2].
[0055] During the enable period EA[3] immediately following the disable period DA[3], the timing pulse generation circuit 133 will not receive the adjustment pulse generated by the judgment circuit 137. Therefore, the level rise slope of the timing pulse Toff[4] generated during the disable period DA[4] will not be adjusted or increased. If the timing pulse Toff[3] is set to take a third time length to increase from the reference voltage level to the preset voltage level Ref, then the timing pulse Toff[4] is set to take a fourth time length, which is the same as the third time length, to increase from the reference voltage level to the preset voltage level Ref.
[0056] Before time point A4 when the disabled period DA[4] ends, the timing pulse Toff[4] has reached the preset voltage level Ref (that is, the judgment circuit 137 has detected that the timing pulse Toff[4] has increased to the preset voltage level Ref before receiving the rising signal Vris corresponding to the enabled period EA[4]), so the judgment circuit 137 does not generate an adjustment pulse to the timing pulse generation circuit 133. It should be understood that the output period Pb[4] of the timing pulse Toff[4] and the output period Pb[3] of the timing pulse Toff[3] are the same in length. In addition, the operation of the judgment circuit 137 and the timing pulse generation circuit 133 during the enabled period EA[4] and thereafter can be deduced by analogy from their operation within the period TC[3], so it will not be described in detail here.
[0057] From the above Figure 1 and Figure 2 As can be seen from the description of the embodiment, the carrier frequency control circuit 13 is used to detect at least one enable period EA and at least one disable period DA of the input signal Vin, to generate at least one timing pulse Toff during the at least one disable period DA, and to control the carrier frequency generation circuit 11 to stop outputting the carrier frequency signal Vosi according to the at least one timing pulse Toff. If one of the at least one timing pulse Toff (e.g., timing pulse Toff[2]) does not increase to a preset voltage level Ref before entering the time point of one of the at least one enable period EA (e.g., time point A2 of entering the enable period EA[2]), the level rise slope of the next of the at least one timing pulse Toff (e.g., timing pulse Toff[3]) will be adjusted.
[0058] It should be understood that the carrier frequency control circuit 13 of this utility model is not... Figure 1 The circuit architecture shown is limited, and this will be discussed in the following paragraphs. Figure 3 Detailed explanation. Figure 3 This is another block diagram illustrating an isolated integrated circuit 100 according to some embodiments of the present invention.
[0059] At Figure 3 In one embodiment, the isolated integrated circuit 100 includes a carrier frequency control circuit 23, which replaces... Figure 1 The carrier frequency control circuit 13 in the middle. Compared to Figure 1 Carrier frequency control circuit 13 in the middle, Figure 3 The carrier frequency control circuit 23 also includes a clock counting circuit 139. Specifically, the clock counting circuit 139 is electrically coupled to the carrier frequency generation circuit 11, the edge detection circuit 131, and the timing pulse generation circuit 133, and is used to output an increment signal Vadd to control the timing pulse generation circuit 133 based on the carrier frequency signal Vosi, the frequency filtering signal Vtpl, at least one rising signal Vris, and at least one falling signal Vfal.
[0060] Figure 3 The connection and operation of the edge detection circuit 131, timing pulse generation circuit 133, switch control circuit 135, and judgment circuit 137 can be referred to in [the documentation / section]. Figure 1 The embodiments are described below. Therefore, the following will describe the combination. Figure 4 Detailed explanation of the operation of clock counting circuit 139. Figure 4 The illustrations are based on some embodiments of the present invention. Figure 3 Timing diagram of some signals related to the operation of the primary side circuit 10.
[0061] For clarity and ease of explanation, Figure 4 In this context, the number indexes [5] to [7] are used to refer to individual elements or signals, but this is not intended to limit the number of elements or signals to a specific number. If only the element or signal symbol is used without specifying the index of the element or signal symbol, it means that the element or signal symbol refers to any unspecified one in the group of elements or signals to which it belongs. For example, period TC refers to any unspecified one in periods TC [5] to TC [7].
[0062] At Figure 3In this embodiment, the clock counting circuit 139 determines that the disabled period DA[5] has not ended based on the fact that it has not yet received the rising signal Vris corresponding to the enable period EA[5] (or is still receiving the falling signal Vfal corresponding to the disabled period DA[5]), and determines the time point B5 when the timing pulse Toff[5] reaches the preset voltage level Ref based on the voltage level change of the frequency filtering signal Vtpl (i.e., the time point B5 when the falling edge of the timing pulse Toff[5] occurs). In this case, the clock counting circuit 139 starts counting the pulses in the carrier frequency signal Vosi at time point B5. Then, the clock counting circuit 139 determines the time point A5 when the disabled period DA[5] ends (or the time point A5 when the enable period EA[5] begins) based on the fact that it has received the rising signal Vris corresponding to the enable period EA[5] (or does not receive the falling signal Vfal corresponding to the disabled period DA[5]). In this case, the clock counting circuit 139 stops counting the pulses in the carrier frequency signal Vosi at time point A5. In short, the clock counting circuit 139 will obtain the number of pulses CONT of the carrier frequency signal Vosi between time point B5 when the timing pulse Toff[5] has a preset voltage level Ref and time point A5 when the enable period EA[5] begins.
[0063] As described above, the clock counting circuit 139 is also used to compare the number of pulses CONT of the carrier frequency signal Vosi with the threshold number N. In some embodiments, the number of pulses CONT corresponding to the disabled period DA[5] is not greater than the threshold number N. Therefore, during the enabled period EA[5], the clock counting circuit 139 controls the increment signal Vadd to be at the disabled level or the reference voltage level. The timing pulse generation circuit 133 receives the increment signal Vadd of the reference voltage level and determines that there is no need to change or adjust the level rise slope of the timing pulse Toff[6] to be generated during the disabled period DA[6]. If the timing pulse Toff[5] is set to take a fifth time length to increase from the reference voltage level to the preset voltage level Ref, then the timing pulse Toff[6] is set to take a sixth time length, which is the same as the fifth time length, to increase from the reference voltage level to the preset voltage level Ref.
[0064] During the disable period DA[6] immediately following the enable period EA[5], the clock counting circuit 139 receives a falling signal Vfal corresponding to the disable period DA[6]. In response to the receipt of the falling signal Vfal, the clock counting circuit 139 resets the number of pulses CONT of the carrier frequency signal Vosi and controls the increment signal Vadd to be at the reference voltage level. Furthermore, similar to the operation of the clock counting circuit 139 during the disable period DA[5], the clock counting circuit 139 acquires the number of pulses CONT of the carrier frequency signal Vosi between time point B6 when the timing pulse Toff[6] has a preset voltage level Ref and time point A6 when the enable period EA[6] begins. It should be understood that the output period Pb[5] of the timing pulse Toff[5] and the output period Pb[6] of the timing pulse Toff[6] are the same in length.
[0065] In some embodiments, the number of pulses CONT corresponding to the disabled period DA[6] is greater than the threshold number N. Therefore, during the enabled period EA[6], the clock counting circuit 139 changes or adjusts the voltage level of the increment signal Vadd, for example, by switching the increment signal Vadd from the disabled level to the enabled level, to generate an adjustment pulse (not shown). The timing pulse generation circuit 133 receives the adjustment pulse generated by the clock counting circuit 139 and reduces the level rise slope of the timing pulse Toff[7] to be generated during the disabled period DA[7] according to the adjustment pulse. If the timing pulse Toff[6] is set to take a sixth time length to increase from the reference voltage level to the preset voltage level Ref, then the seventh time length required for the timing pulse Toff[7] to increase from the reference voltage level to the preset voltage level Ref will be longer than the sixth time length. In some embodiments, the seventh time length is the sixth time length plus the preset time length.
[0066] The operation of the clock counter circuit 139 and the timing pulse generation circuit 133 during the disabled period DA[7] and the subsequent enabled period EA[7] can be deduced by analogy from their operation within the period TC[5], and therefore will not be elaborated here. It should be noted that, in Figure 4 In the embodiment, the number of pulses CONT of the carrier signal Vosi between the time point B7 when the timing pulse Toff[7] has a preset voltage level Ref and the time point A7 when the enable period EA[7] begins is not greater than the threshold number N. Furthermore, it should be understood that the output period Pb[7] of the timing pulse Toff[7] will be longer than the output period Pb[6] of the timing pulse Toff[6].
[0067] From the above Figure 3 and Figure 4As can be seen from the description of the embodiments, when one of the at least one timing pulse Toff (e.g., timing pulses Toff[5], Toff[6], or Toff[7]) has increased to a preset voltage level Ref before entering the time point of one of the at least one uniform energy period EA (e.g., time point A5, A6, or A7), the carrier frequency control circuit 23 is used to count the number of pulses CONT of the carrier frequency signal Vosi between the time point when one of the at least one timing pulse Toff has the preset voltage level Ref and the time point when entering the at least one uniform energy period EA (e.g., between time points B5 and A5, between time points B6 and A6, or between time points B7 and A7). Furthermore, when the number of pulses CONT is greater than the threshold number N, the level rise slope of the next of the at least one timing pulse Toff will be adjusted, for example, reduced.
[0068] In the above embodiments, the timing pulse generation circuit 133 generates a buffer pulse Ton and a timing pulse Toff to the switch control circuit 135 via a single signal (i.e., the frequency filtering signal Vtpl). However, the present invention is not limited thereto. In some embodiments, the timing pulse generation circuit 133 generates the buffer pulse Ton and the timing pulse Toff to the switch control circuit 135 via two independent signals. For example, when a falling signal Vfal is received, the timing pulse generation circuit 133 adjusts the voltage level of the first signal to generate the buffer pulse Ton. After the buffer pulse Ton is generated, the timing pulse generation circuit 133 adjusts the voltage level of the second signal to generate the timing pulse Toff.
[0069] Furthermore, the frequency filtering signal Vtpl of this invention is not based on... Figure 2 or Figure 4 The waveforms shown are for illustrative purposes only. In some embodiments, when the falling signal Vfal is received, the timing pulse generation circuit 133 adjusts the voltage level of the frequency filter signal Vtpl to generate the timing pulse Toff. In other words, the buffer pulse Ton is omitted.
[0070] Please see Figure 5 , Figure 5 The flowchart illustrates a modulation signal generation method 500 according to some embodiments of the present invention. In some embodiments, the modulation signal generation method 500 may be... Figure 1 or Figure 3 The isolated integrated circuit 100 performs this. For example... Figure 5 As shown, the modulation signal generation method 500 includes steps S501 to S504.
[0071] In step S501, the carrier frequency generation circuit 11 generates the carrier frequency signal Vosi.
[0072] In step S502, the carrier frequency control circuit 13 or 23 detects at least one enable period EA and at least one disable period DA of the input signal Vin. In some embodiments, the carrier frequency control circuit 13 or 23 detects the enable period EA and disable period DA of the input signal Vin through the edge detection circuit 131. The edge detection circuit 131 is used to output a rising signal Vris during the enable period EA of the input signal Vin and to output a falling signal Vfal during the disable period DA of the input signal Vin.
[0073] In step S503, during at least one disabled period DA, the carrier frequency control circuit 13 or 23 generates at least one timing pulse Toff and controls the carrier frequency generation circuit 11 to stop outputting the carrier frequency signal Vosi based on the at least one timing pulse Toff. In some embodiments, the timing pulse generation circuit 133 in the carrier frequency control circuit 13 or 23 adjusts the voltage level of the frequency filter signal Vtpl according to the falling signal Vfal to sequentially generate a buffer pulse Ton and a timing pulse Toff to the switch control circuit 135. The switch control circuit 135 controls the carrier frequency generation circuit 11 to stop outputting the carrier frequency signal Vosi during the output period of the timing pulse Toff based on the timing pulse Toff.
[0074] In step S504, the modulation circuit 15 outputs a modulation signal Vmod based on the input signal Vin and the carrier frequency signal Vosi. In some embodiments, the modulation circuit 15 controls the modulation signal Vmod to oscillate at the frequency of the carrier frequency signal Vosi based on the enable level input signal Vin (i.e., during the enable period EA of the input signal Vin), and controls the modulation signal Vmod to stop oscillating based on the disable level input signal Vin (i.e., during the disable period DA of the input signal Vin).
[0075] The remaining descriptions of steps S501 to S504 can be found in the description of the isolated integrated circuit 100 described above, and will not be repeated here.
[0076] As can be seen from the above embodiments of this utility model, the carrier frequency control circuit 13 or 23 of this utility model detects the enable period EA and disable period DA of the input signal Vin, and controls the carrier frequency generation circuit 11 to stop outputting the carrier frequency signal Vosi during the output period Pb of the timing pulse Toff during the disable period DA of the input signal Vin. Therefore, compared with related technologies that allow the oscillator to continuously output high-frequency signals, the isolated integrated circuit 100 and the modulation signal generation method 500 of this utility model have advantages such as lower overall circuit power consumption.
[0077] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
[0078] [Symbol Explanation]
[0079] 10: Primary circuit
[0080] 11: Carrier frequency generation circuit
[0081] 13,23: Carrier frequency control circuit
[0082] 15: Modulation circuit
[0083] 17: Buffer circuit
[0084] 19: Transmitting circuit
[0085] 20: Isolation circuit
[0086] 30: Secondary side circuit
[0087] 31: Receiving circuit
[0088] 33: Demodulation circuit
[0089] 100: Isolated Integrated Circuits
[0090] 131: Edge detection circuit
[0091] 133: Timing Pulse Generation Circuit
[0092] 135: Switch control circuit
[0093] 137: Determine the circuit
[0094] 139: Clock Counting Circuit
[0095] 500: Modulation signal generation method; A1, A2, A3, A4, A5, A6, A7, B5, B6, B7: Time point; CONT: Number of pulses.
[0096] DA: During the energy ban
[0097] EA: Enabling period; GND1: First ground voltage; GND2: Second ground voltage
[0098] N: Number of thresholds
[0099] Pb: Output period
[0100] Ref: Preset voltage level S501~S504: Steps
[0101] TC: Cycle
[0102] Toff: Timing Pulse
[0103] Ton: Buffer pulse
[0104] Vadd: Add signal VCC1: First power supply voltage VCC2: Second power supply voltage
[0105] Vfal: Decline signal
[0106] Vin: Input signal
[0107] Vjud: Judge signal
[0108] Vmod: Modulation signal
[0109] Vosi: Carrier frequency signal
[0110] Vout: Output signal
[0111] Vris: Rising Signal
[0112] Vtpl: Frequency filtering signal.
Claims
1. An isolated integrated circuit, characterized in that, Include: The primary circuit includes: Carrier frequency generation circuit, used to generate carrier frequency signal; A carrier frequency control circuit, electrically coupled to the carrier frequency generation circuit, is used to detect at least one active period and at least one inactive period of the input signal, to generate at least one timing pulse during the at least one inactive period, and to control the carrier frequency generation circuit to stop outputting the carrier frequency signal based on the at least one timing pulse. If one of the at least one timing pulses fails to increase to a preset voltage level before entering the time point of the at least one active period, the level rise slope of the next of the at least one timing pulses will be adjusted, and the next of the at least one active period is directly after the next of the at least one timing pulses. as well as A modulation circuit is electrically coupled to the carrier frequency generation circuit to receive the input signal and the carrier frequency signal, and to output a modulation signal based on the input signal and the carrier frequency signal. An isolation circuit is coupled to the primary circuit and used to transmit the modulation signal; as well as A secondary circuit, coupled to the isolation circuit, is used to generate an output signal based on the modulation signal, wherein the waveform of the output signal is substantially the same as the waveform of the input signal.
2. The isolated integrated circuit according to claim 1, characterized in that, The carrier frequency control circuit includes: An edge detection circuit is configured to output at least one rising signal during the at least one unblocking period and at least one falling signal during the at least one disabled period; A timing pulse generation circuit, electrically coupled to the edge detection circuit, is used to output a frequency filtering signal and to adjust the voltage level of the frequency filtering signal according to the at least one falling signal to generate the at least one timing pulse. A switch control circuit is electrically coupled to the carrier frequency generation circuit, the edge detection circuit, and the timing pulse generation circuit, for controlling the carrier frequency generation circuit to output the carrier frequency signal according to the at least one rising signal, and for controlling the carrier frequency generation circuit to stop outputting the carrier frequency signal during the output of the at least one timing pulse according to the at least one timing pulse. as well as The judgment circuit is electrically coupled to the edge detection circuit and the timing pulse generation circuit, and is used to output a judgment signal to control the timing pulse generation circuit based on the frequency filtering signal, the at least one rising signal and the at least one falling signal.
3. The isolated integrated circuit according to claim 2, characterized in that, The at least one rising signal includes a first rising signal corresponding to the at least one uniform energy period. If the first rising signal is received but the voltage level of the at least one timing pulse has not yet been detected to increase to the preset voltage level, the judgment circuit adjusts the voltage level of the judgment signal to generate an adjustment pulse, thereby controlling the timing pulse generating circuit to increase the rising slope of the next voltage level of the at least one timing pulse.
4. The isolated integrated circuit according to claim 3, characterized in that, In the at least one timing pulse, the pulse is set to take a first time length to increase to the preset voltage level, and in the next timing pulse, the pulse is set to take a second time length to increase to the preset voltage level, wherein the second time length is the first time length minus the preset time length.
5. The isolated integrated circuit according to claim 1, characterized in that, If, during the at least one timing pulse, the voltage level increases to the preset voltage level before the point in time during the at least one uniform energy period, the carrier frequency control circuit is further configured to count the number of pulses of the carrier frequency signal between the point in time during the at least one timing pulse when the voltage level is reached and the point in time during the at least one uniform energy period. When the number of pulses is greater than the threshold number, the level rise slope of the next pulse in the at least one timing pulse will be adjusted.
6. The isolated integrated circuit according to claim 5, characterized in that, The carrier frequency control circuit includes: An edge detection circuit is configured to output at least one rising signal during the at least one unblocking period and at least one falling signal during the at least one disabled period; A timing pulse generation circuit, electrically coupled to the edge detection circuit, is used to output a frequency filtering signal and to adjust the voltage level of the frequency filtering signal according to the at least one falling signal to generate the at least one timing pulse. A switch control circuit is electrically coupled to the carrier frequency generation circuit, the edge detection circuit, and the timing pulse generation circuit, for controlling the carrier frequency generation circuit to output the carrier frequency signal according to the at least one rising signal, and for controlling the carrier frequency generation circuit to stop outputting the carrier frequency signal during the output of the at least one timing pulse according to the at least one timing pulse. The judgment circuit is electrically coupled to the edge detection circuit and the timing pulse generation circuit, and is used to output a judgment signal to control the timing pulse generation circuit based on the frequency filtering signal, the at least one rising signal and the at least one falling signal. as well as A clock counting circuit is electrically coupled to the carrier frequency generation circuit, the edge detection circuit, and the timing pulse generation circuit, and is used to output an increasing signal to control the timing pulse generation circuit based on the carrier frequency signal, the frequency filtering signal, the at least one rising signal, and the at least one falling signal.
7. The isolated integrated circuit according to claim 6, characterized in that, The at least one rising signal includes a first rising signal corresponding to the at least one uniform energy period. If, in the case where the voltage level of the at least one timing pulse increases to the preset voltage level before the first rising signal is received, the clock counting circuit adjusts the voltage level of the increasing signal to generate an adjustment pulse in response to the pulse count being greater than the threshold count, thereby controlling the timing pulse generating circuit to reduce the rising slope of the next voltage level in the at least one timing pulse.
8. The isolated integrated circuit according to claim 7, characterized in that, In the at least one timing pulse, the pulse is set to take a first time length to increase to the preset voltage level, and in the next timing pulse, the pulse is set to take a second time length to increase to the preset voltage level, wherein the second time length is the first time length plus the preset time length.
9. The isolated integrated circuit according to claim 1, characterized in that, During the at least one disabled period, the carrier frequency control circuit is used to generate at least one buffer pulse and the at least one timing pulse, and to control the carrier frequency generation circuit to output the carrier frequency signal according to the at least one buffer pulse.
10. A carrier frequency control circuit, characterized in that, The carrier frequency control circuit is electrically coupled to the carrier frequency generation circuit to receive the input signal and includes: An edge detection circuit is configured to output at least a rising signal during at least a uniform energy period of the input signal, and to output at least a falling signal during at least a disabled energy period of the input signal; A timing pulse generation circuit, electrically coupled to the edge detection circuit, is used to output a frequency filtering signal and to adjust the voltage level of the frequency filtering signal according to the at least one falling signal to generate at least one timing pulse. A switch control circuit is electrically coupled to the carrier frequency generation circuit, the edge detection circuit, and the timing pulse generation circuit, for controlling the carrier frequency generation circuit to output a carrier frequency signal according to the at least one rising signal, and for controlling the carrier frequency generation circuit to stop outputting the carrier frequency signal during the output of the at least one timing pulse according to the at least one timing pulse. as well as The judgment circuit is electrically coupled to the edge detection circuit and the timing pulse generation circuit, and is used to output a judgment signal to control the timing pulse generation circuit based on the frequency filtering signal, the at least one rising signal, and the at least one falling signal. If one of the at least one timing pulses fails to increase to a preset voltage level before entering the time point of the at least one consistent energy period, the level rise slope of the next of the at least one timing pulses will be adjusted, and the next of the at least one consistent energy periods will be directly after the previous of the at least one timing pulses.