A multi-disk E3.S hard disk backboard and server
By adopting the GenZ 1C connector and I²C bus design, combined with the management chip and multiple MCIO interfaces, the problems of hard drive backplanes in adapting to new generation high-speed protocols and low space utilization have been solved, achieving high-density storage and efficient management.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHENZHEN TONGTAIYI INFORMATION TECH CO LTD
- Filing Date
- 2025-07-03
- Publication Date
- 2026-07-07
AI Technical Summary
Existing hard drive backplanes are difficult to design to accommodate next-generation high-speed protocols such as PCIe 5.0×4 and CXL 3.0, and have low space utilization, resulting in performance bottlenecks and insufficient storage density.
It adopts a GenZ 1C connector and I²C bus design, combined with a management chip and multiple MCIO interfaces to achieve high-density array layout and high-speed signal transmission. It supports next-generation protocols such as PCIe 5.0×4 and centrally manages the hard drive status through the management chip.
It significantly improves storage density, reduces signal transmission attenuation and crosstalk, supports efficient management and fault diagnosis, and adapts to the efficient management needs of high-density storage scenarios.
Smart Images
Figure CN224471998U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of server technology, specifically to a multi-bay E3.S hard drive backplane and server. Background Technology
[0002] With the deep integration of emerging technologies such as cloud computing, big data, the Internet of Things and artificial intelligence, the global data center industry is expanding at an exponential rate, and the demand for data storage is characterized by "massive, high-speed and diverse". As one of the core components of data center servers, hard drive backplanes play a key role in connecting storage media (such as NVMe SSDs) and the motherboard to realize signal transmission and management control. Their performance directly determines the storage density, transmission rate and expansion flexibility of the server, making it a core track for technological innovation.
[0003] Currently, mainstream server manufacturers still generally use the SFF-8639 interface for NVMe SSD expansion when designing hard drive backplanes. The SFF-8639 interface, by integrating SATA, SAS, and PCIe signal channels, has effectively promoted the standardized application of the NVMe protocol. However, the SFF-8639 is developed based on the PCIe 3.0 / 4.0 standard, and its differential signal bandwidth is difficult to adapt to new-generation high-speed protocols such as PCIe 5.0×4 and CXL 3.0, which can easily become a performance bottleneck when multiple drive bays are read and written concurrently. In addition, the SFF-8639 uses a large-size connector and requires independent debugging, management, and power space for each hard drive interface, making it difficult for the backplane to support more drive bays within a limited area. Utility Model Content
[0004] In view of the above problems, in a first aspect, this utility model embodiment provides a multi-bay E3.S hard drive backplane, the multi-bay E3.S hard drive backplane comprising: a backplane base;
[0005] Located on the first side surface of the back plate substrate:
[0006] Management chip;
[0007] A debugging interface is electrically interconnected with the management chip.
[0008] A mode selection interface, wherein the mode selection pin of the mode selection interface is electrically connected to the mode selection pin of the management chip;
[0009] I²C expansion interface, the I²C expansion interface is used to connect external I²C devices;
[0010] Multiple MCIO interfaces are distributed on both sides of the management chip, and the MCIO interfaces are used to receive external PCIe signals;
[0011] Located on the second side surface of the back plate substrate:
[0012] The array has multiple E3.S hard disk interfaces, wherein the MCIO interface is connected to the corresponding E3.S hard disk interface via PCIe differential signal traces, and the management chip is connected to the pins of the E3.S hard disk interface for hard disk status control and management via I²C bus signal traces. The E3.S hard disk interface uses a GenZ 1C connector.
[0013] In one possible implementation, the multi-bay E3.S hard drive backplane further includes:
[0014] Power input interface; the power input interface provides operating voltage for the management chip, the debugging interface, the mode selection interface and the I²C expansion interface.
[0015] In one possible implementation, the debugging interface, mode selection interface, I²C expansion interface, and power input interface are all located in the edge region of the first side surface of the backplane substrate; the management chip is located in the middle region of the first side surface.
[0016] In one possible implementation, the management chip is a field-programmable gate array (FPGA).
[0017] The general purpose input / output pins of the field programmable gate array are connected to the hard disk status indicator pins and hot-swap detection pins of each E3.S hard disk interface via signal traces.
[0018] In one possible implementation, the mode selection interface is a jumper switch socket.
[0019] In one possible implementation, there are 4 MCIO interfaces and 8 E3.S hard disk interfaces. The E3.S hard disk interfaces are arranged in a rectangular array, and each MCIO interface is directly connected to two E3.S hard disk interfaces through PCIe differential signal traces.
[0020] Secondly, embodiments of the present invention provide a server including a multi-bay E3.S hard drive backplane as described above.
[0021] In one possible implementation, the server further includes: a chassis body, the multi-bay E3.S hard drive backplane being installed within the chassis body, the chassis body having multiple hard drive modules for installing E3.S specification solid-state drives, the positions of the hard drive modules corresponding to the positions of the E3.S hard drive interfaces.
[0022] The above-described one or more technical solutions in the embodiments of this utility model have at least one or more of the following technical effects:
[0023] This embodiment of the invention provides a multi-bay E3.S hard drive backplane. The backplane features an array of E3.S hard drive interfaces on its second side, using GenZ 1C connectors. The compact size of the GenZ 1C connector significantly optimizes the backplane space layout, supporting more drive bays within the same area, thus significantly increasing storage density and meeting the high-capacity demands of data centers. Simultaneously, the high pin density of the GenZ 1C connector supports next-generation high-speed protocols such as PCIe 5.0×4, effectively reducing signal transmission attenuation and crosstalk, and ensuring the integrity of high-speed signals. Furthermore, a management chip connects to the pins of each E3.S hard drive interface via an I²C bus for hard drive status control and management. This allows for centralized control of backplane hard drive LED indicators and hot-swapping functionality. The electrical interconnection design between the debugging interface and the management chip simplifies the access process for external tools, supports real-time parameter configuration and rapid fault diagnosis, further adapting to the efficient management needs of high-density storage scenarios. The mode selection pin of the mode selection interface is directly connected to the management chip, providing flexible operating mode switching capabilities to adapt to the functional requirements of different application scenarios.
[0024] The above description is merely an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this utility model more obvious and understandable, specific embodiments of this utility model are given below. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 This is a schematic diagram of the structure of the first side surface of the multi-bay E3.S hard disk backplate in an embodiment of the present invention;
[0027] Figure 2 This is a schematic diagram of the structure of the second side surface of the multi-bay E3.S hard disk backplate in an embodiment of the present invention;
[0028] Figure 3 This is a front view of the server in an embodiment of the present invention.
[0029] Explanation of reference numerals in the attached diagram: 100, backplane base; 200, management chip; 300, debugging interface; 400, mode selection interface; 500, I²C expansion interface; 600, MCIO interface; 700, E3.S hard drive interface; 800, power input interface; 900, chassis body; 910, hard drive module; 920, left mounting bracket module; 930, right mounting bracket module. Detailed Implementation
[0030] To make the objectives, technical solutions, and advantages of this utility model clearer, the embodiments of this utility model will be described in further detail below with reference to the accompanying drawings.
[0031] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. In the following description, when referring to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this invention as detailed in the appended claims.
[0032] The overall concept of the technical solution provided by this utility model is as follows:
[0033] Please see Figures 1 to 2 The multi-bay E3.S hard drive backplane includes:
[0034] Backplane substrate 100; The core function of the backplane substrate 100 is to provide mechanical support for all electronic components on the backplane substrate 100 and to realize electrical interconnection between the components through the routing design of multi-layer PCB.
[0035] Provided on the first side surface of the back plate substrate 100:
[0036] Management chip 200; Management chip 200 is the core control unit of the hard drive backplane, responsible for comprehensive monitoring, management and control of the hard drive;
[0037] A debug interface 300 is electrically interconnected with the management chip 200. The debug interface 300 is a crucial channel for interaction between external maintenance tools and the internal management chip 200 on the backplane, undertaking core functions such as real-time monitoring, parameter configuration, fault diagnosis, and firmware upgrades. The selection of the debug interface 300 must consider versatility, compatibility, and high-speed requirements. Common types include JTAG interfaces, UART interfaces, and USB debug interfaces, with a JTAG interface being preferred.
[0038] In some embodiments, a CPLD (Complex Programmable Logic Device) chip is also provided on the backplane substrate 100. The CPLD chip usually undertakes the logic control functions of the backplane, such as signal routing, hot-swap timing management, status signal generation, etc. The debugging interface 300 can be connected to the CPLD chip, providing developers with the ability to debug the CPLD logic in real time, program it, and configure its parameters.
[0039] A mode selection interface 400 is provided, wherein the mode selection pin of the mode selection interface 400 is electrically connected to the mode selection pin of the management chip 200. The main function of the mode selection interface 400 is to provide the hard disk backplane with a variety of operating modes for selection and control, so as to meet the performance, power consumption, security and other requirements of different application scenarios. In some embodiments, the mode selection interface 400 can adopt a jumper switch socket (SW JP), and different circuit connections can be realized by changing the position of the jumper, thereby switching the working mode.
[0040] I²C expansion interface 500 is used to connect external I²C devices. It is understood that the I²C (Inter-Integrated Circuit) protocol is widely used for short-distance device communication due to its simplicity, low speed and multi-device compatibility. The number of I²C interfaces on the motherboard is usually limited (e.g., 1-2), while the backplane needs to connect external I²C devices. The I²C expansion interface 500 meets the I²C device access requirements by providing additional I²C bus channels.
[0041] Multiple sets of MCIO interfaces 600 are distributed on both sides of the management chip 200. The MCIO interfaces 600 are used to receive external PCIe signals. Preferably, the spacing between each MCIO interface 600 is not less than 16mm.
[0042] Provided on the second side surface of the back plate substrate 100:
[0043] The array includes multiple E3.S hard drive interfaces 700. The MCIO interface 600 is connected to the corresponding E3.S hard drive interface 700 via PCIe differential signal traces. The management chip 200 is connected to the pins of the E3.S hard drive interface 700 for hard drive status control and management via I²C bus signal traces. The E3.S hard drive interface 700 uses a GenZ 1C connector. GenZ 1C is a single-link high-speed connector standard launched by the Gen-Z Alliance (an open interconnect standards organization jointly established by technology giants such as Intel, AMD, Micron, and Western Digital). It is positioned as a "compact, high-bandwidth, multi-protocol compatible" interconnect solution. GenZ 1C focuses on high-speed data transmission in a single link, supporting mainstream protocols such as PCIe and CXL (Compute Express Link). The size of the GenZ 1C connector is only about 1 / 3 of the traditional SFF-8639 interface, making it suitable for high-density array layouts. Furthermore, the GenZ 1C connector supports PCIe... E3.S supports 5.0×4 (32GT / s), CXL 3.0 (128GT / s), and future evolved Gen-Z protocols (such as Gen-Z 2.0), adapting to scenarios such as AI training and big data analysis. E3.S is a next-generation storage interface standard, supporting higher data transfer rates and a more compact physical size, suitable for high-density storage applications. Multiple E3.S hard drive interfaces 700 are arranged in an array on the second side surface of the backplane substrate 100. This layout maximizes the use of backplane space and improves storage density. The MCIO interface 600 connects to the E3.S hard drive interface 700 via PCIe differential signal traces, ensuring the stability and integrity of high-speed data transfer. The management chip 200 connects to the status control and management pins of the E3.S hard drive interface 700 via I²C bus signal traces, enabling real-time monitoring and management of the hard drive. The E3.S hard drive interface 700 uses a GenZ 1C connector, which supports high-speed protocols such as PCIe 5.0, providing higher data transfer rates. Compared to traditional connectors, the GenZ 1C connector is smaller in size, which helps to improve the integration and space utilization of the backplane. The GenZ 1C connector is designed for high-density, high-bandwidth storage applications and has higher connection reliability and durability.
[0044] The E3.S hard drive interfaces 700, arranged in an array on the second side of the backplane, utilize GenZ 1C connectors. The compact size of the GenZ 1C connector significantly optimizes backplane space layout, supporting more drive bays within the same area, thus greatly increasing storage density and meeting the high-capacity demands of data centers. Simultaneously, the high pin density of the GenZ 1C connector supports next-generation high-speed protocols such as PCIe 5.0×4, effectively reducing signal transmission attenuation and crosstalk, and ensuring the integrity of high-speed signals. Furthermore, the management chip 200 connects to the pins of each E3.S hard drive interface 700 via the I²C bus for hard drive status control and management. This allows for centralized control of backplane hard drive LED indicators and hot-swapping functionality. The electrical interconnection design between the debug interface 300 and the management chip 200 simplifies the external tool access process, supports real-time parameter configuration and rapid fault diagnosis, further adapting to the efficient management needs of high-density storage scenarios. The mode selection pin of the mode selection interface 400 is directly connected to the management chip 200, providing flexible operating mode switching capabilities to adapt to the functional requirements of different application scenarios.
[0045] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0046] Please see Figure 1 The multi-bay E3.S hard drive backplate also includes:
[0047] A power input interface 800 provides operating voltage to the management chip 200, the debug interface 300, the mode selection interface 400, and the I²C expansion interface 500. The power input interface 800 is responsible for introducing external power to the backplane and providing operating voltage to all electronic components on the backplane.
[0048] Please see Figure 1The debugging interface 300, mode selection interface 400, I²C expansion interface 500, and power input interface 800 are all located in the edge area of the first side surface of the backplane substrate 100; the management chip 200 is located in the middle area of the first side surface. The management chip 200, located in the middle area of the first side surface, serves as the core control unit of the entire system, responsible for coordinating and managing all functional modules. The management chip 200's central location effectively shortens the signal transmission path with various interfaces and components, reducing signal delay and loss. Simultaneously, the middle area typically has better heat dissipation conditions, more effectively dissipating the heat generated by the management chip 200. The debugging interface 300, mode selection interface 400, I²C expansion interface, and power input interface 800 are all located in the edge area of the first side surface of the backplane substrate 100, facilitating external connections and signal transmission.
[0049] In some embodiments, the management chip 200 is a field-programmable gate array (FPGA); a field-programmable gate array (FPGA) is a highly flexible programmable logic device that can be hardware programmed as needed to achieve specific functions;
[0050] The general purpose input / output (PPO) pins of the field-programmable gate array (FPGA) are connected via signal traces to the hard drive status indicator pins and hot-swap detection pins of each E3.S hard drive interface 700. The FPGA is connected via PPO pins to the hard drive status indicator pins of each E3.S hard drive interface 700 to control the status of the LEDs; for example, a green LED indicates normal operation, a yellow LED indicates a warning, and a red LED indicates a fault. The FPGA is also connected via PPO pins to the hot-swap detection pins of each E3.S hard drive interface to detect the hot-swap status of the hard drive.
[0051] Please see Figure 1 and Figure 2 The system comprises four MCIO interfaces 600 and eight E3.S hard disk interfaces 700, arranged in a rectangular array. Each MCIO interface 600 is directly connected to two E3.S hard disk interfaces 700 via PCIe differential signal traces. This efficient resource utilization and avoidance of interface resource waste, combined with the eight E3.S hard disk interfaces 700, provides a high-density storage solution to meet the demands of massive data storage.
[0052] This utility model embodiment also provides a server, including a multi-bay E3.S hard drive backplane as described in the foregoing embodiments. Various variations and specific embodiments in the foregoing embodiments are also applicable to the server in this embodiment. Through the foregoing detailed description of a multi-bay E3.S hard drive backplane, those skilled in the art can clearly understand the implementation method of the server in this embodiment. For the sake of brevity, it will not be described in detail here.
[0053] For further details, please refer to Figure 3 The server also includes: a chassis body 900, the multi-bay E3.S hard drive backplane being installed inside the chassis body 900, and the chassis body 900 having multiple hard drive modules 910 for installing E3.S specification solid-state drives. The positions of the hard drive modules 910 correspond to the positions of the E3.S hard drive interfaces 700. The chassis body 900 provides robust physical support for all internal components of the server, while the hard drive modules 910 are used to install E3.S specification solid-state drives, providing mechanical support and electrical connections. The positions of the hard drive modules 910 correspond one-to-one with the E3.S hard drive interfaces on the E3.S hard drive backplane, ensuring that each hard drive module 910 can be correctly connected to the corresponding hard drive interface.
[0054] For further details, please refer to Figure 3 The chassis body 900 has a left mounting ear module 920 and a right mounting ear module 930 on its left and right sides, respectively. As can be understood, mounting ear modules are common components in server chassis design, mainly used for server installation, fixation and transportation. For example, the mounting ear modules can be fixed to the guide rails or mounting posts of a standard rack by means of screws, clips and other methods.
[0055] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.
[0056] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this utility model without departing from the spirit and scope of the embodiments of this utility model. Therefore, if these modifications and variations to the embodiments of this utility model fall within the scope of the claims of this utility model and their equivalents, then this utility model also intends to include these modifications and variations.
Claims
1. A multi-bay E3.S hard drive backplane, characterized in that, include: Backing substrate; Located on the first side surface of the back plate substrate: Management chip; A debugging interface is electrically interconnected with the management chip. A mode selection interface, wherein the mode selection pin of the mode selection interface is electrically connected to the mode selection pin of the management chip; I²C expansion interface, the I²C expansion interface is used to connect external I²C devices; Multiple MCIO interfaces are distributed on both sides of the management chip, and the MCIO interfaces are used to receive external PCIe signals; Located on the second side surface of the back plate substrate: The array has multiple E3.S hard disk interfaces, wherein the MCIO interface is connected to the corresponding E3.S hard disk interface via PCIe differential signal traces, and the management chip is connected to the pins of the E3.S hard disk interface for hard disk status control and management via I²C bus signal traces. The E3.S hard disk interface uses a GenZ 1C connector.
2. The multi-bay E3.S hard drive backplane according to claim 1, characterized in that, Also includes: Power input interface; The power input interface provides operating voltage to the management chip, the debugging interface, the mode selection interface, and the I²C expansion interface.
3. The multi-bay E3.S hard drive backplane according to claim 2, characterized in that, The debugging interface, mode selection interface, I²C expansion interface, and power input interface are all located on the edge area of the first side surface of the backplane substrate; the management chip is located in the middle area of the first side surface.
4. The multi-bay E3.S hard drive backplane according to claim 1, characterized in that, The management chip is a field-programmable gate array; The general purpose input / output pins of the field programmable gate array are connected to the hard disk status indicator pins and hot-swap detection pins of each E3.S hard disk interface via signal traces.
5. A multi-bay E3.S hard drive backplane according to claim 1, characterized in that, The mode selection interface is a jumper switch socket.
6. The multi-bay E3.S hard drive backplane according to claim 1, characterized in that, The number of MCIO interfaces is 4, and the number of E3.S hard disk interfaces is 8. The E3.S hard disk interfaces are arranged in a rectangular array, and each MCIO interface is directly connected to two E3.S hard disk interfaces through PCIe differential signal traces.
7. A server, characterized in that, Including a multi-bay E3.S hard drive backplane as described in any one of claims 1-6.
8. A server according to claim 7, characterized in that, Also includes: The chassis body has the multi-bay E3.S hard drive backplate installed inside it. The chassis body has multiple hard drive modules for installing E3.S solid-state drives, and the positions of the hard drive modules correspond to the positions of the E3.S hard drive interfaces.