An IGBT device with high short circuit capability

Abstract

A kind of high short-circuit capability IGBT device, including trench on N type substrate, the P type trap region is below the trench outside, the conductive channel of the IGBT device is located in P trap type region near the side wall of trench, when the device gate applies voltage and makes the device open, the width of each channel in vertical direction remains consistent, the error value of channel width does not exceed the maximum error value set.The high short-circuit capability IGBT device of the utility model, inhibits the appearance of device short channel effect, reduces the saturation current of device, improves short-circuit capability, simultaneously, because P type trap region average concentration is higher than traditional structure, therefore, bulk region resistance reduces, and the anti-latch-up capability of device is improved.

Description

Technical Field

[0001] This utility model belongs to the field of integrated circuit technology, and relates to integrated circuit device technology, specifically to an IGBT device with high short-circuit capability and its manufacturing method. Background Technology

[0002] An IGBT (Insulated Gate Bipolar Transistor) is a composite, fully controllable, voltage-driven power semiconductor device composed of a BJT (Bipolar Junction Transistor) and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). It combines the advantages of the high input impedance of a MOSFET and the low on-state voltage drop of a BJT. It is ideally suited for applications in converter systems with DC voltages of 600V and above, such as AC motors, frequency converters, switching power supplies, lighting circuits, and traction drives.

[0003] In industrial applications, IGBT devices typically require a certain short-circuit capability to provide sufficient time for protection circuits to turn them off. During this period of complete turn-off (usually several microseconds), the device must simultaneously withstand the electrical stress of high voltage and high current. The losses generated by the high voltage and high current cause the IGBT device temperature to rise rapidly. If the IGBT device is not designed with short-circuit capability, it will be damaged and fail before it can be turned off under short-circuit conditions.

[0004] With the continuous development of IGBT technology, trench gate IGBTs have gradually become the mainstream. Compared with planar structures, trench gate structures use conductive channels perpendicular to the chip surface, which greatly increases the channel density. At the same time, due to the absence of the JFET effect, the saturation voltage drop and conduction loss of the device are significantly reduced. However, the negative impact is the increased saturation current density and a significant decrease in the short-circuit capability of the device.

[0005] To improve the short-circuit capability of trench IGBT devices, current research focuses on suppressing the short-channel effect. For example, in Chinese patent application CN 202110167453.3, a second gate structure is added between the traditional trench gate and emitter to increase the channel length and avoid the short-channel effect. This additional gate structure increases the channel length, reduces the device's saturation current density, and improves the device's short-circuit resistance. Another example is Chinese patent application CN202010302854.0, which designs the device cell structure as a composite structure of a planar channel and a trench to avoid the short-channel effect. This allows the conductive current to pass through both the planar and vertical channels simultaneously, thereby increasing the channel length.

[0006] In trench IGBT technology, the P-type well region is formed through a single boron implantation followed by high-temperature (typically exceeding 1000℃) and long-term junction push-out. Boron ions within the well region diffuse to form a Gaussian distribution, resulting in a significant concentration gradient in the vertical direction. Typically, the boron ion concentration is high near the chip surface (emitter side) and low near the bottom of the well. When the device is turned on, the channel is narrower where the boron ion concentration is high and wider where it is low, resulting in a funnel-shaped channel. This makes matching the junction depth to device performance difficult: too shallow a depth (short channel length) easily leads to short-channel effects, resulting in high saturation current and low short-circuit capability; too deep a depth enhances short-circuit capability but significantly increases saturation voltage drop, conduction losses, and, because the peak electric field is closer to the bottom of the trench, the breakdown voltage drops significantly. Simultaneously, the increased base resistance Rb of the parasitic transistor reduces the device's latch-up resistance.

[0007] In Chinese patent application CN 202110167453.3, the addition of a second trench increases the complexity of the device structure, requiring at least one additional trench lithography step, thus raising manufacturing costs. In Chinese patent application CN202010302854.0, a composite structure is used, incorporating both planar and trench gates. This results in a larger cell size, which is detrimental to increasing channel density. Utility Model Content

[0008] In view of the deficiencies of the existing technology, this utility model discloses an IGBT device with high short-circuit capability.

[0009] The high short-circuit capability IGBT device of this invention includes a trench on an N-type substrate, a P-type well region below the outside of the trench, and a channel extending downward from the upper surface of the P-type well region near the trench. The deviation Q of the projected area of ​​the channel in the vertical direction at various heights is less than QA, where QA is a set vertical projection deviation threshold, Q=A(H) / AM, AM is the maximum projected area of ​​the channel in the vertical direction, A(H) is the projected area of ​​the channel at height H, and QA is not greater than 10%.

[0010] Preferably, a gate oxide layer is disposed on the inner wall of the trench, and the trench is filled with a polysilicon gate; the P-type well region includes a covered region with an emitter heavily doped region above it and an uncovered region without an emitter heavily doped region, a dielectric layer is disposed above the emitter heavily doped region, an emitter metal layer is disposed above the dielectric layer, and the emitter metal layer extends downward around it and forms an electrical connection with the uncovered region of the P-type well region.

[0011] Preferably, the formed channel projects vertically into a ring shape with a uniform width that surrounds the P-shaped trap region.

[0012] This utility model also discloses a method for manufacturing a high short-circuit capability IGBT device, including the following steps:

[0013] Step 1. Form trenches perpendicular to the substrate surface on the N-type substrate 1 by etching;

[0014] Step 2. A gate oxide layer is formed on the upper surface of the N-type substrate where the trench is formed by oxidation;

[0015] Step 3. Form a polysilicon layer above the gate oxide layer inside the trench as a polysilicon gate;

[0016] Step 4. Ion implantation is used to form a P-type well region around the trench above the N-type substrate;

[0017] Ion implantation forms a P-type well region through multiple implantations. The energy during each implantation causes the effective channel intervals of each implantation to connect or overlap. The effective channel interval B2 refers to the channel depth range between the peak concentration T and T*(1-S) of the ion implantation near the trench in the P-type well region, where S is the maximum error value of the set peak concentration.

[0018] The number of injections N1 = B1 / B2 rounded down, where B1 is the total channel depth;

[0019] Step 5. Form an N-type emitter heavily doped region 5 above the P-type well region 4; complete the ion activation of the P-type well region and the annealing of the emitter heavily doped region;

[0020] Step 6. Deposit a dielectric layer 6 above the emitter-heavily doped region and the channel;

[0021] Step 7. Form a contact hole down to the P-type well region 4 at the edge of the dielectric layer 6, so that the area from the bottom of the edge of the dielectric layer 6 to the top of the edge of the P-type well region 4 is etched.

[0022] Step 8. An emitter metal layer 7 is formed by deposition at the edge of the dielectric layer and the P-type well region 4 not covered by the dielectric layer; the boundary of the emitter metal layer is electrically connected to the periphery of the P-type well region 4 after etching in step 7, thus forming a complete IGBT structure.

[0023] Preferably, step 1 specifically involves: firstly, forming a hard mask on an N-type substrate using a thermal oxidation or thin film process; then, using photolithography and etching processes to etch the hard mask and the N-type substrate to form trenches, and finally removing the hard mask.

[0024] Preferably, step 3 specifically involves depositing a polysilicon layer on top of the gate oxide layer, and then using photolithography and etching processes to etch away the polysilicon layer in areas other than the trench, leaving only the polysilicon layer inside the trench.

[0025] Preferably, in step 4, the implanted ions are boron ions, and in step 5, ion activation and annealing of the emission-heavily doped region are performed simultaneously at a temperature of 900-980 degrees Celsius.

[0026] The high short-circuit capability IGBT device described in this invention, compared with the traditional horn channel, suppresses the short-channel effect of the device, reduces the saturation current of the device, and improves the short-circuit capability. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a specific embodiment of the high short-circuit capability IGBT device of this utility model;

[0028] Figure 2 This is a schematic diagram of a specific embodiment of step 1 in the preparation method of this utility model;

[0029] Figure 3 This is a schematic diagram of a specific embodiment of step 2 in the preparation method of this utility model;

[0030] Figure 4 This is a schematic diagram of a specific embodiment of step 3 in the preparation method of this utility model;

[0031] Figure 5 This is a schematic diagram of a specific embodiment of step 4 in the preparation method of this utility model;

[0032] Figure 6 This is a schematic diagram of a specific embodiment of step 5 in the preparation method of this utility model;

[0033] Figure 7 This is a schematic diagram of a specific embodiment of step 6 in the preparation method of this utility model;

[0034] Figure 8 This is a schematic diagram of a specific embodiment of step 7 in the preparation method of this utility model;

[0035] Figure 9 This is a schematic diagram showing the boron ion concentration distribution in the P-type well channel of the high short-circuit capability IGBT device of this invention compared with that obtained by conventional methods.

[0036] Figure 10 This is a schematic diagram showing the distribution of boron ion concentration with channel depth formed by five implantations in a specific fabrication method of the high short-circuit capability IGBT device of this utility model.

[0037] Figure 11This is a schematic diagram showing the change of collector current with base-collector voltage between the high short-circuit capability IGBT device described in this utility model and the IGBT device prepared by existing conventional methods.

[0038] The figures are labeled as follows: 1-substrate, 2-gate oxide layer, 3-polysilicon gate, 4-P-type well region, 5-heavily doped emitter region, 6-dielectric layer, 7-emitter metal layer, 8-channel. Detailed Implementation

[0039] To more intuitively and clearly describe the specific details of the technical solution of this utility model, a detailed description will be provided below in conjunction with specific embodiments and example drawings.

[0040] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions of this utility model will be clearly and completely described below in conjunction with specific embodiments. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0041] The manufacturing method of the IGBT device with high short-circuit capability described in this utility model includes the following steps:

[0042] Step 1. Trenches perpendicular to the substrate surface are formed on the N-type substrate 1 by etching; the trench depth is 4.0um~6.0um;

[0043] This step can first use thermal oxidation or thin film processes to form a hard mask on an N-type substrate, and then use photolithography and etching processes to etch the hard mask and the N-type substrate to form trenches; and then remove the hard mask.

[0044] Step 2. A gate oxide layer is formed on the upper surface of the N-type substrate where the trench is formed by oxidation;

[0045] Step 3. A polysilicon layer is deposited on top of the gate oxide layer. Then, photolithography and etching processes are used to etch away the polysilicon layer in areas other than the inside of the trench, leaving only the polysilicon layer inside the trench.

[0046] Step 4. Ion implantation is used to form a P-type well region 4 around the trench above the N-type substrate;

[0047] The formation of a P-type well region by ion implantation involves multiple implantations, with each subsequent implantation using 30%-70% of the energy of the previous implantation; the total number of implantations is no less than 5; the ion implanted into the P-type well region is boron.

[0048] For example, if the number of ion implantations is 5:

[0049] The initial injection dose was 4.0E12 / cm². 2 ~10.0E12 / cm 2 The energy is 700keV~1000keV;

[0050] The second injection dose was 4.0E12 / cm². 2 ~10.0E12 / cm 2 The energy is 400keV~600keV;

[0051] The third injection dose was 4.0E12 / cm². 2 ~10.0E12 / cm 2 The energy is 200keV~400keV;

[0052] The fourth injection dose was 4.0E12 / cm³. 2 ~10.0E12 / cm 2 The energy is 100keV~200keV;

[0053] The fifth injection dose was 4.0E12 / cm³. 2 ~10.0E12 / cm 2 The energy is 30keV~100keV;

[0054] After five implantations, boron ion activation is required. This activation can be performed at the end of this step or after the emitter-heavily doped region is formed in step 5. Since the annealing temperature of the emitter-heavily doped region and the boron ion activation temperature are both 900-980 degrees Celsius, boron ion implantation activation and annealing of the emitter-heavily doped region can be performed simultaneously at 900-980 degrees Celsius after step 5, for a time of 10 to 100 minutes. In this embodiment, the final junction depth of the P-type well region is 2.0 to 3.0 μm.

[0055] The injection energy is related to the injection depth. For example, for a P-type well region with a depth of 3 micrometers, the injection energy is 700 keV to 1500 keV when the maximum concentration is formed at the deepest point.

[0056] To ensure uniform concentration in the channel, a maximum allowable error value of S is set for the concentration deviation in the channel. After each injection, the concentration distribution with channel depth near the sidewall of the P-type well region is as follows: Figure 10 As shown, the depth range between the concentration peak T and T*(1-S) is B2, then the number of injections N1=B1 / B2, where B1 is the total channel depth;

[0057] For example, with a channel depth B1 of 3 micrometers, a maximum allowable error S of 20%, and an ion implantation dose of 4.0 E12 / cm², the appropriate dose is... 2~10.0E12 / cm 2 When the depth range between the concentration peak T and 0.9T is B2 = 700 nm, the number of injections N = B1 / B2, which is 5 after rounding. In this invention, the maximum allowable error S is generally 5% to 25%, and can usually be controlled within 20%.

[0058] The energy at each implantation causes the effective channel intervals of each implantation to connect or overlap. The effective channel interval refers to the depth range between the peak ion implantation concentration T and 0.9T at the junction of the P-type well region and the trench. For example, for a channel depth of 3 micrometers, the five implantation energies are 700keV~1000keV, 400keV~700keV, 200keV~400keV, 100keV~200keV, 70keV~100keV, and 30keV~70keV, respectively. The effective channel intervals of the five implantations are approximately 2400-3000 nm, 1800-2400 nm, 1200-1800 nm, 650-1300 nm, and 0-700 nm, respectively. The boundaries of the five effective channel intervals connect or overlap. Figure 10 As shown.

[0059] By varying the implantation energy, after five implantations, when the IGBT device is in the on-state, the resulting channel width is uniformly distributed from top to bottom in the height direction, with a rectangular cross-section. For those skilled in the art, a channel refers to a region with a doping concentration higher than a set value, typically defined as a region where the ion implantation concentration is greater than a certain value. In this embodiment, the channel can be defined as a region with a concentration greater than T*(1-S), where T is the peak concentration. Through multiple implantations, the ion implantation concentration is made greater than T*(1-S). Ideally, the channel region's vertical projection forms a ring with a consistent width surrounding the P-type well region, i.e., a ring with a consistent thickness around the P-type well region. In contrast, with traditional single implantation processes, the channel shape is trumpet-shaped.

[0060] In this invention, after multiple injections, the ideally formed channel is cylindrical. In the actual fabrication process, the deviation Q of the projected area of ​​the channel in the vertical direction at various heights is less than QA, where QA is a set vertical projection deviation threshold, Q = A(H) / AM, AM is the maximum projected area of ​​the channel in the vertical direction, and A(H) is the projected area of ​​the channel at height H. QA is generally no greater than 10%. Simultaneously, by using multiple injections, the channel depth of this invention can be significantly improved compared to existing technologies, reaching over 70% of the depth of the P-type well region, and ideally approaching 100%, i.e., penetrating the entire depth of the P-type well region.

[0061] To facilitate calculation and simplify the process, the injection dose is preferably related to the peak concentration for each injection. To keep the peak concentrations basically the same, the injection dose can preferably be set to a decreasing dose compared to the previous injection as the injection energy decreases.

[0062] Step 5. Above the P-type well region 4, an N-type emitter heavily doped region 5 is formed using existing semiconductor processes such as photolithography, etching, and implantation;

[0063] Step 6. A dielectric layer 6 is deposited above the emitter heavy doping region and the channel. The dielectric layer 6 is generally silicon oxide and is the same material as the gate oxide layer formed in step 2.

[0064] Step 7. Form a contact hole extending down to the P-type well region 4 at the edge of the dielectric layer 6, such that the area below the edge of the dielectric layer 6 and above the edge of the P-type well region 4 is etched.

[0065] Step 8. An emitter metal layer 7 is formed by deposition at the edge of the dielectric layer and the P-type well region 4 not covered by the dielectric layer; the boundary of the emitter metal layer is electrically connected to the periphery of the P-type well region 4 after etching in step 7, thus forming a complete IGBT structure.

[0066] like Figure 1 As shown, the final IGBT structure obtained in this application includes a trench on an N-type substrate, a gate oxide layer on the inner wall of the trench, a polysilicon gate filled in the trench, and a P-type well region outside the trench. The conductive channel of the IGBT device is located in the P-well region near the sidewall of the trench. When a voltage is applied to the device gate to turn on the device, ideally, the width of the channel is consistent in all vertical directions. The P-type well region near the trench has a channel formed by ion implantation. The depth of the channel extends through the entire P-type well region. The deviation Q of the projected area of ​​the channel in the vertical direction at various heights is less than QA, where QA is a set vertical projection deviation threshold, Q=A(H) / AM, AM is the maximum projected area of ​​the channel in the vertical direction, and A(H) is the projected area of ​​the channel at height H.

[0067] The P-type well region includes a covered region with a heavily doped emitter region above it and an uncovered region without a heavily doped emitter region. A dielectric layer is located above the heavily doped emitter region, and an emitter metal layer is located above the dielectric layer. The emitter metal layer extends downward around the surface and forms an electrical connection with the uncovered region of the P-type well region.

[0068] This invention reduces the device saturation current by suppressing the short-channel effect, such as... Figure 11 As shown, compared with the prior art, under the same base-collector voltage, the collector current of this invention is significantly reduced, improving short-circuit capability and enhancing the device's latch-up resistance.

[0069] The foregoing descriptions are preferred embodiments of this utility model. Unless there is a clear contradiction between the preferred embodiments or a prerequisite for a particular preferred embodiment, the preferred embodiments can be arbitrarily combined and used. The embodiments and specific parameters described are only for clearly illustrating the utility model verification process of the inventor and are not intended to limit the patent protection scope of this utility model. The patent protection scope of this utility model is still subject to its claims. Similarly, any equivalent structural changes made based on the content of this utility model's specification should also be included within the protection scope of this utility model.

Claims

1. An IGBT device with high short-circuit capability, characterized in that, The system includes a trench on an N-type substrate, with a P-type well region below the outside of the trench. Near the trench, the P-type well region has a channel extending downward from the upper surface of the P-type well region. The vertical projection area of ​​the channel deviates by Q at various heights, where QA is a set vertical projection deviation threshold, Q = A(H) / AM, AM is the maximum vertical projection area of ​​the channel, A(H) is the channel projection area at height H, and QA is not greater than 10%.

2. The IGBT device with high short-circuit capability as described in claim 1, characterized in that, A gate oxide layer is disposed on the inner wall of the trench, and the trench is filled with a polysilicon gate. The P-type well region includes a covered region with an emitter heavily doped region above it and an uncovered region without an emitter heavily doped region. A dielectric layer is disposed above the emitter heavily doped region, and an emitter metal layer is disposed above the dielectric layer. The emitter metal layer extends downward around it and forms an electrical connection with the uncovered region of the P-type well region.

3. The IGBT device with high short-circuit capability as described in claim 1, characterized in that, The resulting channel projects vertically into a ring of uniform width that surrounds the P-shaped trap region.

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