Chip package structure, memory, and electronic device
By arranging the main control chip within the insulating support layer and connecting it using multiple wiring layers, and stacking the chipset in a staggered manner, the problems of poor soldering and excessive thickness in the chip packaging structure are solved, achieving thinner and more efficient signal transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BIWIN STORAGE TECH CO LTD
- Filing Date
- 2025-08-15
- Publication Date
- 2026-07-07
Smart Images
Figure CN224473695U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of chip packaging technology, and in particular to chip packaging structures, memory, and electronic devices. Background Technology
[0002] Common chip packaging structures in existing chips include: Figure 1 As shown, the main control chip and multiple flash memory chips are interconnected by wiring on the substrate. Due to the limited free area on the substrate excluding the flip-chip main control chip, the multiple flash memory chips are arranged in an alternating stacking manner on the substrate; each flash memory chip is connected to the substrate by bonding wires.
[0003] However, existing chip packaging structures have many drawbacks: on the one hand, thermal stress can easily cause poor soldering when the bumps of the main control chip are interconnected with the substrate, which can easily lead to internal signal transmission failures when the finished product is in use; on the other hand, the stacking of flash memory chips results in an excessively thick finished product, and the bonding wires in some parts are too long, which can easily cause inconvenience in product installation and use. Utility Model Content
[0004] The technical problem to be solved by this utility model is to provide a chip packaging structure, memory and electronic equipment, reduce the thickness of the finished product and the length of the bonding wire, and eliminate the risk of poor soldering.
[0005] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows:
[0006] The chip packaging structure includes an insulating support layer, a main control chip, and a chipset;
[0007] The main control chip is disposed within the insulating support layer. The top surface of the insulating support layer is provided with a first wiring layer, and the bottom surface of the insulating support layer is provided with a second wiring layer.
[0008] The main control chip is electrically connected to the second wiring layer, and at least two sets of the chip groups are horizontally laid on the first wiring layer. The chip groups are electrically connected to the first wiring layer, and the first wiring layer is electrically connected to the second wiring layer.
[0009] Furthermore, the chipset includes at least two sub-chipsets that are stacked in a staggered manner;
[0010] The sub-chip group has bonding points in a position not obscured by other adjacent sub-chip groups, and the sub-chip group is electrically connected to the first rewiring layer through the bonding points.
[0011] Furthermore, all of the sub-chipsets are stacked in a stepped manner;
[0012] The sub-chipset includes one or two memory chips, with the two memory chips in the same sub-chipset overlapping, the chip pad pins of the upper memory chip facing upwards, and the chip pad pins of the lower memory chip facing downwards.
[0013] Furthermore, the sub-chipset includes two staggered stacked memory chips, each of which has a bonding point, and the memory chip is electrically connected to the first redistribution layer through the bonding point.
[0014] Furthermore, the first wiring layer is provided with bumps, and the bumps are electrically connected to the bonding points one by one.
[0015] Furthermore, the first rewiring layer is provided with an insulating protective layer covering all of the chipsets.
[0016] Furthermore, the insulating support layer is provided with insulating channels;
[0017] The first wiring layer is electrically connected to the second wiring layer through the insulating channel.
[0018] Furthermore, the insulating support layer is a plastic-encapsulated structure with the second rewiring layer as the base.
[0019] To solve the above-mentioned technical problems, another technical solution adopted by this utility model is as follows:
[0020] The memory includes a motherboard and the aforementioned chip package structure, wherein the chip package structure is disposed on the motherboard.
[0021] To solve the above-mentioned technical problems, another technical solution adopted by this utility model is as follows:
[0022] An electronic device includes the aforementioned memory.
[0023] The beneficial effects of this utility model are as follows: It provides a chip packaging structure, memory, and electronic device, and sets up an insulating support layer with a first wiring layer and a second wiring layer. The main control chip is arranged in the insulating support layer and connected to the main control chip by the second wiring layer. This avoids the problem of poor soldering caused by thermal stress when the bumps of the main control chip are directly interconnected with the substrate. At the same time, since the influence of the main control chip is eliminated, other chips are grouped and horizontally arranged on the support surface provided by the first wiring layer. The bonding wires connecting other chips are connected by the first wiring layer. Compared with the single stacking method, it effectively reduces the thickness of the finished product and the length of the bonding wires, and optimizes the finished product structure. Attached Figure Description
[0024] Figure 1 This is a schematic diagram of an existing chip packaging structure;
[0025] Figure 2 This is a schematic diagram of the chip packaging structure of this utility model after an insulating channel has been grown on a carrier board;
[0026] Figure 3 This is a schematic diagram of the chip packaging structure of this utility model after an insulating support layer has been formed on a carrier board;
[0027] Figure 4 This is a schematic diagram of the chip packaging structure of this utility model after the first and second wiring layers are formed on the insulating support layer.
[0028] Figure 5 This is a schematic diagram of the chip packaging structure of this utility model after the chipset is installed in the first wiring layer;
[0029] Figure 6 This is a schematic diagram of the chip packaging structure of this utility model, showing the formation of an insulating protective layer in the first wiring layer.
[0030] Figure 7 This is a schematic diagram of an optional chip stacking structure for the chipset of the present invention.
[0031] Label Explanation:
[0032] 1. Insulating support layer; 2. Main control chip; 3. Chipset; 4. First wiring layer; 5. Second wiring layer; 6. Insulating protective layer; 7. Electronic components; 8. Carrier board;
[0033] 11. Insulated passage;
[0034] 31. Sub-chipset; 32. Memory chip; 33. Bonding point;
[0035] 41. Protrusion. Detailed Implementation
[0036] To explain in detail the technical content, objectives, and effects of this utility model, the following description is provided in conjunction with the embodiments and accompanying drawings.
[0037] Please refer to Figures 2 to 7 The chip packaging structure includes an insulating support layer 1, a main control chip 2, and a chipset 3;
[0038] The main control chip 2 is disposed within the insulating support layer 1. The top surface of the insulating support layer 1 is provided with a first rewiring layer 4, and the bottom surface of the insulating support layer 1 is provided with a second rewiring layer 5.
[0039] The main control chip 2 is electrically connected to the second rewiring layer 5, and at least two sets of the chip group 3 are horizontally laid on the first rewiring layer 4. The chip group 3 is electrically connected to the first rewiring layer 4, and the first rewiring layer 4 is electrically connected to the second rewiring layer 5.
[0040] As can be seen from the above description, the beneficial effects of this utility model are as follows: An insulating support layer 1 with a first wiring layer 4 and a second wiring layer 5 is provided. The main control chip 2 is arranged within the insulating support layer 1, and the second wiring layer 5 is used to connect the main control chip 2. This avoids the problem of poor soldering caused by thermal stress when the bumps 41 of the main control chip 2 are directly interconnected with the substrate. Simultaneously, due to the absence of the influence of the main control chip 2, other chips are grouped and horizontally arranged on the support surface provided by the first wiring layer 4. The bonding wires connecting other chips are connected using the first wiring layer 4. Compared with a single stacking arrangement, this effectively reduces the thickness of the finished product and the length of the bonding wires, optimizing the finished product structure.
[0041] Furthermore, the chipset 3 includes at least two sub-chipsets 31 that are stacked in a staggered manner;
[0042] The sub-chip group 31 has a bonding point 33 in a position not obstructed by other adjacent sub-chip groups 31, and the sub-chip group 31 is electrically connected to the first redistribution layer 4 through the bonding point 33.
[0043] As can be seen from the above description, staggered stacking can make full use of space, accommodating more sub-chips 31 on the limited support surface of the first wiring layer 4, thereby improving integration. At the same time, by cleverly utilizing the structural characteristics of staggered stacking, the unobstructed bonding points 33 ensure that each sub-chip 31 can be successfully bonded to the first wiring layer 4.
[0044] Furthermore, all of the sub-chipsets 31 are stacked in a stepped manner;
[0045] The sub-chip group 31 includes one or two memory chips 32. The two memory chips 32 of the same sub-chip group 31 overlap, with the chip pad pins of the upper memory chip 32 facing upwards and the chip pad pins of the lower memory chip 32 facing downwards.
[0046] As can be seen from the above description, the stepped stacking makes the wire bonding points 33 of each sub-chip group 31 regularly distributed, which facilitates the precise operation of automated wire bonding equipment and improves production efficiency. Meanwhile, the pin directions of the memory chips 32 in the same sub-chip group 31 are opposite, which can avoid pin conflicts when they are stacked. This increases the storage capacity without occupying additional horizontal space, significantly improving space utilization. At the same time, it ensures that the upper and lower memory chips 32 can be stably connected to the first wiring layer 4 respectively without interfering with each other.
[0047] Furthermore, the sub-chip group 31 includes two staggered stacked memory chips 32, each of which is provided with a bonding point 33, and the memory chip 32 is electrically connected to the first redistribution layer 4 through the bonding point 33.
[0048] As can be seen from the above description, the two staggered stacked memory chips 32 increase the single-group storage capacity while ensuring that their respective bonding points 33 are not blocked by the stagger, thus improving the flexibility of the bonding connection.
[0049] Furthermore, the first rewiring layer 4 is provided with bumps 41, and the bumps 41 are electrically connected to the bonding points 33 in a one-to-one correspondence.
[0050] As can be seen from the above description, the precise correspondence between the protrusion 41 and the bonding point 33 can improve the reliability of the bonding connection and reduce the risk of poor contact; as a fulcrum for the physical connection, the protrusion 41 can enhance the mechanical strength of the bonding part and avoid connection breakage caused by external force or thermal expansion and contraction.
[0051] Furthermore, the first redistribution layer 4 is provided with an insulating protective layer 6 covering all of the chipsets 3.
[0052] As can be seen from the above description, the insulating protective layer 6 can provide a physical barrier for the chipset 3 and the wire bonding structure, effectively isolating external dust, moisture and other pollutants, and reducing the impact of environmental factors on chip performance.
[0053] Furthermore, the insulating support layer 1 is provided with an insulating channel 11;
[0054] The first rewiring layer 4 is electrically connected to the second rewiring layer 5 through the insulating channel 11.
[0055] As can be seen from the above description, the insulating channel 11, while realizing the electrical connection between the two layers of wiring, avoids electrical interference between the layers due to its insulation characteristics, ensuring the purity of signal transmission. Compared with other connection methods, the through-hole structure is more compact, which can reduce the space occupied by wiring, make the overall structure lighter and thinner, and at the same time improve the signal transmission speed and reduce the delay.
[0056] Furthermore, the insulating support layer 1 is a plastic-encapsulated structure with the second rewiring layer 5 as the base.
[0057] As can be seen from the above description, the molding process is mature and the cost is low. It can tightly wrap the main control chip 2, provide stable mechanical support, and has good insulation effect.
[0058] Example 1
[0059] Chip packaging structure, such as Figure 6As shown, the chip packaging structure includes an insulating support layer 1, a main control chip 2, and a chipset 3. The main control chip 2 is disposed within the insulating support layer 1. A first wiring layer 4 is provided on the top surface of the insulating support layer 1, and a second wiring layer 5 is provided on the bottom surface of the insulating support layer 1. The main control chip 2 is electrically connected to the second wiring layer 5. At least two chipsets 3 are horizontally laid on the first wiring layer 4, and the chipsets 3 are electrically connected to the first wiring layer 4. The first wiring layer 4 is electrically connected to the second wiring layer 5.
[0060] In this embodiment, combined with Figure 6 As shown, compared to existing designs, the main control chip 2 is not horizontally laid out with other chips; instead, it has a vertical layer relationship with the other chips. The insulating support layer 1 protects the main control chip 2 while providing support for the other chips. With less interference from the main control chip 2, the other chips can be laid out in groups horizontally, and each group of chips can be stacked, effectively reducing the thickness of the entire chip package structure.
[0061] Where space permits or in accordance with actual design requirements, the insulating support layer 1 may integrate not only the main control chip 2, but also other electronic components 7, such as slave chips and resistors. The insulating support layer 1 is preferably a plastic-encapsulated structure with the second wiring layer 5 as its base. The insulating support layer 1 has an insulating channel 11; the first wiring layer 4 is electrically connected to the second wiring layer 5 through the insulating channel 11.
[0062] In this embodiment, taking a plastic encapsulation structure as an example, the fabrication process of the chip packaging structure is as follows:
[0063] First, such as Figure 2 As shown, a TMV (Through Molding Via), i.e., an insulating channel 11, is electroplated and grown on the carrier plate 8 (for temporary fixation).
[0064] Secondly, such as Figure 3 As shown, the main control chip 2 and electronic components 7 are attached to the carrier board 8 and then encapsulated to obtain the insulating support layer 1.
[0065] Again, such as Figure 4 As shown, the carrier board 8 is removed, and RDL rewiring is performed on the upper and lower sides of the insulating support layer 1. The upper RDL is called the first rewiring layer 4, and the lower RDL is called the second rewiring layer 5. The first rewiring layer 4 and the second rewiring layer 5 are electrically connected through plastic-sealed through-holes.
[0066] Then, as Figure 5 As shown, two chipsets 3 are horizontally laid on the first wiring layer 4, and wire bonding is performed on the chipsets 3 to connect them to the first wiring layer.
[0067] Finally, as Figure 6As shown, an insulating protective layer 6 covering all chipsets 3 is disposed on the first redistribution layer 4. The insulating protective layer 6 can be made by filling with molding compound.
[0068] In this embodiment, the chipset 3 includes at least two sub-chipsets 31 that are stacked in a staggered manner; the sub-chipsets 31 are provided with wire bonding points 33 at positions not obscured by other adjacent sub-chipsets 31, and the sub-chipsets 31 are electrically connected to the first rewiring layer 4 through the wire bonding points 33.
[0069] Example 2
[0070] The chip packaging structure, based on the above embodiment one, is as follows: Figure 4 and Figure 5 As shown, all sub-chipsets 31 are stacked in a stepped manner; each sub-chipset 31 includes one or two memory chips 32, with the two memory chips 32 in the same sub-chipset 31 overlapping, the chip pad pins of the upper memory chip 32 facing upwards, and the chip pad pins of the lower memory chip 32 facing downwards. The first redistribution layer 4 has bumps 41, which are electrically connected to bonding points 33 in a one-to-one correspondence.
[0071] like Figure 4 As shown, multiple chipsets 3 are stacked in a stepped manner, where the arrows indicate the orientation of the chip pad pins of the memory chip 32. The topmost chipset 3 contains one memory chip 32 with its chip pad pins facing downwards, electrically connected to the bumps 41 of the first redistribution layer 4 via vertical bonding wires. The bottommost chipset 3 also contains only one memory chip 32 with its chip pad pins facing upwards, electrically connected to the bumps 41 of the first redistribution layer 4 via forward bonding wires. The middle chipset 3 contains two overlapping memory chips 32, with the upper memory chip 32 having its chip pad pins facing upwards and using horizontal bonding wires, and the lower memory chip 32 having its chip pad pins facing downwards and using vertical bonding wires.
[0072] Therefore, combined Figure 5 As shown, the specific process of bonding wires to the first super-wiring layer 4 on the chipset 3 includes: for memory chips 32 with their chip pad pins facing down, vertical bonding wires are used to electrically connect them to the bumps 41 of the first super-wiring layer 4; while for each memory chip 32 with its chip pad pins facing down, horizontal bonding wires are used to electrically connect it to the bumps 41 of the first super-wiring layer 4.
[0073] In other equivalent embodiments, the two chipsets 3 can be stacked symmetrically or in the same direction; it is understood that, based on the upper and lower layer structure of this application, the above-described stacking method for the chipsets 3 is a preferred solution. Specifically, the memory chips 32 of different chipsets 3 or the memory chips 32 of different sub-chipsets 31 can also adopt other stacking methods such as staggered stacking, for example... Figure 6 As shown. Compared to Figure 6 Given the same size, the solution described in this embodiment saves more space and is more suitable for stacking multiple memory chips 32. Furthermore, the solution described in this embodiment can be adapted to more complex main control chips 2, supporting four-channel operation. Figure 6 Only two channels can be used.
[0074] Example 3
[0075] The memory includes a motherboard and a chip package structure according to Embodiment 1 or 2, wherein the chip package structure is disposed on the motherboard.
[0076] Example 4
[0077] An electronic device includes the memory described in Embodiment 3.
[0078] In summary, the chip packaging structure, memory, and electronic device provided by this utility model feature an insulating support layer with a first and second wiring layer. The main control chip is arranged within the insulating support layer and connected to the main control chip via the second wiring layer. This avoids the problem of poor soldering caused by thermal stress when the bumps of the main control chip are directly interconnected with the substrate. Furthermore, since the main control chip is no longer a concern, other chips are grouped and horizontally arranged on the support surface provided by the first wiring layer. The bonding wires connecting these other chips are connected via the first wiring layer. Compared to a single stacking arrangement, this effectively reduces the thickness of the finished product and the length of the bonding wires, optimizing the finished product structure. Within the chipset, the stepped stacking ensures a regular distribution of bonding points in each sub-chip group, facilitating precise operation of automated bonding equipment and improving production efficiency. Moreover, the memory chips within the same sub-chip group have opposite pin directions, avoiding pin conflicts even when stacked. This increases storage capacity without requiring additional horizontal space, significantly improving space utilization. Simultaneously, it ensures that the upper and lower memory chips can be stably connected to the first wiring layer without interference. Furthermore, while achieving electrical connection between two layers of wiring, the insulating channel avoids electrical interference between layers due to its insulation properties, ensuring the purity of signal transmission. Compared with other connection methods, the through-hole structure is more compact, which can reduce the space occupied by wiring, making the overall structure lighter and thinner, while improving signal transmission speed and reducing latency.
[0079] The above description is merely an embodiment of this utility model and does not limit the patent scope of this utility model. Any equivalent modifications made based on the content of this utility model specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of this utility model.
Claims
1. A chip packaging structure, characterized in that, This includes an insulating support layer, a main control chip, and a chipset. The main control chip is disposed within the insulating support layer. The top surface of the insulating support layer is provided with a first wiring layer, and the bottom surface of the insulating support layer is provided with a second wiring layer. The main control chip is electrically connected to the second wiring layer, and at least two sets of the chip groups are horizontally laid on the first wiring layer. The chip groups are electrically connected to the first wiring layer, and the first wiring layer is electrically connected to the second wiring layer.
2. The chip packaging structure according to claim 1, characterized in that, The chipset includes at least two sub-chipsets that are stacked in a staggered manner; The sub-chip group has bonding points in a position not obscured by other adjacent sub-chip groups, and the sub-chip group is electrically connected to the first rewiring layer through the bonding points.
3. The chip packaging structure according to claim 2, characterized in that, All the aforementioned sub-chipsets are stacked in a stepped manner; The sub-chipset includes one or two memory chips, with the two memory chips in the same sub-chipset overlapping, the chip pad pins of the upper memory chip facing upwards, and the chip pad pins of the lower memory chip facing downwards.
4. The chip packaging structure according to claim 2, characterized in that, The sub-chipset includes two staggered stacked memory chips, each of which has a bonding point, and the memory chip is electrically connected to the first redistribution layer through the bonding point.
5. The chip packaging structure according to claim 2, characterized in that, The first wiring layer has bumps, and each bump is electrically connected to a corresponding bonding point.
6. The chip packaging structure according to claim 1, characterized in that, The first wiring layer has an insulating protective layer covering all of the chipsets.
7. The chip packaging structure according to claim 1, characterized in that, The insulating support layer is provided with insulating channels; The first wiring layer is electrically connected to the second wiring layer through the insulating channel.
8. The chip packaging structure according to claim 1, characterized in that, The insulating support layer is a plastic-encapsulated structure with the second redistribution layer as its base.
9. A memory, characterized in that, The invention includes a motherboard and a chip packaging structure as described in any one of claims 1 to 8, wherein the chip packaging structure is disposed on the motherboard.
10. An electronic device, characterized in that, Includes the memory as described in claim 9.