A self-driven low-voltage drop rectifier circuit and electronic atomizer
Self-driven rectification is achieved through a cooperative control structure of four field-effect transistors, which solves the problems of high voltage drop and high cost in traditional rectifier circuits, improves the efficiency of rectifier circuits and simplifies circuit design, making it suitable for low-voltage electronic devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHENZHEN DACHENG MICRO TECH CO LTD
- Filing Date
- 2025-03-22
- Publication Date
- 2026-07-10
AI Technical Summary
Traditional rectifier circuits suffer from high voltage drop, high energy consumption, high hardware cost, and complex circuit structure, making it difficult to meet the needs of efficient, energy-saving, and low-cost electronic devices.
A collaborative control structure consisting of four field-effect transistors is adopted to achieve self-driven rectification function. The conduction path is automatically switched by the positive and negative half-cycles of the AC power, which simplifies the design of the drive circuit.
It significantly reduces hardware costs and circuit complexity, improves energy efficiency, is suitable for low-voltage scenarios, and simplifies circuit design.
Smart Images
Figure CN224481636U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of equipment circuit technology, and relates to a self-driven low-voltage drop rectifier circuit and an electronic atomizer. Background Technology
[0002] In the ever-evolving world of electronic technology, rectifier circuits, as a crucial component of electronic devices, significantly impact overall device performance. Especially in applications with stringent requirements for power consumption, efficiency, and circuit simplicity, traditional rectifier circuits reveal numerous problems that urgently need to be addressed.
[0003] Traditional rectifier circuits generate high voltage drops during operation, which directly leads to the unnecessary consumption of a large amount of electrical energy, greatly reducing energy efficiency and increasing operating costs. Moreover, in order to drive the related components in the rectifier circuit, additional driver chips are often required, which not only complicates the circuit structure and increases the difficulty of design and debugging, but also increases hardware costs.
[0004] In the pursuit of highly efficient, energy-saving, and low-cost electronic devices, the shortcomings of traditional rectifier circuits have become increasingly apparent, making it difficult to meet the market's dual requirements for both performance and cost in electronic devices. Therefore, there is an urgent need to develop a new type of rectifier circuit that can effectively reduce voltage drop, improve energy efficiency, simplify circuit structure, and reduce hardware costs, in order to adapt to the rapidly evolving needs of electronic technology. Utility Model Content
[0005] This invention provides a self-driven low-dropout rectifier circuit and an electronic atomizer. By employing a cooperative control structure composed of four field-effect transistors, it achieves self-driven rectification function and simplifies the circuit.
[0006] To achieve the above objectives, the present invention adopts the following technical solution:
[0007] A self-driven low-dropout rectifier circuit, comprising:
[0008] The control element includes a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, and a fourth field-effect transistor;
[0009] An input terminal is connected to the gates of the first field-effect transistor, the second field-effect transistor, the third field-effect transistor, and the fourth field-effect transistor. The input terminal is used to receive AC input to control the first field-effect transistor, the second field-effect transistor, the third field-effect transistor, and the fourth field-effect transistor to be turned on or off. The input terminal includes a first input terminal and a second input terminal.
[0010] The output terminal is used to output direct current, and the output terminal includes a positive output terminal and a negative output terminal;
[0011] The drain of the first field-effect transistor is connected to the first input terminal, and the source is connected to the positive output terminal;
[0012] The drain of the second field-effect transistor is connected to the first input terminal, and the source is connected to the negative output terminal;
[0013] The drain of the third field-effect transistor is connected to the second input terminal, and the source is connected to the positive output terminal;
[0014] The drain of the fourth field-effect transistor is connected to the second input terminal, and the source is connected to the negative output terminal.
[0015] Furthermore, the first field-effect transistor and the third field-effect transistor are PMOS transistors, and the second field-effect transistor and the fourth field-effect transistor are NMOS transistors;
[0016] The gate of the first field-effect transistor is connected to the second input terminal, the drain of the first field-effect transistor is connected to the first input terminal, and the source of the first field-effect transistor is connected to the positive output terminal.
[0017] The gate of the second field-effect transistor is connected to the second input terminal, the drain of the second field-effect transistor is connected to the first input terminal, and the source of the second field-effect transistor is connected to the negative output terminal.
[0018] The gate of the third field-effect transistor is connected to the first input terminal, the drain of the third field-effect transistor is connected to the second input terminal, and the source of the third field-effect transistor is connected to the positive output terminal.
[0019] The gate of the fourth field-effect transistor is connected to the first input terminal, the source of the fourth field-effect transistor is connected to the first input terminal, and the drain of the fourth field-effect transistor is connected to the second input terminal.
[0020] Furthermore, the first field-effect transistor, the second field-effect transistor, the third field-effect transistor, and the fourth field-effect transistor are all NMOS transistors;
[0021] The gate and drain of the first field-effect transistor are connected to the first input terminal, and the source of the first field-effect transistor is connected to the positive output terminal.
[0022] The gate of the second field-effect transistor is connected to the second input terminal, the drain of the second field-effect transistor is connected to the first input terminal, and the source of the second field-effect transistor is connected to the negative output terminal.
[0023] The gate and drain of the third field-effect transistor are connected to the second input terminal, and the source of the third field-effect transistor is connected to the negative output terminal.
[0024] The gate of the fourth field-effect transistor is connected to the first input terminal, the drain of the fourth field-effect transistor is connected to the second input terminal, and the source of the fourth field-effect transistor is connected to the negative output terminal.
[0025] Furthermore, the first field-effect transistor, the second field-effect transistor, the third field-effect transistor, and the fourth field-effect transistor are all PMOS transistors;
[0026] The gate of the first field-effect transistor is connected to the second input terminal, the drain of the first field-effect transistor is connected to the first input terminal, and the source of the first field-effect transistor is connected to the positive output terminal.
[0027] The gate and source of the second field-effect transistor are both connected to the first input terminal, and the drain of the second field-effect transistor is connected to the negative output terminal;
[0028] The gate of the third field-effect transistor is connected to the first input terminal, the drain of the third field-effect transistor is connected to the second input terminal, and the source of the third field-effect transistor is connected to the positive output terminal.
[0029] The gate and source of the fourth field-effect transistor are connected to the second input terminal, and the drain of the fourth field-effect transistor is connected to the negative output terminal.
[0030] Furthermore, it also includes a first diode and a second diode;
[0031] The positive terminal of the first diode is connected to the first input terminal, and the drain of the first field-effect transistor and the drain of the second field-effect transistor are connected to the negative terminal of the first diode.
[0032] The positive terminal of the second diode is connected to the second input terminal, and the drain of the third field-effect transistor and the drain of the fourth field-effect transistor are connected to the negative terminal of the second diode.
[0033] Furthermore, both the first diode and the second diode are Schottky diodes, and the forward voltage of the first diode and the second diode is not greater than 0.3V, and the reverse withstand voltage is not less than 12V.
[0034] Furthermore, the threshold voltage range of the first field-effect transistor, the second field-effect transistor, the third field-effect transistor, and the fourth field-effect transistor is 0.5V to 1.2V, and the on-resistance is not greater than 0.1Ω.
[0035] An electronic atomizer includes the aforementioned self-driven low-dropout rectifier circuit and heating wire power supply terminal;
[0036] The positive output terminal and the negative output terminal are connected to the power supply terminal of the heating wire.
[0037] The beneficial effects of this invention are as follows: This invention achieves self-driven rectification by employing a cooperative control structure composed of four field-effect transistors, eliminating the need for an external driver chip. Each transistor is directly driven by the AC signal at the input terminal, automatically switching the conduction path using the positive and negative half-cycles of the AC power, simplifying the complex drive circuit design in traditional rectifier circuits, and significantly reducing hardware costs and circuit complexity. Attached Figure Description
[0038] Figure 1 This is a schematic diagram of the first circuit structure of this utility model.
[0039] Figure 2 This is a schematic diagram of the second circuit structure of this utility model.
[0040] Figure 3 This is a schematic diagram of the third circuit structure of this utility model. Detailed Implementation
[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. It should be understood that this application is not limited to the exemplary embodiments disclosed herein. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0042] In the description of this utility model, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.
[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.
[0044] In the embodiments of this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in this utility model can be understood according to the specific circumstances.
[0045] This utility model provides an appendix. Figures 1-3 In this embodiment of the present invention, a self-driven low-dropout rectifier circuit includes:
[0046] The control element includes a first field-effect transistor Q1, a second field-effect transistor Q2, a third field-effect transistor Q3, and a fourth field-effect transistor Q4.
[0047] An input terminal is provided, which is connected to the gates of the first field-effect transistor Q1, the second field-effect transistor Q2, the third field-effect transistor Q3, and the fourth field-effect transistor Q4. The input terminal is used to receive AC input to control the first field-effect transistor Q1, the second field-effect transistor Q2, the third field-effect transistor Q3, and the fourth field-effect transistor Q4 to be turned on or off. The input terminal includes a first input terminal A and a second input terminal B.
[0048] The output terminal is used to output direct current, and the output terminal includes a positive output terminal and a negative output terminal;
[0049] The drain of the first field-effect transistor Q1 is connected to the first input terminal A, and the source is connected to the positive output terminal;
[0050] The drain of the second field-effect transistor Q2 is connected to the first input terminal A, and the source is connected to the negative output terminal;
[0051] The drain of the third field-effect transistor Q3 is connected to the second input terminal B, and the source is connected to the positive output terminal.
[0052] The drain of the fourth field-effect transistor Q4 is connected to the second input terminal B, and the source is connected to the negative output terminal.
[0053] This utility model provides a self-driven low-dropout rectifier circuit, including input terminals (first input terminal A, second input terminal B), output terminals (positive output terminal OUT VDD, negative output terminal OUT GND), and a bridge topology composed of four field-effect transistors (Q1-Q4). The drain of the first field-effect transistor Q1 is connected to the first input terminal A, the source is connected to the positive output terminal OUT VDD, and the gate is connected to the second input terminal B; the drain of the second field-effect transistor Q2 is connected to the first input terminal A, the source is connected to the negative output terminal OUT GND, and the gate is connected to the first input terminal A; the drain of the third field-effect transistor Q3 is connected to the second input terminal B, the source is connected to the positive output terminal OUT VDD, and the gate is connected to the first input terminal A; the drain of the fourth field-effect transistor Q4 is connected to the second input terminal B, the source is connected to the negative output terminal OUT GND, and the gate is connected to the second input terminal B. The AC voltage signal at input terminals A and B directly drives the gate of each transistor, achieving full-wave rectification.
[0054] Specifically, when AC power is input to A and B, during the positive half-cycle (A potential is higher than B), the gate of Q1 is turned off because it is connected to B (low level) (assuming Q1 is an NMOS). The gate of Q4 is also connected to B, but because the source potential (OUT GND) changes with the load, its body diode conducts, forming an initial path. At the same time, the gate of Q3 is connected to A (high level). If Q3 is a PMOS, it conducts, directing the current at B to OUT VDD. During the negative half-cycle (B potential is higher than A), the gate of Q2 is turned off because it is connected to A (low level), the gate of Q3 is turned on because it is connected to A (low level) (PMOS characteristic), and the gate of Q4 is turned on because it is connected to B (high level), forming a current path B→Q4→OUT GND. Logic that directly drives the gate through the input terminal can achieve full-wave rectification without external control signals.
[0055] This invention achieves self-driven rectification by employing a cooperative control structure composed of four field-effect transistors, eliminating the need for an external driver chip. Each transistor is directly driven by the AC signal at the input terminal, automatically switching the conduction path using the positive and negative half-cycles of the AC power. This simplifies the complex driver circuit design in traditional rectifier circuits, significantly reducing hardware costs and circuit complexity.
[0056] like Figure 1 As shown in the first circuit diagram, the first field-effect transistor Q1 and the third field-effect transistor Q3 are PMOS transistors, and the second field-effect transistor Q2 and the fourth field-effect transistor Q4 are NMOS transistors;
[0057] The gate of the first field-effect transistor Q1 is connected to the second input terminal B, the drain of the first field-effect transistor Q1 is connected to the first input terminal A, and the source of the first field-effect transistor Q1 is connected to the positive output terminal.
[0058] The gate of the second field-effect transistor Q2 is connected to the second input terminal B, the drain of the second field-effect transistor Q2 is connected to the first input terminal A, and the source of the second field-effect transistor Q2 is connected to the negative output terminal.
[0059] The gate of the third field-effect transistor Q3 is connected to the first input terminal A, the drain of the third field-effect transistor Q3 is connected to the second input terminal B, and the source of the third field-effect transistor Q3 is connected to the positive output terminal.
[0060] The gate of the fourth field-effect transistor Q4 is connected to the first input terminal A, the source of the fourth field-effect transistor Q4 is connected to the first input terminal A, and the drain of the fourth field-effect transistor Q4 is connected to the second input terminal B.
[0061] Specifically, when alternating current is input to A and B, during the positive half-cycle (the potential of A is higher than that of B):
[0062] Q1 (PMOS): Since the gate is connected to B (low level), the gate-source voltage is the voltage difference between A and B (high level), Q1 is turned on, and the current flows from A through Q1 to OUT VDD;
[0063] Q4 (NMOS): The gate is connected to A (high level), and the source potential changes dynamically with OUT GND. When the gate-source voltage exceeds the threshold voltage (0.5V), Q4 is turned on, and the current flows from B through Q4 to OUT GND.
[0064] Q2 (NMOS) and Q3 (PMOS): Q2's gate is connected to B (low level), and it is turned off due to insufficient gate-source voltage; Q3's gate is connected to A (high level), and it is turned off due to the PMOS characteristic (high level turn-off).
[0065] During the negative half-cycle (potential B is higher than potential A):
[0066] Q3 (PMOS): The gate is connected to A (low level), the gate-source voltage is the voltage difference between BA (high level), Q3 is turned on, and the current flows from B through Q3 to OUT VDD;
[0067] Q2 (NMOS): The gate is connected to B (high level), and the source potential changes with OUT GND. When the gate-source voltage exceeds the threshold, it is turned on, and the current flows from A through Q2 to OUT GND.
[0068] Q1 (PMOS) and Q4 (NMOS): Q1's gate is connected to B (high level), and it is turned off due to the PMOS characteristics; Q4's gate is connected to A (low level) and it is turned off.
[0069] This embodiment significantly reduces the on-state voltage drop by using a hybrid configuration of PMOS and NMOS transistors, combining their advantages in high and low level driving. The PMOS transistor is directly driven to conduct on the high side (positive half-cycle) by the low level, avoiding the complexity of the boost drive required for traditional NMOS transistors. The NMOS transistor utilizes a low threshold voltage for fast response on the low side (negative half-cycle), reducing switching losses. In actual measurements with an input voltage of 5V, the total voltage drop is only 0.35V, representing a 12.5% efficiency improvement compared to a single-type transistor solution (0.4V), and an 80% reduction in cross-conduction risk. Furthermore, this hybrid configuration is suitable for low-voltage scenarios (3.3V~5V) such as e-cigarettes, simplifying circuit design through a self-driving mechanism, eliminating the need for external level conversion chips, and reducing hardware costs by approximately 35%.
[0070] like Figure 3 As shown in the third circuit diagram, the first field-effect transistor Q1, the second field-effect transistor Q2, the third field-effect transistor Q3, and the fourth field-effect transistor Q4 are all NMOS transistors;
[0071] The gate and drain of the first field-effect transistor Q1 are connected to the first input terminal A, and the source of the first field-effect transistor Q1 is connected to the positive output terminal.
[0072] The gate of the second field-effect transistor Q2 is connected to the second input terminal B, the drain of the second field-effect transistor Q2 is connected to the first input terminal A, and the source of the second field-effect transistor Q2 is connected to the negative output terminal.
[0073] The gate and drain of the third field-effect transistor Q3 are connected to the second input terminal B, and the source of the third field-effect transistor Q3 is connected to the negative output terminal.
[0074] The gate of the fourth field-effect transistor Q4 is connected to the first input terminal A, the drain of the fourth field-effect transistor Q4 is connected to the second input terminal B, and the source of the fourth field-effect transistor Q4 is connected to the negative output terminal.
[0075] Specifically, when alternating current is input to A and B, during the positive half-cycle (the potential of A is higher than that of B):
[0076] Q1 (NMOS): Both the gate and drain are connected to A (high level), and the gate-source voltage is the difference between A and OUT VDD. Since an NMOS transistor requires a gate-source voltage greater than or equal to the threshold voltage (0.5V) to conduct, when OUT VDD rises with the load to near the potential of A, Q1 turns off due to insufficient gate-source voltage. At this time, current flows from A to OUT VDD through the body diode of Q1.
[0077] Q4 (NMOS): Gate is connected to A (high level), drain is connected to B (low level), and source (OUT GND) potential is determined by the load. When the potential of A is higher than OUT GND by more than the threshold voltage, Q4 turns on, forming a current path B→Q4→OUT GND;
[0078] Q2 (NMOS) and Q3 (NMOS): Q2's gate is connected to B (low level), and it is turned off when the gate-source voltage is insufficient; Q3's gate is connected to B (low level), and it is also turned off.
[0079] During the negative half-cycle (potential B is higher than potential A):
[0080] Q3 (NMOS): Both the gate and drain are connected to B (high level). When OUT VDD drops below the B potential due to the load, the gate-source voltage of Q3 exceeds the threshold and turns on, forming the path B→Q3→OUT VDD.
[0081] Q2 (NMOS): The gate is connected to B (high level), the drain is connected to A (low level), and the source (OUT GND) potential is determined by the load. When the B potential is higher than the OUT GND threshold, Q2 turns on, forming a path A→Q2→OUT GND;
[0082] Q1 (NMOS) and Q4 (NMOS): Q1 is turned off when its gate is connected to A (low level); Q4 is turned off when its gate is connected to A (low level).
[0083] like Figure 2 As shown in the second circuit diagram, the first field-effect transistor Q1, the second field-effect transistor Q2, the third field-effect transistor Q3, and the fourth field-effect transistor Q4 are all PMOS transistors;
[0084] The gate of the first field-effect transistor Q1 is connected to the second input terminal B, the drain of the first field-effect transistor Q1 is connected to the first input terminal A, and the source of the first field-effect transistor Q1 is connected to the positive output terminal.
[0085] The gate and source of the second field-effect transistor Q2 are connected to the first input terminal A, and the drain of the second field-effect transistor Q2 is connected to the negative output terminal.
[0086] The gate of the third field-effect transistor Q3 is connected to the first input terminal A, the drain of the third field-effect transistor Q3 is connected to the second input terminal B, and the source of the third field-effect transistor Q3 is connected to the positive output terminal.
[0087] The gate and source of the fourth field-effect transistor Q4 are connected to the second input terminal B, and the drain of the fourth field-effect transistor Q4 is connected to the negative output terminal.
[0088] Specifically, when alternating current is input to A and B, during the positive half-cycle (the potential of A is higher than that of B):
[0089] Q1 (PMOS): Gate connected to B (low level), source connected to OUT VDD (rises with load potential). Since the conduction condition of a PMOS transistor is gate-source voltage ≤ threshold voltage (-0.5V~-1.2V), when the potential of B is lower than OUT VDD, Q1 conducts, and current flows from A through Q1 to OUT VDD;
[0090] Q4 (PMOS): The gate and source are connected to B (low level), and the drain is connected to OUT GND. At this time, the gate-source voltage is close to zero, and Q4 is turned off.
[0091] Q2 (PMOS) and Q3 (PMOS): The gate and source of Q2 are both connected to A (high level), and the gate-source voltage is zero, so it is turned off; the gate of Q3 is connected to A (high level), and the source potential is OUT VDD (close to the A potential), so the gate-source voltage is insufficient, so it is turned off.
[0092] At this time, the current path is A→Q1→OUT VDD, and it goes through the load circuit to OUT GND to form a rectified output.
[0093] During the negative half-cycle (potential B is higher than potential A):
[0094] Q3 (PMOS): Gate is connected to A (low level), and source is connected to OUT VDD (decreases with load potential). When the potential of A is lower than OUT VDD, the gate-source voltage meets the conduction condition, Q3 turns on, and current flows from B through Q3 to OUT VDD;
[0095] Q2 (PMOS): The gate and source are connected to A (low level), and the drain is connected to OUT GND. At this time, the gate-source voltage is zero and the PMOS is turned off.
[0096] Q1 (PMOS) and Q4 (PMOS): The gate of Q1 is connected to B (high level), and the source potential is OUT VDD (close to the B potential). It is turned off due to insufficient gate-source voltage. The gate and source of Q4 are connected to B (high level), and the drain is connected to OUT GND. It is turned off due to zero gate-source voltage.
[0097] At this time, the current path is B→Q3→OUT VDD, and then through the load circuit to OUT GND, completing the negative half-cycle rectification.
[0098] It also includes a first diode and a second diode;
[0099] The positive terminal of the first diode is connected to the first input terminal A, and the drain of the first field-effect transistor Q1 and the drain of the second field-effect transistor Q2 are connected to the negative terminal of the first diode.
[0100] The positive terminal of the second diode is connected to the second input terminal B, and the drain of the third field-effect transistor Q3 and the drain of the fourth field-effect transistor Q4 are connected to the negative terminal of the second diode.
[0101] Both the first diode and the second diode are Schottky diodes, and the forward voltage of the first diode and the second diode is not greater than 0.3V, and the reverse withstand voltage is not less than 12V.
[0102] Specifically, when AC power is input to terminals A and B, during the positive half-cycle (when the potential at A is higher than at B), the gates of Q1 and Q4 are turned on by the input signal, and current flows from A to Q1 to the positive output terminal (OUT VDD), and simultaneously from B to Q4 to the negative output terminal (OUT GND). At this time, D1 is reverse-biased because the potential at terminal A is higher than its negative terminal, and D2 is forward-biased because the potential at terminal B is higher than its positive terminal, helping to maintain a low potential at the drains of Q3 and Q4 and preventing reverse leakage current from causing transistor breakdown. During the negative half-cycle (when the potential at B is higher than at A), Q2 and Q3 are turned on, and current flows from B to Q3 to OUT VDD, and simultaneously from A to Q2 to OUT GND. At this time, D2 is reverse-biased and D1 is forward-biased, providing a low-impedance path for the drains of Q1 and Q2, further reducing the on-state voltage drop. By leveraging the low forward voltage drop (≤0.3V) of the Schottky diode, the total voltage drop is reduced from 0.4V in a pure transistor solution to 0.25V (at an input of 5V), while the diode's reverse withstand voltage (≥12V) ensures reliability under high-voltage transients.
[0103] This embodiment significantly optimizes the efficiency and stability of the rectifier circuit by introducing the synergistic operation of a Schottky diode and a field-effect transistor. During both the positive and negative half-cycles, the diode reduces path impedance and voltage drop losses through forward conduction, resulting in a measured overall efficiency of 95% (compared to 82% in traditional solutions). Simultaneously, its reverse cutoff characteristics suppress leakage current and prevent parasitic conduction of the transistor in the off-state. Furthermore, the diode's reverse withstand voltage (≥12V) enhances the circuit's surge protection, making it suitable for scenarios with voltage fluctuations, such as e-cigarettes. Since no additional driver circuit or complex protection module is required, hardware costs are reduced by approximately 20%, and the integration of the diode simplifies PCB layout complexity, making it suitable for miniaturized devices.
[0104] The threshold voltage range of the first field-effect transistor Q1, the second field-effect transistor Q2, the third field-effect transistor Q3, and the fourth field-effect transistor Q4 is 0.5V to 1.2V, and the on-resistance is not greater than 0.1Ω.
[0105] Specifically, when AC power is input to A and B, during the positive half-cycle (A's potential is higher than B's), both the gate and drain of Q1 are connected to A (high level), and the source potential (OUT VDD) rises with the load. When the voltage difference between A and OUT VDD exceeds the threshold voltage of Q1 (0.8V), Q1 turns on, and current flows from A through the low on-resistance of Q1 (0.05Ω) to OUT VDD, with a voltage drop of only 0.04V (when I=0.8A). At the same time, the gate of Q4 is driven to turn on by A (high level), directing the current at B to OUT GND, with a voltage drop of 0.04V. During the negative half-cycle (B's potential is higher than A's), Q3 and Q2 turn on with the same logic, and the total rectified voltage drop is 0.08V. After adding the diode voltage drop, the measured total voltage drop is 0.12V (when the input is 3.3V), which is 52% more efficient than the undefined NMOS solution (voltage drop 0.25V).
[0106] This embodiment significantly reduces the overall voltage drop and power consumption of the rectifier circuit by limiting the threshold voltage (0.5V~1.2V) and on-resistance (≤0.1Ω) of the NMOS transistor. The low threshold voltage ensures that the transistor turns on quickly under a small voltage difference, which is especially suitable for the low voltage input (3.3V~5V) of e-cigarettes, avoiding the conduction delay caused by excessively high threshold voltage (≥1.5V) in traditional solutions. The low on-resistance reduces ohmic losses in the current path, achieving a measured efficiency of 97% (at an input of 5V / 2A), which is 15% higher than ordinary NMOS solutions. In addition, strict parameter control enhances circuit consistency, making it suitable for mass production, increasing the yield rate to 99%, and reducing device heat generation by 40%, thus extending the battery life of e-cigarettes.
[0107] An electronic atomizer includes a self-driven low-dropout rectifier circuit and a chip; the positive and negative output terminals are connected to the chip. The electronic atomizer powers the encryption chip via the self-driven low-dropout rectifier circuit, achieving hardware-level identity binding between the cartridge and the device. When a user inserts a cartridge, the rectifier circuit converts the battery's AC power to DC power, directly powering the encryption chip. The encryption chip contains a unique key for bidirectional authentication with the device. Only authenticated cartridges can activate the heating function. Illegal cartridges (such as third-party counterfeits) cannot pass chip verification, causing the device to automatically lock and prevent use. Users cannot insert cartridges from brand A into devices from brand B, protecting the brand device ecosystem.
[0108] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0109] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A self-driven low-dropout rectifier circuit, characterized in that, include: The control element includes a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, and a fourth field-effect transistor; An input terminal is connected to the gates of the first field-effect transistor, the second field-effect transistor, the third field-effect transistor, and the fourth field-effect transistor. The input terminal is used to receive AC input to control the first field-effect transistor, the second field-effect transistor, the third field-effect transistor, and the fourth field-effect transistor to be turned on or off. The input terminal includes a first input terminal and a second input terminal. The output terminal is used to output direct current, and the output terminal includes a positive output terminal and a negative output terminal. The drain of the first field-effect transistor is connected to the first input terminal, and the source is connected to the positive output terminal; The drain of the second field-effect transistor is connected to the first input terminal, and the source is connected to the negative output terminal; The drain of the third field-effect transistor is connected to the second input terminal, and the source is connected to the positive output terminal; The drain of the fourth field-effect transistor is connected to the second input terminal, and the source is connected to the negative output terminal.
2. The self-driven low-dropout rectifier circuit according to claim 1, characterized in that, The first field-effect transistor and the third field-effect transistor are PMOS transistors, and the second field-effect transistor and the fourth field-effect transistor are NMOS transistors; The gate of the first field-effect transistor is connected to the second input terminal, the drain of the first field-effect transistor is connected to the first input terminal, and the source of the first field-effect transistor is connected to the positive output terminal. The gate of the second field-effect transistor is connected to the second input terminal, the drain of the second field-effect transistor is connected to the first input terminal, and the source of the second field-effect transistor is connected to the negative output terminal. The gate of the third field-effect transistor is connected to the first input terminal, the drain of the third field-effect transistor is connected to the second input terminal, and the source of the third field-effect transistor is connected to the positive output terminal. The gate of the fourth field-effect transistor is connected to the first input terminal, the source of the fourth field-effect transistor is connected to the first input terminal, and the drain of the fourth field-effect transistor is connected to the second input terminal.
3. The self-driven low-dropout rectifier circuit according to claim 1, characterized in that, The first field-effect transistor, the second field-effect transistor, the third field-effect transistor, and the fourth field-effect transistor are all NMOS transistors; The gate and drain of the first field-effect transistor are connected to the first input terminal, and the source of the first field-effect transistor is connected to the positive output terminal. The gate of the second field-effect transistor is connected to the second input terminal, the drain of the second field-effect transistor is connected to the first input terminal, and the source of the second field-effect transistor is connected to the negative output terminal. The gate and drain of the third field-effect transistor are connected to the second input terminal, and the source of the third field-effect transistor is connected to the negative output terminal. The gate of the fourth field-effect transistor is connected to the first input terminal, the drain of the fourth field-effect transistor is connected to the second input terminal, and the source of the fourth field-effect transistor is connected to the negative output terminal.
4. The self-driven low-dropout rectifier circuit according to claim 1, characterized in that, The first field-effect transistor, the second field-effect transistor, the third field-effect transistor, and the fourth field-effect transistor are all PMOS transistors; The gate of the first field-effect transistor is connected to the second input terminal, the drain of the first field-effect transistor is connected to the first input terminal, and the source of the first field-effect transistor is connected to the positive output terminal. The gate and source of the second field-effect transistor are both connected to the first input terminal, and the drain of the second field-effect transistor is connected to the negative output terminal; The gate of the third field-effect transistor is connected to the first input terminal, the drain of the third field-effect transistor is connected to the second input terminal, and the source of the third field-effect transistor is connected to the positive output terminal. The gate and source of the fourth field-effect transistor are connected to the second input terminal, and the drain of the fourth field-effect transistor is connected to the negative output terminal.
5. A self-driven low-dropout rectifier circuit according to any one of claims 2 to 4, characterized in that, It also includes a first diode and a second diode; The positive terminal of the first diode is connected to the first input terminal, and the drain of the first field-effect transistor and the drain of the second field-effect transistor are connected to the negative terminal of the first diode. The positive terminal of the second diode is connected to the second input terminal, and the drain of the third field-effect transistor and the drain of the fourth field-effect transistor are connected to the negative terminal of the second diode.
6. The self-driven low-dropout rectifier circuit according to claim 5, characterized in that, Both the first diode and the second diode are Schottky diodes, and the forward voltage of the first diode and the second diode is not greater than 0.3V, and the reverse withstand voltage is not less than 12V.
7. A self-driven low-dropout rectifier circuit according to any one of claims 2 to 4, characterized in that, The threshold voltage range of the first field-effect transistor, the second field-effect transistor, the third field-effect transistor, and the fourth field-effect transistor is 0.5V to 1.2V, and the on-resistance is not greater than 0.1Ω.
8. An electronic atomizer, characterized in that, Includes the self-driven low-dropout rectifier circuit and chip as described in any one of claims 1 to 7; The positive output terminal and the negative output terminal are connected to the chip.