Semiconductor structure

Abstract

A semiconductor structure includes a base fin located above a substrate; a first source / drain component and a second source / drain component located above the base fin; a plurality of nanostructures extending between the first source / drain component and the second source / drain component; a gate structure surrounding each of the plurality of nanostructures; and a plurality of inner spacer components interleaved with the plurality of nanostructures, each of the plurality of inner spacer components extending partially into the first source / drain component.

Description

Technical Field

[0001] This utility model relates to semiconductor technology, and more particularly to semiconductor structures. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in generations of ICs, each with smaller and more complex circuits than the previous one. Throughout the history of IC development, functional density (the number of interconnected devices per wafer area) has increased, while geometric dimensions (the smallest components or lines produced during manufacturing) have shrunk. This miniaturization of device size offers the benefits of increased production efficiency and reduced associated costs. However, this miniaturization has also increased the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology moves towards smaller technology nodes, multi-gate metal-oxide-semiconductor field-effect transistors (multi-gate MOSFETs) (or multi-gate devices) have been introduced to improve gate control by increasing gate channel coupling, reducing off-state current, and minimizing short-channel effects (SCEs). A multi-gate device generally refers to a device having a gate structure or part of a gate structure disposed above more than one facet of the channel region. The gate-all-around (GAA) transistor is an example of a multi-gate device and has become a popular and promising candidate for high-efficiency and low-leakage applications. A GAA transistor has a gate structure that can extend to partially or completely surround the channel region, providing a path to the channel region on two or more faces. Because the gate structure of a GAA transistor surrounds the channel region, it can also be called a surrounding-gate transistor (SGT) or a multi-bridge-channel (MBC) transistor. Utility Model Content

[0004] In some embodiments, a semiconductor structure is provided, the semiconductor structure including a base fin located above a substrate; a first source / drain component and a second source / drain component located above the base fin; a plurality of nanostructures extending between the first source / drain component and the second source / drain component; a gate structure surrounding each of the plurality of nanostructures; and a plurality of internal spacer wall components interleaved with the plurality of nanostructures, wherein each of the plurality of internal spacer wall components partially extends into the first source / drain component.

[0005] In some embodiments, each of the plurality of internal spacer wall components includes: a first internal spacer layer contacting at least one of the gate structure and the plurality of nanostructures; and a second internal spacer layer spaced apart from the gate structure and the plurality of nanostructures by the first internal spacer layer.

[0006] In some embodiments, the first inner spacer layer has a sidewall recess.

[0007] In some embodiments, the first source / drain component extends into the sidewall recess of the first internal spacer layer.

[0008] In some embodiments, the second inner spacer layer has a circular protrusion that protrudes toward the first source / drain component.

[0009] In some embodiments, the circular protrusion of the second inner spacer layer protrudes from the sidewall of each of the plurality of nanostructures.

[0010] In some embodiments, the first source / drain component includes a bottom epitaxial component and a main epitaxial component above the bottom epitaxial component.

[0011] In some embodiments, the plurality of internal spacer wall components are in direct contact with the main extension component.

[0012] In some embodiments, the main extension component is spaced apart from the base fin by the bottom extension component.

[0013] In some embodiments, the semiconductor structure further includes a gate spacer layer located on both sides of the gate structure and in direct contact with the sidewall of the first source / drain component. Attached Figure Description

[0014] The embodiments of this utility model can be better understood from the following detailed description and accompanying drawings. It should be noted that, according to industry standard practice, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity.

[0015] Figure 1This diagram shows a flowchart of a method for forming a semiconductor device according to one or more aspects of embodiments of the present invention.

[0016] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 According to one or more aspects of the embodiments of this utility model, based on Figure 1 The method is a partial cross-sectional schematic diagram of the work-in-progress (WIP) structure during the manufacturing process.

[0017] Figure 26 This illustrates one or more aspects of embodiments of the present utility model. Figure 17 An enlarged cross-sectional view of the internal spacer wall component.

[0018] Figure 27 This illustrates one or more aspects of embodiments of the present utility model. Figure 25 An enlarged cross-sectional view of the internal spacer wall component.

[0019] The reference numerals in the attached figures are explained as follows:

[0020] 100: Method

[0021] 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130: Boxes

[0022] 200: Semi-finished product structure

[0023] 202: Base

[0024] 204: Stacks

[0025] 206: Sacrifice Layer

[0026] 207: Semiconductor Pad

[0027] 208: Channel Layer

[0028] 212: Fin-like structure

[0029] 212B: Base fin structure

[0030] 212C: Passage Area

[0031] 212SD: Source / Drain Region

[0032] 214: Isolation component

[0033] 216: Dummy Dielectric Layer

[0034] 218: Dummy Electrode Layer

[0035] 220: Dummy gate stack

[0036] 222: Hard masking layer at the top of the gate

[0037] 223: Silicon oxide layer

[0038] 224: Silicon nitride layer

[0039] 226: Gate spacer layer

[0040] 228: Source / Drain Trench

[0041] 230: Virtual Layer

[0042] 232: Internal spacer wall notch

[0043] 234: First internal spacer layer

[0044] 235: Side wall notch

[0045] 236: Second inner spacer layer

[0046] 237: Circular protrusion

[0047] 240: Internal spacer wall component

[0048] 242: Bottom extension component

[0049] 244: Main epitaxial components

[0050] 244N: n-type main epitaxial component

[0051] 244P: p-type main epitaxial component

[0052] 246: Source / Drain Components

[0053] 246N: n-type source / drain component

[0054] 246P: p-type source / drain device

[0055] 247: Contact Etching Stop Layer

[0056] 248: Interlayer dielectric layer

[0057] 250: Gate structure

[0058] 2080: Channel Component

[0059] 2340: Side wall portion

[0060] A, B: Dashed boxes Detailed Implementation

[0061] It is important to understand that the following content provides many different embodiments or examples to implement different components of the provided subject. Specific examples of the various components and their arrangements are described below to simplify the explanation. Of course, these are merely examples and are not intended to limit the embodiments of this utility model. For example, the dimensions of the components are not limited to the range or values ​​of one embodiment disclosed, but may depend on the processing conditions and / or required nature of the components. Furthermore, the embodiments in the following description where the first component is formed above or on the second component include those where the first and second components are formed in direct contact, and may also include embodiments where additional components may be formed between the first and second components, such that the first and second components are not in direct contact. In addition, different examples in the disclosure may use repeated reference numerals and / or words. These repeated numerals or words are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures.

[0062] Furthermore, to facilitate the description of the relationship between one element or component and another (or multiple elements or components) in the diagram, spatially related terms such as "below," "under," "lower part," "above," "upper part," and similar terms may be used. In addition to the orientation shown in the diagram, spatially related terms also cover different orientations of the device during use or operation. The device may also be positioned elsewhere (e.g., rotated 90 degrees or located in other orientations), and the descriptions using the spatially related terms will be interpreted accordingly.

[0063] Furthermore, when using terms such as "approximately," "about," and similar terms to describe numbers or ranges of numbers, the purpose of these terms is to cover numbers within a reasonable range that takes into account variations inherent in the manufacturing process, as understood by those skilled in the art. For example, a number or range of numbers covers a reasonable range including, for example, within + / -10% of the described number, based on known manufacturing tolerances associated with manufacturing a part having the characteristics associated with that number. For example, a material layer having a thickness of "approximately 5 nm" could cover a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / -15%.

[0064] This article generally relates to fully wound gate transistors (FMTs) and their fabrication methods. FMTs can be manufactured using a gate replacement process, in which a dummy gate stack is first formed as a placeholder, and then the dummy gate stack is replaced with a functional gate structure. In some gate replacement processes, sacrificial material in the nanostructure of the FMT is removed after the epitaxial source / drain components are formed. During sacrificial material removal, internal spacer components are used to control the etching process to define the profile of the gate structure and protect the epitaxial source / drain components from etching. When the etch selectivity between the internal spacer components and the sacrificial material is unsatisfactory, the profile of the gate structure may be inconsistent, potentially damaging the epitaxial source / drain components.

[0065] This invention provides a method for forming a fully wrapped gate transistor. In an exemplary process, a fin structure having a channel layer and a sacrificial layer is formed over a substrate. After a dummy gate stack is formed over the channel region of the fin structure, at least one gate spacer is formed over the dummy gate stack. The source / drain regions of the fin structure are recessed. The sacrificial layer is selectively removed to release the channel layer as a channel element. Next, a dielectric dummy layer is deposited to surround each channel element. Then, the dielectric dummy layer is selectively and partially recessed to form internal spacer recesses between the multiple channel elements. A first internal spacer layer and a second internal spacer layer are sequentially deposited over the internal spacer recesses. The first internal spacer layer may comprise alumina, polyethylene, polypropylene, or a boron-containing dielectric layer. The second internal spacer layer may comprise silicon carbide, silicon oxynitride, silicon nitride, silicon carbide, or silicon oxynitride. The first and second internal spacer layers are etched back to form internal spacer components. Etching back can etch the first internal spacer layer faster than etching the second internal spacer layer, causing the second internal spacer layer to protrude towards the source / drain notch. Next, source / drain components are formed above the source / drain notch. After selective removal of the dummy gate stack, the dummy layer is selectively removed to release the channel elements again. Then, a gate structure is formed to surround each channel element. The composition of the first internal spacer layer is selected such that when the dummy layer is etched away, the first internal spacer layer is essentially not etched.

[0066] Various aspects of embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This diagram illustrates a flowchart of a method 100 for forming a semiconductor structure from a work-in-process (WIP) structure, according to one or more aspects of embodiments of the present invention. Method 100 is merely exemplary and is not intended to limit the embodiments of the present invention to what is explicitly shown in method 100. Additional steps may be provided before, during, and after method 100, and for additional embodiments of the method, some described steps may be substituted, eliminated, or moved. For simplicity, not all steps are described in detail herein. The following is in conjunction with… Figures 2 to 26 Description method 100, Figures 2 to 26 Based on Figure 1 This is a partial cross-sectional schematic diagram of the semi-finished structure 200 at different stages of manufacturing, as described in an embodiment of the method. Since the semi-finished structure 200 will be manufactured as a semiconductor structure or semiconductor device, it may be referred to herein as a semiconductor structure or semiconductor device, depending on the context. For the avoidance of ambiguity, Figures 2 to 26 The X, Y, and Z directions are perpendicular to each other. In this document, unless otherwise explicitly stated, the same reference numerals are used to label the same parts or steps.

[0067] Please refer to Figure 1 and Figure 2Method 100 includes block 102, wherein a stack 204 of interlaced semiconductor layers is formed over a semi-finished structure 200. (As...) Figure 2 As shown, the semi-finished structure 200 includes a substrate 202. In some embodiments, the substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. The substrate 202 may include various doping configurations depending on design requirements known in the art. In embodiments where the semiconductor device is p-type, an n-type doped profile (i.e., an n-type well or n-well region) may be formed on the substrate 202. In some embodiments, the n-type dopant used to form the n-type well may include phosphorus (P), arsenic (As), or antimony (Sb). In embodiments where the semiconductor device is n-type, a p-type doped profile (i.e., a p-type well or p-well region) may be formed on the substrate 202. In some embodiments, the p-type dopant used to form the p-type well may include boron (B) or gallium (Ga). Suitable doping may include ion implantation and / or diffusion processes of the dopant. The substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), germanium tin (GeSn), or diamond. Alternatively, the substrate 202 may include compound semiconductors and / or alloy semiconductors. Furthermore, the substrate 202 may optionally include an epitaxial layer, which may be strained for performance enhancement, and may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure and / or have other suitable reinforcing components.

[0068] In some embodiments, the stack 204 above the substrate 202 includes an interleaved channel layer 208 composed of a first semiconductor and a sacrificial layer 206 composed of a second semiconductor. Alternatively, the sacrificial layer 206 and the channel layer 208 may be interleaved. The first semiconductor composition and the second semiconductor composition may be different. In some embodiments, the sacrificial layer 206 comprises silicon-germanium (SiGe) or germanium-tin (GeSn), and the channel layer 208 comprises silicon (Si). It should be noted that... Figure 2 The diagram shows three sacrificial layers 206 and three channel layers 208 arranged in an alternating pattern. This is for illustrative purposes only and is not intended to limit the scope beyond the specific description in the claims. It should be understood that any number of epitaxial layers may be formed in the stack 204. The number of epitaxial layers depends on the number of channel elements desired for use in the semiconductor device. In some embodiments, the number of channel layers 208 is between two and ten.

[0069] The sacrificial layer 206 and channel layer 208 in stack 204 can be deposited using molecular beam epitaxy (MBE), vapor phase deposition (VPE), and / or other suitable epitaxial growth processes. As described above, in at least some examples, the sacrificial layer 206 comprises an epitaxially grown silicon-germanium (SiGe) layer, and the channel layer 208 comprises an epitaxially grown silicon (Si) layer. In some embodiments, the sacrificial layer 206 and channel layer 208 are substantially doped (i.e., having an external doping concentration from about 0 atoms / cm). 3 To approximately 1x10 17 atoms / cm 3 For example, no deliberate doping was performed during the epitaxial growth process of stack 204.

[0070] Please refer to Figure 1 and Figure 3 Method 100 includes block 104, wherein a fin structure 212 is formed from a stack 204 and a substrate 202. To pattern the stack 204, a hard mask layer may be deposited over the stack 204 to form an etch mask. The hard mask layer may be a single layer or multiple layers. For example, the hard mask layer may include a pad oxide layer and a pad nitride layer disposed above the pad oxide layer. The fin structure 212 may be patterned from the stack 204 and the substrate 202 using lithography and etching processes. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., reactive ion etching), wet etching, and / or other etching methods. Figure 3 As shown, the etching process of box 104 forms a trench extending vertically through a portion of the stack 204 and the substrate 202. The trench defines a fin structure 212. In some embodiments, a dual patterning or multiple patterning process can be used to define the fin structure to create a fin structure with a smaller pitch, for example, a fin structure with a smaller pitch than that achievable using a single direct photolithography process. For example, in one embodiment, a material layer is formed over the substrate and patterned using a photolithography process. Spacers are formed next to the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrel can then be used to pattern the fin structure 212 by etching a portion of the stack 204 and the substrate 202. Figure 3 As shown, the fin structure 212, comprising the sacrificial layer 206 and the channel layer 208, extends vertically along the Z direction and longitudinally along the X direction. Figure 3As shown, the fin structure 212 includes a base fin structure 212B patterned from the base 202 and a patterned stack 204 disposed directly above the base fin structure 212B.

[0071] Please refer to Figure 1 and Figure 3 Method 100 includes block 106, wherein an isolation member 214 is formed around a base fin structure 212B of a fin structure 212. Figure 3 In some embodiments, the isolation member 214 is disposed on the sidewall of the base fin structure 212B. In some embodiments, the isolation member 214 may be formed in a trench to isolate the fin structure 212 from the adjacent fin structure. The isolation member 214 may also be referred to as a shallow trench isolation (STI) member. For example, in some embodiments, a dielectric layer is first deposited over the substrate 202 to fill the trench. In some embodiments, the dielectric layer may comprise silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low dielectric constant dielectric, a combination of the foregoing, and / or other suitable materials. In various examples, the dielectric layer may be deposited using chemical vapor deposition (CVD), subatmospheric CVD (SACVD), flowable CVD (FCVD), spin coating, and / or other suitable processes. Next, the deposited dielectric material is thinned and planarized, for example, using a chemical mechanical polishing (CMP) process. The planarized dielectric layer is then further recessed or pulled back using dry etching, wet etching, and / or a combination thereof to form... Figure 3 The isolation member 214 is shown. After the recess, the fin structure 212 protrudes from the isolation member 214, while the base fin structure 212B is embedded or hidden in the isolation member 214.

[0072] Please refer to Figure 1 and Figure 4Method 100 includes block 108, wherein a semiconductor pad 207 is deposited over a fin structure 212. After the isolation member 214 is formed, the semiconductor pad 207 may be deposited over the pre-finished structure 200, including over the isolation member 214, over the top surface of the fin structure 212, and over the sidewalls of the fin structure 212. The semiconductor pad 207 serves to protect the sidewalls of the sacrificial layer 206, as the sacrificial layer 206 may suffer unintended damage during manufacturing. In some embodiments, the semiconductor pad 207 may comprise silicon (Si). In some embodiments, the semiconductor pad 207 may be deposited using physical vapor deposition (PVD), chemical vapor deposition, or atomic layer deposition (ALD).

[0073] Please refer to Figure 1 , Figure 5 , Figure 6 Method 100 includes block 110, wherein a dummy gate stack 220 is formed over the channel region 212C of the fin structure 212. The dummy gate stack 220 serves as a placeholder to undergo various processes and will be removed and replaced by a functional gate structure. Other processes and configurations may be possible. Figure 6 In some embodiments shown, a dummy gate stack 220 is formed above the fin structure 212, and the fin structure 212 can be divided into a channel region 212C below the dummy gate stack 220 and a source / drain region 212SD not below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. Figure 6 As shown, the channel region 212C is disposed between the two source / drain regions 212SD along the X direction.

[0074] The formation of the dummy gate stack 220 includes depositing layers in the dummy gate stack 220 and patterning these layers. Please refer to... Figure 5A dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 can be blanket-deposited over the pre-finished structure 200. The dummy dielectric layer 216 can be formed on the fin structure 212 using chemical vapor deposition (CVD), atomic layer deposition (ALD), oxygen plasma oxidation (OPO), or other suitable processes. In the illustrated embodiment, the dummy dielectric layer 216 can be formed using an OPO process that substantially oxidizes the semiconductor pad 207 to form the dummy dielectric layer 216. In some examples, the dummy dielectric layer 216 may comprise silicon oxide. Subsequently, the dummy electrode layer 218 can be deposited over the dummy dielectric layer 216 using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable processes. In some examples, the dummy electrode layer 218 may comprise polysilicon. For patterning purposes, the gate top hard mask layer 222 can be deposited on the dummy electrode layer 218 using a chemical vapor deposition process, an atomic layer deposition process, or other suitable processes. Then, the gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 can be patterned to form a dummy gate stack 220, such as... Figure 6 As shown. For example, the patterning process may include lithography (e.g., photolithography or electron beam lithography) and etching. The lithography process may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. The photolithography process forms a patterned photoresist layer. Then, in the etching process, the patterned photoresist layer is used as an etching mask to pattern the gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216. In some embodiments, the etching process may include dry etching (e.g., reactive ion etching), wet etching, and / or other etching methods. In some embodiments, the gate top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 above the silicon oxide layer 223. Figure 6 As shown, the dummy gate stack 220 is patterned such that the dummy gate stack 220 is disposed only above the channel region 212C, and not above the source / drain region 212SD.

[0075] Please refer to Figure 1 and Figure 7Method 100 includes block 112, wherein a gate spacer layer 226 is deposited over a semi-finished structure 200, including deposition over a dummy gate stack 220. In some embodiments, the gate spacer layer 226 is compliantly deposited over the semi-finished structure 200, including deposition over the top surface and sidewalls of the dummy gate stack 220. The term “compliant” may be used herein to conveniently describe layers having a generally uniform thickness over various regions. The gate spacer layer 226 may be a single layer or multiple layers. At least one layer of the gate spacer layer 226 may comprise silicon carbide, silicon oxycarbide, silicon oxycarbide, or silicon nitride. The gate spacer layer 226 may be deposited over the dummy gate stack 220 using processes such as chemical vapor deposition, sub-atmospheric chemical vapor deposition (SACVD), atomic layer deposition, or other suitable processes.

[0076] Please refer to Figure 1 , Figure 8 , Figure 9 Method 100 includes block 114, wherein the source / drain regions 212SD of the anisotropic recessed fin structure 212 are formed to create a source / drain trench 228. The anisotropic etching may include dry etching or a suitable etching process that etches the source / drain regions 212SD and a portion of the substrate 202. The formed source / drain trench 228 extends vertically through the depth of the stack 204 and partially into the substrate 202. An exemplary dry etching process for block 114 may use oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma and / or combinations thereof. Figure 8 As shown, the source / drain region 212SD of the fin structure 212 is recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. Since the source / drain trench 228 extends below the stack 204 and into the substrate 202, the source / drain trench 228 includes a bottom surface and underlying sidewalls defined in the substrate 202. Please refer to... Figure 9 , Figure 9 This includes a partial cross-sectional schematic diagram of the 212SD region spanning two adjacent source / drain regions. (See attached diagram.) Figure 9 As shown, most of the fin structure 212 is etched away above the source / drain region 212SD, and the top surface of the base fin structure 212B is exposed in the source / drain region 212SD. Since the etching rate of the gate spacer layer 226 is less than the etching rate of the fin structure 212, the gate spacer layer 226 in the source / drain region 212SD protrudes above the top surface of the base fin structure 212B.

[0077] Please refer to Figure 1 , Figure 10 , Figure 11 Method 100 includes block 116, wherein a plurality of channel layers 208 in the release channel region serve as channel elements 2080. After forming the source / drain trench 228, sacrificial layers 206 interleaved with the channel layers 208 in the channel region 212C are selectively removed. The selective removal of sacrificial layers 206 releases the channel layers 208. Figure 8 (as shown), to form Figure 10 The channel element 2080 is shown. Selective removal of the sacrificial layer 206 forms spaces between and around adjacent channel elements 2080. Selective removal of the sacrificial layer 206 can be performed by selective dry etching, selective wet etching, or other selective etching processes. An example selective dry etching process may involve using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An example selective wet etching process may involve etching with an ammonium hydroxide-hydrogen peroxide-water mixture (APM). Please refer to... Figure 11 In box 116, the base fin structure 212B in the source / drain region 212SD is not etched.

[0078] Please refer to Figure 1 , Figure 12 , Figure 13 Method 100 includes block 118, wherein a dummy layer 230 is deposited around the channel element 2080 and over the source / drain trench 228. The dummy layer 230 may comprise silicon oxide and can be deposited using plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition. Figure 12 As shown, the dummy layer 230 fills the space between the channel elements 2080 and covers the sidewalls at both ends of the channel elements 2080. Furthermore, the dummy layer 230 directly contacts the sidewalls of the gate spacer layer 226 and the top surface of the substrate 202. Please refer to... Figure 13 , Figure 13 This includes a partial cross-sectional schematic diagram of the 212SD region spanning two adjacent source / drain regions. (See attached diagram.) Figure 13 As shown, the dummy layer 230 extends compliantly above the isolation member 214, the sidewalls of the gate spacer layer 226, and the top surface of the gate spacer layer 226. Depending on the design, the channel element 2080 may take the form of nanowires, nanosheets, or other nanostructures.

[0079] Please refer to Figure 1 and Figure 14 Method 100 includes a box 120 in which an internal gap wall recess 232 is formed. Please refer to... Figure 14The dummy layer 230 is selectively and partially recessed to form an internal spacer wall notch 232, while the gate spacer layer 226, the dummy gate stack 220, the exposed portion of the substrate 202, and the channel layer 208 are largely left unetched. In one embodiment, where the channel layer 208 is primarily composed of silicon (Si) and the dummy layer 230 is formed of silicon oxide, the selective recessing of the dummy layer 230 can be performed using a selective wet etching process or a selective dry etching process. An exemplary selective dry etching process may include the use of carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), hydrogen (H2), or a mixture thereof. An exemplary selective wet etching process may include the use of hydrofluoric acid, ammonium fluoride, or a mixture thereof.

[0080] Please refer to Figure 1 and Figure 15 Method 100 includes block 122, wherein a first internal spacer layer 234 is deposited over an internal spacer wall recess 232. According to an embodiment of the present invention, the first internal spacer layer 234 is formed of a material that is substantially not etched when the dummy layer 230 is removed. That is, the first internal spacer layer 234 is formed of a material that allows selective removal of the dummy layer 230. In some embodiments, the first internal spacer layer 234 comprises a metal oxide, such as polycrystalline alumina. Since the dummy layer 230 is formed of silicon oxide, removal of the dummy layer 230 in subsequent steps may involve the use of hydrofluoric acid or hydrogen fluoride. It has been observed that crystalline or polycrystalline alumina undergoes slow etching with hydrofluoric acid. When the first internal spacer layer 234 comprises polycrystalline alumina, the polycrystalline alumina can be deposited using atomic layer deposition (ALD). In some embodiments, an annealing process may be performed after deposition of the first internal spacer layer 234 to increase the crystallinity of the first internal spacer layer 234. Since the source / drain components and gate structure have not yet been formed at this stage, the annealing process is unlikely to cause any adverse side effects, such as changes in the doping profile or a shift in the critical voltage. In some examples, the annealing process may involve annealing temperatures between about 200°C and about 500°C. When the first internal spacer layer 234 comprises polycrystalline alumina, the first internal spacer layer 234 has a dielectric constant between about 8 and about 9.5.

[0081] In some alternative embodiments, the first internal spacer layer 234 comprises a polymeric material, such as polyethylene (PE) or polypropylene (PP). While polymeric materials may be susceptible to dry etching involving plasma, they can be quite resistant to acids, such as hydrofluoric acid used to etch the dummy layer 230. In these embodiments, to deposit the polymeric material over the semi-finished structure 200, the surface of the semi-finished structure 200 may be plasma-treated to increase the number of dangling hydroxyl bonds on the surface. In some cases, the plasma treatment may involve the use of oxygen plasma. After the surface plasma treatment, monomers of the polymeric material (e.g., ethylene or propylene) are brought into contact with and reacted with the dangling bonds in the presence of at least one catalyst. In one exemplary process, a first catalyst is first used to promote the reaction between the monomers and the dangling bonds, and then a second catalyst is used to promote the polymerization of the monomers. When the first internal spacer layer 234 comprises polyethylene or polypropylene, the first internal spacer layer 234 has a dielectric constant between about 2.2 and about 2.6.

[0082] In some alternative embodiments, the first inner spacer layer 234 comprises a boron-containing dielectric material, such as boron carbon nitride oxide (BCNO) or boron-doped silicon carbon nitride oxide (B-SiOCN). In these embodiments, the boron content enables the boron-containing dielectric material to resist the chemical reaction of etching the dummy layer 230. Furthermore, boron carbon nitride oxide (BCNO) may have a dielectric constant between about 1.2 and about 3.7, which is beneficial for reducing parasitic capacitance. In some embodiments, when the first inner spacer layer 234 comprises a boron-containing dielectric material, the first inner spacer layer 234 may be deposited using chemical vapor deposition (CVD) or atomic layer deposition.

[0083] Please refer to Figure 1 and Figure 16Method 100 includes block 124, wherein a second internal spacer layer 236 is deposited over an internal spacer wall recess 232. In block 124, the second internal spacer layer 236 is deposited over a first internal spacer layer 234. The composition of the second internal spacer layer 236 is selected such that the etch-back operation of subsequent blocks 126 etches the second internal spacer layer 236 at a rate less than the etch-back rate of the first internal spacer layer 234. In some embodiments, the second internal spacer layer 236 may comprise silicon carbide (SiCN), silicon oxynitride (SiOCN), silicon nitride (SiN), silicon oxycarbide (SiOC), or silicon oxynitride (SiON). In some embodiments, the second internal spacer layer 236 may be deposited using chemical vapor deposition or atomic layer deposition. The second internal spacer layer 236 may have a dielectric constant between about 3.5 and about 6. When the first internal spacer layer 234 comprises polycrystalline alumina, the dielectric constant of the second internal spacer layer 236 is less than the dielectric constant of the first internal spacer layer 234. However, when the first inner spacer layer 234 comprises boron carbon nitride, polyethylene, polypropylene, or other polymer materials, the dielectric constant of the second inner spacer layer 236 is greater than that of the first inner spacer layer 234. When the first inner spacer layer 234 comprises boron-doped nitrogen carbon nitride, the dielectric constant of the second inner spacer layer 236 may be approximately similar to that of the first inner spacer layer 234.

[0084] Please refer to Figure 1 , Figure 17 , Figure 18 Method 100 includes block 126, wherein a first internal spacer layer 234 and a second internal spacer layer 236 are etched back to form an internal spacer wall component 240 over an internal spacer wall recess 232. Please refer to... Figure 17 The first internal spacer layer 234 and the second internal spacer layer 236 are etched back to expose the sidewalls of the channel element 2080, thereby forming an internal spacer wall component 240 in the internal spacer wall recess 232. In some embodiments, the etch back of block 126 may include the use of a dry etching process, such as a plasma-assisted reactive ion etching (RIE) process. An exemplary dry etching process may include the use of boron trifluoride (BCl3), chlorine (Cl2), hydrogen chloride (HCl), methane (CH4), nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen (N2), or a combination thereof. Figure 17As shown, although the dry etching process exhibits some degree of anisotropy, it etches the first internal spacer layer 234 at a greater rate. For example, when the first internal spacer layer 234 comprises polycrystalline alumina, chlorination chemicals (such as boron trifluoride (BCl3), chlorine (Cl2), and hydrogen chloride (HCl)) etch the first internal spacer layer 234 at a greater rate than the second internal spacer layer 236. When the first internal spacer layer 234 comprises polyethylene (PE) or polypropylene (PP), the plasma energy causes dry etching to etch the first internal spacer layer 234 at a greater rate than the second internal spacer layer 236. When the first internal spacer layer 234 comprises a boron-containing dielectric material, fluorine-containing chemicals (such as nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), and sulfur hexafluoride (SF6)) etch the first internal spacer layer 234 at a greater rate than the second internal spacer layer 236. This difference in etching rate can lead to over-etching of the first internal spacer layer 234 and under-etching of the second internal spacer layer 236. In at least some embodiments, each internal spacer wall component 240 may have Figure 26 The cross-sectional profile shown. The dashed box A represents... Figure 26 The following are one or more aspects of the embodiments of the present utility model. Figure 17 An enlarged cross-sectional view of the internal spacer wall component 240 is shown below. Please refer to... Figure 26 Over-etching of the first internal spacer layer 234 can form a sidewall notch 235. In some examples, the sidewalls of the first internal spacer layer 234 do not extend to be flush with the sidewalls of the channel element 2080. Insufficient etching of the second internal spacer layer 236 can form a source / drain trench 228 (shown in...). Figure 14 A circular protrusion 237 extending from the center. When the formation of the source / drain components (described below) involves both deposition and etching elements, the circular protrusion 237 provides additional protection and buffering in case the etching element removes excessive internal spacer wall components 240. Please refer to... Figure 18 , Figure 18 This includes a partial cross-sectional schematic diagram of the 212SD region spanning two adjacent source / drain regions. (See attached diagram.) Figure 18 As shown, back etching may not completely remove the sidewall portion 2340 of the first inner spacer layer 234 extending along the sidewall of the isolation member 214.

[0085] Please refer to Figure 1 , Figure 19 , Figure 20Method 100 includes block 128, wherein a source / drain component 246 is formed over the source / drain region 212SD. Although not explicitly shown, method 100 may include a cleaning process to clean the surface of the semi-finished structure 200 before forming any epitaxial layer. The cleaning process may include dry cleaning, wet cleaning, or a combination thereof. In some examples, wet cleaning may include the use of deionized (DI) water, a mixture of ammonium hydroxide and hydrogen peroxide, a mixture of deionized water, hydrochloric acid and hydrogen peroxide, a sulfur peroxide mixture (SPM), and hydrofluoric acid for oxide removal. A dry cleaning process may include helium (He) and hydrogen (H2) treatment. Cleaning may convert silicon on the surface into silane (SiH4), which can then be extracted and removed.

[0086] Please refer to Figure 19 In some embodiments, the source / drain component 246 includes a bottom epitaxial component 242 and a primary epitaxial component 244 above the bottom epitaxial component 242. The source / drain component 246 may be n-type or p-type. When the source / drain component 246 is n-type, the bottom epitaxial component 242 may include undoped silicon (Si) or undoped silicon germanium (SiGe), and the primary epitaxial component 244 may include silicon (Si) and an n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. When the source / drain component 246 is p-type, the bottom epitaxial component 242 may include undoped silicon (Si) or undoped silicon germanium (SiGe), and the primary epitaxial component 244 may include silicon germanium (SiGe) and a p-type dopant, such as boron (B), boron difluoride (BF2), or a combination thereof. As used herein, undoped semiconductor materials are considered undoped when there is no intentional doping. In some alternative embodiments, the bottom epitaxial component 242 may contain an anti-dopermeable material to reduce leakage current into the bulk substrate 202. For example, the bottom epitaxial component 242 in an n-type source / drain component may contain a p-type dopant, such as boron (B). As another example, the bottom epitaxial component 242 in a p-type source / drain component may contain an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). The source / drain component 246 may be formed using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or molecular beam epitaxy (MBE). Doping of the source / drain component 246 may be achieved through in-situ doping.

[0087] Please refer to Figure 20 , Figure 20 This is a partial cross-sectional schematic diagram of a 212SD transistor spanning two adjacent source / drain regions. Figure 20In some of the presented embodiments, the n-type source / drain component 246N may be adjacent to the p-type source / drain component 246P. The n-type source / drain component 246N includes a bottom epitaxial component 242 and an n-type main epitaxial component 244N. The n-type main epitaxial component 244N may include silicon (Si) and an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). The p-type source / drain component 246P includes a bottom epitaxial component 242 and a p-type main epitaxial component 244P. The p-type main epitaxial component 244P may include silicon germanium (SiGe) and a p-type dopant, such as boron (B). The n-type source / drain component 246N and the p-type source / drain component 246P may each directly contact the top surface of the base fin structure 212B and the sidewall of the gate spacer layer 226. For ease of display and description, the n-type source / drain device 246N and the p-type source / drain device 246P can be collectively referred to as source / drain device 246, such as Figure 19 As shown.

[0088] Please refer to Figure 1 and Figures 21 to 25 Method 100 includes block 130, wherein a gate structure 250 replaces the dummy gate stack 220 and the dummy layer 230. Operation of block 130 may include depositing a contact etch stop layer (CESL) 247 (shown in...) over the source / drain components 246. Figure 21 An interlayer dielectric layer 248 (shown in) is deposited above the contact etch stop layer 247. Figure 21 Remove dummy gate stack 220 (shown in) Figure 22 Remove dummy layer 230 (displayed in) Figure 23 and Figure 24 ), and deposited gate structure 250 to surround each channel element 2080 (shown in Figure 25 Please refer to... Figure 21A contact etch stop layer 247 is deposited over the pre-finished structure 200, including a layer deposited over the source / drain components 246. The contact etch stop layer 247 may comprise silicon nitride or aluminum nitride. In some embodiments, the contact etch stop layer 247 may be deposited using chemical vapor deposition or atomic layer deposition (ALD). Next, an interlayer dielectric layer 248 is deposited over the contact etch stop layer 247. In some embodiments, the interlayer dielectric layer 248 comprises materials such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or undoped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. The interlayer dielectric layer 248 may be deposited using chemical vapor deposition, flowable chemical vapor deposition (FCVD), spin coating, or suitable deposition techniques. After depositing the interlayer dielectric layer 248, the pre-formed structure 200 can be planarized using a planarization process to expose the dummy gate stack 220. For example, the planarization process may include a chemical mechanical polishing (CMP) process. Exposing the dummy gate stack 220 allows for its removal. Removal of the dummy gate stack 220 may include one or more etching processes selectively targeting the material of the dummy gate stack 220. For example, removal of the dummy gate stack 220 may be performed using selective wet etching, selective dry etching, or a combination thereof.

[0089] After removing the dummy gate stack 220, the dummy layer 230 in the channel region 212C is exposed. Individual etching processes can be performed to selectively remove the dummy layer 230 in the channel region 212C. For example, selective wet etching or selective dry etching processes can be performed to remove the dummy layer 230. An example selective wet etching process may include using diluted hydrofluoric acid (DHF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F). An example selective dry etching process may include using anhydrous hydrogen fluoride (HF) vapor, trifluoromethane (CHF3), nitrogen trifluoride (NF3), hydrogen (H2), ammonia (NH3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), or a combination thereof. As described above, the step of selectively etching the dummy layer 230 etches the first internal spacer layer 234 at a slower rate. After selectively removing the dummy layer 230, the channel element 2080 in the channel region 212C is exposed again, such as Figure 23 and Figure 24 As shown.

[0090] After the channel element 2080 is released, a gate structure 250 is formed to surround each channel element 2080, such as... Figure 25 As shown. The dashed box B represents... Figure 27 The following are one or more aspects of the embodiments of the present utility model. Figure 25 An enlarged cross-sectional view of the internal spacer wall component 240 is shown. Although not explicitly shown, the gate structure 250 includes an interface layer in contact with the substrate 202 in the channel element 2080 and channel region 212C, a gate dielectric layer above the interface layer, and a gate electrode layer above the gate dielectric layer. The interface layer may contain a dielectric material, such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may contain a high dielectric constant dielectric material, such as hafnium oxide. Alternatively, the gate dielectric layer may comprise other high-dielectric-constant dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable materials. The gate dielectric layer may be formed by atomic layer deposition, physical vapor deposition (PVD), chemical vapor deposition, oxidation, and / or other suitable methods.

[0091] The gate electrode layer of gate structure 250 may comprise a multilayer structure, such as various combinations of metal layers with selected work functions to enhance device performance (work function metal layers), pad layers, wetting layers, adhesive layers, metal alloys, or metal silicides. For example, the gate electrode layer may comprise titanium nitride (TiN), aluminum titanium nitride (TiAl), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum nitride (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), but tantalum carbide (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), silicon tantalum nitride (TaSiN), copper (Cu), other refractory metals, other suitable metallic materials, or combinations thereof. In various embodiments, the gate electrode layer may be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable processes. In various embodiments, a chemical mechanical polishing process may be performed to remove excess metal, thereby providing a generally flat top surface of the gate structure. Gate structure 250 includes portions disposed between channel elements 2080 in channel region 212C. In some embodiments, gate structure 250 may include a p-type gate structure portion and an n-type gate structure portion. The p-type gate structure portion includes a p-type work function metal layer disposed closer to the channel element 2080. The n-type gate structure portion includes an n-type work function metal layer disposed closer to the channel element 2080.

[0092] In one exemplary aspect, embodiments of the present invention relate to a method comprising: forming a stack over a substrate, the stack including a plurality of staggered channel layers and a plurality of sacrificial layers; patterning the stack and the substrate to form a fin structure having a base portion formed by the substrate and a stack portion formed by the stack; forming an isolation member around the base portion; forming a dummy gate stack over the channel regions of the fin structure; depositing a gate spacer layer over the dummy gate stack; after depositing the gate spacer layer, recessing the source / drain regions of the fin structure; and selectively removing the plurality of sacrificial layers in the channel regions to... The process involves: releasing multiple channel layers as multiple channel elements; depositing dummy layers over the multiple channel elements; selectively and partially recessing the dummy layers to form internal spacer recesses between the multiple channel elements; depositing a first internal spacer layer over the internal spacer recesses; depositing a second internal spacer layer over the first internal spacer layer; etching back the first and second internal spacers to form internal spacer components in the internal spacer recesses; forming source / drain components over the source / drain regions; removing the dummy gate stack; removing the dummy layers; and forming a gate structure to surround each of the multiple channel elements.

[0093] In some embodiments, the etch-back step etches the first inner spacer layer at a rate greater than the etch-back rate of the second inner spacer layer. In some embodiments, the second inner spacer layer comprises silicon carbide, silicon oxynitride, silicon nitride, silicon oxycarbide, or silicon oxynitride. In some embodiments, the first inner spacer layer comprises boron carbon oxynitride or boron-doped silicon oxynitride. In some embodiments, the first inner spacer layer comprises aluminum oxide. In some examples, the first inner spacer layer comprises a boron-containing dielectric layer. In some embodiments, the first inner spacer layer comprises polyethylene or polypropylene. In some embodiments, the step of depositing the first inner spacer layer comprises: processing the surfaces of a plurality of channel elements, a substrate, and a dummy layer to form a plurality of dangling bonds; and reacting a precursor monomer with the plurality of dangling bonds.

[0094] In another aspect, embodiments of the present invention relate to a method comprising: forming a stack over a substrate, the stack comprising a plurality of interleaved silicon layers and a plurality of silicon-germanium layers; patterning the stack and the substrate to form a fin structure having a base portion formed by the substrate and a stack portion formed by the stack; forming an isolation member around the base portion; forming a dummy gate stack over a channel region of the fin structure; depositing a gate spacer layer over the dummy gate stack; after depositing the gate spacer layer, recessing the source / drain regions of the fin structure; selectively removing a plurality of silicon-germanium layers in the channel region to release a plurality of A silicon layer serves as multiple channel elements; a semiconductor oxide layer is deposited over the multiple channel elements; the semiconductor oxide layer is selectively and partially recessed to form internal spacer recesses between the multiple channel elements; a first internal spacer layer is deposited over the internal spacer recesses; a second internal spacer layer is deposited over the first internal spacer layer; the first and second internal spacers are etched back to form internal spacer components in the internal spacer recesses; source / drain components are formed over the source / drain regions; a dummy gate stack is removed; the semiconductor oxide layer is removed; and a gate structure is formed to surround each of the multiple channel elements.

[0095] In some embodiments, the second inner spacer layer comprises silicon carbide, silicon carbon oxynitride, silicon nitride, silicon carbide, or silicon oxynitride. In some embodiments, the first inner spacer layer comprises a boron-containing dielectric layer. In some embodiments, the boron-containing dielectric layer comprises boron carbon oxynitride or boron-doped silicon carbon oxynitride. In some embodiments, the dielectric constant of the first inner spacer layer is less than the dielectric constant of the second inner spacer layer. In some embodiments, the etch-back step etches the first inner spacer layer at a rate greater than the etch rate of the second inner spacer layer.

[0096] In another aspect, embodiments of the present invention relate to a semiconductor structure comprising a base fin located above a substrate; a first source / drain component and a second source / drain component located above the base fin; a plurality of nanostructures extending between the first source / drain component and the second source / drain component; a gate structure surrounding each of the plurality of nanostructures; and a plurality of internal spacer wall components interspersed with the plurality of nanostructures, each of the plurality of internal spacer wall components partially extending into the first source / drain component.

[0097] In some embodiments, each of the plurality of internal spacer wall components includes: a first internal spacer layer contacting at least one of the gate structure and the plurality of nanostructures; and a second internal spacer layer spaced apart from the gate structure and the plurality of nanostructures by the first internal spacer layer. In some embodiments, the second internal spacer layer comprises silicon carbide, silicon carbon oxynitride, silicon nitride, silicon carbon oxynitride, or silicon oxynitride. In some embodiments, the first internal spacer layer comprises boron carbon oxynitride or boron-doped silicon carbon oxynitride. In some embodiments, the first internal spacer layer comprises aluminum oxide. In some examples, the first internal spacer layer comprises polyethylene or polypropylene.

[0098] The foregoing outlines the features of numerous embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: A base fin, located above a base; A first source / drain component and a second source / drain component are located above the base fin; Multiple nanostructures extend between the first source / drain component and the second source / drain component; A gate structure surrounds each of the plurality of nanostructures; as well as Multiple internal spacer wall components are interspersed with the multiple nanostructures, wherein a portion of each of the multiple internal spacer wall components extends into the first source / drain component.

2. The semiconductor structure as described in claim 1, characterized in that, Each of the plurality of internal spacer wall components includes: A first internal spacer layer, contacting at least one of the gate structure and the plurality of nanostructures; and A second internal spacer layer is spaced apart from at least one of the gate structure and the plurality of nanostructures by the first internal spacer layer.

3. The semiconductor structure as described in claim 2, characterized in that, The first internal spacer layer has a sidewall notch.

4. The semiconductor structure as described in claim 3, characterized in that, The first source / drain component extends into the sidewall recess of the first internal spacer layer.

5. The semiconductor structure as described in claim 2, characterized in that, The second internal spacer layer has a circular protrusion that extends toward the first source / drain component.

6. The semiconductor structure as described in claim 5, characterized in that, The circular protrusion of the second inner spacer layer protrudes from the sidewall of each of the plurality of nanostructures.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that, The first source / drain component includes a bottom epitaxial component and a main epitaxial component above the bottom epitaxial component.

8. The semiconductor structure as described in claim 7, characterized in that, The multiple internal spacer wall components are in direct contact with the main extension component.

9. The semiconductor structure as described in claim 7, characterized in that, The main extension component is separated from the base fin by the bottom extension component.

10. The semiconductor structure according to any one of claims 1 to 6, characterized in that, Including: A gate spacer layer is located on both sides of the gate structure and directly contacts the sidewall of the first source / drain component.

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