A package structure of a memory chip

By employing a layered stacking structure and molding encapsulation technology in memory chip packaging, the problems of high integration and reliability have been solved, production costs have been reduced, and signal transmission quality and storage performance have been improved.

CN224521678UActive Publication Date: 2026-07-17JIANGSU JINGKAI SEMICON TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
JIANGSU JINGKAI SEMICON TECH CO LTD
Filing Date
2025-08-11
Publication Date
2026-07-17

AI Technical Summary

Technical Problem

Existing memory chip packaging technologies are insufficient to meet the requirements for high integration, yield, and reliability, while also incurring high production costs.

Method used

A layered stacking structure is adopted, in which volatile memory chips and non-volatile memory chips are respectively placed on different sides of the substrate and in the grooves. They are electrically connected by connectors and encapsulated by molding. The encapsulation layer is formed by molding and the circuit connection is achieved by solder balls, which optimizes the signal transmission path and structural strength.

Benefits of technology

It improves the integration and reliability of the packaging structure, reduces production costs, and enhances signal transmission quality and anti-interference capabilities, thus ensuring storage performance.

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Abstract

The application discloses a packaging structure of a storage chip, wherein the packaging structure comprises a substrate, a first side surface of the substrate is provided with a groove, and the first side surface is provided with a substrate pad; a first chip and a second chip, the first chip and the second chip are storage chips; the first chip is arranged on a second side surface of the substrate, and the second chip is arranged in the groove; and a connecting piece is connected with a first chip pad of the first chip and the substrate pad, connected with a second chip pad of the second chip and the substrate pad, and used for electrically connecting the first chip and the second chip and transmitting storage data. In the manner, the transmission performance and the storage performance can be ensured, the integration of the packaging structure is improved, the reliability and yield are ensured, and the production cost is reduced.
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Claims

1. A package structure of a memory chip, characterized by, The packaging structure includes: A substrate, wherein a groove is provided on a first side surface of the substrate, and a substrate pad is provided on the first side surface; A first chip and a second chip, the first chip and the second chip being memory chips; the first chip is disposed on the second side surface of the substrate, and the second chip is disposed inside the groove; A connector connects the first chip pad of the first chip to the substrate pad, and the connector connects the second chip pad of the second chip to the substrate pad. The connector is used to electrically connect the first chip and the second chip and transmit stored data.

2. The package structure of claim 1, wherein, The first chip is a volatile memory chip, and the second chip is a non-volatile memory chip.

3. The package structure of claim 1 or 2, wherein, The first chip is disposed on the second side surface of the substrate, and the second chip is disposed on the first side surface of the substrate, with the first side surface and the second side surface of the substrate being disposed opposite to each other. The first chip is flip-chip mounted on one side surface of the substrate, and the mounting surface of the first chip and the first chip pad are located on the same surface of the first chip. The second chip is mounted inside the groove, and the mounting surface of the first chip and the pad of the second chip are located on different surfaces of the second chip.

4. The packaging structure according to claim 1, characterized in that, The substrate is also provided with a window that extends through both sides of the substrate. The substrate pad includes a first substrate pad, which is symmetrically arranged on both sides of the window with the center line of the window along a first direction as the axis of symmetry; the first direction is a direction parallel to the long side of the window. The first chip is disposed overlapping the window, the first chip pad is exposed on the first side through the window, and the connector passes through the window to connect the first chip pad and the first substrate pad.

5. The package structure of claim 4, wherein, The length of the window along the first direction is greater than the length of the chip along the first direction; The first chip pads of the first chip are arranged symmetrically, and the axis of symmetry of the first chip pads coincides with the projection of the center line of the window onto the substrate. At least some of the connectors are arranged symmetrically with respect to the centerline of the window along the first direction, and at least two of the symmetrically arranged connectors have the same length.

6. The package structure of claim 4, wherein, The projection of the window and the groove onto the substrate along the centerline in the first direction coincides; The substrate pad includes a second substrate pad, which is arranged on both sides of the groove with the center line of the groove along the first direction as the axis of symmetry. At least a portion of the connector connects the second chip pad to the second substrate pad.

7. The package structure of claim 1, wherein, The connector includes a first bonding wire and a second bonding wire, wherein the first bonding wire connects the first chip pad to the substrate pad, and the second bonding wire connects the second chip pad to the substrate pad.

8. The packaging structure according to claim 1, characterized in that, The packaging structure further includes a packaging layer, which is formed by molding and is disposed on both sides of the substrate, encapsulating the first chip, the second chip, and the connector.

9. The package structure of claim 8, wherein, The encapsulation layer includes a first encapsulation layer and a second encapsulation layer, wherein the first encapsulation layer is connected to the second encapsulation layer. The second encapsulation layer is disposed on the first side surface of the substrate, and the second encapsulation layer fills the groove and wraps the second chip, the connector and the mounting surface of the first chip; The first encapsulation layer is disposed on the second side surface of the substrate, covering the side surface and the other top surface of the first chip.

10. The packaging structure according to claim 8, characterized in that, The packaging structure further includes solder balls disposed on the first side surface of the substrate. The height of the solder balls is higher than the packaging layer height on the first side surface of the substrate. The solder balls are used to transmit the storage data of the first chip and / or the second chip when the packaging structure is mounted to the circuit board.