Array substrate, display panel and display device

Abstract

The array substrate, the display panel and the display device provided by the present disclosure comprise: a substrate; a plurality of pixel electrodes arranged in an array on the substrate; a plurality of gate lines located at the row gaps of the pixel electrodes; a common electrode line located at the gaps of the pixel electrodes, the common electrode line comprising a first common electrode line in the same layer as the pixel electrodes and a second common electrode line in the same layer as the gate lines; an insulating layer between the layer where the pixel electrodes are located and the layer where the gate lines are located, the first common electrode line being electrically connected to the second common electrode line through a first via hole penetrating the insulating layer, the size of the first via hole along the row direction being greater than the size along the column direction.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Utility Model Content

[0003] The array substrate, display panel, and display device provided in this disclosure are specifically designed as follows:

[0004] On one hand, embodiments of this disclosure provide an array substrate, including:

[0005] Substrate;

[0006] Multiple pixel electrodes are arranged in an array on the substrate.

[0007] Multiple gate lines are located at the row gaps of the pixel electrodes;

[0008] A common electrode line is located at the gap between the pixel electrodes. The common electrode line includes a first common electrode line on the same layer as the pixel electrodes and a second common electrode line on the same layer as the gate line.

[0009] An insulating layer is located between the layer containing the pixel electrode and the layer containing the gate line. The first common electrode line is electrically connected to the second common electrode line through a first via penetrating the insulating layer. The size of the first via along the row direction is larger than the size along the column direction.

[0010] In some embodiments, the array substrate provided in this disclosure further includes a plurality of transistors;

[0011] The insulating layer includes a first insulating layer located between the layer containing the first electrode of the transistor and the layer containing the pixel electrode. The first electrode of the transistor is electrically connected to the pixel electrode through a second via penetrating the first insulating layer. The size of the second via along the row direction is larger than the size along the column direction, and at least a portion of the orthographic projection of the second via on the substrate is substantially aligned with the orthographic projection of at least a portion of the first via on the substrate along the row direction.

[0012] In some embodiments, in the array substrate provided in the present disclosure, the substrate includes a plurality of red sub-pixel regions, a plurality of green sub-pixel regions, and a plurality of blue sub-pixel regions, and the plurality of pixel electrodes are located within the plurality of red sub-pixel regions, the plurality of green sub-pixel regions, and the plurality of blue sub-pixel regions;

[0013] The orthographic projection of the second via corresponding to the pixel electrode in the blue sub-pixel region on the substrate is approximately aligned with the orthographic projection of the first via on the substrate along the row direction.

[0014] In some embodiments, in the array substrate provided in the present disclosure, the first insulating layer includes a color resist layer, the color resist layer includes a third via, the size of the third via along the row direction is larger than the size along the column direction, and the first via and the second via, which are substantially aligned along the row direction, are located in the same area where the third via is located.

[0015] In some embodiments, in the array substrate provided in the present disclosure, every two pixel electrodes arranged along the row direction constitute a pixel electrode group, and the second common electrode line includes a plurality of common electrode repeating units, which are disposed on both sides of the opening area of ​​the pixel electrode group extending along the row direction and between the opening areas of the pixel electrode group.

[0016] In some embodiments, in the array substrate provided in the present disclosure, the second common electrode line further includes multiple connecting lines, which connect adjacent common electrode repeating units in the same row.

[0017] In some embodiments, the array substrate provided in the present disclosure further includes a plurality of common electrodes, each pair of pixel electrodes arranged along the row direction constitutes a pixel electrode group, the common electrode is in contact with the second common electrode line, and the orthogonal projection of the common electrode on the substrate covers the orthogonal projection of the opening area of ​​the pixel electrode group on the substrate.

[0018] In some embodiments, the array substrate provided in the present disclosure further includes multiple data lines, and each pair of pixel electrodes arranged along the row direction constitutes a pixel electrode group. The orthographic projection of the data lines on the substrate overlaps with the orthographic projection of the edge of the pixel electrode group extending along the column direction on the substrate.

[0019] In some embodiments, the array substrate provided in this disclosure further includes multiple data lines, each pair of pixel electrodes arranged along the row direction constitutes a pixel electrode group, the data lines are located in the column gaps between the pixel electrode groups, the first common electrode line includes a first sub-common electrode line located in the column gaps between the pixel electrode groups, and the orthographic projection of the first sub-common electrode line on the substrate at least partially covers the orthographic projection of the data lines on the substrate.

[0020] In some embodiments, in the array substrate provided in the present disclosure, two gate lines are provided in the same row gap of the pixel electrode, and the first common electrode line includes a second sub-common electrode line disposed in the row gap of the pixel electrode. The orthogonal projection of the second sub-common electrode line on the substrate passes through the orthogonal projection of the gap between the two gate lines on the substrate along the column direction.

[0021] In some embodiments, in the array substrate provided in the present disclosure, the orthographic projection of the second sub-common electrode line on the substrate at least partially overlaps with the orthographic projection of the edges of the two gate lines near the pixel electrode on the substrate.

[0022] On the other hand, this disclosure provides a display panel including an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate provided in this disclosure.

[0023] In some embodiments, in the display panel provided in the present disclosure, the opposing substrate includes a common electrode layer.

[0024] In some embodiments, in the display panel provided in the present disclosure, the opposing substrate further includes a black matrix, and the common electrode layer is located on the side of the black matrix facing the array substrate;

[0025] The orthographic projection of the black matrix on the substrate overlaps with the orthographic projection of the row spacing of the pixel electrode on the substrate, and the orthographic projection of the column spacing between the row spacing of the pixel electrode on the substrate does not overlap.

[0026] On the other hand, this disclosure provides a display device including the display panel described above. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of 2*6 sub-pixels in an array substrate provided in an embodiment of this disclosure;

[0028] Figure 2 for Figure 1 A magnified structural diagram of the Z1 region;

[0029] Figure 3 for Figure 2 A magnified structural diagram of the Z2 region;

[0030] Figure 4 For along Figure 2 Schematic diagram of the cross-sectional structure of line I-I' in the middle;

[0031] Figure 5 For along Figure 2 Schematic diagram of the cross-sectional structure of line II-II';

[0032] Figure 6 For along Figure 2 Schematic diagram of the cross-sectional structure of line III-III';

[0033] Figure 7 for Figure 2 Schematic diagram of the structure of the layer containing the common electrode;

[0034] Figure 8 for Figure 2 Schematic diagram of the structure of the layer containing the middle grid lines;

[0035] Figure 9 for Figure 2 A schematic diagram of the active layer structure;

[0036] Figure 10 for Figure 2 A schematic diagram of the structure of the layer where the data cable is located;

[0037] Figure 11 for Figure 2 Schematic diagram of the structure of the layer containing the via;

[0038] Figure 12 for Figure 2 Schematic diagram of the structure of the layer where the middle pixel electrode is located;

[0039] Figure 13 for Figure 1 A magnified structural diagram of the Z3 region in the middle;

[0040] Figure 14 For along Figure 13 Schematic diagram of the cross-sectional structure of line IV-IV';

[0041] Figure 15 For along Figure 13 Schematic diagram of the cross-sectional structure of the V-V' line;

[0042] Figure 16 for Figure 1 Another enlarged structural diagram of the Z3 region;

[0043] Figure 17 For along Figure 16 Schematic diagram of the cross-sectional structure of line VI-VI';

[0044] Figure 18 For along Figure 16 Schematic diagram of the cross-sectional structure of line VII-VII' in the middle;

[0045] Figure 19 for Figure 2 A schematic diagram of the display panel corresponding to the array substrate shown;

[0046] Figure 20 For along Figure 19 Schematic diagram of the cross-sectional structure of line VIII-VIII' in the middle;

[0047] Figure 21 For along Figure 19 Schematic diagram of the cross-sectional structure of line IX-IX';

[0048] Figure 22 For along Figure 19 Schematic diagram of the cross-sectional structure of the X-X' line;

[0049] Figure 23 for Figure 13 A schematic diagram of the display panel corresponding to the array substrate shown;

[0050] Figure 24 For along Figure 23 Schematic diagram of the cross-sectional structure of line XI-XI' in the middle;

[0051] Figure 25 For along Figure 23 Schematic diagram of the cross-sectional structure of line XII-XII';

[0052] Figure 26 for Figure 16 A schematic diagram of the display panel corresponding to the array substrate shown;

[0053] Figure 27 For along Figure 26 Schematic diagram of the cross-sectional structure of line XIII-XIII' in the middle;

[0054] Figure 28 For along Figure 26 A schematic diagram of the cross-sectional structure of the XIV-XIV' line. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the following description will be made in conjunction with the accompanying drawings of the embodiments of this disclosure. For clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shapes in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics; sharp corners illustrated may be rounded, etc. Therefore, the regions shown in the drawings are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shapes of the regions or reflect true proportions, but are only intended to illustrate the content of this disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0056] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0057] In the following description, when an element or layer is referred to as "on" another element or layer or "connected" to another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" another element or layer" or "directly connected" to another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the related listed items. The various embodiments of this disclosure may be combined and integrated with each other without conflict.

[0058] In some embodiments, to reduce the resistance of the common electrode lines, a mesh structure can be formed by first and second common electrode lines disposed in different layers, and the first and second common electrode lines are electrically connected through vias penetrating the insulating layer between them. However, since the via is a vertical via located within the pixel electrode row gap (i.e., the size of the via in the column direction is larger than the size in the row direction), the black matrix covering the row gap is wider, resulting in a larger loss of pixel aperture ratio.

[0059] To address the aforementioned technical problems, this disclosure provides an array substrate. Figure 1 This is a schematic diagram of the structure of 2*6 sub-pixels in an array substrate provided in an embodiment of this disclosure. Figure 1 As can be seen, in this disclosure, a row of sub-pixels (e.g., red sub-pixel R, green sub-pixel G, blue sub-pixel B) is electrically connected to two gate lines (GL) via transistors (TFTs). Two sub-pixels in adjacent rows and columns (e.g., red sub-pixel R and green sub-pixel G, blue sub-pixel B and green sub-pixel G, blue sub-pixel B and red sub-pixel R) are electrically connected to the same data line (DL) via transistors (TFTs). This connection method results in two gate lines (GL) between two adjacent rows of sub-pixels (e.g., red sub-pixel R, green sub-pixel G, blue sub-pixel B), and one data line (DL) between each two adjacent columns of sub-pixels (e.g., the column containing red sub-pixel R and the column containing green sub-pixel G, the column containing blue sub-pixel B and the column containing red sub-pixel R, the column containing green sub-pixel G and the column containing blue sub-pixel B). This reduces the number of data lines (DL), and correspondingly reduces the total number of source driver chips (SourceICs) connected to the data lines (DL), significantly reducing material costs. This method is particularly suitable for medium and large-sized products such as automotive displays and televisions.

[0060] In some embodiments, Figure 2 Given Figure 1 A magnified structural diagram of the Z1 region. Figure 3 Given Figure 2 A magnified structural diagram of the Z2 region. Figures 4 to 6 They respectively gave along Figure 2 Schematic diagrams of the cross-sectional structures of lines I-I', II-II', and III-III'. Figures 7 to 12 They were given respectively Figure 2 Schematic diagrams of the different membrane layers. (Combined with...) Figures 2 to 12 As can be seen, the array substrate provided in this embodiment may include:

[0061] The substrate 101 can be a substrate that allows visible light to pass through, such as glass, quartz, plastic and other materials.

[0062] Multiple pixel electrodes 102 are arranged in an array on a substrate 101. Each pair of pixel electrodes 102 arranged along the row direction x forms a pixel electrode group PX. The two pixel electrodes 102 in the same pixel electrode group PX can be electrically connected to the same data line 103. The pixel electrode 102 can be a plate electrode or a slit electrode. Optionally, the material of the pixel electrode 102 can include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc aluminum oxide (AZO), or zinc gallium oxide (GZO). The material of the data line 103 can include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), or nickel (Ni). The data line 103 can be a single-layer structure or a multilayer structure; for example, the data line 103 can be a single-layer structure composed of an aluminum metal layer.

[0063] Multiple gate lines 104 are located at the row gaps of the pixel electrode 102, and two gate lines 104 may be provided at the same row gap. In some embodiments, the material of the gate lines 104 may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The gate lines 104 may be a single-layer structure or a stacked structure. For example, the gate lines 104 may be a single-layer structure composed of a copper metal layer.

[0064] The common electrode line 105 is located at the gap of the pixel electrode 102. The common electrode line 105 includes a first common electrode line 1051 that is in the same layer and material as the pixel electrode 102, and a second common electrode line 1052 that is in the same layer and material as the gate line 104. This avoids the need to add a separate film layer for the common electrode line 105, which is beneficial for cost savings and thinner design. In addition, the first common electrode line 1051 overlaps at least partially with the data line 103, which can shield the influence between the data line 103 and the pixel electrode 102, improve display quality, and avoid light leakage. Furthermore, with this design, when forming the display panel, the opposing substrate can only set a black matrix in the row direction X of the gate line 104 for shielding, omitting the black matrix in the column direction Y of the data line 103.

[0065] An insulating layer 106 is located between the layer containing the pixel electrode 102 and the layer containing the gate line 104. The first common electrode line 1051 is electrically connected to the second common electrode line 1052 through a first via V1 penetrating the insulating layer 106. The size of the first via V1 along the row direction x is larger than the size along the column direction y, which means that the first via V1 connecting the first common electrode line 1051 and the second common electrode line 1052 in this disclosure is a horizontal via. By changing the vertical via to a horizontal via, the width of the row gap can be reduced, and correspondingly, the width of the black matrix covering the row gap can also be reduced, thereby improving the pixel aperture ratio.

[0066] See also Figures 2 to 12As can be seen, the array substrate provided in this embodiment may further include multiple transistors 107. The second electrode s of transistor 107 may be integrally disposed with data line 103. The active layer a of transistor 107 may be made of amorphous silicon, polycrystalline silicon, indium gallium zinc oxide, etc. The insulating layer 106 may include a first insulating layer 1061 located between the layer where the first electrode d of transistor 107 is located and the layer where the pixel electrode 102 is located, and a second insulating layer 1062 located between the layer where the first electrode d of transistor 107 is located and the layer where the gate line 104 is located. The first electrode d of transistor 107 is electrically connected to the pixel electrode 102 through a second via V2 penetrating the first insulating layer 1061. The size of the second via V2 along the row direction x is larger than the size along the column direction y. Optionally, the size of the second via V2 is the same as that of the first via V1 (i.e., the size of the two is within the error range caused by factors such as process and measurement). In some embodiments, at least a portion of the orthographic projection of the second via V2 on the substrate 101 and at least a portion of the orthographic projection of the first via V1 on the substrate 101 are arranged approximately parallel to each other along the x-direction. The approximately parallel arrangement of the first via V1 and the second via V2 in this disclosure can be understood as their long sides being collinear or their long sides being within the offset range caused by factors such as process and measurement. The morphology of the vias affects the alignment film (PI) process; the more boundaries of the vias, the greater the risk of non-sticking of the alignment liquid. By arranging at least a portion of the second via V2 and at least a portion of the first via V1 approximately parallel to each other along the x-direction, the number of via boundaries can be reduced, the via morphology improved, the flowability of the alignment liquid ensured, and the risk of non-sticking of the alignment liquid reduced. Furthermore, both the first via V1 and the second via V2 are rectangular vias, which are more conducive to the drainage of the alignment liquid than square vias, resulting in better alignment performance.

[0067] In some embodiments, such as Figures 2 to 12As shown, the first insulating layer 1061 may include a color resist layer (including a red color resist CF_R, a green color resist CF_G, and a blue color resist CF_B), a first sub-insulating layer 601 located between the color resist layer (including the red color resist CF_R, the green color resist CF_G, and the blue color resist CF_B) and the layer containing the first electrode d of the transistor 107, and a second sub-insulating layer 602 located between the color resist layer (including the red color resist CF_R, the green color resist CF_G, and the blue color resist CF_B) and the layer containing the pixel electrode 102. The color resist layer (including the red color resist CF_R, the green color resist CF_G, and the blue color resist CF_B) includes a third via V3. The dimension of the third via V3 along the row direction x is larger than its dimension along the column direction y, and the first via V1 and the second via V2, which are approximately aligned along the row direction x, may be located within the same region of the third via V3. In COA product pixels, since the color resist layer is located on the array substrate, for each additional signal via (including the first via V1 and / or the second via V2) in the pixel, the color resist layer will also have an additional third via V3. For process considerations, the distance n between the third via V3 and the signal via (including the first via V1 and / or the second via V2) needs to be designed to a minimum value. To avoid light leakage, the distance m between the edge of the third via V3 and the edge of the metal layer is also required. Non-COA products do not require the color resist layer opening design. Therefore, the width of the black matrix on the gate side of the pixel in COA products is much wider than that in non-COA products. This disclosure allows the first via V1 and the second via V2, which are approximately aligned along the row direction x, to be located in the same area as the third via V3. This ensures that the distance between m and n meets the minimum design value. Optionally, both m and n are 3μm to 6μm, for example, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, etc. This ensures that the black matrix covering the row gap is not too wide and has little impact on the pixel aperture ratio.

[0068] It should be understood that the more first vias V1 used to connect the first common electrode line 1051 and the second common electrode line 1052, the smaller the overall resistance of the first common electrode line 1051 and the second common electrode line 1052, which is more conducive to ensuring the stability of the common electrode signal. In order to reduce pixel aperture ratio loss and improve transmittance, the first via V1 and the second via V2 can be set to be located in the same third via V3. However, this will inevitably make the third via V3 that simultaneously accommodates the first via V1 and the second via V2 larger than the third via V3 that only accommodates the first via V1 or the second via V2. This is more likely to cause the alignment film formed on the color resist layer (including red color resist CF_R, green color resist CF_G and blue color resist CF_B) to accumulate at the third via V3 that simultaneously accommodates the first via V1 and the second via V2, which is not conducive to improving the film uniformity and alignment effect of the alignment film. Based on this, to balance the alignment effect and the stability of the common electrode signal, this disclosure only sets the orthographic projection of the second via V2 corresponding to the pixel electrode 102 of the blue sub-pixel B on the substrate 101 to be approximately aligned with the orthographic projection of the first via V1 on the substrate 101 along the row direction x, and the second via V2 and the first via V1 corresponding to the pixel electrode 102 of the blue sub-pixel B are disposed within the third via V3. Although this has a certain impact on the alignment effect of the blue sub-pixel B, given that the brightness of the blue sub-pixel B is the lowest among the red sub-pixel R, green sub-pixel G, and blue sub-pixel B, even sacrificing part of the alignment effect of the blue sub-pixel B will not have a significant impact on the overall display effect.

[0069] In some embodiments, in the array substrate provided in the present disclosure, such as Figure 2 , Figure 8 and Figure 12 As shown, every two pixel electrodes 102 arranged along the row direction x constitute a pixel electrode group PX. The second common electrode line 1052 includes multiple common electrode repeating units RU. The common electrode repeating units RU are located on both sides of the opening area OA of the pixel electrode group RX extending along the row direction x, and between the opening areas OA of the pixel electrode group PX. In related technologies, the second common electrode line 1052 surrounds the opening area OA. This disclosure eliminates the second common electrode line 1052 extending on both sides of the opening area OA of the pixel electrode group RX along the column direction y. This improves the product transmittance and reduces metallic reflection, thus simultaneously improving contrast. Optionally, two adjacent common electrode repeating units RU in the same row can be electrically connected by a connecting line 108 (e.g., the connecting line 108 is integrally set with the common electrode repeating unit RU), thereby realizing the lateral transmission of the common electrode signal.

[0070] In some embodiments, in the array substrate provided in the present disclosure, such as Figure 2 , Figures 6 to 8 ,as well as Figure 12 As shown, the design may also include multiple common electrodes 109. Each pair of pixel electrodes 102 arranged along the row direction x forms a pixel electrode group PX. There is no insulating layer between the common electrode 109 and the second common electrode line 1052; they are in direct contact. Optionally, the orthogonal projection of the common electrode 109 onto the substrate 101 can cover the orthogonal projection of the opening area OA of the pixel electrode group PX onto the substrate 101. In related designs, the second common electrode line 1052 and the first electrode d of the transistor 107 overlap to form a pixel storage capacitor Cst. The pixel storage capacitor Cst is increased by increasing the overlap area between the second common electrode line 1052 and the first electrode d of the transistor 107, but this results in a significant loss of transmittance. In this disclosure, the common electrode 109 is located throughout the opening area OA, significantly increasing the overlap area with the pixel electrode 102. This increases the pixel storage capacitor Cst formed by the common electrode 109 and the pixel electrode 102, ensuring higher transmittance and improving display quality, especially in high-resolution PPI products. Furthermore, the direct contact between the common electrode 109 and the second common electrode line 1052 results in a lower overall resistance between the two lines. This reduces the recovery time of the common electrode signal after coupling on the second common electrode line 1052, improving the lateral crosstalk (H-crosstalk) level at high refresh rates. Additionally, the common electrode signal can also influence the electric field of the data line 103, weakening the electric field between the pixel electrode 102 and the adjacent but not electrically connected data line 103, without affecting the product's vertical crosstalk level.

[0071] In some embodiments, in the array substrate provided in the present disclosure, such as Figure 2 , Figure 5 , Figure 10 and Figure 12 As shown, the data line 103 is disposed in the column gap between the pixel electrode groups PX. The first common electrode line 1051 may include a first sub-common electrode line SCL1 located in the column gap between the pixel electrode groups PX. The orthographic projection of the first sub-common electrode line SCL1 on the substrate 101 at least partially covers the orthographic projection of the data line 103 on the substrate 101. In this way, the first sub-common electrode line SCL1 can be used to shield the data signal of the data line 103 from the interference of the data signal of the data line 103 to the data signal of the adjacent but unconnected pixel electrode 102, and the vertical transmission of the common electrode signal on the first sub-common electrode line SCL1 can be realized.

[0072] In some embodiments, in the array substrate provided in the present disclosure, such as Figure 2 , Figure 8 and Figure 12As shown, two gate lines 104 can be provided in the same row gap of the pixel electrode 102. The first common electrode line 1051 may include a second sub-common electrode line SCL2 provided in the row gap of the pixel electrode 102. The second sub-common electrode line SCL2 may include a widened portion extending towards the connection position between the pixel electrode 102 and the first electrode d, so that the second sub-common electrode line SCL2 can achieve electrical connection with the second common electrode line 1052 of the layer where the gate line 104 is located at the widened position. The orthographic projection of the second sub-common electrode line SCL2 on the substrate 101 passes through the orthographic projection of the gap between the two gate lines 104 on the substrate 101 along the column direction y. This can avoid the second sub-common electrode line SCL2 from being short-circuited with the pixel electrode 102 in the same layer, and make the first sub-common electrode line SCL1 and the second sub-common electrode line SCL2 form a mesh structure, which is beneficial to improve the uniformity and anti-interference ability of the common electrode signal. Furthermore, since the first sub-common electrode line SCL1 of the first common electrode line 1051 in this disclosure is located in the column gap between pixel electrode groups PX, and the second sub-common electrode line SCL2 of the first common electrode line 1051 is located in the row gap of pixel electrode 102, in other words, this disclosure does not provide the first common electrode line 1051 in the column gap within the pixel electrode group PX. Therefore, the column gap within the pixel electrode group PX can be narrower, thereby increasing the pixel aperture ratio and improving the product transmittance. (Continue to see...) Figure 2 , Figure 8 and Figure 12 It is understood that the orthographic projection of the second sub-common electrode line SCL2 on the substrate 101 can at least partially overlap with the orthographic projection of the edges of the two gate lines 104 near the pixel electrode 102 on the substrate 101, thereby effectively shielding the scanning signal of the gate line 104 by using the second sub-common electrode line SCL2, reducing the coupling interference between the pixel electrode 102 and the gate line 104.

[0073] In some embodiments, in the array substrate provided in the present disclosure, such as Figure 2 , Figures 8 to 10 ,as well as Figure 12 As shown, two adjacent transistors 107 between two adjacent data lines 103 can be symmetrically arranged about the center of the row gap between two adjacent pixel electrode groups PX arranged along the column direction y. This ensures that the other film layers in each transistor 107 other than the gate g (e.g., the layer containing the first electrode d and the second electrode s, and the active layer a) are approximately the same as the parasitic capacitance formed by the gate line 104 (e.g., within ±5% error range). This ensures that the signal change (ΔVp) caused by the parasitic capacitance of each pixel electrode 102 is similar, thereby effectively improving the head-shaking pattern.

[0074] In some embodiments, Figure 13 Given Figure 1A schematic diagram of the structure of the Z3 region. Figure 14 For along Figure 13 Schematic diagram of the cross-sectional structure of line IV-IV'. Figure 15 For along Figure 13 A schematic diagram of the cross-sectional structure of the V-V' line. (See diagram below.) Figures 13 to 15 As shown, the array substrate provided in this disclosure may also not have [a specific feature]. Figures 2 to 12 The common electrode 109 in the illustrated embodiment. Without the common electrode 109, the capacitance Cdc between the data line 103 and the second common electrode line 1052 is significantly reduced, thereby improving the lateral crosstalk level of the product under high refresh rate. At the same time, the total load on the data line 103 is reduced, and the product charging rate is improved.

[0075] In some embodiments, Figure 16 Given Figure 1 Another structural diagram of the Z3 region. Figure 17 For along Figure 16 Schematic diagram of the cross-sectional structure of line VI-VI'. Figure 18 For along Figure 16 A schematic diagram of the cross-sectional structure of line VII-VII' in the middle. (See diagram below.) Figures 16 to 18 As shown, in the array substrate provided in the embodiments of this disclosure, the orthographic projection of the data line 103 on the substrate 101 can overlap with the orthographic projection of the edge of the pixel electrode group PX extending along the column direction y on the substrate 101. That is, the pixel electrode 102 can be directly connected to the data line 103 with an overlap value > 2μm (mainly based on the fact that the pixel electrode 102 will not run out of the data line 103 after the CD & OVL offset in the manufacturing process). The edge electric field of the pixel electrode 102 is directly blocked by the metal of the data line 103, and the first sub-common electrode line SCL1 can be eliminated on the data line 103. Similarly, there is no need to add a black matrix to block light on the opposite substrate. In this way, the width of the opaque area can be reduced, and the column gap width in the pixel electrode group PX can be reduced simultaneously, and the aperture ratio and contrast are improved.

[0076] Based on the same inventive concept, embodiments of this disclosure provide a display panel, such as... Figures 19 to 28As shown, the display includes an array substrate 001 and a counter substrate 002 placed opposite each other. The array substrate 001 is the array substrate 001 provided in the embodiments of this disclosure. The counter substrate 002 includes a substrate 200, a black matrix 202 located on the side of the substrate 200 facing the array substrate 001, and a common electrode layer 201 located on the side of the black matrix 202 facing the array substrate 001. Optionally, the common electrode layer 201 disposed on the counter substrate is disposed over the entire surface of the display area AA. The orthographic projection of the black matrix 202 on the substrate 101 and the orthographic projection of the row spacing of the pixel electrodes 102 on the substrate 101 are... The shadows overlap to hide the gate line 104, the second sub-common electrode line SCL2, and the transistor 107 at the row gaps of the pixel electrode 102 within the area of ​​the black matrix 202. Optionally, the orthographic projection of the black matrix 202 on the substrate 101 and the orthographic projection of the column gaps between the row gaps on the substrate 101 do not overlap. The black matrix 202 can be used for light blocking in the row gaps, and the first sub-common electrode line SCL1 or the data line 103 can be used for light blocking in the column gaps between the row gaps. In the intersection area of ​​the row gaps and the column gaps, both the black matrix 202 and the first sub-common electrode line SCL1 can be used for light blocking. In some embodiments, the common electrode layer 201 can also be disposed on the array substrate 001, which is not limited here. This disclosure describes a VA-type panel with the common electrode layer 201 located on the opposing substrate 002 as an example.

[0077] In some embodiments, the display panel provided in this disclosure may further include a liquid crystal layer between an array substrate and a counter substrate, a first polarizer on the side of the array substrate away from the counter substrate, and a second polarizer on the side of the counter substrate away from the array substrate, wherein the polarization direction of the first polarizer and the polarization direction of the second polarizer are perpendicular to each other. Other essential components of the display panel are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the scope of this disclosure.

[0078] Based on the same inventive concept, this disclosure provides a display device, including the display panel described above and a backlight module located on the light-incident side of the display panel. The backlight module can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature LEDs (Mini LEDs, Micro LEDs, etc.).

[0079] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.

[0080] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0081] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0082] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, include: Substrate; Multiple pixel electrodes are arranged in an array on the substrate. Multiple gate lines are located at the row gaps of the pixel electrodes; A common electrode line is located at the gap between the pixel electrodes. The common electrode line includes a first common electrode line on the same layer as the pixel electrodes and a second common electrode line on the same layer as the gate line. An insulating layer is located between the layer containing the pixel electrode and the layer containing the gate line. The first common electrode line is electrically connected to the second common electrode line through a first via penetrating the insulating layer. The size of the first via along the row direction is larger than the size along the column direction.

2. The array substrate as claimed in claim 1, wherein, It also includes multiple transistors; The insulating layer includes a first insulating layer located between the layer containing the first electrode of the transistor and the layer containing the pixel electrode. The first electrode of the transistor is electrically connected to the pixel electrode through a second via penetrating the first insulating layer. The size of the second via along the row direction is larger than the size along the column direction, and at least a portion of the orthographic projection of the second via on the substrate is substantially aligned with the orthographic projection of at least a portion of the first via on the substrate along the row direction.

3. The array substrate as described in claim 2, wherein, The substrate includes multiple red sub-pixel regions, multiple green sub-pixel regions, and multiple blue sub-pixel regions, and the multiple pixel electrodes are located within the multiple red sub-pixel regions, the multiple green sub-pixel regions, and the multiple blue sub-pixel regions; The orthographic projection of the second via corresponding to the pixel electrode in the blue sub-pixel region on the substrate is approximately aligned with the orthographic projection of the first via on the substrate along the row direction.

4. The array substrate as described in claim 2 or 3, wherein, The first insulating layer includes a color resist layer, the color resist layer includes a third via, the dimension of the third via along the row direction is larger than the dimension along the column direction, and the first via and the second via, which are approximately aligned along the row direction, are located in the same area of ​​the third via.

5. The array substrate according to any one of claims 1 to 3, wherein, Each pair of pixel electrodes arranged along the row direction constitutes a pixel electrode group. The second common electrode line includes multiple common electrode repeating units, which are located on both sides of the opening area of ​​the pixel electrode group extending along the row direction and between the opening areas of the pixel electrode group.

6. The array substrate as claimed in claim 5, wherein, The second common electrode line also includes multiple connecting lines, which connect adjacent common electrode repeating units in the same row.

7. The array substrate according to any one of claims 1 to 3 and 6, wherein, It also includes multiple common electrodes, with each pair of pixel electrodes arranged along the row direction forming a pixel electrode group. The common electrode is in contact with the second common electrode line, and the orthogonal projection of the common electrode on the substrate covers the orthogonal projection of the opening area of ​​the pixel electrode group on the substrate.

8. The array substrate according to any one of claims 1 to 3, 6, wherein, It also includes multiple data lines, and each pair of pixel electrodes arranged along the row direction constitutes a pixel electrode group. The orthographic projection of the data line on the substrate overlaps with the orthographic projection of the edge of the pixel electrode group extending along the column direction on the substrate.

9. The array substrate according to any one of claims 1 to 3 and 6, wherein, It also includes multiple data lines, with each pair of pixel electrodes arranged along the row direction forming a pixel electrode group. The data lines are located within the column gaps between the pixel electrode groups. The first common electrode line includes a first sub-common electrode line located within the column gaps between the pixel electrode groups. The orthographic projection of the first sub-common electrode line on the substrate at least partially covers the orthographic projection of the data lines on the substrate.

10. The array substrate according to any one of claims 1 to 3, 6, wherein, The pixel electrode has two gate lines in the same row gap. The first common electrode line includes a second sub-common electrode line disposed in the row gap of the pixel electrode. The orthographic projection of the second sub-common electrode line on the substrate passes through the orthographic projection of the gap between the two gate lines on the substrate along the column direction.

11. The array substrate as claimed in claim 10, wherein, The orthographic projection of the second sub-common electrode line on the substrate at least partially overlaps with the orthographic projection of the edges of the two gate lines near the pixel electrode on the substrate.

12. A display panel, wherein, It includes an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate as described in any one of claims 1 to 11.

13. The display panel as claimed in claim 12, wherein, The opposing substrate includes a common electrode layer.

14. The display panel as claimed in claim 12 or 13, wherein, The opposing substrate further includes a black matrix, and the common electrode layer is located on the side of the black matrix facing the array substrate; The orthographic projection of the black matrix on the substrate overlaps with the orthographic projection of the row spacing of the pixel electrode on the substrate, and the orthographic projection of the column spacing between the row spacing of the pixel electrode on the substrate does not overlap.

15. A display device, wherein, Includes the display panel as described in any one of claims 12 to 14.

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