Display substrate and display device

Abstract

A display substrate and a display device, wherein the display substrate comprises: a plurality of pixel driving circuits, at least one pixel driving circuit comprising: a first light-emitting transistor, a first reset transistor, a write transistor and a driving transistor, the first light-emitting transistor in the at least one pixel driving circuit being a P-type transistor, the transistor type of the first light-emitting transistor in the at least one pixel driving circuit being different from the transistor types of the remaining transistors except the first light-emitting transistor, the active pattern of the first reset transistor and the active pattern of the write transistor in the at least one pixel driving circuit being an integral structure and being referred to as an active structure, and the orthographic projection of the active pattern of the first light-emitting transistor on a base at least partially overlapping the orthographic projection of the active structure on the base.

Description

Technical Field

[0001] This article relates to the field of display technology, specifically to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, display devices using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Utility Model Content

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate and a display device.

[0005] This disclosure provides a display substrate, including: a substrate and a plurality of pixel driving circuits disposed on the substrate. At least one pixel driving circuit includes: a plurality of transistors, the plurality of transistors including: a first light-emitting transistor, a first reset transistor, a write transistor and a drive transistor. The first light-emitting transistor is electrically connected to a first light-emitting signal terminal and a first power supply terminal, respectively. The first reset transistor is electrically connected to a first initial signal terminal, a first reset signal terminal and the control electrode of the drive transistor, respectively. The write transistor is electrically connected to a scan signal terminal, a data signal terminal and the control electrode of the drive transistor, respectively. The signal at the first power supply terminal is a positive voltage signal, the first light-emitting transistor in at least one pixel driving circuit is a P-type transistor, and the transistor type of the first light-emitting transistor in at least one pixel driving circuit is different from the transistor types of the other transistors besides the first light-emitting transistor. The active pattern of the first reset transistor and the active pattern of the write transistor in at least one pixel driving circuit are an integral structure, and are referred to as an active structure. The orthographic projection of the active pattern of the first light-emitting transistor in at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the active structure on the substrate.

[0006] Secondly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0007] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0008] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0009] Figure 1 This is a schematic diagram of the structure of a display device; Figure 2 This is a schematic diagram of a planar structure of a display substrate; Figure 3 This is the equivalent circuit diagram of the pixel driving circuit; Figure 4 for Figure 3 The provided timing diagram for the pixel driving circuit; Figure 5 This is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure; Figure 6 for Figure 5 Schematic diagram of part of the film layer Figure 1 ; Figure 7 for Figure 5 Schematic diagram of part of the film layer Figure 2 ; Figure 8 for Figure 6 Cross-sectional view along direction AA; Figure 9 for Figure 6 Cross-sectional view along the BB direction; Figure 10 for Figure 6 Cross-sectional view along the CC direction; Figure 11 This is a schematic diagram of the structure of the display substrate in an exemplary embodiment. Figure 1 ; Figure 12 This is a schematic diagram of the structure of the display substrate in an exemplary embodiment. Figure 2 ; Figure 13 for Figure 5 A schematic diagram of the pattern of the first semiconductor layer; Figure 14 for Figure 5 A schematic diagram of the pattern of the first conductive layer; Figure 15 for Figure 5 A schematic diagram after the first conductive layer pattern has been formed; Figure 16 for Figure 5 A schematic diagram of the pattern of the second conductive layer; Figure 17 for Figure 5 A schematic diagram after the second conductive layer pattern has been formed; Figure 18 for Figure 5 A schematic diagram of the pattern of the second semiconductor layer; Figure 19 for Figure 5 A schematic diagram after the second semiconductor layer pattern has been formed; Figure 20 for Figure 5 A schematic diagram of the pattern of the third conductive layer in the middle; Figure 21 for Figure 5 A schematic diagram after the formation of the third conductive layer pattern; Figure 22 for Figure 5 A schematic diagram showing the formation of the fifth insulating layer pattern; Figure 23 for Figure 5 A schematic diagram of the pattern of the fourth conductive layer; Figure 24 for Figure 5 A schematic diagram after the fourth conductive layer pattern has been formed; Figure 25 for Figure 5 A schematic diagram after the first planarization layer pattern has been formed; Figure 26 for Figure 5 A schematic diagram of the pattern of the fifth conductive layer; Figure 27 for Figure 5 A schematic diagram after the fifth conductive layer pattern has been formed. Detailed Implementation

[0010] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0011] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0012] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0013] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0014] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0015] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0016] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0017] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0018] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0019] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0020] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0021] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1 As shown, the display device may include: a timing controller, a data driving circuit, a scanning driving circuit, a light-emitting driving circuit, and a pixel array. The timing controller is connected to both the data driving circuit and the gate driving circuit. The data driving circuit is connected to multiple data lines (D1 to Dn), and the gate driving circuit is connected to multiple gate lines (G1 to Gm). The pixel array may include multiple sub-pixels PX. At least one sub-pixel PX may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the gate lines and data lines respectively.

[0022] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driving circuit to the data driving circuit, and can provide clock signals, gate start signals, etc. of specifications suitable for the gate driving circuit to the gate driving circuit.

[0023] In an exemplary embodiment, the data driving circuit can use grayscale values ​​and control signals received from the timing controller to generate data voltages that will be provided to data lines D1, D2, D3, ..., Dn. For example, the data driving circuit can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data lines D1 to Dn on a pixel-row basis, where n can be a natural number.

[0024] In an exemplary embodiment, the gate drive circuit can generate scan signals to be provided to gate lines G1, G2, G3, ..., Gm by receiving clock signals, gate start signals, etc., from a timing controller. For example, the gate drive circuit can sequentially provide gate signals with on-level pulses to gate signal lines G1 to Gm. For example, the gate drive circuit can be configured as a shift register and can generate scan signals by sequentially transmitting gate start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number.

[0025] In an exemplary embodiment, the display device may include a display substrate. The gate driving circuit may be directly disposed on the display substrate. For example, the gate driving circuit may be disposed on the left bezel and the right bezel of the display substrate; or, it may be disposed on both the left and right bezels of the display substrate. In an exemplary embodiment, the gate driving circuit may be formed together with the sub-pixels during the sub-pixel formation process.

[0026] In an exemplary embodiment, the data driving circuit can be disposed on a separate chip or printed circuit board to connect to sub-pixels via signals on the display substrate. For example, the data driving circuit can be formed on the bezel of the display substrate using a chip-on-glass, chip-on-plastic, or chip-on-film method. The timing controller can be disposed separately from or integrated with the data driving circuit. However, this embodiment is not limited to this. In an exemplary embodiment, the data driving circuit can be directly disposed on the display substrate.

[0027] Figure 2 This is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include multiple pixel units PI arranged in a matrix. At least one pixel unit of the multiple pixel units PI includes a first sub-pixel PI1 emitting a first color light, a second sub-pixel PI2 emitting a second color light, and a third sub-pixel PI3 emitting a third color light. Each of the first sub-pixel PI1, second sub-pixel PI2, and third sub-pixel PI3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel PI1, second sub-pixel PI2, and third sub-pixel PI3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting devices in the first sub-pixel PI1, second sub-pixel PI2, and third sub-pixel PI3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0028] In an exemplary embodiment, the first sub-pixel PI1 may be a red sub-pixel (R) that emits red light, the second sub-pixel PI2 may be a green sub-pixel (G) that emits green light, and the third sub-pixel PI3 may be a blue sub-pixel (B) that emits blue light.

[0029] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal.

[0030] In an exemplary embodiment, the three sub-pixels may be arranged horizontally side by side, vertically side by side, or in a triangular pattern, and this disclosure is not limited thereto. Figure 2 This explanation is based on the example of a pixel unit comprising three sub-pixels arranged horizontally side by side.

[0031] In an exemplary embodiment, the light-emitting device L may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). The typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0032] In an exemplary embodiment, the light-emitting device can emit red, green, blue, white, or other colors of light when driven by its corresponding pixel driving circuit. The color of the light emitted by the light-emitting device can be determined as needed. In an exemplary embodiment, the light-emitting device L may include a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0033] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent pixel driving circuits may have a small overlap or may be isolated, and the electron block layers of adjacent pixel driving circuits may have a small overlap or may be isolated.

[0034] The pixel driving circuit in the display substrate, which uses all N-type transistors, includes transistors connected to a high-level power supply terminal. Because all transistors are N-type, the turn-on voltage of the transistors connected to the high-level power supply terminal is relatively high, resulting in higher power consumption of the display substrate.

[0035] Therefore, this disclosure provides a display substrate and a display device.

[0036] This disclosure provides a display substrate, including: a substrate and a plurality of pixel driving circuits disposed on the substrate. Figure 3 This is the equivalent circuit diagram of the pixel driving circuit. (Example:) Figure 3As shown, the pixel driving circuit includes multiple transistors. These transistors include: first transistors T1 to seventh transistors T7, a first capacitor C1, and a second capacitor C2. The first capacitor C1 and the second capacitor C2 each include a first electrode and a second electrode. Specifically, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal Reset1, the first electrode of the first transistor T1 is electrically connected to the first initial signal terminal INIT1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second reset signal terminal Reset2, the first electrode of the second transistor T2 is electrically connected to the second initial signal terminal INIT2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the scan signal terminal Gate, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the first node N1. The fifth transistor T5... The control electrode is electrically connected to the first light-emitting signal terminal EM1. The first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD. The second electrode of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2. The first electrode of the sixth transistor T6 is electrically connected to the third node N3. The second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The control electrode of the seventh transistor T7 is electrically connected to the third reset signal terminal Reset3. The first electrode of the seventh transistor T7 is electrically connected to the fifth node N5. The second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The first plate C11 of the first capacitor C1 is electrically connected to the first node N1. The second plate C12 of the first capacitor C1 is electrically connected to the third node N3. The first plate C21 of the second capacitor C2 is electrically connected to the fifth node N5. The second plate C22 of the second capacitor C2 is electrically connected to the third node N3.

[0037] In an exemplary embodiment, the first transistor T1 can be referred to as the first reset transistor, the second transistor T2 can be referred to as the second reset transistor, the third transistor T3 can be referred to as the driving transistor, the fourth transistor T4 can be referred to as the writing transistor, the fifth transistor T5 can be referred to as the first light-emitting transistor, the sixth transistor T6 can be referred to as the second light-emitting transistor, and the seventh transistor T7 can be referred to as the third reset transistor.

[0038] In an exemplary embodiment, either the first capacitor C1 or the second capacitor C2 can be a capacitor device manufactured through a process, for example, by fabricating dedicated capacitor electrodes. Multiple capacitor electrodes can be implemented using metal layers, semiconductor layers (e.g., doped polysilicon), etc. Alternatively, either the first capacitor C1 or the second capacitor C2 can be a parasitic capacitance between multiple devices, implemented using the transistor itself and other devices or circuits. The connection method of either the first capacitor C1 or the second capacitor C2 includes, but is not limited to, the methods described above; other applicable connection methods can be used, as long as the level of the corresponding node is stored. Here, the exemplary embodiments of this disclosure do not limit this.

[0039] In an exemplary embodiment, transistors can be categorized into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0040] In an exemplary embodiment, the signal at the first power supply terminal VDD is a positive voltage signal, and the first light-emitting transistor (also the fifth transistor T5) in at least one pixel driving circuit is a P-type transistor.

[0041] In an exemplary embodiment, the transistor type of the first light-emitting transistor (also the fifth transistor T5) in at least one pixel driving circuit is different from the transistor types of the other transistors (first transistor T1 to fourth transistor T4, sixth transistor T6 and seventh transistor T7) besides the first light-emitting transistor (also the fifth transistor T5).

[0042] In an exemplary embodiment, since the transistor type of the first light-emitting transistor (also the fifth transistor T5) in at least one pixel driving circuit is different from the transistor types of the other transistors besides the first light-emitting transistor (also the fifth transistor T5), the other transistors in at least one pixel driving circuit besides the first light-emitting transistor (also the fifth transistor T5) are N-type transistors.

[0043] When the first light-emitting transistor T5 is an N-type transistor, the voltage value of the signal that enables the first light-emitting transistor T5 to conduct must be greater than the voltage value of the signal at the first power supply terminal VDD in order for the first light-emitting transistor T5 to conduct. However, by setting the first light-emitting transistor in the pixel driving circuit to a P-type transistor, the first light-emitting transistor can be turned on by providing a negative voltage signal with a smaller voltage value to the first light-emitting signal terminal EM1, thereby reducing the absolute value of the voltage value of the signal provided to the first light-emitting signal terminal and thus reducing the power consumption of the display substrate.

[0044] Figure 4 for Figure 3 The provided timing diagram for the pixel driving circuit. Figure 4 Under the control of the provided timing, Figure 3 The operation of the provided pixel driving circuit is as follows: In the first stage S1, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals. The signals at the first reset signal terminal Reset1, the second reset signal terminal Reset2, and the third reset signal terminal Reset3 change from low-level signals to high-level signals sequentially in the first stage S1. The signal at the scan signal terminal Gate is low-level. The sixth transistor T6 is turned on, and the first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on sequentially. The fourth transistor T4 and the fifth transistor T5 are turned off.

[0045] The first transistor T1 is turned on, and the signal at the first initial signal terminal INIT1 is written to the first node N1 to initialize the first node N1 and clear its charge. The second transistor T2, the sixth transistor T6, and the seventh transistor T7 are turned on, and the signal at the second initial signal terminal INIT2 is written to the third node N3, the fourth node N4, and the fifth node N5 to initialize the third node N3, the fourth node N4, and the fifth node N5 and clear their charge.

[0046] In the second stage (S2), the signals at the first light-emitting signal terminal EM1, the first reset signal terminal Reset1, the second reset signal terminal Reset2, and the third reset signal terminal Reset3 are high-level signals, while the signals at the scan signal terminal Gate and the second light-emitting signal terminal EM2 are low-level signals. The first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, while the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0047] The first transistor T1 is turned on, and the signal at the first initial signal terminal INIT1 is continuously written to the first node N1 to initialize the first node N1 and clear its charge. The second transistor T2 and the seventh transistor T7 are turned on, and the signal at the second initial signal terminal INIT2 is continuously written to the fourth node N4 and the fifth node N5 to initialize the fourth node N4 and the fifth node N5 and clear their charge.

[0048] In the third stage (S3), the signals at the first reset signal terminal (Reset1), the second reset signal terminal (Reset2), and the third reset signal terminal (Reset3) are high-level signals, while the signals at the scan signal terminal (Gate), the first light-emitting signal terminal (EM1), and the second light-emitting signal terminal (EM2) are low-level signals. The first transistor (T1), the second transistor (T2), the fifth transistor (T5), and the seventh transistor (T7) are turned on, while the fourth transistor (T4) and the sixth transistor (T6) are turned off.

[0049] The first transistor T1 is turned on, and the signal at the first initial signal terminal INIT1 is continuously written to the first node N1, initializing the first node N1 and clearing its charge. The second transistor T2 and the seventh transistor T7 are turned on, and the signal at the second initial signal terminal INIT2 is continuously written to the fourth node N4 and the fifth node N5, initializing the fourth node N4 and the fifth node N5 and clearing their charge. The fifth transistor T5 is turned on, and the signal at the first power supply terminal VDD charges the third node N3 through the second node N2 and the turned-on third transistor T3.

[0050] In the fourth stage (S4), the signals at the first light-emitting signal terminal EM1, the first reset signal terminal Reset1, the second reset signal terminal Reset2, and the third reset signal terminal Reset3 are high-level signals, while the signals at the scan signal terminal Gate and the second light-emitting signal terminal EM2 are low-level signals. The first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, while the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0051] The first transistor T1 is turned on, and the signal at the first initial signal terminal INIT1 is continuously written to the first node N1 to initialize the first node N1 and clear its charge. The second transistor T2 and the seventh transistor T7 are turned on, and the signal at the second initial signal terminal INIT2 is continuously written to the fourth node N4 and the fifth node N5 to initialize the fourth node N4 and the fifth node N5 and clear their charge. The second node N2 continuously charges the third node N3.

[0052] In the fifth stage (S5), the signals at the first light-emitting signal terminal (EM1), the second reset signal terminal (Reset2), and the third reset signal terminal (Reset3) are high-level signals, while the signals at the scan signal terminal (Gate), the first reset signal terminal (Reset1), and the second light-emitting signal terminal (EM2) are low-level signals. The second transistor (T2) and the seventh transistor (T7) are turned on, while the first transistor (T1), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) are turned off.

[0053] The second transistor T2 and the seventh transistor T7 are turned on, and the signal at the second initial signal terminal INIT2 is continuously written to the fourth node N4 and the fifth node N5 to initialize and clear the charge of the fourth node N4 and the fifth node N5. The first transistor T1 is turned off. At this time, the voltage value of the signal at the third node N3 is Vinit1-Vth, and the charge stored in the first capacitor C1 is Vth, where Vinit1 is the voltage value of the signal at the first initial signal terminal INIT1, and Vth is the threshold voltage of the driving transistor.

[0054] In the sixth stage (S6), the data writing stage, the signals at the scan signal terminal Gate, the first light-emitting signal terminal EM1, the second reset signal terminal Reset2, and the third reset signal terminal Reset3 are high-level signals, while the signals at the first reset signal terminal Reset1 and the second light-emitting signal terminal EM2 are low-level signals. The second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on, while the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0055] The second transistor T2 and the seventh transistor T7 are turned on, and the signal at the second initial signal terminal INIT2 is continuously written to the fourth node N4 and the fifth node N5 to initialize the fourth node N4 and the fifth node N5 and clear their charges. The fourth transistor T4 is turned on, and the signal at the data signal terminal Data is written to the first node N1. The signal at the first node N1 changes direction, and under the action of the first capacitor C1, the signal at the third node N3 also changes direction. The voltage value of the signal at the third node N3 after the change is Vinit1-Vth+[C1 / (C1+C2)](Vdata-Vinit1), where C1 is the capacitance value of the first capacitor C1, C2 is the voltage value of the second capacitor C2, and Vdata is the voltage value of the signal at the data signal terminal Data.

[0056] In the seventh stage S7, the light-emitting stage, the signal of the second light-emitting signal terminal EM2 is a high-level signal, and the signals of the scan signal terminal Gate, the first reset signal terminal Reset1, the second reset signal terminal Reset2, the third reset signal terminal Reset3 and the first light-emitting signal terminal EM1 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned off.

[0057] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the fourth node N4, and the light-emitting device L emits light.

[0058] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its first electrode. The voltage value of the signal at the first node N1 is Vdata, and the voltage value of the signal at the third node N3 is Vinit1 - Vth + [C1 / (C1+C2)](Vdata - Vinit1). The difference Vgs between the voltage values ​​of the signals at the first node N1 and the third node N3 is [C2 / (C1+C2)](Vdata - Vinit1) + Vth. Therefore, the drive current I of the third transistor T3 is: I = K * (Vgs - Vth) 2 =K*[C2 / (C1+C2)](Vdata-Vinit1) 2 Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device L, and K is a constant related to the process and design.

[0059] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 in each pixel driving circuit is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product, and improving the display effect of the entire display product.

[0060] In addition, by setting the first light-emitting transistor as a P-type transistor, this disclosure can help increase the lateral trace space.

[0061] In an exemplary embodiment, Figure 5 This is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure. Figure 6 for Figure 5 Schematic diagram of part of the film layer Figure 1 , Figure 7 for Figure 5 Schematic diagram of part of the film layer Figure 2 . Figure 5 , Figure 6 and Figure 7 This explanation uses a single pixel as an example.

[0062] In an exemplary implementation, such as Figures 5 to 7 As shown, for at least one pixel driving circuit, the active pattern 51 of the first light-emitting transistor (also the fifth transistor T5) is made of polysilicon, and the active patterns of the other transistors (first transistor T1 to fourth transistor T4, sixth transistor T6 and seventh transistor T7) are made of metal oxide.

[0063] In an exemplary implementation, such as Figure 7 As shown, the active pattern 11 of the first reset transistor (also the first transistor) and the active pattern 41 of the write transistor (also the fourth transistor) in at least one pixel driving circuit are an integral structure, referred to as an active structure. The orthographic projection of the active pattern of the first light-emitting transistor (also the fifth transistor T5) in at least one pixel driving circuit onto the substrate at least partially overlaps with the orthographic projection of the active structure onto the substrate. The at least partial overlap of the orthographic projection of the active pattern of the first light-emitting transistor (also the fifth transistor T5) in at least one pixel driving circuit of this disclosure onto the substrate can reduce the area occupied by the pixel driving circuit and can achieve a high PPI of the display substrate.

[0064] In an exemplary implementation, such as Figures 5 to 7 As shown, the pixel driving circuit includes: a first pixel driving circuit P1, a second pixel driving circuit P2, and a third pixel driving circuit P3. At least one pixel unit includes: the first pixel driving circuit P1, the second pixel driving circuit P2, and the third pixel driving circuit P3 arranged along the first direction P1.

[0065] In an exemplary embodiment, the first pixel driving circuit P1 is configured to drive a light-emitting device that emits red light. The second pixel driving circuit P2 is configured to drive a light-emitting device that emits green light. The third pixel driving circuit P3 is configured to drive a light-emitting device that emits blue light.

[0066] In an exemplary implementation, such as Figure 7 As shown, the area of ​​the active pattern 31 of the driving transistor (also the third transistor T3) in the third pixel driving circuit located in the same pixel unit is greater than the area of ​​the active pattern 31 of the driving transistor (also the third transistor T3) in at least one of the first pixel driving circuit and the second pixel driving circuit.

[0067] In an exemplary implementation, such as Figure 5 As shown, the first pixel driving circuit P1 and the second pixel driving circuit P2 in at least one pixel unit are arranged in a mirror symmetry with respect to a straight line extending along the second direction D2. The structure of the second pixel driving circuit in at least one pixel unit, except for the active pattern of the driving transistor (which is also the third transistor T3), and the structure of the third pixel driving circuit, except for the active pattern of the driving transistor (which is also the third transistor T3), are arranged in a mirror symmetry with respect to a straight line extending along the second direction D2.

[0068] In an exemplary implementation, such as Figure 6 and Figure 7 As shown, the display substrate also includes: multiple first light-emitting signal lines EL1, multiple second light-emitting signal lines EL2, multiple first reset signal lines RL1, multiple second reset signal lines RL2, multiple third reset signal lines RL3, multiple scan signal lines GL, multiple power connection lines VCL, multiple first initial signal lines NL1, multiple second initial signal lines NL2, multiple third initial signal lines NL3, and multiple fourth initial signal lines NL4 disposed on the substrate. Specifically, the first reset signal line RL1 is electrically connected to the first reset signal terminal Reset1 of the pixel driving circuit; the second reset signal line RL2 is electrically connected to the second reset signal terminal Reset2 of the pixel driving circuit; the third reset signal line RL3 is electrically connected to the third reset signal terminal Reset3 of the pixel driving circuit; the first light emission signal line EL1 is electrically connected to the first light emission signal terminal EM1 of the pixel driving circuit; the second light emission signal line EL2 is electrically connected to the second light emission signal terminal EM2 of the pixel driving circuit; the scan signal line GL is electrically connected to the scan signal terminal GL of the pixel driving circuit; the first initial signal line NL1 is electrically connected to the first initial signal terminal INIT1 of the pixel driving circuit; the second initial signal line NL2 is electrically connected to the second initial signal terminal INIT2 of the first pixel driving circuit P1; the third initial signal line NL3 is electrically connected to the second initial signal terminal INIT2 of the second pixel driving circuit P2; and the fourth initial signal line NL4 is electrically connected to the second initial signal terminal INIT2 of the third pixel driving circuit P3.

[0069] In an exemplary embodiment, pixel driving circuits located in the same row are connected to the same first light-emitting signal line EL1. Pixel driving circuits located in the same row are connected to the same second light-emitting signal line EL2. Pixel driving circuits located in the same row are connected to the same first reset signal line RL1. Pixel driving circuits located in the same row are connected to the same second reset signal line RL2. Pixel driving circuits located in the same row are connected to the same third reset signal line RL3. Pixel driving circuits located in the same row are connected to the same scan signal line GL. Pixel driving circuits located in the same row are connected to the same power connection line VCL. Pixel driving circuits located in the same row are connected to the same first initial signal line NL1. The first pixel driving circuit in the pixel driving circuits located in the same row is connected to the same second initial signal line NL2. The second pixel driving circuit in the pixel driving circuits located in the same row is connected to the same third initial signal line NL3. The third pixel driving circuit in the pixel driving circuits located in the same row is connected to the same fourth initial signal line NL4.

[0070] In an exemplary embodiment, at least one of the following signal lines extends at least partially along the first direction D1: a plurality of first light-emitting signal lines EL1, a plurality of second light-emitting signal lines EL2, a plurality of first reset signal lines RL1, a plurality of second reset signal lines RL2, a plurality of third reset signal lines RL3, a plurality of scan signal lines GL, a plurality of power connection lines VCL, a plurality of first initial signal lines NL1, a plurality of second initial signal lines NL2, a plurality of third initial signal lines NL3, and a plurality of fourth initial signal lines NL4.

[0071] In an exemplary implementation, such as Figure 5 As shown, the display substrate also includes: multiple first power lines VL, multiple data signal lines DL, multiple first initial connection lines NCL1, multiple second initial connection lines NCL2, multiple third initial connection lines NCL3, and multiple fourth initial connection lines NCL4 disposed on the substrate. The first power lines VL are electrically connected to the first power supply terminal VDD of the pixel driving circuit, and the data signal lines DL are electrically connected to the data signal terminal Data of the pixel driving circuit.

[0072] In an exemplary embodiment, at least one of the following signal lines extends along a second direction D2: a plurality of first power lines VL, a plurality of data signal lines DL, a plurality of first initial connection lines NCL1, a plurality of second initial connection lines NCL2, a plurality of third initial connection lines NCL3, and a plurality of fourth initial connection lines NCL4.

[0073] In an exemplary embodiment, the first direction D1 intersects the second direction D2. Exemplarily, the angle between the first direction D1 and the second direction D2 can be in the range of 70 degrees to 90 degrees, and the first direction D1 can be perpendicular to the second direction D.

[0074] Figure 8 for Figure 6 Cross-sectional view along direction AA. Figure 9 for Figure 6 Cross-sectional view along the BB direction. Figure 10 for Figure 6 A cross-sectional view along the CC direction. (e.g.) Figures 6 to 9 As shown, in an exemplary embodiment, the orthographic projection of the first light-emitting signal line EL1 connected to at least one row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projection of the first reset signal line RL1 connected to at least one row of pixel driving circuits on the substrate.

[0075] In this disclosure, the orthographic projection of the first light-emitting signal line EL1 connected to at least one row of pixel driving circuits on the substrate and the orthographic projection of the first reset signal line RL1 connected to at least one row of pixel driving circuits on the substrate at least partially overlap, which can reduce the area occupied by the pixel driving circuits and achieve a high PPI of the display substrate.

[0076] In an exemplary implementation, such as Figure 7 As shown, for at least one pixel driving circuit, the minimum distance W between the orthographic projection of the first plate C11 of the first capacitor in the pixel driving circuit on the substrate and the orthographic projection of the first light-emitting signal line EL1 connected to the pixel driving circuit on the substrate along the second direction D2 is greater than the length L of the control electrode 42 of the write transistor (also the fourth transistor) in the pixel driving circuit along the second direction D2.

[0077] In this disclosure, the minimum distance W between the orthographic projection of the first electrode C11 of the first capacitor in the pixel driving circuit onto the substrate and the orthographic projection of the first light-emitting signal line EL1 connected to the pixel driving circuit onto the substrate along the second direction D2 is greater than the length L of the control electrode 42 of the write transistor (also the fourth transistor) in the pixel driving circuit along the second direction D2. This can increase the spacing between the first electrode C11 of the first capacitor in the pixel driving circuit and the first light-emitting signal line EL1 connected to the pixel driving circuit, thereby reducing the parasitic capacitance between them, improving the multi-pulse horizontal stripes of the display substrate, and enhancing the display effect of the display substrate.

[0078] In an exemplary implementation, such as Figure 5As shown, the second terminal 14 of the first reset transistor (also the first transistor) and the second terminal 44 of the write transistor (also the fourth transistor) in at least one pixel driving circuit are integrated into a single structure, referred to as a node structure. The node structure is also electrically connected to the control terminal 32 of the driving transistor (also the third transistor T3). This node structure is the first node N1 in the pixel driving circuit. For at least one pixel driving circuit, the orthographic projection of the node structure on the substrate and the orthographic projection of the data signal line DL connected to the pixel driving circuit on the substrate are located on different sides of the orthographic projection of the first power line VL connected to the pixel driving circuit on the substrate.

[0079] In an exemplary implementation of the protection, at least a portion of the first power line VL connected to the pixel driving circuit passes through the centerline of the pixel driving circuit extending in the second direction. That is, the orthographic projection of the node structure in the pixel driving circuit onto the substrate and the orthographic projection of the data signal line DL connected to the pixel driving circuit onto the substrate are located on opposite sides of the pixel driving circuit.

[0080] The orthographic projection of the node structure on the substrate in the pixel driving circuit of this disclosure and the orthographic projection of the data signal line DL connected to the pixel driving circuit on the substrate are located on different sides of the orthographic projection of the first power line VL connected to the pixel driving circuit on the substrate. This reduces the parasitic capacitance between the signal of the data signal line DL and the first node N1 in the pixel driving circuit, reduces the crosstalk between the signal of the data signal line DL and the first node N1, ensures the stability of the signal of the first node N1 in the pixel driving circuit, and thus improves the reliability of the pixel driving circuit.

[0081] In an exemplary embodiment, combined with Figure 5 and Figure 6 As shown, at least one power connection line VCL is electrically connected to multiple first power lines VL. This electrical connection allows the multiple first power lines VL to be interwoven horizontally and vertically, ensuring that the signals at the first power terminals in different pixel driving circuits are identical, thus guaranteeing the display uniformity of the display substrate.

[0082] In an exemplary implementation, such as Figure 6 , Figure 8 and Figure 9 As shown, the orthographic projection of the power connection line VCL connected to at least one row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projection of the first light-emitting signal line EL1 connected to at least one row of pixel driving circuits on the substrate. For example, the orthographic projection of the power connection line connected to the i-th row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projection of the first light-emitting signal line EL1 connected to the i-th row of pixel driving circuits on the substrate.

[0083] The orthographic projection of the power connection line connected to at least one row of pixel driving circuits on the substrate and the orthographic projection of the first light-emitting signal line EL1 connected to at least one row of pixel driving circuits on the substrate at least partially overlap, which can reduce the area occupied by the pixel driving circuits and achieve a high PPI of the display substrate.

[0084] In an exemplary implementation, such as Figure 6 , Figure 8 and Figure 9 As shown, the orthographic projection of the scan signal line GL connected to at least one row of pixel driving circuits on the substrate 100 at least partially overlaps with the orthographic projection of the first reset signal line RL1 connected to at least one row of pixel driving circuits on the substrate 100. For example, the orthographic projection of the scan signal line GL connected to the i-th row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projection of the first reset signal line RL1 connected to the i-th row of pixel driving circuits on the substrate.

[0085] In an exemplary embodiment, the orthographic projection of the scan signal line GL connected to at least one row of pixel driving circuits on the substrate and the orthographic projection of the first reset signal line RL1 connected to at least one row of pixel driving circuits on the substrate at least partially overlaps, which can reduce the area occupied by the pixel driving circuits and achieve a high PPI of the display substrate.

[0086] In an exemplary implementation, such as Figure 6 As shown, at least a portion of the orthographic projection of the first reset signal line RL1 connected to at least one row of pixel driving circuits onto the substrate lies between the orthographic projection of the power connection line VCL connected to at least one row of pixel driving circuits onto the substrate and the orthographic projection of the scan signal line GL connected to at least one row of pixel driving circuits onto the substrate. Exemplarily, at least a portion of the orthographic projection of the first reset signal line RL1 connected to the i-th row of pixel driving circuits onto the substrate lies between the orthographic projection of the power connection line connected to the i-th row of pixel driving circuits onto the substrate and the orthographic projection of the scan signal line connected to the i-th row of pixel driving circuits onto the substrate.

[0087] In an exemplary embodiment, the orthographic projection of at least a portion of the first reset signal line RL1 connected to at least one row of pixel driving circuits on the substrate is located between the orthographic projection of the power connection line connected to at least one row of pixel driving circuits on the substrate and the orthographic projection of the scan signal line connected to at least one row of pixel driving circuits on the substrate. This can reduce the parasitic capacitance between the first reset signal line RL1 and the scan signal line GL and between the first reset signal line RL1 and the power connection line, avoid crosstalk between the signals of the first reset signal line RL1 and the scan signal line GL and between the first reset signal line RL1 and the power connection line, and improve the reliability of the display substrate.

[0088] In an exemplary implementation, such as Figure 6 and Figure 7 As shown, at least one pixel driving circuit further includes: a first capacitor C1 and a second capacitor C2, and at least one of the first capacitor and the second capacitor includes: a first electrode plate and a second electrode plate.

[0089] In an exemplary embodiment, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are arranged along the second direction D2, and the area of ​​the first plate of the first capacitor C1 is larger than the area of ​​the first plate of the second capacitor C2.

[0090] In an exemplary embodiment, the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 are an integral structure.

[0091] In an exemplary implementation, such as Figure 7 As shown, the first plate C11 of the first capacitor C1 includes: a first capacitor body part C11A and a first capacitor connection part C11B connected to each other, and the first capacitor body part C11A and the first capacitor connection part C11B are arranged along the first direction D1.

[0092] In an exemplary implementation, such as Figure 7 As shown, the first plate C21 of the second capacitor C2 includes: a second capacitor body part C22A and a second capacitor connection part C22B connected to each other, and the second capacitor body part C22A and the second capacitor connection part C22B are arranged along the first direction D1.

[0093] In an exemplary implementation, such as Figure 7 As shown, the first capacitor connection portion C11B and the second capacitor connection portion C22B are located on different sides of at least one of the main body portions C11A and C22A, respectively.

[0094] In an exemplary implementation, such as Figure 7 As shown, the orthographic projection of the integrated structure of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 on the substrate covers the orthographic projection of the main body C11A and the main body C22A of the first capacitor on the substrate, and does not overlap with the orthographic projection of the connecting part C11B and the connecting part C22B of the first capacitor on the substrate.

[0095] In an exemplary implementation, such as Figure 6 As shown, the orthographic projection of at least one of the second light-emitting signal lines EL2 and the third reset signal line RL3 connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second capacitor C2 in at least one pixel driving circuit on the substrate.

[0096] In an exemplary embodiment, the orthographic projection of at least one of the second light-emitting signal lines EL2 and the third reset signal line RL3 connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second capacitor C2 in at least one pixel driving circuit on the substrate, which can reduce the area occupied by the pixel driving circuit and achieve a high PPI of the display substrate.

[0097] In an exemplary implementation, such as Figure 6 As shown, the second initial signal line NL2 is located on the side of the fourth initial signal line NL4 closer to the substrate, while the third initial signal line NL3 and the first initial signal line NL1 are located on the side of the fourth initial signal line NL4 farther from the substrate.

[0098] In an exemplary embodiment, connecting the second initial signal lines of different pixel driving circuits in the same pixel unit to different signal lines can improve the display effect of the display substrate at low grayscale.

[0099] In an exemplary implementation, such as Figure 6 As shown, the orthographic projection of the second initial signal line NL2 connected to at least one row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projection of the third initial signal line NL3 connected to at least one row of pixel driving circuits on the substrate, while the orthographic projections of the second initial signal line NL2 and the third initial signal line NL3 connected to at least one row of pixel driving circuits on the substrate do not overlap with the orthographic projection of the fourth initial signal line NL4 connected to at least one row of pixel driving circuits on the substrate. For example, the orthographic projection of the second initial signal line NL2 connected to the i-th row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projection of the third initial signal line NL3 connected to the i-th row of pixel driving circuits on the substrate, while the orthographic projections of the second initial signal line NL2 and the third initial signal line NL3 connected to the i-th row of pixel driving circuits on the substrate do not overlap with the orthographic projection of the fourth initial signal line NL4 connected to the i-th row of pixel driving circuits on the substrate.

[0100] In an exemplary implementation, such as Figure 6 As shown, the orthographic projection of the second reset signal line RL2 connected to at least one row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projections of the second initial signal line NL2 and the third initial signal line NL3 connected to at least one row of pixel driving circuits on the substrate, but does not overlap with the orthographic projection of the fourth initial signal line NL4 connected to at least one row of pixel driving circuits on the substrate. For example, the orthographic projection of the second reset signal line RL2 connected to the i-th row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projections of the second initial signal line NL2 and the third initial signal line NL3 connected to the i-th row of pixel driving circuits on the substrate, but does not overlap with the orthographic projection of the fourth initial signal line NL4 connected to the i-th row of pixel driving circuits on the substrate.

[0101] The orthographic projection of the second reset signal line RL2 connected to at least one row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projections of the second initial signal line NL2 and the third initial signal line NL3 connected to at least one row of pixel driving circuits on the substrate, and the orthographic projection of the second initial signal line NL2 connected to at least one row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projection of the third initial signal line NL3 connected to at least one row of pixel driving circuits on the substrate, can reduce the area occupied by the pixel driving circuits and achieve a high PPI of the display substrate.

[0102] In an exemplary embodiment, combined with Figure 5 and Figure 6 As shown, at least one first initial connection line NCL1 is electrically connected to multiple first initial signal lines NL1. This electrical connection ensures that the multiple first initial connection lines NCL1 and NL1 are interwoven, guaranteeing that the signals at the first initial signal terminals connected to different pixel driving circuits are identical, thus improving the uniformity of the display substrate.

[0103] In an exemplary embodiment, combined with Figure 5 and Figure 6 As shown, at least one second initial connection line NCL2 is electrically connected to multiple second initial signal lines NL2. This electrical connection ensures that the multiple second initial connection lines NCL2 and NL2 are interwoven, guaranteeing that the signals at the second initial signal terminals connected to different first pixel driving circuits are identical, thus improving the uniformity of the display substrate.

[0104] In an exemplary embodiment, combined with Figure 5 and Figure 6 As shown, at least one third initial connection line NCL3 is electrically connected to multiple third initial signal lines NL3. This electrical connection ensures that the multiple third initial connection lines NCL3 and NL3 are interwoven, guaranteeing that the signals at the second initial signal terminals connected to different second pixel driving circuits are identical, thus improving the uniformity of the display substrate.

[0105] In an exemplary embodiment, combined with Figure 5 and Figure 6As shown, at least one fourth initial connection line NCL4 is electrically connected to multiple fourth initial signal lines NL4. This electrical connection ensures that the multiple fourth initial connection lines NCL4 and NL4 are interwoven, guaranteeing that the signals at the second initial signal terminals connected to different third pixel driving circuits are identical, thus improving the uniformity of the display substrate.

[0106] In an exemplary embodiment, at least one of the first initial connection line NCL1, the second initial connection line NCL2, the third initial connection line NCL3, and the fourth initial connection line NCL4 is located on the side of the first initial signal line NL1, the second initial signal line NL2, the third initial signal line NL3, and the fourth initial signal line NL4 that is away from the substrate.

[0107] Figure 11 This is a schematic diagram of the structure of the display substrate in an exemplary embodiment. Figure 1 The first pixel driving circuits in different pixel units located in the same row of pixel units have the same structure. Figure 11 The node structure in the first pixel driving circuit of the provided second pixel unit is close to the data signal line connected to the third pixel driving circuit of the first pixel unit.

[0108] Figure 12 This is a schematic diagram of the structure of the display substrate in an exemplary embodiment. Figure 2 The first pixel driving circuit in different pixel units located in the same row of pixel units is arranged in a mirror-symmetric manner with respect to a straight line extending along the second direction D2. Figure 12 The node structure in the first pixel driving circuit of the provided second pixel unit is far from the data signal line connected to the third pixel driving circuit of the first pixel unit, which avoids crosstalk between the two signals and can improve the reliability of the display substrate.

[0109] In an exemplary implementation, such as Figure 6 and Figure 10 As shown, in at least one pixel driving circuit, the control electrodes of the transistors other than the first light-emitting transistor (also the fifth transistor T5) are located on the side of the active pattern away from the substrate. That is, all N-type transistors in the pixel driving circuit are single-gate structures.

[0110] In an exemplary embodiment, all N-type transistors in the pixel driving circuit are single-gate structures, which not only reduces the area occupied by the pixel driving circuit and achieves a high PPI of the display substrate, but also reduces the parasitic capacitance in the N-type transistors, improves the follow-up ratio of the pixel driving circuit, and thus improves the threshold compensation effect of the pixel driving circuit.

[0111] In an exemplary embodiment, the display substrate further includes a circuit structure layer disposed on the substrate, the circuit structure layer including a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially stacked on the substrate.

[0112] In an exemplary implementation, such as Figure 5 and Figure 6 As shown, the first semiconductor layer includes at least an active pattern of a first light-emitting transistor (also the fifth transistor T5) located in at least one pixel driving circuit.

[0113] In an exemplary implementation, such as Figure 5 and Figure 6 As shown, the first conductive layer includes at least: the control electrode of the first light-emitting transistor (also the fifth transistor T5) located in at least one pixel driving circuit and the first plate of at least one capacitor, multiple first light-emitting signal lines EL1 and multiple second initial signal lines NL2.

[0114] In an exemplary implementation, such as Figure 5 and Figure 6 As shown, the second conductive layer includes at least: the second plate of at least one capacitor located in at least one pixel driving circuit and multiple fourth initial signal lines NL4.

[0115] In an exemplary implementation, such as Figure 5 and Figure 6 As shown, the second semiconductor layer includes at least: an active pattern of the remaining transistors, excluding the first light-emitting transistor (which is also the fifth transistor T5), located in at least one pixel driving circuit.

[0116] In an exemplary implementation, such as Figure 5 and Figure 6 As shown, the third conductive layer includes at least: the control electrode of the transistors other than the first light-emitting transistor (which is also the fifth transistor T5) located in at least one pixel driving circuit, multiple first reset signal lines RL1 and multiple second reset signal lines RL2.

[0117] In an exemplary implementation, such as Figure 5 and Figure 6 As shown, the fourth conductive layer includes at least: the first and second poles of a plurality of transistors located in at least one pixel driving circuit, a plurality of first initial signal lines NL1, a plurality of power connection lines VCL, a plurality of scan signal lines GL, a plurality of second light emission signal lines EL2, a plurality of third reset signal lines RL3, and a plurality of third initial signal lines NL3.

[0118] In an exemplary embodiment, the fifth conductive layer includes at least: multiple data signal lines DL, multiple first power lines VL, multiple first initial connection lines NCL1, multiple second initial connection lines NCL2, multiple third initial connection lines NCL3, and multiple fourth initial connection lines NCL4.

[0119] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0120] Figures 13 to 27 A schematic diagram of the fabrication process of a display substrate provided for an exemplary embodiment. Figures 13 to 27 This explanation uses a single pixel as an example.

[0121] The following is based on... Figures 13 to 27 As shown, the fabrication process of the display substrate provided in this disclosure may include: (1) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming a first semiconductor layer pattern may include: depositing a first semiconductor thin film on a substrate, and patterning the first semiconductor thin film using a patterning process to form a first semiconductor layer pattern, such as... Figure 13 As shown, Figure 13 for Figure 5 A schematic diagram of the pattern of the first semiconductor layer.

[0122] In an exemplary implementation, such as Figure 13As shown, the first semiconductor layer pattern may include at least: an active pattern of at least one P-type transistor located in at least one pixel driving circuit. The active pattern of the at least one P-type transistor includes: an active pattern 51 of a fifth transistor.

[0123] In an exemplary embodiment, for the same pixel unit, the active pattern of at least one P-type transistor of at least one pixel driving circuit is at least partially symmetrical with respect to the active pattern of at least one P-type transistor of an adjacent pixel driving circuit with respect to a straight line extending along the second direction D2.

[0124] In an exemplary embodiment, the active pattern 51 of the fifth transistor includes a first active portion 51A and a second active portion 51B interconnected. The first active portion 51A extends along a first direction D1, and the second active portion 51B extends along a second direction D2. The first active portion 51A and the second active portion 51B are arranged at right angles.

[0125] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 51-1 and the second region 51-2 of the active pattern 51 of the fifth transistor of at least one pixel driving circuit are separately configured.

[0126] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first insulating film and the first conductive film using a patterning process to form a first insulating layer pattern and a first conductive layer pattern located on the first insulating layer, such as 14 and Figure 15 As shown, where, Figure 14 for Figure 5 A schematic diagram of the pattern of the first conductive layer. Figure 15 for Figure 5 A schematic diagram showing the formation of the first conductive layer pattern. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0127] In an exemplary implementation, such as Figure 14 and Figure 15 As shown, the first conductive layer pattern may include: a control electrode of at least one P-type transistor located in at least one pixel driving circuit and a first electrode of at least one capacitor; a first light-emitting signal line EL1 connected to at least one pixel driving circuit; and a second initial signal line NL2 connected to the first pixel driving circuit P1. The first electrode of the at least one capacitor includes: a first electrode C11 of the first capacitor and a second electrode C21 of the second capacitor. The control electrode of the at least one P-type transistor includes: a control electrode 52 of the fifth transistor.

[0128] In an exemplary embodiment, for the same pixel unit, the control electrode of at least one P-type transistor and the first plate of at least one capacitor of at least one pixel driving circuit are at least partially symmetrical with respect to a straight line extending along the second direction D2.

[0129] In an exemplary embodiment, the main body of the first light-emitting signal line EL1 has a line shape along the first direction D1. The overlapping area of ​​the first light-emitting signal line EL1 and the active pattern of the fifth transistor in the connected pixel driving circuit can serve as the control electrode 52 of the fifth transistor.

[0130] In an exemplary embodiment, the main body portion of the second initial signal line NL2 has a line shape along the first direction D1.

[0131] In an exemplary embodiment, the orthographic projection of at least one of the first plates of the first capacitor C11 and the first plate of the second capacitor C21 in at least one pixel driving circuit of the i-th row pixel driving circuit is located between the orthographic projections of the first light-emitting signal line EL1 connected to the i-th row pixel driving circuit and the second initial signal line NL2 connected to the i-th row pixel driving circuit on the substrate.

[0132] In an exemplary embodiment, the first plate C11 of the first capacitor and the first plate C21 of the second capacitor are arranged along the second direction D2, and the area of ​​the first plate C11 of the first capacitor is larger than the area of ​​the first plate C21 of the second capacitor.

[0133] In an exemplary embodiment, the first plate C11 of the first capacitor includes a first capacitor body portion C11A and a first capacitor connection portion C11B. The first capacitor body portion C11A and the first capacitor connection portion C11B are arranged along a first direction D1.

[0134] In an exemplary embodiment, for at least one pixel driving circuit, the shape of the first capacitor body portion C11A can be rectangular, and the corners of the rectangle can be chamfered. The shape of the first capacitor connection portion C11B can be block-shaped.

[0135] In an exemplary embodiment, the first plate C21 of the second capacitor includes: a second capacitor body portion C21A and a second capacitor connection portion C21B connected to each other. The second capacitor body portion C21A and the second capacitor connection portion C21B are arranged along a first direction D1.

[0136] In an exemplary embodiment, for at least one pixel driving circuit, the shape of the second capacitor body portion C21A can be rectangular, and the corners of the rectangle can be chamfered. The shape of the second capacitor connection portion C21B can be a polygonal line.

[0137] In an exemplary embodiment, the first capacitor connection portion C11B and the second capacitor connection portion C21B are located on different sides of at least one of the main body portions of the first capacitor body portion C11A and the second capacitor body portion C21A.

[0138] In an exemplary embodiment, the control electrode 52 of the fifth transistor is disposed across the active pattern of the fifth transistor.

[0139] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed, and patterning the second insulating film and the second conductive film using a patterning process to form a second insulating layer pattern and a second conductive layer pattern located on the second insulating layer. Figure 16 and Figure 17 As shown, Figure 16 for Figure 5 A schematic diagram of the pattern of the second conductive layer. Figure 17 for Figure 5 A schematic diagram showing the formation of the second conductive layer pattern. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0140] In an exemplary implementation, such as Figure 16 and Figure 17 As shown, the second conductive layer pattern may include: the second plate C12 of the first capacitor and the second plate C22 of the second capacitor located in at least one pixel driving circuit, and the fourth initial signal line NL4 connected to the third pixel driving circuit P3.

[0141] In an exemplary embodiment, for the same pixel unit, the second plate C12 of the first capacitor and the second plate C22 of the second capacitor located in at least one pixel driving circuit are at least partially symmetrical with respect to a straight line extending along the second direction D2.

[0142] In an exemplary embodiment, the second plate C12 of the first capacitor and the second plate C22 of the second capacitor are integrally formed. The main outline of the integral structure of the second plate C12 and the second plate C22 of the first capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the integral structure of the second plate C12 and the second plate C22 of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the first capacitor on the substrate, and at least partially overlaps with the orthographic projection of the first plate of the second capacitor on the substrate.

[0143] In an exemplary embodiment, the orthographic projection of the integrated structure of the second electrode C12 of the first capacitor and the second electrode C22 of the second capacitor onto the substrate covers the orthographic projection of the main body of the first capacitor and the main body of the second capacitor onto the substrate, and does not overlap with the orthographic projection of the connection part of the first capacitor and the connection part of the second capacitor onto the substrate.

[0144] In an exemplary embodiment, the shape of the fourth initial signal line NL4 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the fourth initial signal line NL4 connected to the i-th row pixel driving circuit on the substrate is located on the side of the orthographic projection of the second initial signal line NL2 connected to the i-th row pixel driving circuit on the substrate away from the orthographic projection of at least one of the first and second capacitors in at least one pixel driving circuit of the i-th row pixel driving circuit on the substrate.

[0145] (4) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: sequentially depositing a third insulating film and a second semiconductor film on a substrate, and patterning the third insulating film and the second semiconductor film using a patterning process to form a third insulating layer covering the substrate and a second semiconductor layer pattern disposed on the third insulating layer, such as... Figure 18 and Figure 19 As shown, Figure 18 for Figure 5 A schematic diagram of the pattern of the second semiconductor layer. Figure 19 for Figure 5 A schematic diagram after the second semiconductor layer pattern has been formed.

[0146] In an exemplary implementation, such as Figure 18 and Figure 19 As shown, the second semiconductor layer pattern may include at least the active pattern of at least one N-type transistor located in at least one pixel driving circuit. The active pattern of at least one N-type transistor includes: an active pattern 11 of a first transistor, an active pattern 21 of a second transistor, an active pattern 31 of a third transistor, an active pattern 41 of a fourth transistor, an active pattern 61 of a sixth transistor, and an active pattern 71 of a seventh transistor.

[0147] In an exemplary embodiment, for the same pixel unit, the active patterns 11 of the first transistor, the active patterns 21 of the second transistor, the active patterns 41 of the fourth transistor, the active patterns 61 of the sixth transistor, and the active patterns 71 of the seventh transistor of at least one pixel driving circuit and the active patterns 11 of the first transistor, the active patterns 21 of the second transistor, the active patterns 41 of the fourth transistor, the active patterns 61 of the sixth transistor, and the active patterns 71 of the seventh transistor of an adjacent pixel driving circuit are at least partially symmetrically arranged with respect to a straight line extending along the second direction D2.

[0148] In an exemplary embodiment, for the same pixel unit, the active pattern 31 of the third transistor in the first pixel driving circuit P1 and the active pattern 31 of the third transistor in the second pixel driving circuit P2 are at least partially symmetrically arranged with respect to a straight line extending along the second direction D2.

[0149] In an exemplary embodiment, for at least one pixel driving circuit, the active pattern 11 of the first transistor and the active pattern 41 of the fourth transistor are an integral structure. The active patterns 21 of the second transistor, the active patterns 61 of the sixth transistor, and the active patterns 71 of the seventh transistor are an integral structure. The active pattern 31 of the third transistor is separately provided.

[0150] In an exemplary embodiment, in the first direction D1, the active pattern 11 of the first transistor, the active pattern 21 of the second transistor, and the active pattern 61 of the sixth transistor may be located on the same side of the active pattern 31 of the third transistor. In the second direction D2, the active pattern 41 of the fourth transistor may be located on the side of the active pattern 31 of the third transistor closer to the pixel driving circuit in the upper row, and the active pattern 71 of the seventh transistor may be located on the side of the active pattern 31 of the third transistor closer to the pixel driving circuit in the lower row.

[0151] In an exemplary embodiment, for the same pixel driving circuit, the active pattern 11 of the first transistor, the active pattern 61 of the sixth transistor, and the active pattern 21 of the second transistor are arranged in sequence along the second direction D2. The active pattern 41 of the fourth transistor and the active pattern 71 of the seventh transistor are arranged along the second direction D2.

[0152] In an exemplary embodiment, the shape of at least one of the active patterns 11 of the first transistor, the active patterns 21 of the second transistor, the active patterns 31 of the third transistor, and the active patterns 61 of the sixth transistor is an "I" shape. The shape of the active pattern 71 of the seventh transistor is a "-" shape. The shape of the active pattern 41 of the fourth transistor is a "7" shape or a horizontally flipped "7" shape.

[0153] In an exemplary embodiment, the orthographic projection of the active pattern 11 of the first transistor in at least one pixel driving circuit of the i-th row pixel driving circuit onto the substrate overlaps with the orthographic projection of the first light-emitting signal line connected to the i-th row pixel driving circuit onto the substrate, and the orthographic projection onto the substrate overlaps with the orthographic projection of the second plate of the first capacitor and the second plate of the second capacitor onto the substrate.

[0154] In an exemplary embodiment, the orthographic projection of the active pattern 21 of the second transistor in at least one pixel driving circuit of the i-th row pixel driving circuit onto the substrate overlaps with the orthographic projection of the second initial signal line connected to the i-th row pixel driving circuit onto the substrate.

[0155] In an exemplary embodiment, for at least one row of pixel driving circuits, the orthographic projection of the active pattern 31 of the third transistor in at least one pixel driving circuit onto the substrate is located within the range of the orthographic projection of the second plate of the first capacitor and the second plate of the second capacitor onto the substrate.

[0156] In an exemplary embodiment, the area of ​​the active pattern 31 of the third transistor in the first pixel driving circuit P1 and the second pixel driving circuit P2 is smaller than the area of ​​the active pattern 31 of the third transistor in the third pixel driving circuit P3.

[0157] In an exemplary embodiment, the aspect ratio of the active pattern 31 of the third transistor in the third pixel driving circuit P3 is greater than the aspect ratio of the active pattern 31 of the third transistor in the first pixel driving circuit P1 and the second pixel driving circuit P2.

[0158] In an exemplary embodiment, the orthographic projection of the portion of the active pattern 41 of the fourth transistor extending along the first direction D1 onto the substrate overlaps with the orthographic projection of the second active portion onto the substrate.

[0159] In an exemplary embodiment, the orthographic projection of the active pattern 61 of the sixth transistor in at least one pixel driving circuit onto the substrate overlaps with the orthographic projection of the second plate of the first capacitor and at least one of the second plates of the second capacitor onto the substrate.

[0160] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. For at least one pixel driving circuit, the second region 11-2 of the active pattern of the first transistor may simultaneously serve as the second region 41-2 of the active pattern 41 of the fourth transistor, and the second region 21-2 of the active pattern 21 of the second transistor may simultaneously serve as the second region 61-2 of the active pattern 61 of the sixth transistor and the second region 71-2 of the active pattern 71 of the seventh transistor. The first region 11-1 of the active pattern 11 of the first transistor, the first region 21-1 of the active pattern of the second transistor, the first region 31-1 and the second region 31-2 of the active pattern of the third transistor, the first region 61-1 of the active pattern 61 of the sixth transistor, and the first region 71-1 of the active pattern 71 of the seventh transistor may be set individually.

[0161] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: sequentially depositing a fourth insulating film and a third conductive film on a substrate, and patterning the fourth insulating film and the third conductive film using a patterning process to form a fourth insulating layer covering the substrate and a third conductive layer pattern disposed on the fourth insulating layer, such as... Figure 20 and Figure 21 As shown, Figure 20 for Figure 5 A schematic diagram of the pattern of the third conductive layer. Figure 21 for Figure 5 A schematic diagram after the third conductive layer pattern has been formed.

[0162] In an exemplary implementation, such as Figure 20 and Figure 21 As shown, the third conductive layer pattern includes: a control electrode of at least one N-type transistor located in at least one pixel driving circuit, and a first reset signal line RL1 and a second reset signal line RL2 connected to at least one row of pixel driving circuits. The control electrode of at least one N-type transistor includes: a control electrode 12 of a first transistor, a control electrode 22 of a second transistor, a control electrode 32 of a third transistor, a control electrode 42 of a fourth transistor, a control electrode 62 of a sixth transistor, and a control electrode 72 of a seventh transistor.

[0163] In an exemplary embodiment, for the same pixel unit, the control electrode of at least one N-type transistor of at least one pixel driving circuit is at least partially symmetrical with respect to the control electrode of at least one N-type transistor of an adjacent pixel driving circuit with respect to a straight line extending along the second direction D2.

[0164] In an exemplary embodiment, the main body of the first reset signal line RL1 is a line shape extending along the first direction D1. The overlapping region of the first reset signal line RL1 connected to the i-th row pixel driving circuit and the active pattern of the first transistor in at least one pixel driving circuit of the i-th row pixel driving circuit can serve as the control electrode 12 of the first transistor.

[0165] In an exemplary embodiment, the orthographic projection of the first reset signal line RL1 connected to the i-th row pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the first light emission signal line connected to the i-th row pixel driving circuit on the substrate.

[0166] In an exemplary embodiment, the main body of the second reset signal line RL2 is a line shape extending along the first direction D1. The overlapping region of the second reset signal line RL2 connected to the i-th row pixel driving circuit and the active pattern of the second transistor in at least one pixel driving circuit of the i-th row pixel driving circuit can serve as the control electrode 22 of the second transistor.

[0167] In an exemplary embodiment, the orthographic projection of the second reset signal line RL2 connected to the i-th row pixel driving circuit on the substrate overlaps at least partially with the orthographic projection of the second initial signal line connected to the i-th row pixel driving circuit on the substrate, but does not overlap with the orthographic projection of the fourth initial signal line connected to the i-th row pixel driving circuit on the substrate.

[0168] In an exemplary embodiment, for at least one pixel driving circuit, the control electrode 32 of the third transistor is provided separately. The control electrode 32 of the third transistor is rectangular in shape.

[0169] In an exemplary embodiment, for at least one pixel driving circuit, the control electrode 42 of the fourth transistor is provided separately. The control electrode 42 of the fourth transistor is strip-shaped and extends along the second direction D2.

[0170] In an exemplary embodiment, for at least one pixel driving circuit, the control electrode 62 of the sixth transistor is provided separately. The control electrode 62 of the sixth transistor is strip-shaped and extends along the first direction D1.

[0171] In an exemplary embodiment, for at least one pixel driving circuit, the control electrode 72 of the seventh transistor is provided separately. The control electrode 72 of the seventh transistor is strip-shaped and extends along the second direction D2.

[0172] In an exemplary embodiment, the control electrode of the first transistor is disposed across the active pattern of the first transistor, the control electrode of the second transistor is disposed across the active pattern of the second transistor, the control electrode of the third transistor is disposed across the active pattern of the third transistor, the control electrode of the fourth transistor is disposed across the active pattern of the fourth transistor, the control electrode of the sixth transistor is disposed across the active pattern of the sixth transistor, and the control electrode of the seventh transistor is disposed across the active pattern of the seventh transistor. That is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0173] (6) Forming a fifth insulating layer pattern includes: depositing a fifth insulating film on a substrate having the aforementioned pattern, and patterning the fifth insulating film using a patterning process to form a fifth insulating layer pattern covering the aforementioned pattern. The fifth insulating layer has multiple via patterns, such as... Figure 22 As shown, Figure 22 for Figure 5 A schematic diagram after the fifth insulating layer pattern has been formed.

[0174] In an exemplary implementation, such as Figure 22 As shown, the plurality of vias in the fifth insulating layer pattern include at least: a first via V1 to an eighteenth via V18, a nineteenth via V19, and a twentieth via V20 located in at least one pixel driving circuit.

[0175] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the orthographic projection of the first region of the active pattern of the fifth transistor onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the first via V1 are etched away, exposing the surface of the first region of the active pattern of the fifth transistor. The first via V1 is configured to allow the first electrode of the subsequently formed fifth transistor to be connected to the first region of the active pattern of the fifth transistor through the via.

[0176] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the orthographic projection of the second region of the active pattern of the fifth transistor onto the substrate. The fourth, third, second, and first insulating layers within the second via V2 are etched away, exposing the surface of the second region of the active pattern of the fifth transistor. The second via V2 is configured to allow the first electrode of the subsequently formed third transistor (which is also the second electrode of the fifth transistor) to be connected to the second region of the active pattern of the fifth transistor through the via.

[0177] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is within the range of the orthographic projection of the first electrode plate of the first capacitor on the substrate. The fourth insulating layer, the third insulating layer and the second insulating layer in the third via V3 are etched away, exposing the surface of the first electrode plate of the first capacitor. The third via V3 is configured to allow the second electrode of the subsequently formed first transistor (which is also the second electrode of the fourth transistor) to be connected to the first electrode plate of the first capacitor through the via.

[0178] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is within the range of the orthographic projection of the first electrode of the second capacitor on the substrate. The fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via V4 are etched away, exposing the surface of the first electrode of the second capacitor. The fourth via V4 is configured to allow the first electrode of the subsequently formed seventh transistor to be connected to the first electrode of the second capacitor through the via.

[0179] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is located within the range of the orthographic projection of the second plate of the first capacitor (which is also the second plate of the second capacitor) onto the substrate. The fourth and third insulating layers within the fifth via V5 are etched away, exposing the surface of the second plate of the first capacitor (which is also the second plate of the second capacitor). The fifth via V5 is configured to allow the second electrode of the subsequently formed third transistor (which is also the first electrode of the sixth transistor) to be connected to the second plate of the first capacitor (which is also the second plate of the second capacitor) through the via.

[0180] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the orthographic projection range of the first region of the active pattern of the first transistor onto the substrate. The fourth insulating layer within the sixth via V6 is etched away, exposing the surface of the first region of the active pattern of the first transistor. The sixth via V6 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first region of the active pattern of the first transistor through the via.

[0181] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate lies within the orthographic projection of the second region of the active pattern of the first transistor (which is also the second region of the active pattern of the fourth transistor) onto the substrate. The fourth insulating layer within the seventh via V7 is etched away, exposing the surface of the second region of the active pattern of the first transistor (which is also the second region of the active pattern of the fourth transistor). The seventh via V7 is configured to allow the second electrode of the subsequently formed first transistor (which is also the second electrode of the fourth transistor) to be connected to the second region of the active pattern of the first transistor (which is also the second region of the active pattern of the fourth transistor) through the via.

[0182] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the range of the orthographic projection of the first region of the active pattern of the second transistor onto the substrate. The fourth insulating layer within the eighth via V8 is etched away, exposing the surface of the first region of the active pattern of the second transistor. The eighth via V8 is configured to allow the first electrode of the subsequently formed second transistor to be connected to the first region of the active pattern of the second transistor through the via.

[0183] In an exemplary embodiment, the orthogonal projection of the ninth via V9 onto the substrate lies within the range of the orthogonal projection of the second region of the active pattern of the second transistor (which is also the second region of the active pattern of the sixth transistor and the second region of the active pattern of the seventh transistor) onto the substrate. The fourth insulating layer within the ninth via V9 is etched away, exposing the surface of the second region of the active pattern of the second transistor (which is also the second region of the active pattern of the sixth transistor and the second region of the active pattern of the seventh transistor). The ninth via V9 is configured to allow the second electrode of the subsequently formed second transistor (which is also the second electrode of the sixth transistor and the second electrode of the seventh transistor) to be connected to the second region of the active pattern of the second transistor (which is also the second region of the active pattern of the sixth transistor and the second region of the active pattern of the seventh transistor) through the via.

[0184] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate is within the orthographic projection of the first region of the active pattern of the third transistor onto the substrate. The fourth insulating layer within the tenth via V10 is etched away, exposing the surface of the first region of the active pattern of the third transistor. The tenth via V10 is configured to allow the first electrode of the subsequently formed third transistor (which is also the second electrode of the fifth transistor) to be connected to the first region of the active pattern of the third transistor through the via.

[0185] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the second region of the active pattern of the third transistor onto the substrate. The fourth insulating layer within the eleventh via V11 is etched away, exposing the surface of the second region of the active pattern of the third transistor. The eleventh via V11 is configured to allow the second terminal of the subsequently formed third transistor (which is also the first terminal of the sixth transistor) to be connected to the second region of the active pattern of the third transistor through the via.

[0186] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate is within the orthographic projection of the first region of the active pattern of the fourth transistor onto the substrate. The fourth insulating layer within the twelfth via V12 is etched away, exposing the surface of the first region of the active pattern of the fourth transistor. The twelfth via V12 is configured to allow the first electrode of the subsequently formed fourth transistor to be connected to the first region of the active pattern of the fourth transistor through the via.

[0187] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate is within the orthographic projection of the first region of the active pattern of the sixth transistor onto the substrate. The fourth insulating layer within the thirteenth via V13 is etched away, exposing the surface of the first region of the active pattern of the sixth transistor. The thirteenth via V13 is configured to allow the second electrode of the subsequently formed third transistor (which is also the first electrode of the sixth transistor) to be connected to the first region of the active pattern of the sixth transistor through the via.

[0188] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate is within the orthographic projection of the first region of the active pattern of the seventh transistor onto the substrate. The fourth insulating layer within the fourteenth via V14 is etched away, exposing the surface of the first region of the active pattern of the seventh transistor. The fourteenth via V14 is configured to allow the first electrode of the subsequently formed seventh transistor to be connected to the first region of the active pattern of the seventh transistor through the via.

[0189] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is within the range of the orthographic projection of the control electrode of the third transistor on the substrate. The fifteenth via V15 exposes the surface of the control electrode of the third transistor. The fifteenth via V15 is configured to allow the second electrode of the subsequently formed first transistor (which is also the second electrode of the fourth transistor) to be connected to the control electrode of the third transistor through the via.

[0190] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is within the range of the orthographic projection of the control electrode of the fourth transistor on the substrate. The sixteenth via V16 exposes the surface of the control electrode of the fourth transistor. The sixteenth via V16 is configured to allow subsequently formed scan signal lines to be connected to the control electrode of the fourth transistor through the via.

[0191] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is within the range of the orthographic projection of the control electrode of the sixth transistor on the substrate. The seventeenth via V17 exposes the surface of the control electrode of the sixth transistor. The seventeenth via V17 is configured to allow a subsequently formed second light-emitting signal line to be connected to the control electrode of the sixth transistor through the via.

[0192] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate is within the range of the orthographic projection of the control electrode of the seventh transistor on the substrate. The eighteenth via V18 exposes the surface of the control electrode of the seventh transistor. The eighteenth via V18 is configured to allow a subsequently formed third reset signal line to be connected to the control electrode of the seventh transistor through the via.

[0193] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 onto the substrate is within the range of the orthographic projection of the second initial signal line onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the nineteenth via V19 are etched away, exposing the surface of the second initial signal line. The nineteenth via V19 is configured to allow the first electrode of the second transistor of the subsequently formed first pixel driving circuit to be connected to the second initial signal line through the via.

[0194] In an exemplary embodiment, the orthographic projection of the twentieth via V20 onto the substrate is within the range of the orthographic projection of the fourth initial signal line onto the substrate. The fourth and third insulating layers within the twentieth via V20 are etched away, exposing the surface of the fourth initial signal line. The twentieth via V20 is configured to allow the first electrode of the second transistor of the subsequently formed third pixel driving circuit to be connected to the fourth initial signal line through the via.

[0195] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer pattern, such as... Figure 23 and Figure 24 As shown, Figure 23 for Figure 5 A schematic diagram of the pattern of the fourth conductive layer. Figure 24 for Figure 5 A schematic diagram showing the formation of the fourth conductive layer pattern. In an exemplary embodiment, the fourth conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0196] In an exemplary implementation, such as Figure 23 and Figure 24 As shown, the fourth conductive layer pattern may include: a first initial signal line NL1, a power connection line VCL, a scan signal line GL, a second light emission signal line EL2, and a third reset signal line RL3 connected to at least one pixel driving circuit; a third initial signal line NL3 connected to the second pixel driving circuit P2; and a first and second electrode of at least one transistor located in at least one pixel driving circuit. The first and second electrodes of the at least one transistor include: the first electrode 13 and second electrode 14 of the first transistor to the first electrode 73 and second electrode 74 of the seventh transistor.

[0197] In an exemplary embodiment, for the same pixel unit, the first and second poles of at least one transistor of at least one pixel driving circuit are symmetrically arranged with respect to the first and second poles of at least one transistor in an adjacent pixel driving circuit with respect to a straight line extending along the second direction D2.

[0198] In an exemplary embodiment, the first initial signal line NL1, the power connection line VCL, the scan signal line Gate, the second light emission signal line EL2, and the third reset signal line RL3 connected to the i-th row pixel driving circuit are arranged sequentially along the second direction D2.

[0199] In an exemplary embodiment, the orthographic projection of the third initial signal line connected to the i-th row pixel driving circuit on the substrate is located between the orthographic projection of the third reset signal line connected to the i-th row pixel driving circuit on the substrate and the orthographic projection of the fourth initial signal line connected to the i-th row pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of at least one of the second reset signal line and the second initial signal line connected to the i-th row pixel driving circuit on the substrate.

[0200] In an exemplary embodiment, the orthographic projection of the power connection line connected to the i-th row pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the first light-emitting signal line connected to the i-th row pixel driving circuit on the substrate, the orthographic projection of the scan signal line connected to the i-th row pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the first reset signal line connected to the i-th row pixel driving circuit on the substrate, and the orthographic projection of at least a portion of the first reset signal line connected to the i-th row pixel driving circuit on the substrate is located between the orthographic projection of the power connection line connected to the i-th row pixel driving circuit on the substrate and the orthographic projection of the scan signal line connected to the i-th row pixel driving circuit on the substrate.

[0201] In an exemplary embodiment, the orthographic projection of the second light-emitting signal line and the third reset signal line connected to the i-th row pixel driving circuit onto the substrate at least partially overlaps with the orthographic projection of the second plate of the first capacitor and the second plate of the second capacitor in at least one pixel driving circuit of the i-th row pixel driving circuit onto the substrate.

[0202] In an exemplary embodiment, the shape of the first initial signal line NL1 can be a line shape in which the main body extends along the first direction D1. The region where the first initial signal line NL1 connected to the i-th row pixel driving circuit overlaps with the first region of the active structure of the first transistor in at least one pixel driving circuit of the i-th row pixel driving circuit can serve as the first electrode 13 of the first transistor. The first electrode 13 of the first transistor in at least one pixel driving circuit is connected to the first region of the active pattern of the first transistor through a sixth via.

[0203] In an exemplary embodiment, the power connection line VCL can be a line shape in which the main body extends along the first direction D1. The area where the power connection line VCL connected to the i-th row pixel driving circuit overlaps with the first region of the active structure of the fifth transistor in at least one pixel driving circuit of the i-th row pixel driving circuit can serve as the first electrode 53 of the fifth transistor. The first electrode 53 of the fifth transistor in at least one pixel driving circuit is connected to the first region of the active pattern of the fifth transistor through a first via.

[0204] In an exemplary embodiment, the scan signal line GL can be a line shape in which the main body extends along the first direction D1. The scan signal line GL, to which the pixel driving circuit of at least one row of sub-pixels is connected, is connected to the control electrode of the fourth transistor through the sixteenth via.

[0205] In an exemplary embodiment, the shape of the second light-emitting signal line EL2 can be a line shape in which the main body extends along the first direction D1. The second light-emitting signal line EL2, to which the pixel driving circuit of at least one row of sub-pixels is connected, is connected to the control electrode of the sixth transistor through the seventeenth via.

[0206] In an exemplary embodiment, the third reset signal line RL3 can be a line shape in which the main body extends along the first direction D1. The third reset signal line RL3, to which the pixel driving circuit of at least one row of sub-pixels is connected, is connected to the control electrode of the seventh transistor through the eighteenth via.

[0207] In an exemplary embodiment, the shape of the third initial signal line NL3 can be a line shape in which the main body extends along the first direction D1. The region where the third initial signal line NL3 connected to the i-th row pixel driving circuit overlaps with the first region of the active structure of the second transistor in at least one pixel driving circuit of the i-th row pixel driving circuit can serve as the first electrode 23 of the second transistor. The first electrode 23 of the second transistor in the second pixel driving circuit is connected to the first region of the active pattern of the second transistor through an eighth via.

[0208] In an exemplary embodiment, the second electrode 14 of the first transistor and the second electrode 44 of the fourth transistor in at least one pixel driving circuit are integrally formed. The shape of the integral structure of the second electrode 14 of the first transistor and the second electrode 44 of the fourth transistor in at least one pixel driving circuit can be "L"-shaped or a horizontally flipped "L"-shaped structure. The second electrode 14 of the first transistor (which is also the second electrode 44 of the fourth transistor) in at least one pixel driving circuit is connected to the first plate of the first capacitor through a third via, connected to the second region of the active pattern of the first transistor (which is also the second region of the active pattern of the fourth transistor) through a seventh via, and connected to the control electrode of the third transistor through a fifteenth via.

[0209] In an exemplary embodiment, the first electrode 23 of the second transistor in at least one of the first and third pixel driving circuits is separately disposed. The first electrode 23 of the second transistor in at least one of the first and third pixel driving circuits is strip-shaped and extends along a first direction D1. The first electrode of the second transistor in the first pixel driving circuit is connected to the first region of the active pattern of the second transistor through an eighth via and to the second initial signal line through a nineteenth via. The first electrode of the second transistor in the third pixel driving circuit is connected to the first region of the active pattern of the second transistor through an eighth via and to the fourth initial signal line through a twentieth via.

[0210] In an exemplary embodiment, the second electrode 24 of the second transistor, the second electrode 64 of the sixth transistor, and the second electrode 74 of the seventh transistor in at least one pixel driving circuit are integrally formed. The integral structure of the second electrode 24 of the second transistor, the second electrode 64 of the sixth transistor, and the second electrode 74 of the seventh transistor in at least one pixel driving circuit may be strip-shaped and extend along the second direction D2. The second electrode 24 of the second transistor in at least one pixel driving circuit (which is also the second electrode 64 of the sixth transistor and the second electrode 74 of the seventh transistor) is connected to the second region of the active pattern of the second transistor (which is also the second region of the active pattern of the sixth transistor and the second region of the active pattern of the seventh transistor) through a ninth via.

[0211] In an exemplary embodiment, the first electrode 33 of the third transistor and the second electrode 54 of the fifth transistor in at least one pixel driving circuit are an integral structure. The integral structure of the first electrode 33 of the third transistor and the second electrode 54 of the fifth transistor in at least one pixel driving circuit is strip-shaped and extends at least partially along the second direction D2. The first electrode 33 of the third transistor (which is also the second electrode 54 of the fifth transistor) in at least one pixel driving circuit is connected to the second region of the active pattern of the fifth transistor through a second via, and is connected to the first region of the active pattern of the third transistor through a tenth via.

[0212] In an exemplary embodiment, the second electrode 34 of the third transistor and the first electrode 63 of the sixth transistor in at least one pixel driving circuit are integrally formed. The integral structure of the second electrode 34 of the third transistor and the first electrode 63 of the sixth transistor in at least one pixel driving circuit is strip-shaped and extends along a first direction D1. The second electrode 34 of the third transistor (which is also the first electrode 63 of the sixth transistor) in at least one pixel driving circuit is connected to the second plate of the first capacitor (which is also the second plate of the second capacitor) through a fifth via, connected to the second region of the active pattern of the third transistor through an eleventh via, and connected to the first region of the active pattern of the sixth transistor through a thirteenth via.

[0213] In an exemplary embodiment, the first electrode 43 of the fourth transistor in at least one pixel driving circuit is separately disposed. The first electrode 43 of the fourth transistor is strip-shaped and extends along the second direction D2. The first electrode 43 of the fourth transistor in at least one pixel driving circuit is connected to the first region of the active pattern of the fourth transistor through a twelfth via.

[0214] In an exemplary embodiment, the first electrode 73 of the seventh transistor in at least one pixel driving circuit is separately disposed. The first electrode 73 of the seventh transistor is strip-shaped and extends along a first direction D1. The first electrode 73 of the seventh transistor in at least one pixel driving circuit is connected to the first region of the active pattern of the seventh transistor through a fourteenth via.

[0215] In an exemplary embodiment, the first initial signal line NL1, the power connection line VCL, the scan signal line Gate, the second light emission signal line EL2, the third reset signal line RL3, and the third initial signal line NL3 can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between signal lines. This disclosure does not limit the scope of the invention.

[0216] (8) Forming a first planarization layer pattern. In an exemplary embodiment, forming the first planarization layer pattern may include: depositing a sixth insulating film on a substrate having the aforementioned pattern, patterning the sixth insulating film using a patterning process to form a sixth insulating layer, coating the first planarization film on the sixth insulating layer, and patterning the first planarization film using a patterning process to form a first planarization layer pattern covering the aforementioned pattern. The first planarization layer has a plurality of via patterns, such as... Figure 25 As shown, Figure 25 for Figure 5 A schematic diagram after the first flattening layer pattern has been formed.

[0217] In an exemplary implementation, such as Figure 25 As shown, the plurality of via patterns on the first planarization layer pattern include: a twenty-first via V21 to a twenty-third via V23 located in at least one pixel driving circuit, a twenty-fourth via V24 located in the first pixel driving circuit, a twenty-fifth via V25, a twenty-sixth via V26, and a twenty-seventh via V27 located in the third pixel driving circuit.

[0218] In an exemplary embodiment, the orthographic projection of the 21st via V21 onto the substrate is within the range of the orthographic projection of the first electrode of the fourth transistor onto the substrate. The sixth insulating layer within the 21st via V21 is etched away, exposing the surface of the first electrode of the fourth transistor. The 21st via V21 is configured to allow subsequently formed data signal lines to be connected to the first electrode of the fourth transistor through the via.

[0219] In an exemplary embodiment, the orthographic projection of the 22nd via V22 onto the substrate is within the range of the orthographic projection of the first electrode of the fifth transistor onto the substrate. The sixth insulating layer within the 22nd via V22 is etched away, exposing the surface of the first electrode of the fifth transistor. The 22nd via V22 is configured to allow a subsequently formed first power line to be connected to the first electrode of the fifth transistor through the via.

[0220] In an exemplary embodiment, the orthogonal projection of the 23rd via V23 onto the substrate lies within the range of the orthogonal projection of the second electrode of the second transistor (which is also the second electrode of the sixth transistor and the second electrode of the seventh transistor) onto the substrate. The sixth insulating layer within the 23rd via V23 is etched away, exposing the surface of the second electrode of the second transistor (which is also the second electrode of the sixth transistor and the second electrode of the seventh transistor). The 23rd via V23 is configured to allow the subsequently formed anode connection electrode to be connected to the second electrode of the second transistor (which is also the second electrode of the sixth transistor and the second electrode of the seventh transistor) through the via.

[0221] In an exemplary embodiment, the orthographic projection of the 24th via V24 on the substrate is within the range of the orthographic projection of the first electrode of the second transistor of the first pixel driving circuit on the substrate. The sixth insulating layer in the 24th via V24 is etched away, exposing the surface of the first electrode of the second transistor of the first pixel driving circuit. The 24th via V24 is configured to allow the subsequently formed second initial connection line to be connected to the first electrode of the second transistor of the first pixel driving circuit through the via.

[0222] In an exemplary embodiment, the orthographic projection of the 25th via V25 onto the substrate is within the range of the orthographic projection of the first electrode of the second transistor of the third pixel driving circuit onto the substrate. The sixth insulating layer within the 25th via V25 is etched away, exposing the surface of the first electrode of the second transistor of the third pixel driving circuit. The 25th via V25 is configured to allow the subsequently formed fourth initial connection line to be connected to the first electrode of the second transistor of the third pixel driving circuit through the via.

[0223] In an exemplary embodiment, the orthographic projection of the 26th via V26 on the substrate is within the range of the orthographic projection of the first initial signal line on the substrate. The sixth insulating layer within the 26th via V26 is etched away, exposing the surface of the first initial signal line. The 26th via V26 is configured to allow the subsequently formed first initial connection line to be connected to the first initial signal line through the via.

[0224] In an exemplary embodiment, the orthographic projection of the 27th via V27 onto the substrate is within the range of the orthographic projection of the third initial signal line onto the substrate. The sixth insulating layer within the 27th via V27 is etched away, exposing the surface of the third initial signal line. The 27th via V27 is configured to allow the subsequently formed third initial connection line to be connected to the third initial signal line through the via.

[0225] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer pattern, such as... Figure 26 and Figure 27 As shown, Figure 26 for Figure 5 A schematic diagram of the pattern of the fifth conductive layer. Figure 27 for Figure 5 A schematic diagram showing the formation of the fifth conductive layer pattern. In an exemplary embodiment, the fifth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0226] In an exemplary implementation, such as Figure 26 and Figure 27 As shown, the fifth conductive layer pattern may include at least: a data signal line DL and a first power supply line VL connected to at least one pixel driving circuit, as well as a first initial connection line NCL1, a second initial connection line NCL2, a third initial connection line NCL3 and a fourth initial connection line NCL4, and an anode connection electrode AL located in at least one pixel driving circuit.

[0227] In an exemplary embodiment, for the same pixel unit, the data signal line DL connected to at least one pixel driving circuit is at least partially symmetrically arranged with respect to a straight line extending along the second direction D2, as is the data signal line DL connected to the adjacent pixel driving circuit. The first power line VL connected to at least one pixel driving circuit is at least partially symmetrically arranged with respect to a straight line extending along the second direction D2, as is the first power line VL connected to the adjacent pixel driving circuit.

[0228] In an exemplary embodiment, the data signal line DL can be a line shape in which the main body extends along the second direction D2, and is electrically connected to the first electrode of the fourth transistor through the twenty-first via.

[0229] In an exemplary embodiment, the first power line VL can be a line shape in which the main body extends along the second direction D2. The first power line VL is electrically connected to the first electrode of the fifth transistor through a twenty-second via.

[0230] In an exemplary embodiment, the anode connection electrode AL is a strip shape that extends at least partially along the second direction D2, and is electrically connected to the second electrode of the second transistor (which is also the second electrode of the sixth transistor and the second electrode of the seventh transistor) through the twenty-third via.

[0231] In an exemplary embodiment, the shape of the first initial connection line NCL1 can be a line shape in which the main body extends along the second direction D2, and it is electrically connected to the first initial signal line through the second sixteenth via.

[0232] In an exemplary embodiment, the shape of the second initial connection line NCL2 can be a line shape in which the main body extends along the second direction D2, and it is electrically connected to the first electrode of the second transistor in the first pixel driving circuit through the twenty-fourth via.

[0233] In an exemplary embodiment, the shape of the third initial connection line NCL3 can be a line shape in which the main body extends along the second direction D2, and it is electrically connected to the third initial signal line through the twenty-seventh via.

[0234] In an exemplary embodiment, the shape of the fourth initial connection line NCL4 can be a line shape in which the main body extends along the second direction D2, and it is electrically connected to the first pole of the second transistor in the third pixel driving circuit P3 through the twenty-fifth via.

[0235] (10) Forming a second planarization layer pattern. In an exemplary embodiment, forming a second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern is formed, and patterning the second planarization film by a patterning process to form a second planarization layer pattern covering the aforementioned pattern, wherein the second planarization layer has a plurality of via patterns.

[0236] In an exemplary embodiment, the plurality of via patterns on the second planarization layer pattern include: anode vias.

[0237] In an exemplary embodiment, the orthogonal projection of the anode via onto the substrate is within the range of the orthogonal projection of the anode connection electrode onto the substrate. The anode via exposes the surface of the anode connection electrode and is configured to allow the anode of a subsequently formed light-emitting device to be connected to the anode connection electrode through the via.

[0238] At this point, the circuit structure layer is fabricated on the substrate. In a plane parallel to the display substrate, the circuit structure layer may include multiple pixel driving circuits and multiple signal lines connected to the pixel driving circuits. In a plane perpendicular to the display substrate, the circuit structure layer may be disposed on the substrate. At least one pixel driving circuit includes at least one transistor and at least one capacitor, the capacitor including a first electrode and a second electrode.

[0239] In an exemplary embodiment, the first semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer.

[0240] In an exemplary embodiment, the second semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0241] In an exemplary embodiment, at least one of the first to fifth conductive layers may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the material used to fabricate the first conductive layer may include molybdenum.

[0242] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0243] In an exemplary embodiment, the first planarization layer and the second planarization layer may be made of organic materials.

[0244] In an exemplary embodiment, after the circuit structure layer is fabricated, a light-emitting structure layer is fabricated on the circuit structure layer. The fabrication process of the light-emitting structure layer may include the following operations.

[0245] An anode conductive layer is formed. On the substrate with the aforementioned pattern, a pixel definition film is deposited. The pixel definition film is then patterned using a patterning process to form a pixel definition layer pattern that exposes the anode conductive layer pattern. On the substrate with the pixel definition layer pattern, an organic light-emitting material is coated. The organic light-emitting material is then patterned using a patterning process to form an organic structure layer pattern. On the substrate with the organic material layer pattern, a cathode conductive film is deposited. The cathode conductive film is then patterned using a patterning process to form a cathode conductive layer. Thus, the light-emitting structure layer is fabricated on the substrate.

[0246] In an exemplary embodiment, forming an anode conductive layer includes: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer pattern disposed on a circuit structure layer.

[0247] In an exemplary embodiment, the anode conductive layer pattern includes the anode of at least one light-emitting device.

[0248] In an exemplary embodiment, the anode of at least one light-emitting device is connected to the anode connection electrode in at least one pixel driving circuit via an anode via.

[0249] In an exemplary embodiment, the anode conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0250] In an exemplary embodiment, the organic structure layer may include at least an organic light-emitting layer of a light-emitting device.

[0251] In an exemplary embodiment, the cathode conductive layer may include at least the cathodes of a plurality of light-emitting devices.

[0252] In an exemplary embodiment, the cathode layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or the aforementioned conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer can be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0253] In an exemplary embodiment, the subsequent preparation process may include: forming an encapsulation structure layer on the cathode conductive layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0254] The display substrate described in this embodiment can be used in display products of any resolution.

[0255] This disclosure also provides a driving method for a display substrate, configured to fabricate the display substrate provided in any of the foregoing embodiments. At least one pixel driving circuit is electrically connected to at least one of the following signal lines: a first light-emitting signal line, a second light-emitting signal line, a first reset signal line, a second reset signal line, a scan signal line, a data signal line, a first initial signal line, and a second, third, and fourth initial signal line. The driving method for the display substrate may include the following steps: A signal is provided to at least one of the following signal lines connected to the pixel driving circuit: a first reset signal line, a second reset signal line, a scan signal line, a data signal line, a first light emission signal line, a second light emission signal line, a first initial signal line, a second initial signal line, a third initial signal line, and a fourth initial signal line, so that the pixel driving circuit outputs a driving current.

[0256] In an exemplary embodiment, the pixel driving circuit includes: a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit. Providing a signal to at least one of the second initial signal line, the third initial signal line, and the fourth initial signal line connected to the pixel driving circuit includes: The signal of the second initial signal line is provided to the first pixel driving circuit, the signal of the third initial signal line is provided to the second pixel driving circuit, and the signal of the fourth initial signal line is provided to the third pixel driving circuit.

[0257] This disclosure also provides a display device, including: a display substrate provided in any of the foregoing embodiments.

[0258] In an exemplary embodiment, the display device can be any product or component with display function, such as electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0259] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0260] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0261] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, include: A substrate and a plurality of pixel driving circuits disposed on the substrate, wherein at least one pixel driving circuit includes: a plurality of transistors, the plurality of transistors including: a first light-emitting transistor, a first reset transistor, a write transistor and a drive transistor, wherein the first light-emitting transistor is electrically connected to a first light-emitting signal terminal and a first power supply terminal respectively, the first reset transistor is electrically connected to a first initial signal terminal, a first reset signal terminal and the control electrode of the drive transistor respectively, and the write transistor is electrically connected to a scan signal terminal, a data signal terminal and the control electrode of the drive transistor respectively; The signal at the first power supply terminal is a positive voltage signal, the first light-emitting transistor in at least one pixel driving circuit is a P-type transistor, and the transistor type of the first light-emitting transistor in at least one pixel driving circuit is different from the transistor types of the other transistors besides the first light-emitting transistor. The active pattern of the first reset transistor and the active pattern of the write transistor in at least one pixel driving circuit are an integral structure, and are referred to as an active structure. The orthographic projection of the active pattern of the first light-emitting transistor in at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the active structure on the substrate.

2. The display substrate according to claim 1, characterized in that, Also includes: Multiple first light-emitting signal lines and multiple first reset signal lines are disposed on the substrate. At least one of the first light-emitting signal lines and the first reset signal lines extends at least partially along a first direction. The first reset signal line is electrically connected to a first reset signal terminal connected to the pixel driving circuit. The first light-emitting signal line is electrically connected to a first light-emitting signal terminal connected to the pixel driving circuit. The orthographic projection of the first light-emitting signal line connected to at least one row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projection of the first reset signal line connected to at least one row of pixel driving circuits on the substrate.

3. The display substrate according to claim 1, characterized in that, At least one pixel driving circuit further includes: a first capacitor, wherein a first plate of the first capacitor is electrically connected to the control electrode of the driving transistor, and a second plate of the first capacitor is electrically connected to the second electrode of the driving transistor; For at least one pixel driving circuit, the minimum distance between the orthographic projection of the first plate of the first capacitor in the pixel driving circuit onto the substrate and the orthographic projection of the first light-emitting signal line connected to the pixel driving circuit onto the substrate along the second direction is greater than the length of the control electrode of the write transistor in the pixel driving circuit along the second direction.

4. The display substrate according to claim 1, characterized in that, Also includes: Multiple first power lines and multiple data signal lines are disposed on the substrate, at least one of the first power lines and the data signal lines extends at least partially along a second direction, the first power lines are electrically connected to a first power terminal connected to the pixel driving circuit, and the data signal lines are electrically connected to a data signal terminal connected to the pixel driving circuit. The second electrode of the first reset transistor and the second electrode of the write transistor in at least one pixel driving circuit are integrally structured and referred to as a node structure, and the node structure is also electrically connected to the control electrode of the driving transistor. For at least one pixel driving circuit, the orthographic projection of the node structure in the pixel driving circuit onto the substrate and the orthographic projection of the data signal line connected to the pixel driving circuit onto the substrate are respectively located on different sides of the orthographic projection of the first power line connected to the pixel driving circuit onto the substrate.

5. The display substrate according to claim 4, characterized in that, Also includes: Multiple power connection lines are disposed on the base, the power connection lines extend at least partially along a first direction, at least one power connection line is electrically connected to multiple first power lines, and the first direction intersects with the second direction; The orthographic projection of the power connection line connected to at least one row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projection of the first light-emitting signal line connected to at least one row of pixel driving circuits on the substrate.

6. The display substrate according to claim 5, characterized in that, Also includes: Multiple scan signal lines are disposed on a substrate, wherein at least a portion of the scan signal lines extend along a first direction, and the scan signal lines are electrically connected to the scan signal terminals connected to the pixel driving circuit. The orthographic projection of the scan signal line connected to at least one row of pixel driving circuits on the substrate and the orthographic projection of the first reset signal line connected to at least one row of pixel driving circuits on the substrate at least partially overlap, and the orthographic projection of at least part of the first reset signal line connected to at least one row of pixel driving circuits on the substrate is located between the orthographic projection of the power connection line connected to at least one row of pixel driving circuits on the substrate and the orthographic projection of the scan signal line connected to at least one row of pixel driving circuits on the substrate.

7. The display substrate according to claim 1, characterized in that, At least one pixel driving circuit further includes: a first capacitor and a second capacitor, at least one of the first capacitor and the second capacitor includes: a first electrode plate and a second electrode plate; the control electrode of the driving transistor is electrically connected to the first electrode plate of the first capacitor, and the second electrode of the driving transistor is electrically connected to the second electrode plate of the first capacitor and the second electrode plate of the second capacitor, respectively. The first plate of the first capacitor and the first plate of the second capacitor are arranged along the second direction, and the area of ​​the first plate of the first capacitor is larger than the area of ​​the first plate of the second capacitor. The second plates of the first capacitor and the second plates of the second capacitor are integral structures. The first plate of the first capacitor includes: a first capacitor body and a first capacitor connection portion connected to each other, the first capacitor body and the first capacitor connection portion being arranged along a first direction; the first plate of the second capacitor includes: a second capacitor body and a second capacitor connection portion connected to each other, the second capacitor body and the second capacitor connection portion being arranged along a first direction. The first capacitor connection portion and the second capacitor connection portion are respectively located on different sides of at least one of the first capacitor body portion and the second capacitor body portion; The orthographic projection of the integral structure of the second plate of the first capacitor and the second plate of the second capacitor onto the substrate covers the orthographic projection of the main body of the first capacitor and the main body of the second capacitor onto the substrate, and does not overlap with the orthographic projection of the connection part of the first capacitor and the connection part of the second capacitor onto the substrate.

8. The display substrate according to claim 7, characterized in that, Also includes: Multiple second light-emitting signal lines, a third reset signal line, and multiple light-emitting devices are disposed on a substrate, wherein at least one of the second light-emitting signal lines and the third reset signal line extends at least partially along a first direction; The plurality of transistors further includes: a second light-emitting transistor and a third reset transistor, wherein the second light-emitting transistor is electrically connected to a second light-emitting signal terminal, the second electrode of the driving transistor and the light-emitting device, respectively; the third reset transistor is electrically connected to a third reset signal terminal and the light-emitting device, respectively; the second light-emitting signal line is electrically connected to the second light-emitting signal terminal connected to the pixel driving circuit; and the third reset signal line is electrically connected to the third reset signal terminal connected to the pixel driving circuit. The orthographic projection of at least one of the second light-emitting signal lines and the third reset signal lines connected to at least one pixel driving circuit onto the substrate at least partially overlaps with the orthographic projection of the second capacitor in at least one pixel driving circuit onto the substrate.

9. The display substrate according to claim 1, characterized in that, The display substrate includes: a plurality of pixel units, and the pixel driving circuit includes: a first pixel driving circuit, a second pixel driving circuit and a third pixel driving circuit. At least one pixel unit includes: a first pixel driving circuit, a second pixel driving circuit and a third pixel driving circuit arranged sequentially along a first direction. The area of ​​the active pattern of the driving transistor in the third pixel driving circuit located in the same pixel unit is greater than the area of ​​the active pattern of the driving transistor in at least one of the first pixel driving circuit and the second pixel driving circuit.

10. The display substrate according to claim 9, characterized in that, The first pixel driving circuit and the second pixel driving circuit in at least one pixel unit are arranged in a mirror image symmetrical with respect to a straight line extending along a second direction. The structure of the second pixel driving circuit in at least one pixel unit, excluding the active pattern of the driving transistor, and the structure of the third pixel driving circuit, excluding the active pattern of the driving transistor, are arranged in a mirror image symmetrical with respect to a straight line extending along the second direction. The first direction intersects the second direction.

11. The display substrate according to claim 9, characterized in that, Also includes: Multiple first initial signal lines, multiple second initial signal lines, multiple third initial signal lines, multiple fourth initial signal lines, and multiple light-emitting devices are disposed on the substrate, wherein at least one of the first initial signal lines, the second initial signal lines, the third initial signal lines, and the fourth initial signal lines extends at least partially along a first direction; The plurality of transistors further includes: a second reset transistor, which is electrically connected to a second reset signal terminal, a second initial signal terminal, and a light-emitting device, respectively; at least one first initial signal line is electrically connected to a first initial signal terminal connected to at least one pixel driving circuit; at least one second initial signal line is electrically connected to a second initial signal terminal connected to the first pixel driving circuit; at least one third initial signal line is electrically connected to a second initial signal terminal connected to the second pixel driving circuit; and at least one fourth initial signal line is electrically connected to a second initial signal terminal connected to the third pixel driving circuit.

12. The display substrate according to claim 11, characterized in that, The second initial signal line is located on the side of the fourth initial signal line closer to the substrate, and the third initial signal line and the first initial signal line are located on the side of the fourth initial signal line away from the substrate.

13. The display substrate according to claim 11, characterized in that, Also includes: Multiple second reset signal lines are disposed on the substrate, the second reset signal lines extend along a first direction, and the second reset signal lines are electrically connected to the second reset signal terminal of the pixel driving circuit; The orthographic projection of the second initial signal line connected to at least one row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projection of the third initial signal line connected to at least one row of pixel driving circuits on the substrate, and the orthographic projections of the second and third initial signal lines connected to at least one row of pixel driving circuits on the substrate do not overlap with the orthographic projection of the fourth initial signal line connected to at least one row of pixel driving circuits on the substrate. The orthographic projection of the second reset signal line connected to at least one row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projections of the second initial signal line and the third initial signal line connected to at least one row of pixel driving circuits on the substrate, and does not overlap with the orthographic projection of the fourth initial signal line connected to at least one row of pixel driving circuits on the substrate.

14. The display substrate according to claim 11, characterized in that, Also includes: Multiple first initial connection lines, multiple second initial connection lines, multiple third initial connection lines, and multiple fourth initial connection lines are disposed on a substrate, wherein at least one signal line among the first initial connection lines, the second initial connection lines, the third initial connection lines, and the fourth initial connection lines extends at least partially along a second direction; At least one first initial connection line is electrically connected to multiple first initial signal lines, at least one second initial connection line is electrically connected to multiple second initial signal lines, at least one third initial connection line is electrically connected to multiple third initial signal lines, and at least one fourth initial connection line is electrically connected to multiple fourth initial signal lines.

15. The display substrate according to claim 14, characterized in that, At least one of the first initial connection line, the second initial connection line, the third initial connection line, and the fourth initial connection line is located on the side of the first initial signal line, the second initial signal line, the third initial signal line, and the fourth initial signal line that is away from the substrate.

16. The display substrate according to claim 1, characterized in that, In at least one pixel driving circuit, the control electrode of the transistors other than the first light-emitting transistor is located on the side of the active pattern away from the substrate.

17. The display substrate according to claim 1, characterized in that, Also includes: The substrate includes multiple first light-emitting signal lines, multiple second light-emitting signal lines, multiple scan signal lines, multiple first reset signal lines, multiple second reset signal lines, multiple third reset signal lines, multiple first initial signal lines, multiple second initial signal lines, multiple third initial signal lines, multiple fourth initial signal lines, multiple first initial connection lines, multiple second initial connection lines, multiple third initial connection lines, multiple fourth initial connection lines, multiple data signal lines, multiple first power lines, and multiple power connection lines. At least one pixel driving circuit also includes at least one capacitor, which comprises a first electrode plate and a second electrode plate. The display substrate further includes: a circuit structure layer disposed on the substrate, the circuit structure layer including: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially stacked on the substrate; The first semiconductor layer includes at least: an active pattern of a first light-emitting transistor located in at least one pixel driving circuit; The first conductive layer includes at least: a control electrode of a first light-emitting transistor located in at least one pixel driving circuit and a first electrode plate of at least one capacitor, multiple first light-emitting signal lines and multiple second initial signal lines; The second conductive layer includes at least: a second plate of at least one capacitor located in at least one pixel driving circuit and multiple fourth initial signal lines; The second semiconductor layer includes at least: an active pattern of the remaining transistors, excluding the first light-emitting transistor, located in at least one pixel driving circuit; The third conductive layer includes at least: control electrodes of the transistors other than the first light-emitting transistor located in at least one pixel driving circuit, multiple first reset signal lines, and multiple second reset signal lines; The fourth conductive layer includes at least: the first and second poles of a plurality of transistors located in at least one pixel driving circuit, a plurality of first initial signal lines, a plurality of power connection lines, a plurality of scan signal lines, a plurality of second light emission signal lines, a plurality of third reset signal lines, and a plurality of third initial signal lines; The fifth conductive layer includes at least: multiple data signal lines, multiple first power lines, multiple first initial connection lines, multiple second initial connection lines, multiple third initial connection lines, and multiple fourth initial connection lines.

18. A display device, characterized in that, include: The display substrate as described in any one of claims 1 to 17.

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