Display device

Abstract

A display device can include a substrate including a display area and a peripheral area disposed outside the display area; a light emitting element disposed on the display area of the substrate; an anti-static layer configured to cover a side surface of the substrate; and an electrostatic test wiring disposed on the peripheral area, wherein the electrostatic test wiring can include a plurality of first test wirings spaced apart from each other and respectively connected to the anti-static layer, and a second test wiring electrically connected to the plurality of first test wirings.

Description

Technical Field

[0001] This disclosure relates to a display device. Background Technology

[0002] Display devices are devices that display screens, and include liquid crystal displays (LCDs) or organic light-emitting diode (OLED) displays. These display devices are widely used in various electronic devices such as mobile phones, navigation devices, digital cameras, e-books, portable game consoles, or various terminals.

[0003] For example, an organic light-emitting display device includes two electrodes and an organic light-emitting layer located between them. Electrons injected from one electrode and holes injected from the other electrode combine in the organic light-emitting layer to form excitons. When an exciton changes from an excited state to a ground state, it releases energy and emits light.

[0004] Organic light-emitting diode (OLED) displays are self-emissive display devices, and unlike liquid crystal displays (LCDs), they do not require a separate light source, allowing them to be manufactured in a lightweight and thin form. Furthermore, OLEDs are advantageous in terms of power consumption due to their low-voltage operation, and also offer excellent color reproduction, response speed, viewing angle, and contrast, making them promising for applications in various fields. Utility Model Content

[0005] This disclosure attempts to provide a display device that can improve reliability.

[0006] The display device may include: a substrate, including a display area and a peripheral area disposed outside the display area; a light-emitting element disposed on the display area of ​​the substrate; an anti-static layer configured to cover the side surface of the substrate; and electrostatic test wiring disposed on the peripheral area, wherein the electrostatic test wiring may include: a plurality of first test wirings spaced apart from each other and respectively connected to the anti-static layer; and a second test wiring electrically connected to the plurality of first test wirings.

[0007] In one embodiment, the ends of the plurality of first test wirings may be aligned with the ends of the substrate.

[0008] In one embodiment, multiple first test wirings may be repeatedly arranged at the ends of the substrate.

[0009] In one embodiment, the display device may further include: a dam disposed on the peripheral area of ​​the substrate; and crack test wiring disposed between the dam and the electrostatic test wiring.

[0010] In one embodiment, the second test wiring may be disposed between multiple first test wirings and crack test wirings.

[0011] In one embodiment, the electrostatic test wiring may be disposed in the same layer as the crack test wiring and may include the same material as the crack test wiring.

[0012] In an embodiment, each of the plurality of first test wirings may include a horizontal portion in contact with the antistatic layer and an extension portion connecting the horizontal portions.

[0013] In an embodiment, the display device may further include: a first gate insulating layer disposed on a substrate; and a second gate insulating layer disposed on the first gate insulating layer, wherein a plurality of first test wirings and second test wirings are disposed on the second gate insulating layer.

[0014] In an embodiment, the display device may further include: an insulating interlayer disposed on the second gate insulating layer, wherein the insulating interlayer covers a plurality of first test wirings and second test wirings.

[0015] In an embodiment, the display device may further include: a first gate insulating layer disposed on a substrate; a gate electrode disposed on the first gate insulating layer; and a second gate insulating layer disposed on the gate electrode and the first gate insulating layer, wherein a plurality of first test wirings and second test wirings are disposed between the first gate insulating layer and the second gate insulating layer.

[0016] In an embodiment, the multiple first test wirings and second test wirings may include the same material as the gate electrode.

[0017] In an embodiment, the display device may further include: a driving circuit chip disposed on a peripheral region and configured to supply signals for driving light-emitting elements; and a pad portion including terminals electrically connected to the driving circuit chip, first detection terminals connected to a plurality of first test wirings, and second detection terminals connected to second test wirings.

[0018] In an embodiment, the display device may further include: a printed circuit board (PCB) attached to the end of a substrate, wherein the PCB is electrically connected to a terminal electrically connected to a driving circuit chip, a first detection terminal, and a second detection terminal.

[0019] In an embodiment, the display device may include: a display panel; an optical layer disposed on the front surface of the display panel; a cover window disposed on the optical layer; a protective plate disposed on the rear surface of the display panel; and an antistatic layer covering the side surfaces of the display panel, the side surfaces of the optical layer, and the side surfaces of the protective plate. The display panel may include: a substrate including a display area and a peripheral area disposed outside the display area; a light-emitting element disposed on the display area of ​​the substrate; and electrostatic discharge (ESD) test wiring, which includes multiple first test wirings disposed on the peripheral area and respectively connected to the ESD layer, and second test wirings electrically connected to the multiple first test wirings.

[0020] In one embodiment, the ends of the plurality of first test wirings may be aligned with the ends of the substrate.

[0021] In an embodiment, the display panel may further include: a first gate insulating layer disposed on a substrate; a gate electrode disposed on the first gate insulating layer; and a second gate insulating layer disposed on the gate electrode and the first gate insulating layer, wherein a plurality of first test wirings and second test wirings are disposed on the second gate insulating layer.

[0022] In an embodiment, the display device may further include: an insulating interlayer disposed on the second gate insulating layer, wherein the insulating interlayer covers a plurality of first test wirings and second test wirings.

[0023] In one embodiment, multiple first test wirings may be arranged along a second direction, and second test wirings may extend along the second direction.

[0024] In an embodiment, the display device may further include: crack test wiring surrounding the display area of ​​the substrate, wherein the second test wiring may be disposed outside the crack test wiring, and a plurality of first test wirings may be disposed outside the second test wiring.

[0025] In one embodiment, the electrostatic test wiring may be disposed in the same layer as the crack test wiring and may include the same material as the crack test wiring.

[0026] In one embodiment, the display device may include electrostatic discharge (ESD) test wiring disposed at the end of the display panel, such that multiple first test wirings and second test wirings can form a current path through the antistatic layer, and thus, open circuit defects in the antistatic layer can be easily detected. Attached Figure Description

[0027] The above and other embodiments, advantages, and features of this disclosure will become more apparent from the accompanying drawings, which describe embodiments of the present disclosure in more detail, in which:

[0028] Figure 1This is a top view schematically illustrating an embodiment of the display device;

[0029] Figure 2 It is along Figure 1 A cross-sectional view taken from line A-A';

[0030] Figure 3 This is a top view schematically illustrating an embodiment of the display device;

[0031] Figure 4 yes Figure 3 An enlarged top view of area Q1;

[0032] Figure 5 It is along Figure 3 A cross-sectional view taken from line B-B';

[0033] Figure 6 yes Figure 5 Enlarged cross-sectional view of region Q2;

[0034] Figure 7 It is along Figure 3 A cross-sectional view taken from line C-C';

[0035] Figure 8 yes Figure 7 Enlarged cross-sectional view of region Q3;

[0036] Figures 9 to 11 Is with Figure 5 A cross-sectional view of an embodiment of the electrostatic test wiring of the display device, corresponding to area Q2;

[0037] Figure 12 Is with Figure 3 A top view of an embodiment of the electrostatic test wiring of the display device, corresponding to area Q1;

[0038] Figure 13 Is with Figure 3 A top view of an embodiment of the display device corresponding to area Q1;

[0039] Figure 14 This is a block diagram of an electronic device according to an embodiment; and

[0040] Figure 15 Schematic diagrams of electronic devices according to various embodiments are shown. Detailed Implementation

[0041] In the following description, embodiments of the present disclosure will be described more fully with reference to the accompanying drawings, in which embodiments of the present invention are illustrated. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the present invention.

[0042] For the purpose of clearly describing this utility model, parts or components that are not related to the description have been omitted, and throughout the specification, the same or similar constituent elements are indicated by the same reference numerals.

[0043] Furthermore, in the accompanying drawings, for ease of description, the dimensions and thicknesses of each element are arbitrarily illustrated, and this disclosure is not necessarily limited to the dimensions and thicknesses shown in the drawings. In the accompanying drawings, for clarity, the thicknesses of layers, films, panels, areas, regions, etc., are exaggerated. In the accompanying drawings, for ease of description, the thicknesses of some layers and regions are exaggerated.

[0044] It will be understood that when an element such as a layer, film, region, area, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or an intervening element may be present. In contrast, when an element is referred to as being "directly" "on" another element, no intervening element is present. Furthermore, in the specification, the terms "on" or "above" mean disposed on or below a part of an object, and do not necessarily mean disposed on the upper side of a part of an object based on the direction of gravity.

[0045] Furthermore, unless explicitly stated otherwise, the word “including” and variations such as “contains” or “comprising” will be understood to imply the inclusion of the stated element, but not the exclusion of any other element.

[0046] Furthermore, throughout the specification, the phrase "in a plan view" or "in a plane" means viewing the target portion from the top, and the phrase "in a cross-sectional view" or "in a cross-section" means viewing the cross-section formed by vertically cutting the target portion from the side.

[0047] In the following text, see references Figure 1 The display device in the embodiments will be described in detail below.

[0048] refer to Figure 1 The display device in the embodiment may include a substrate 110 comprising a display area DA and a peripheral area PA configured to be adjacent to (near) the display area DA, a light-emitting element ED disposed on the display area DA of the substrate 110, and a driver disposed on the peripheral area PA of the substrate 100.

[0049] The substrate 110 may be flexible, stretchable, foldable or bendable, or may include or be composed of a rollable material.

[0050] The display area DA is an area used for displaying the screen and is typically quadrilateral (e.g., rectangular). In embodiments, the display area DA may be formed into a quadrilateral shape (e.g., a rectangular shape including two sides extending in a first direction DR1 and two sides extending in a second direction DR2), and the corner portions may be rounded by chamfering. However, this may only be one embodiment, and the shape of the display area DA may be changed in various ways depending on the purpose of the display device, etc.

[0051] Multiple light-emitting elements (EDs) can be arranged in a predetermined manner on a display area DA. In an embodiment, for example, the multiple EDs can be arranged along both row and column directions. However, this may only be one embodiment, and the arrangement of the multiple EDs can be varied in various ways. Each ED can be given a predetermined signal via multiple signal lines. The signal lines and the EDs can be connected via transistors. That is, the transistors and signal lines connected to the EDs can be arranged on the display area DA. The signal lines can include scan lines, data lines, drive voltage lines, initialization voltage lines, or common voltage lines, etc. These signal lines can extend in one direction and connect to the multiple EDs.

[0052] The display area DA may further include a touch sensor for detecting user touch and / or non-touch.

[0053] A peripheral region PA can be disposed outside the display region DA and can be formed to surround the display region DA. The peripheral region PA may include a first region A1 surrounding the display region DA, a second region A2 spaced apart from the edge of the first region A1, and a curved region BA disposed between the first region A1 and the second region A2. In an embodiment, for example, the curved region BA may extend from the lower edge of the first region A1, and the second region A2 may extend from the curved region BA. The substrate 110 may be bent within the curved region BA. The curved region BA may be formed in a shape that extends elongated along a first direction DR1. When the substrate 110 is bent along the curved region BA, the second region A2 may be disposed on the rear surface of the first region A1. That is, when the substrate 110 is in a bent state, the second region A2 and the first region A1 may overlap each other.

[0054] In the peripheral area PA, drive circuit units such as drive circuit chip 20, printed circuit board (PCB) 30, integrated circuit (IC) driver chip 50, or scan driver can be provided to generate and transmit signals for driving the display device in the driving embodiment.

[0055] The driver circuit chip 20 and PCB 30 can be disposed in the second area A2. The driver circuit chip 20 can be connected to the light-emitting element ED disposed on the display area DA via wiring, and can transmit various signals. In an embodiment, for example, the driver circuit chip 20 can be connected to a data signal transmission line to transmit data signals. Furthermore, the driver circuit chip 20 can be connected via a pad portion 40 (see reference). Figure 3 Electrically connected to IC driver chip 50 and / or PCB 30.

[0056] PCB 30 can be attached to the edge of substrate 110. In an embodiment, for example, PCB 30 can be attached to the end of the second region A2. PCB 30 may include or be composed of a flexible material, and may contain an IC driver chip 50 for controlling the driving of the display device in the embodiment. IC driver chip 50 may be electrically connected to driver circuit chip 20 and provide signals for driving the light-emitting element ED to driver circuit chip 20. Furthermore, IC driver chip 50 may be electrically connected to scan driver 22 (see reference). Figure 3 ), and supplies signals for driving the light-emitting element ED.

[0057] In an embodiment, the peripheral region PA may include electrostatic test wiring 720 (reference). Figure 2 Electrostatic discharge test wiring 720 (reference) Figure 2 It can be set at the edge of the PA in the peripheral area. Electrostatic discharge test wiring 720 (reference) Figure 2 This can be an antistatic layer 710 used for inspecting the side surface of the display panel 100 (see reference). Figure 2 Wiring with open circuit defects.

[0058] In an embodiment, the peripheral region PA may further include a scan driver 22 (reference 22). Figure 3 Scan driver 22 (reference) Figure 3 The scan driver 22 can be located in the first area A1, and can be located in the first area A1 adjacent to the left edge and / or right edge of the display area DA. The scan driver 22 can be connected to the light-emitting element ED via scan lines and can transmit scan signals. Each of the light-emitting elements ED can be given a data signal according to a predetermined timing sequence based on the scan signal. Signal lines for transmitting various control signals, drive voltages, or common voltages, etc., can be further provided on the peripheral area PA. The signal lines can be connected to the IC driver chip 50 and can receive predetermined signals from the IC driver chip 50.

[0059] In the following text, see references Figure 2 The cross-sectional shape of the display device in the embodiments will be described in detail.

[0060] Figure 2It is along Figure 1 A cross-sectional view taken from line A-A'.

[0061] refer to Figure 2 The display device in the embodiment may include an optical layer 460 and a cover window 490 disposed on the front surface of the display panel 100, an adhesive layer 480 disposed between the optical layer 460 and the cover window 490, a protective plate 430 disposed on the rear surface of the display panel 100, an antistatic layer 710 covering the side surface of the display panel 100, and an electrostatic test wiring 720 disposed on the edge of the display panel 100.

[0062] Optical layer 460 can be disposed on the front surface of display panel 100. It can also be disposed on the upper surface of display panel 100. Optical layer 460 can be embedded within display panel 100. Optical layer 460 may include a phase retardation layer or a polarization layer, etc. Optical layer 460 may be a single layer or composed of such layers, and can be formed as a multilayer in which various layers are stacked.

[0063] Cover window 490 can be disposed on optical layer 460. It can be disposed on the front surface of display panel 100. Cover window 490 can cover the entire display panel 100. Cover window 490 can overlap with the entire display panel 100 on third direction DR3. The width of cover window 490 along first direction DR1 can be greater than the width of display panel 100 along first direction DR1. Cover window 490 can be used to protect display panel 100 from external interference.

[0064] An adhesive layer 480 may be disposed between the optical layer 460 and the cover window 490. The adhesive layer 480 may include or be composed of optically clear adhesive (OCA), optically clear resin (OCR), or pressure-sensitive adhesive (PSA). The adhesive layer 480 can be used to bond the display panel 100 to the cover window 490.

[0065] A protective plate 430 may be disposed on the rear surface of the display panel 100. A protective plate 430 may also be disposed on the lower surface of the display panel 100. A protective film and / or adhesive layer may be further disposed between the display panel 100 and the protective plate 430. The protective plate 430 may help the display panel 100 maintain a constant shape. Furthermore, the protective plate 430 may include or be composed of a metallic material such as copper and perform a heat dissipation function. The protective plate 430 may also include or be composed of a material such as graphite or PET.

[0066] In this embodiment, the antistatic layer 710 may cover the edge of the display panel 100. The antistatic layer 710 may cover the side surfaces of the protective plate 430, the display panel 100, the optical layer 460, and the adhesive layer 480. Furthermore, the antistatic layer 710 may be disposed on the lower surface of the cover window 490 and the lower surface of the protective plate 430. The antistatic layer 710 may be formed by coating the lower surface of the cover window 490, the lower and side surfaces of the protective plate 430, the side surfaces of the display panel 100, the side surfaces of the optical layer 460, and the side surfaces of the adhesive layer 480 with a conductive polymer compound. In this embodiment, the antistatic layer 710 may be, for example, a coating layer of a conductive polymer compound. When static electricity occurs in the cover window 490, the antistatic layer 710 may be used to release static electricity through the protective plate 430. In an embodiment, for example, the antistatic layer 710 can form a current path from the cover window 490 to the grounding terminal of the protective plate 430, thereby reducing the electric field between the cover window 490 and the protective plate 430. In this way, image quality defects caused by static electricity in the display device of the embodiment can be improved.

[0067] Electrostatic discharge (ESD) testing wiring 720 may be disposed at a first end of the display panel 100. In an embodiment, for example, ESD testing wiring 720 may be disposed at a first side end and a second side end of the display panel 100 along a first direction DR1, respectively. However, this is not a limitation, and ESD testing wiring 720 may be disposed at either the first side end or the second side end along the first direction DR1.

[0068] The end of the electrostatic discharge (ESD) test wiring 720 can be aligned with the side surface of the display panel 100. In an embodiment, for example, the end of the ESD test wiring 720 can be aligned with the side surface 100_S of the display panel 100. Therefore, the ESD test wiring 720 can contact the antistatic layer 710. In an embodiment, the ESD test wiring 720 can be wiring for inspecting open-circuit defects in the antistatic layer 710. Here, the term "open-circuit defect in the antistatic layer 710" refers to a situation where, during the process of forming the antistatic layer 710, a portion of the display panel 100 is not covered by the antistatic layer 710. In this case, the current path formed from the cover window 490 to the grounding terminal of the protective plate 430 may be weakened, and this may cause static charge from the cover window 490 to flow into the display panel 100, potentially generating image quality defects. Reference will be made below. Figure 3 A detailed description of the electrostatic discharge test wiring 720.

[0069] In the following text, see references Figure 3 and Figure 4 The electrostatic discharge test wiring 720 of the display device in the embodiments will be described in detail.

[0070] Figure 3This is a top view schematically illustrating an embodiment of the display device. Figure 4 yes Figure 3 An enlarged top view of area Q1.

[0071] refer to Figure 3 and Figure 4 The display device in the embodiments may include a driving circuit unit, and the driving circuit unit may include multiple drivers and signal wiring. In the embodiments, for example, the driving circuit unit may include a scan driver 22, a driving circuit chip 20, or signal transmission wiring and pad portions 40 connected to them, etc. At least a portion of the driving circuit unit may be disposed on the display area DA, and the remainder may be disposed on the peripheral area PA.

[0072] The scan driver 22 can generate a scan signal and transmit it via a scan line to a pixel circuit unit electrically connected to the light-emitting element ED. Depending on the embodiment, the scan driver 22 may be located to the left of the display area DA, but is not limited thereto. In another embodiment, the scan driver 22 may be located on the opposite side of the substrate 110.

[0073] The driving circuit chip 20 can be disposed on the peripheral area PA, and can generate data signals and transmit them to the pixel circuit unit connected to the light-emitting element ED via data lines. The driving circuit chip 20 can be disposed on the first side of the display panel 100, and for example, can be disposed between the pad portion 40 and the display area DA.

[0074] The pad portion 40 may be disposed on a first side end of the substrate 110 and may include a plurality of terminals 41, 42, 44, 45, and 46. In an embodiment, for example, the pad portion 40 of the display panel 100 may include a terminal 41 connected to the driving circuit chip 20, a terminal 42 connected to the scan driver 22, a terminal 44 connected to the crack test wiring 730, and detection terminals 45 and 46 connected to the electrostatic test wiring 720. The pad portion 40 is exposed by not being covered by an insulating layer and may be electrically connected to the PCB 30. The pad portion 40 may be connected to the pad portion 310 of the PCB 30.

[0075] PCB 30 can transmit signals or power from IC driver chip 50 to pad portion 40. Pad portion 310 of PCB 30 may include multiple terminals 311, 315, and 316 corresponding to multiple terminals 41, 42, 44, 45, and 46 of pad portion 40 of display panel 100. In an embodiment, for example, pad portion 310 of PCB 30 may include terminal 311 connected to terminal 41 connected to driver circuit chip 20, and detection terminals 315 and 316 respectively connected to detection terminals 45 and 46 of display panel 100. Therefore, PCB 30 can be electrically connected to terminal 41 and detection terminals 45 and 46 connected to driver circuit chip 20.

[0076] The IC driver chip 50 can convert multiple video signals transmitted from an external source into multiple image data signals, and can transmit the converted signals to the driver circuit chip 20 via terminal 41. Furthermore, the IC driver chip 50 can receive vertical synchronization signals, horizontal synchronization signals, and clock signals, generate control signals for controlling the scan driver 22, and transmit the control signals to the scan driver 22 via terminal 42. The IC driver chip 50 can transmit a crack detection signal for detecting cracks in the display device to the crack test wiring 730 via terminal 44. The IC driver chip 50 can transmit an electrostatic discharge (ESD) test signal to the ESD test wiring 720 via detection terminals 45 and 46. Additionally, the IC driver chip 50 can transmit the drive voltage ELVDD to the drive voltage supply line via terminals, and can also transmit the common voltage ELVSS to the common voltage supply line.

[0077] The display device in the embodiment may further include a crack test wiring 730. The crack test wiring 730 may be disposed on the peripheral region PA of the substrate 110. The crack test wiring 730 may have a shape surrounding the display region DA. The crack test wiring 730 can be used to detect cracks that have occurred in the display panel 100.

[0078] Electrostatic discharge (ESD) test wiring 720 can be disposed on the peripheral region PA of substrate 110. ESD test wiring 720 can be disposed on at least one side of substrate 110. In embodiments, for example, ESD test wiring 720 can be disposed along a first direction DR1 on a first side and a second side of substrate 110, but is not limited thereto. In embodiments, ESD test wiring 720 can be disposed at the edge of substrate 110. ESD test wiring 720 can be configured to be adjacent to (near) a first side surface S1 of substrate 110 and a second side surface S2 facing the first side surface S1 in the first direction DR1. ESD test wiring 720 can be disposed outside crack test wiring 730. That is, crack test wiring 730 can be disposed between ESD test wiring 720 and display area DA.

[0079] Electrostatic discharge (ESD) test wiring 720 can be connected to the detection terminals 45 and 46 of the pad portion 40. Each of the detection terminals 45 and 46 can be connected to the pad portion 310 of the PCB 30 and electrically connected to the IC driver chip 50 or the controller. In an embodiment, for example, the first detection terminal 45 connected to the ESD test wiring 720 can be connected to the first detection terminal 315 of the PCB 30, and the second detection terminal 46 connected to the ESD test wiring 720 can be connected to the second detection terminal 316 of the PCB 30.

[0080] Further reference Figure 4 The electrostatic discharge test wiring 720 may include a plurality of first test wirings 721 arranged at intervals from each other and a second test wiring 722 electrically connected to the plurality of first test wirings 721.

[0081] Multiple first test wirings 721 can be arranged to be spaced apart along a second direction DR2. In an embodiment, for example, multiple first test wirings 721 can be repeatedly arranged at the ends of substrate 110. Multiple first test wirings 721 can be arranged along the elongation direction (e.g., second direction DR2) of the first side surface S1 and the second side surface S2 of substrate 110. Multiple first test wirings 721 can be disposed at the edge of substrate 110. Multiple first test wirings 721 can be disposed outside of second test wirings 722. Multiple first test wirings 721 can be arranged to be adjacent to the first side surface S1 of substrate 110 and the second side surface S2 facing the first side surface S1 in the first direction DR1. The first ends 720_E of multiple first test wirings 721 can be aligned with the side surfaces of substrate 110. In an embodiment, for example, as... Figure 4 As shown, the first ends 720_E of the plurality of first test wires 721 can be aligned with the first side surface S1 of the substrate 110. The first ends 720_E of the plurality of first test wires 721 and the side surface of the substrate 110 can contact the antistatic layer 710. Each of the plurality of first test wires 721 can be connected to the antistatic layer 710.

[0082] Therefore, each of the plurality of first test wires 721 can be electrically connected to the antistatic layer 710. In an embodiment, for example, each of the plurality of first test wires 721 may include a horizontal portion extending generally in a first direction DR1 and contacting the antistatic layer 710 and an extension portion extending generally in a second direction DR2 and connecting the horizontal portions. In this case, the first end of the horizontal portion may be aligned with the side surface of the substrate 110. The horizontal portion of each of the plurality of first test wires 721 can be electrically connected to the antistatic layer 710, and therefore, the plurality of first test wires 721 that are adjacent to each other in the second direction DR2 can be electrically connected to each other through the antistatic layer 710. In the following, for ease of description, the area between the plurality of first test wires 721 that are adjacent to each other in the second direction DR2 may also be referred to as the inspection area DTL, and the area between the horizontal portions of each of the plurality of first test wires 721 may also be referred to as the dummy area CTL. That is, in an embodiment, in the inspection area DTL, the plurality of first test wires 721 can be electrically connected to each other through the antistatic layer 710.

[0083] Therefore, depending on whether an open-circuit defect of the anti-static layer 710 exists in the inspection area DTL, the multiple first test wires 721 may be in an open-circuit or short-circuit state. In an embodiment, for example, when an open-circuit defect of the anti-static layer 710 has occurred in the inspection area DTL, the space between multiple first test wires 721 that are adjacent to each other in the second direction DR2 may be electrically open. When the anti-static layer 710 is formed in the inspection area DTL, the multiple first test wires 721 that are adjacent to each other in the second direction DR2 may be electrically connected to each other. Therefore, depending on whether an open-circuit defect of the anti-static layer 710 exists in the inspection area DTL, the multiple first test wires 721 may be in an open-circuit or short-circuit state. The length of the inspection area DTL along the second direction DR2 may be less than or equal to the length of the dummy area CTL along the second direction DR2. Within this range, the inspection area DTL can be easily protected while preventing an increase in resistance due to the anti-static layer 710.

[0084] In the plan view, the second test wiring 722 may extend substantially along the second direction DR2. The second test wiring 722 may be spaced apart from the plurality of first test wirings 721. In an embodiment, for example, the second test wiring 722 may be spaced apart from the plurality of first test wirings 721 along the first direction DR1, but is not limited thereto. In an embodiment, the second test wiring 722 may be disposed between the crack test wiring 730 and the plurality of first test wirings 721. That is, the second test wiring 722 may be disposed outside the crack test wiring 730. The width of the second test wiring 722 along the first direction DR1 may be substantially the same as, but not limited to, the widths of the plurality of first test wirings 721, and they may be different. The second test wiring 722 may be electrically connected to the plurality of first test wirings 721 through an antistatic layer 710. However, this is not a limitation, and the second test wiring 722 may be directly connected to at least one of the plurality of first test wirings 721.

[0085] In summary, the multiple first test wirings 721 and second test wirings 722 of the display device in the embodiment can form a current path through the anti-static layer 710, and this current path can be in an open-circuit or short-circuit state depending on whether there is an open-circuit defect in the anti-static layer 710 in the inspection area DTL. Therefore, the IC driver chip 50 and / or the controller can transmit an electrostatic test signal to the electrostatic test wiring 720 through the detection terminals 45 and 46, thereby detecting whether there is an open-circuit defect in the anti-static layer 710.

[0086] In the following text, see references Figures 5 to 8 The cross-sectional shape of the peripheral region of the display device in the embodiments will be described in detail.

[0087] Figure 5 It is along Figure 3 The cross-sectional view taken by line B-B'. Figure 6 yes Figure 5 Enlarged cross-sectional view of region Q2. Figure 7 It is along Figure 3 The cross-sectional view taken from line C-C'. Figure 8 yes Figure 7 An enlarged cross-sectional view of region Q3. Figures 5 to 8 The peripheral region PA of the substrate 110 is shown, but the display area is not shown. Furthermore, for better understanding and ease of description, in Figures 5 to 8 The image shows at least a portion of the display panel and optical layer 460, and does not show... Figure 2 The adhesive layer 480, the cover window 490, and the protective panel 430.

[0088] First, refer to Figure 5The display device in the embodiment may include a substrate 110, a buffer layer 111, a barrier layer 112, a semiconductor layer 130, a first gate insulating layer 120, a gate electrode 124, a second gate insulating layer 122, an insulating interlayer 160, a crack test wiring 730, an electrostatic test wiring 720, a source / drain electrode 174, a common voltage supply line 70, a first passivation layer 180, connecting electrodes 176 and 178, a second passivation layer 182, a third passivation layer 184, an extension electrode 78, a common electrode 270, and an encapsulation layer 400.

[0089] Substrate 110 may include at least one of polystyrene, polyvinyl alcohol, poly(methyl methacrylate), polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. Substrate 110 may be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable. Substrate 110 may be single-layered or multi-layered. Substrate 110 may be a substrate in which at least one base layer and at least one inorganic layer are alternately stacked, the at least one inorganic layer comprising sequentially stacked polymer resins.

[0090] A buffer layer 111 may be further disposed on the substrate 110 to planarize the surface of the substrate 110 and block the penetration of impurities. The buffer layer 111 may comprise an inorganic material, and for example, may comprise silicon nitride (SiN). x ), silicon oxide (SiO) x ) or silicon nitride oxide (SiO) x N y Inorganic insulating materials such as silicon nitride (SiN) can be used. The buffer layer 111 can have a single-layer or multi-layer structure of the aforementioned materials. A barrier layer 112 can be further disposed on the substrate 110. The barrier layer 112 can be disposed between the substrate 110 and the buffer layer 111. The barrier layer 112 may include materials such as silicon nitride (SiN). x ), silicon oxide (SiO) x ) or silicon nitride oxide (SiO) x N y Inorganic insulating materials such as (e.g., 112). The barrier layer 112 can be a single-layer or multi-layer structure of this material.

[0091] Semiconductor layer 130 may be disposed on buffer layer 111. Semiconductor layer 130 may include one of amorphous silicon, polycrystalline silicon, and oxide semiconductor. In embodiments, for example, semiconductor layer 130 may include low-temperature polycrystalline silicon (LTPS), or may include an oxide semiconductor material including at least one of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and combinations thereof, or composed of such materials. In embodiments, for example, semiconductor layer 130 may include indium gallium zinc oxide (IGZO). Semiconductor layer 130 may include a channel region, a source region, and a drain region distinguished based on impurity doping. The source region and drain region may be disposed on opposite sides of the channel region of semiconductor layer 130, respectively. The source region and drain region may exhibit conductivity characteristics corresponding to conductors.

[0092] A first gate insulating layer 120 may be disposed on the semiconductor layer 130. The first gate insulating layer 120 may cover the semiconductor layer 130 and the substrate 110. The first gate insulating layer 120 may include materials such as silicon nitride (SiN). x ), silicon oxide (SiO) x ) or silicon nitride oxide (SiO) x N y Inorganic insulating materials such as ) and ). The first gate insulating layer 120 can be a single-layer structure or a multi-layer structure of the material.

[0093] Gate electrode 124 may be disposed on the first gate insulating layer 120. Gate electrode 124 may comprise a metal or metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), or titanium (Ti). Gate electrode 124 may be configured as a single layer or multiple layers. After forming gate electrode 124, doping or plasma treatment may be performed. The portion of semiconductor layer 130 covered by gate electrode 124 remains undoped or untreated by plasma treatment, and conversely, the portion of semiconductor layer 130 not covered by gate electrode 124 may be doped or treated by plasma treatment to exhibit conductor-like properties. Within semiconductor layer 130, the region overlapping with gate electrode 124 in a planar view may be termed a channel region.

[0094] The second gate insulating layer 122 and the inter-insulator layer 160 may be disposed on the gate electrode 124. The second gate insulating layer 122 and the inter-insulator layer 160 may cover the gate electrode 124 and the first gate insulating layer 120. The second gate insulating layer 122 and the inter-insulator layer 160 may include materials such as silicon nitride (SiN). x ), silicon oxide (SiO) x ) or silicon nitride oxide (SiO) x N y Inorganic insulating materials such as ) and . The second grid insulating layer 122 and the insulating interlayer 160 can be a single-layer structure or a multi-layer structure of the material.

[0095] Crack test wiring 730 may be disposed on the second gate insulating layer 122. Crack test wiring 730 may be disposed between the second gate insulating layer 122 and the interlayer insulating layer 160. Crack test wiring 730 may be disposed outside the common voltage supply line 70. Crack test wiring 730 may be disposed between the electrostatic test wiring 720 and the common voltage supply line 70. At least a portion of crack test wiring 730 may overlap with dams 410 and 420 on the third-direction DR3, but is not limited thereto, and may be disposed outside dams 410 and 420. Crack test wiring 730 may include various conductive materials.

[0096] Further reference Figure 6 The display device in the embodiment may further include a first sub-gate insulating layer 120S and a second sub-gate insulating layer 122S disposed on the buffer layer 111.

[0097] The first sub-gate insulating layer 120S may be spaced apart from the first gate insulating layer 120. In an embodiment, for example, the first sub-gate insulating layer 120S may be spaced apart from the first gate insulating layer 120 in a first direction DR1. Here, the first sub-gate insulating layer 120S may mean a portion of the first gate insulating layer 120 patterned to form the electrostatic test wiring 720. That is, the first sub-gate insulating layer 120S may be a portion of the first gate insulating layer 120 disposed on one end of the substrate 110 and on the lower surface of the electrostatic test wiring 720. In other words, the first sub-gate insulating layer 120S may be configured as a part of the first gate insulating layer 120. The first sub-gate insulating layer 120S may be separated from the first gate insulating layer 120 by a trench disposed on a first side of the first gate insulating layer 120. The first end of the first sub-gate insulating layer 120S may be aligned with one end of the substrate 110. The first end of the first sub-gate insulating layer 120S may contact the antistatic layer 710, which will be described later. The second end of the first sub-gate insulating layer 120S may contact the encapsulation layer 400, which will be described later. The first sub-gate insulating layer 120S may be disposed in the same layer as the first gate insulating layer 120 and may comprise the same material as the first gate insulating layer 120.

[0098] The second sub-gate insulating layer 122S may be disposed on the first sub-gate insulating layer 120S. The second sub-gate insulating layer 122S may be spaced apart from the second gate insulating layer 122. In an embodiment, for example, the second sub-gate insulating layer 122S may be spaced apart from the second gate insulating layer 122 in a first direction DR1. Here, the second sub-gate insulating layer 122S may mean a portion of the second gate insulating layer 122 patterned to form the electrostatic test wiring 720. The second sub-gate insulating layer 122S may be a portion of the second gate insulating layer 122 disposed on one end of the substrate 110 and on the lower surface of the electrostatic test wiring 720. The second sub-gate insulating layer 122S may be separated from the second gate insulating layer 122 by a trench disposed on a first side of the second gate insulating layer 122. The first end of the second sub-gate insulating layer 122S may be aligned with one end of the substrate 110. The first end of the second sub-gate insulating layer 122S may contact the antistatic layer 710, which will be described later. The second end of the second sub-gate insulating layer 122S may contact the encapsulation layer 400, which will be described later. The second sub-gate insulating layer 122S can be disposed in the same layer as the second gate insulating layer 122, and can include the same material as the second gate insulating layer 122.

[0099] In an embodiment, electrostatic discharge (ESD) test wiring 720 may be disposed on a first sub-gate insulating layer 120S and a second sub-gate insulating layer 122S. ESD test wiring 720 may be disposed between the second sub-gate insulating layer 122S and an insulating interlayer 160. Here, the second sub-gate insulating layer 122S may constitute a part of the second gate insulating layer 122. ESD test wiring 720 may be covered by the insulating interlayer 160. In an embodiment, for example, the side and top surfaces of the first test wiring 721 and the side and top surfaces of the second test wiring 722 may be covered by the insulating interlayer 160. Multiple first test wirings 721 may be disposed in the same layer as second test wirings 722 and may include the same material as the second test wirings 722. ESD test wiring 720 may be disposed in the same layer as crack test wiring 730 and may include the same material as the crack test wiring 730. However, this is not a limitation, and in another embodiment, for example, ESD test wiring 720 may be disposed in the same layer as the gate electrode 124. Reference will be made later. Figure 9 Provide a detailed description of the above content.

[0100] In one embodiment, the first end of the electrostatic test wiring 720 may be aligned with one end of the substrate 110. In another embodiment, for example, as... Figure 7 and Figure 8As shown, the first end 720_E of the first test wiring 721 can be aligned with the end of the substrate 110. The first end 720_E of the first test wiring 721 can be aligned with the side surface of the first sub-gate insulating layer 120S and the side surface of the second sub-gate insulating layer 122S. The first end 720_E of the first test wiring 721 can contact the antistatic layer 710. The second end of the first test wiring 721 can contact the insulating interlayer 160.

[0101] The electrostatic discharge (ESD) test wiring 720 can be disposed outside the crack test wiring 730 and the common voltage supply line 70. The ESD test wiring 720 can also be disposed outside the dams 410 and 420. Specifically, the second test wiring 722 can be disposed outside the crack test wiring 730, and multiple first test wirings 721 can be disposed outside the second test wiring 722. That is, the second test wiring 722 can be disposed between the multiple first test wirings 721 and the crack test wiring 730.

[0102] Source / drain electrodes 174 may be disposed on insulating interlayer 160. Source / drain electrodes 174 may be connected to the source and drain regions of semiconductor layer 130 through openings defined in insulating interlayer 160, second gate insulating layer 122, and first gate insulating layer 120, respectively. Source / drain electrodes 174 may comprise metals or metal alloys such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), or tantalum (Ta). Source / drain electrodes 174 may be configured as a single layer or multiple layers. In the embodiments, source / drain electrodes 174 may be configured as three layers including an upper layer, an intermediate layer, and a lower layer, wherein the upper and lower layers may include titanium (Ti) and the intermediate layer may include aluminum (Al).

[0103] The semiconductor layer 130, gate electrode 124, and source / drain electrode 174 described above can form a transistor. Depending on the embodiment, the transistor may include only the source and drain regions of the semiconductor layer 130 without the source / drain electrode 174. In an embodiment, each light-emitting element ED (reference) Figure 3 A light-emitting element (ED) can be connected to at least one transistor. In an embodiment, for example, an ED (referencing...) Figure 3 A light-emitting element (ED) can be connected to a switching transistor and a driving transistor. In an alternative embodiment, an ED (reference) Figure 3 It can be connected to three or more transistors.

[0104] A common voltage supply line 70 can be disposed on the insulating interlayer 160. The common voltage supply line 70 can transmit a common voltage ELVSS. The common voltage supply line 70 can be disposed on the peripheral region PA. The common voltage supply line 70 can be positioned closer to the edge of the substrate 110 than the transistor including the semiconductor layer 130.

[0105] A first passivation layer 180 may be disposed on the common voltage supply line 70 and the source / drain electrode 174. The first passivation layer 180 may cover the source / drain electrode 174 and the insulating interlayer 160. The first passivation layer 180, which is used to planarize the transistor surface of the substrate 110, may be an organic insulator and may include one or more materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0106] The connecting electrodes 176 and 178 can penetrate the first passivation layer 180. The connecting electrodes 176 and 178 can be used to connect transistors and light-emitting elements (EDs) (see reference). Figure 3 The connecting electrodes 176 and 178 may comprise a conductive material and may be formed as a single layer or multiple layers. In an embodiment, the first passivation layer 180 may include a via exposing at least a portion of the source / drain electrode 174. The connecting electrodes 176 and 178 may be physically electrically connected to the source / drain electrode 174 through the via of the first passivation layer 180.

[0107] A second passivation layer 182 may be disposed on the first passivation layer 180. The second passivation layer 182 may cover the connecting electrodes 176 and 178 and the first passivation layer 180. A third passivation layer 184 may be disposed on the second passivation layer 182. The second passivation layer 182 and the third passivation layer 184 may be organic insulators and may include one or more materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0108] An extended electrode 78 may be disposed on the second passivation layer 182. An opening overlapping the extended electrode 78 and the connecting electrode 76 may be formed in the second passivation layer 182 and the first passivation layer 180. The extended electrode 78 may be connected to the connecting electrode 76 through the opening. Multiple openings may be defined in the extended electrode 78. The openings in the extended electrode 78 may form emission channels for gases emitted from layers comprising or composed of organic materials during the manufacturing process, thereby reducing their impact on other components.

[0109] A common electrode 270 may be disposed on the third passivation layer 184. The common electrode 270 may also be referred to as a cathode and may be formed as a transparent conductive layer comprising indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO), or a combination thereof. Furthermore, the common electrode 270 may have semi-transparent properties. In an embodiment, the display area may include, for example, a pixel electrode disposed on the second passivation layer 182 and a light-emitting layer disposed on the pixel electrode. The pixel electrode and the light-emitting layer may together with the common electrode 270 constitute a light-emitting element ED (see reference). Figure 3 In this case, the pixel electrode can be an anode, and the common electrode 270 can be a cathode. However, it is not limited to this, and depending on the driving method of the display device, the anode and cathode can be formed relative to each other. Furthermore, the display area may further include a pixel defining layer or spacer disposed on the pixel electrode, etc.

[0110] The display device in the embodiment may further include dams 410 and 420 disposed on the substrate 110. Dams 410 and 420 may be disposed on the peripheral region PA of the substrate 110. Dams 410 and 420 may include a first dam 410 and a second dam 420. However, this may only be one embodiment, and the number of dams may be appropriately changed depending on the circumstances.

[0111] The first dam 410 may include a first layer 411, a second layer 412, and a third layer 413. The second layer 412 may be disposed on the first layer 411 of the first dam 410, and the third layer 413 may be disposed on the second layer 412. The first layer 411 of the first dam 410 may be disposed in the same layer as the second passivation layer 182, and may include the same material as the second passivation layer 182. The second layer 412 of the first dam 410 may be disposed in the same layer as the third passivation layer 184, and may include the same material as the third passivation layer 184.

[0112] The second dam 420 may include a first layer 421, a second layer 422, a third layer 423, and a fourth layer 424. The second layer 422, the third layer 423, and the fourth layer 424 may be sequentially disposed on the first layer 421 of the second dam 420. The first layer 421 of the second dam 420 may be disposed in the same layer as the first passivation layer 180 and may include the same material as the first passivation layer 180. The second layer 422 of the second dam 420 may be disposed in the same layer as the second passivation layer 182 and may include the same material as the second passivation layer 182. The third layer 423 of the second dam 420 may be disposed in the same layer as the third passivation layer 184 and may include the same material as the third passivation layer 184.

[0113] In the foregoing, although it has been described that the first dam 410 is formed as a three-layer structure and the second dam 420 is formed as a four-layer structure, this is not a limitation and can be changed in various ways. The number of layers forming dams 410 and 420 can be smaller or larger.

[0114] Encapsulation layer 400 may be disposed on common electrode 270 and dams 410 and 420. Encapsulation layer 400 may include at least one inorganic layer and at least one organic layer. In the illustrated embodiment, encapsulation layer 400 may include a first inorganic encapsulation layer 401, an organic encapsulation layer 402, and a second inorganic encapsulation layer 403. However, this may only be one embodiment, and the number of inorganic and organic layers forming encapsulation layer 400 may be varied in various ways.

[0115] A first inorganic encapsulation layer 401, an organic encapsulation layer 402, and a second inorganic encapsulation layer 403 may be disposed in at least a portion of the peripheral region PA. Depending on the embodiment, the organic encapsulation layer 402 may be disposed in the display region DA (referencing...). Figure 3 The first inorganic encapsulation layer 401 and the second inorganic encapsulation layer 403 are formed around the central region PA, and can be formed to reach the peripheral region PA. The encapsulation layer 400 is designed to protect the light-emitting element ED (see reference). Figure 3 It is protected from moisture or oxygen that may penetrate from the outside, and the ends of the first inorganic encapsulation layer 401 and the second inorganic encapsulation layer 403 can be in direct contact.

[0116] The first inorganic encapsulation layer 401 and the second inorganic encapsulation layer 403 can be integrally disposed in the display area DA (reference). Figure 3 The side surfaces of the first inorganic encapsulation layer 401 and the second inorganic encapsulation layer 403 can be aligned with the side surfaces of the substrate 110. An organic encapsulation layer 402 can be disposed within a portion of the peripheral region PA. The end of the organic encapsulation layer 402 can reach the first dam 410. The organic encapsulation layer 402 can overlap a portion of the first dam 410 on the third direction DR3. During the process of forming the organic encapsulation layer 402, the first dam 410 can control the diffusion of the material used to form the organic encapsulation layer 402. The organic encapsulation layer 402 can have a filling display region DA (reference DR3). Figure 3 The shape of the space between the end of the first inorganic encapsulation layer 401 and the first dam 410. In the part where the organic encapsulation layer 402 is provided, the organic encapsulation layer 402 may be provided between the first inorganic encapsulation layer 401 and the second inorganic encapsulation layer 403. In the part where the organic encapsulation layer 402 is not provided, the second inorganic encapsulation layer 403 may be directly provided on the first inorganic encapsulation layer 401.

[0117] The optical layer 460 can be disposed on the encapsulation layer 400. The optical layer 460 can be disposed entirely on the encapsulation layer 400. The ends of the optical layer 460 can be aligned with the ends of the first inorganic encapsulation layer 401 and the second inorganic encapsulation layer 403.

[0118] An antistatic layer 710 can be disposed on the side surface of the substrate 110 and the side surface of the optical layer 460. The antistatic layer 710 can be disposed within the coating area ASA, which is located outside the peripheral area PA. The antistatic layer 710 can cover the side surface of the substrate 110. The antistatic layer 710 can be aligned with the side surface of the substrate 110, the side surface of the first inorganic encapsulation layer 401, the side surface of the second inorganic encapsulation layer 403, and the side surface of the optical layer 460. Furthermore, as... Figure 7 and Figure 8 As shown, the antistatic layer 710 can contact the first ends 720_E of the plurality of first test wires 721. The antistatic layer 710 can be formed by coating a conductive polymer compound onto the side surface of the substrate 110 and the side surface of the plurality of first test wires 721. In an embodiment, for example, the antistatic layer 710 can be a coating layer of conductive polymer compound.

[0119] In the following text, see references Figures 9 to 12 The electrostatic discharge (ESD) test wiring of the display device in some embodiments will be described in detail.

[0120] Figures 9 to 11 Is with Figure 5 The section corresponding to Q2 shows a cross-sectional view of the electrostatic test wiring of the display device in some embodiments. Figure 12 Is with Figure 3 The area Q1 corresponds to a top view of the electrostatic test wiring of the display device in some embodiments.

[0121] First, refer to Figure 9In some embodiments, the electrostatic test wiring 720 of the display device can be disposed between the first sub-gate insulating layer 120S and the second sub-gate insulating layer 122S. In some embodiments, for example, multiple first test wirings 721 and second test wirings 722 can be directly disposed on the upper surface of the first sub-gate insulating layer 120S. The multiple first test wirings 721 and second test wirings 722 can be covered by the second sub-gate insulating layer 122S. That is, the side and top surfaces of the multiple first test wirings 721 and the side and top surfaces of the second test wirings 722 can be covered by the second sub-gate insulating layer 122S. In some embodiments, the electrostatic test wiring 720 can be disposed in the same layer as the gate electrode 124 and can include the same material as the gate electrode 124. In some embodiments, for example, the electrostatic test wiring 720 can include metals or metal alloys such as copper (Cu), molybdenum (Mo), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), or titanium (Ti).

[0122] refer to Figure 10 In some embodiments, at least a portion of the first sub-gate insulating layer 120S and at least a portion of the second sub-gate insulating layer 122S of the display device may not contact the antistatic layer 710. In some embodiments, for example, the side surfaces of the first sub-gate insulating layer 120S and the second sub-gate insulating layer 122S may be surrounded by a first inorganic encapsulation layer 401. That is, the first inorganic encapsulation layer 401 may be disposed between the antistatic layer 710 and the first sub-gate insulating layer 120S, and between the antistatic layer 710 and the second sub-gate insulating layer 122S.

[0123] refer to Figure 11 In some embodiments, the first gate insulating layer 120 and the second gate insulating layer 122 of the display device can extend to the end of the substrate 110 in the first direction DR1. The side surfaces of the first gate insulating layer 120 and the second gate insulating layer 122 can be aligned with the side surfaces of the substrate 110. The side surfaces of the first gate insulating layer 120 and the second gate insulating layer 122 can contact the antistatic layer 710. In this case, electrostatic test wiring 720 can be disposed on the second gate insulating layer 122.

[0124] refer to Figure 12In some embodiments, the electrostatic discharge (ESD) test wiring 720 of the display device can have various shapes. In one embodiment, for example, multiple first test wirings 721 can have a quadrilateral shape (e.g., a rectangular shape). In this case, the multiple first test wirings 721 can be arranged to be spaced apart in the second direction DR2, and the first surface 720_P of each of the multiple first test wirings 721 can contact the antistatic layer 710. The first surface 720_P of each of the multiple first test wirings 721 can be aligned with the first side surface S1 of the substrate 110. However, this is not a limitation, and the multiple first test wirings 721 can have polygonal, circular, or elliptical shapes, etc.

[0125] In the following text, see references Figure 13 The electrostatic discharge (ESD) test wiring of the display device in some embodiments will be described in detail.

[0126] refer to Figure 13 In some embodiments, the electrostatic discharge (ESD) test wiring 720 may surround the display area DA. In one embodiment, for example, the ESD test wiring 720 may be arranged adjacent to (close to) a first side surface S1 of the substrate 110, a second side surface S2 facing the first side surface S1 in a first direction DR1, and a third side surface S3 intersecting the first side surface S1 and the second side surface S2. Therefore, the antistatic layer 710 disposed on the first side surface S1, the second side surface S2, and the third side surface S3 of the substrate 110 may contact multiple first test wirings 721. A second test wiring 722 may be disposed between the crack test wiring 730 and multiple first test wirings 721.

[0127] In this embodiment, the electronic device may include a processor, a memory device, a storage device, an input / output (I / O) device, a power supply, and a display device. Here, the display device may be connected to... Figure 1 Corresponding to the display device 10. The electronic device may further include multiple ports for communicating with video cards, sound cards, memory cards, or universal serial bus (USB) devices. In one embodiment, the electronic device may be implemented as a television. In another embodiment, the electronic device may be implemented as a smartphone. However, the embodiments are not limited thereto; in another embodiment, the electronic device may be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet PC, car navigation system, computer monitor, laptop computer, or head-mounted display (e.g., helmet-mounted display) such as a helmet-mounted display.

[0128] A processor can perform various computational functions. In embodiments, the processor may be a microprocessor, a central processing unit (CPU), or an application processor (AP), etc. The processor may be coupled to other components via address buses, control buses, or data buses, etc. In embodiments, the processor may be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0129] The memory device can store data for the operation of an electronic device. In embodiments, the memory device may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, or a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, or a mobile DRAM device.

[0130] In embodiments, the storage device may include a solid-state drive (SSD) device, a hard disk drive (HDD) device, or a CD-ROM device, etc. In embodiments, the I / O device may include input devices such as a keyboard, keypad, mouse device, touchpad, or touch screen, and output devices such as a printer or speaker.

[0131] A power supply can provide power for the operation of an electronic device. The power supply can also provide power to a display device. The display device can be coupled to other components via a bus or other communication link. In this embodiment, the display device may be included in an I / O device.

[0132] In this embodiment, the electronic device may be implemented as a smartphone. However, the embodiments of this disclosure are exemplary and may not be limited thereto. For example, the electronic device may be implemented as a mobile phone, video phone, smart tablet, smartwatch, television, tablet PC, vehicle display, computer monitor, laptop computer, helmet display device, etc. Furthermore, the electronic device may be a television, monitor, laptop computer, or tablet PC. Additionally, the electronic device may be an automobile.

[0133] The display device according to the embodiments can be applied to various electronic devices. The electronic device according to the embodiments may include the display device, and in addition to the display device, may further include modules or devices with additional functions.

[0134] Figure 14 This is a block diagram of an electronic device according to an embodiment. (Reference) Figure 14 The electronic device 10 according to the embodiment may include a display module 11, a processor 12, a memory 13 and a power module 14.

[0135] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0136] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application program stored in the memory 13, video data signals and / or input control signals are transmitted to the display module 11, and the display module 11 can process the received signals to output video information through the display screen.

[0137] The power module 14 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10.

[0138] According to the above embodiments, at least one of the components of the electronic device 10 may be included within the display device. Furthermore, some individual modules that are functionally included within a single module may be incorporated into the display device, while other individual modules may be provided separately from the display device. For example, the display device may include a display module 11, while the processor 12, memory 13, and power module 14 may be provided as other devices within the electronic device 10 that are not part of the display device.

[0139] Figure 15 Schematic diagrams of electronic devices according to various embodiments are shown.

[0140] refer to Figure 15 Various electronic devices having a display device according to the embodiments may include not only image display electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e, but also wearable electronic devices such as smart glasses 10_2a, helmet displays 10_2b, and smartwatches 10_2c, as well as automotive electronic devices having display modules 10_3 such as those placed on car dashboards, center dashboards, CID (Center Information Display), and rearview mirror displays.

[0141] While this disclosure has been described in conjunction with what is now considered to be actual embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the claims.

Claims

1. A display device, comprising: The substrate includes a display area and a peripheral area disposed outside the display area; A light-emitting element is disposed on the display area of ​​the substrate; An antistatic layer covers the side surface of the substrate; as well as Electrostatic discharge (ESD) test wiring is disposed on the peripheral area, and the ESD test wiring includes: Multiple first test wires, spaced apart from each other, are connected to the antistatic layer respectively; as well as The second test wiring is electrically connected to the plurality of first test wirings.

2. The display device according to claim 1, wherein, The ends of the plurality of first test wirings are aligned with the ends of the substrate.

3. The display device according to claim 1, wherein, The multiple first test wirings are repeatedly arranged at the ends of the substrate.

4. The display device according to claim 1, further comprising: A dam is provided on the peripheral area of ​​the substrate; as well as Crack test wiring is disposed between the dam and the electrostatic test wiring.

5. The display device according to claim 4, wherein, The second test wiring is disposed between the plurality of first test wirings and the crack test wiring.

6. The display device according to claim 4, wherein, The electrostatic test wiring and the crack test wiring are disposed in the same layer and comprise the same material as the crack test wiring.

7. The display device according to claim 1, wherein, Each of the plurality of first test wirings includes a horizontal portion in contact with the antistatic layer and an extension portion connecting the horizontal portions.

8. The display device according to any one of claims 1 to 7, further comprising: A first gate insulating layer is disposed on the substrate; as well as A second gate insulating layer is disposed on the first gate insulating layer. The plurality of first test wirings and the second test wirings are disposed on the second gate insulating layer.

9. The display device according to claim 8, further comprising: An insulating interlayer is disposed on the second gate insulating layer. The insulating interlayer covers the plurality of first test wirings and second test wirings.

10. A display device, comprising: A display panel includes: a substrate, including a display area and a peripheral area disposed outside the display area; a light-emitting element disposed on the display area of ​​the substrate; and electrostatic discharge (ESD) test wiring, the ESD test wiring including a plurality of first test wirings disposed on the peripheral area and a second test wiring electrically connected to the plurality of first test wirings; An optical layer is disposed on the front surface of the display panel; A cover window is disposed on the optical layer; A protective plate is disposed on the rear surface of the display panel; and An antistatic layer covers the side surfaces of the display panel, the optical layer, and the protective plate. The plurality of first test wires are respectively connected to the antistatic layer.

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