Graphical User Interface for Resource Scheduling and Management of Small-Model AI Platform for Electronic Devices

CN310000259SActive Publication Date: 2026-05-26TERMINUSBEIJING TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Designs(China)
Current Assignee / Owner
TERMINUSBEIJING TECH CO LTD
Filing Date
2025-06-26
Publication Date
2026-05-26

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Abstract

1. Name of the product in this design: Graphical User Interface for Resource Scheduling and Management of Small Model AI Platform for Electronic Devices. 2. Intended use of this design: for use in an electronic device. 3. The key design features of this product are: the graphical user interface content that displays information. 4. The image or photo that best illustrates the design points: Interface change state diagram 2. 5. Purpose of the graphical user interface: This graphical user interface is used for resource scheduling and management of the small model AI platform. The main view is the login interface for the small model AI platform. In the main view, after the user enters their account, password and verification code, they can click the "Log in Now" button to enter the interface change state diagram 1, which displays the small model AI middleware video integrated management interface. In Interface Change State Diagram 1, when the user clicks the "Resource Scheduling Center" button, they enter Interface Change State Diagram 2, which displays the Resource Scheduling Center interface. In the interface change state diagram 2, the user clicks the "Scheduling Strategy" item in the "Scheduling Strategy" column on the left to enter the interface change state diagram 3, which displays the scheduling strategy interface. In the interface change state diagram 3, the user clicks the "Idle Time Scheduling" button to enter the interface change state diagram 4, which displays the idle time scheduling interface. In the interface change state diagram 4, the user clicks the "Priority Preemption" button to enter the interface change state diagram 5, which displays the priority preemption interface.
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