Device and method for repairing a memory cell and memory system using the device

Abstract

Storage system that features the following: a storage device (200, 300, 5000, 8200) comprising a non-volatile storage device (340, 1000, 3601-3604, 5100, 7301, 8221) having a matrix arrangement structure of at least NxM, where N and M are integers equal to or greater than 2; and a test device (100) which is configured to test the storage device (200, 300, 5000, 8200), wherein an error address, which is detected by the test device (100), is transferred to the storage device (200, 300, 5000, 8200) and stored in the non-volatile storage device (340, 1000, 3601-3604, 5100, 7301, 8221), the test device includes a semiconductor chip, wherein the semiconductor chip has an error correction code, ECC, machine or a built-in self-test, BIST, unit and an error address memory (110, 260) configured to the error address, wherein the error address memory (110, 260) is controlled by a control unit (130, 270, 360, 4100, 8110), wherein the control unit (130, 270, 360, 4100, 8110) is configured to check or control the fault address to be stored in the fault address memory (110, 260) and transmitted according to a test command.

Description

BACKGROUND area

[0001] Embodiments of the inventive concept relate to a storage system and more precisely to a method and a device for repairing a memory cell by testing the storage device, which has a non-volatile storage device, using a test device, and a system which has the device. Description of the state of the art

[0002] DE 102 44 620 A1 discloses a memory with: a memory array having a plurality of memory elements, a plurality of spare memory elements, a plurality of address backup units, each of which has a plurality of fusible connections and is operable to store a spare address, each spare address identifying a memory element of the memory elements of the memory array that is to be replaced by an associated memory element of the spare memory elements, and forming a respective 2m-bit row or 2n-bit column of a backup array; a vector generator that is operable to generate a 2n-bit row vector based on the rows of the backup array, and to generate a 2m-bit column vector based on the columns of the backup array;and a compression unit that is operable to generate a row checksum from the row vector and to generate a column checksum from the column vector.

[0003] US Patent 6,542,419 B2 discloses a fuse circuit comprising an electrically programmable fuse and a data hold circuit for storing the programmed fuse data. In the data hold circuit, prior to programming, a node is preloaded to "H" by a preload circuit and preset to "H" by a preset circuit as the result of the logical product of a fault address and a hold signal when the fuse needs to be programmed. A programming selection circuit monitors the node to select whether or not to perform fuse programming. Accordingly, efficient electrical programming control is achieved without the need for a dedicated register to store a fuse address to be programmed.

[0004] US Patent 5,357,473 A discloses a semiconductor memory system comprising: a semiconductor memory element assembly with a plurality of semiconductor memory elements, a data bus for transferring data to the semiconductor memory element assembly, an address bus for inputting an address into the semiconductor memory element assembly, a read / write controller for controlling the reading / writing of data written to the semiconductor memory element assembly, an interface control module for controlling the transmission / reception of data and commands to and from an external system, a microprocessor for controlling the read / write controller and the interface control module, an error address memory for storing and outputting information about an address containing at least one faulty bit and an alternative address to replace that address, and an error address handling circuit for replacing the address.where the faulty bit is present, by the alternative address according to an output of the error address memory.

[0005] A semiconductor chip is manufactured according to a semiconductor fabrication process and is then tested in the form of a wafer, die, or package using test equipment. Testing allows for the rejection of defective sections or chips. If some memory cells of a semiconductor chip are defective, the chip is repaired by restoring these defective cells.

[0006] Recently, as processes for manufacturing semiconductor chips, such as dynamic random access memory (DRAM), have become increasingly refined, it has become much more likely that defects will occur during the manufacturing process. Similarly, even if no defect is detected during an initial testing period, a fault may still occur during the operation of a chip. To address this problem, various testing procedures and devices have been developed. SUMMARY

[0007] It is an object of the present invention to solve the problems explained above.

[0008] This problem is solved by the storage system with the features of claim 1, the storage device with the features of claim 18, the test device with the features of claim 24, the method with the features of claim 31, the method with the features of claim 35, the method with the features of claim 39, and the storage system with the features of claim 41. Advantageous embodiments are found in the respective dependent claims.

[0009] Embodiments of the inventive concept provide a test device for the reliable repair of a memory cell.

[0010] Embodiments of the inventive concept also provide a test procedure for reliably repairing a memory cell.

[0011] Embodiments of the inventive concept also include a storage system which has a test device and a method for reliably repairing a storage cell.

[0012] The technical problems of the inventive concept are not limited to the above disclosure. Other problems may become apparent to those skilled in the art from the following description.

[0013] In accordance with one aspect of the inventive concept, a storage system comprises a storage device, which includes a non-volatile storage device having a matrix arrangement of at least N x M, where N and M are each integers equal to or greater than 2; and a test device configured to test the storage device. An error address detected by the test device is transferred to the storage device and stored in the non-volatile storage device.

[0014] In one embodiment, the test device can include a semiconductor chip.

[0015] In one embodiment, the semiconductor chip may include an error correcting code (ECC) machine, and the non-volatile storage device may include an anti-fuse arrangement having a matrix arrangement structure of at least NxM, where N and M are integers equal to or greater than 2.

[0016] In one embodiment, the semiconductor chip may have a built-in self-test (BIST) unit, and the non-volatile memory device may have an anti-fuse arrangement having a matrix arrangement structure of at least NxM, where N and M are integers equal to or greater than 2.

[0017] In one embodiment, the BIST unit can be connected to the ECC machine.

[0018] In one embodiment, the semiconductor chip may include an error correcting code (ECC) machine or a built-in self-test (BIST) unit and an error address memory configured to the error address.

[0019] In one embodiment, the error address memory can be controlled by a control unit.

[0020] In one embodiment, the semiconductor chip may include an error correcting code (ECC) machine or a built-in self-test (BIST) unit, an error address memory, an address output unit, a control output unit, a data buffer, and a control unit.

[0021] In one embodiment, the control output unit can control the operation of the ECC machine or the BIST unit, the fault address memory, the data buffer, and the control unit.

[0022] In one embodiment, the semiconductor chip can be contained in a memory controller and is connected to a central processing unit (CPU).

[0023] In one embodiment, the CPU can provide a test instruction for the storage device.

[0024] In one embodiment, the test instruction may include a test start instruction, a test end instruction, or an error address transfer instruction.

[0025] In one embodiment, the test device can be included in a test set.

[0026] In one embodiment, the test equipment may include a sample generator, a test card, and a socket or plug socket.

[0027] In one embodiment, the non-volatile storage device may include an anti-fuse arrangement which has a matrix arrangement structure of at least NxM, where N and M are integers equal to or greater than 2.

[0028] In one embodiment, the storage system may further include a preliminary or temporary error address memory which is configured to store the error address.

[0029] In one embodiment, the fault address can be stored in the anti-fuse arrangement under the control of the control unit.

[0030] In one embodiment, the control unit can be activated in response to a mode activation signal received from a decoding unit.

[0031] In one embodiment, the control unit controls the fault address to be written to or read from the anti-fuse arrangement, and a verification result to be transferred outside the storage device.

[0032] In one embodiment, the anti-fuse arrangement can be connected to a repair address memory configured to store the fault address, the repair address memory can be connected to a comparator configured to compare the fault address with an external address, and the comparator can be connected to a multiplexer configured to select one of the fault address and the external address.

[0033] In accordance with one aspect of the inventive concept, a storage device comprises a temporary fault address memory for temporarily storing the fault address; a non-volatile storage device having a matrix arrangement structure of at least NxM for storing the fault address, where N and M each denote an integer equal to or greater than 2; and a control unit configured to control a transfer of the fault address stored in the temporary fault address memory to the non-volatile storage device.

[0034] In one embodiment, the non-volatile storage device may include an anti-fuse arrangement.

[0035] In one embodiment, in order to determine whether the error address is written correctly, the control unit can check the error address to be read from the anti-fuse arrangement and a verification result to be transmitted outside the storage device.

[0036] In one embodiment, the control unit can control or check the anti-fuse arrangement to be scanned or programmed.

[0037] In one embodiment, the anti-fuse arrangement can be connected to a repair address memory configured to store the fault address, the repair address memory can be connected to a comparator configured to compare the fault address with an external address, and the comparator can be connected to a multiplexer configured to select one of the fault address and the external address.

[0038] In one embodiment, the preliminary error address memory can be connected to an address buffer configured to receive an external address.

[0039] In one embodiment, the control unit can be activated according to a mode activation signal generated by a decoding unit.

[0040] In one embodiment, the decoding unit can be connected to the address buffer and a control buffer configured to receive a control signal.

[0041] In accordance with another aspect of the inventive concept, a test device comprises an error correcting code (ECC) circuit configured to detect and correct an error bit; an error address memory configured to store an error address of the error bit; and a control unit configured to check or control the error address to be stored in the error address memory and transmitted externally according to a test command.

[0042] In one embodiment, the ECC circuit can be connected to a data buffer which is configured to receive the error bit.

[0043] In one embodiment, the test instruction may include a test start instruction, a test end instruction, or an error address transfer instruction.

[0044] In one embodiment, the ECC circuit can have a built-in self-test (BIST) unit.

[0045] In one embodiment, the test device can be contained in a memory controller or memory control unit, and it is connected to a central processing unit (CPU).

[0046] In one embodiment, the test device can be included in a test set.

[0047] In one embodiment, the test equipment may further include a sample generator, a test card and a socket or plug socket.

[0048] In accordance with another aspect of the inventive concept, a method for operating a test device for transmitting a fault address comprises acquiring the fault address using an error correcting code (ECC) circuit; storing the fault address in a fault address memory; entering a fault address transmission mode according to a test instruction; transmitting a transmission signal which includes a mode register setting instruction; and transmitting the fault address.

[0049] In one embodiment, the fault address can be detected by an ECC machine or a built-in self-test (BIST) unit.

[0050] In one embodiment, the transmission signal may also include a write command and a chip selection signal.

[0051] In one embodiment, the test instruction may include an instruction that commands to start the transmission of the error address or an instruction that commands to stop the transmission of the error address, and it is given by a central processing unit (CPU).

[0052] In accordance with another aspect of the inventive concept, a method for operating a storage device for writing an error address to the storage device comprises receiving the error address according to a mode register setting instruction; storing the error address in a temporary error address memory; and storing the error address in a non-volatile storage device having a matrix arrangement structure of at least NxM, where N and M are each an integer equal to or greater than 2.

[0053] In one embodiment, before the error address is stored in the non-volatile memory device, the method may further include checking a memory location of the non-volatile memory device.

[0054] In one embodiment, after the fault address has been stored in the non-volatile memory device, the method may still include a reading of the stored fault address.

[0055] In one embodiment, after the stored error address has been read, the method may further include transmitting a verification result serially or in parallel to the outside, which indicates a state of the read error address.

[0056] In accordance with another aspect of the inventive concept, a method for operating a test device for transmitting a fault address to a storage device comprises: acquiring the fault address by an error correction code (ECC) circuit; storing the fault address in an error address memory; entering a fault address transmission mode according to a test instruction; transmitting a transmission signal comprising a mode register setting instruction; transmitting the fault address; receiving the fault address according to the mode register setting signal; storing the fault address in a temporary fault address memory; and storing the fault address in a non-volatile storage device having a matrix arrangement structure of at least NxM, where N and M are each integers equal to or greater than 2.

[0057] In one embodiment, before the error address is stored in the non-volatile memory device, the method may further include checking a memory location of the non-volatile memory device.

[0058] In accordance with another aspect of the inventive concept, a storage system comprises a test device configured to provide test data for a storage device; the storage device having a built-in self-test (BIST) unit configured to test the storage device; and a non-volatile storage device having a matrix array structure of at least N x M, where N and M are integers equal to or greater than 2. An error address generated by testing the storage device by the BIST unit is stored in the non-volatile storage device.

[0059] In one embodiment, the non-volatile storage device may include an anti-fuse arrangement which has a matrix arrangement structure of at least NxM, where N and M are integers equal to or greater than 2.

[0060] In one embodiment, the storage device may further comprise at least two fault address register arrangements configured to temporarily store the fault address.

[0061] In one embodiment, the BIST unit can transfer the error address to the at least two error address memory registers according to an error flag.

[0062] In one embodiment, the fault generation flag can be replaced by a pre-charge command. Brief description of the drawings

[0063] The foregoing and other features and advantages of the inventive concepts will become clear from the more specific description of preferred embodiments of the inventive concepts, as illustrated in the accompanying drawings, in which the same reference numerals refer to the same parts across the different views. The drawings are not necessarily to scale; the emphasis is instead placed on illustrating the principles of the inventive concepts. In the drawings: Fig. Figures 1-4 are conceptual representations of storage systems in accordance with embodiments of the inventive concept; Fig. Figure 5 illustrates a circuit block of a test device in accordance with an embodiment of the inventive concept; Fig. Figure 6A is a representation illustrating a system-on-a-chip (SOC) or single-chip system which includes a test device in accordance with an embodiment of the inventive concept; Fig. Figure 6B is a representation illustrating a test setup which uses a test device in accordance with an embodiment of the inventive concept; Fig. Figure 7 illustrates a circuit block of a storage device in accordance with an embodiment of the inventive concept; Fig. Figure 8 is a representation illustrating a non-volatile storage device in accordance with one embodiment of the inventive concept; Fig. Figure 9 illustrates a structure of a module in accordance with an embodiment of the inventive concept; Fig. 10 and Fig. 11 are timing diagrams or time sequence diagrams which, in accordance with an embodiment of the inventive concept, illustrate a time sequence when an error address is transmitted; Fig. Figure 12 is a time diagram which, in accordance with an exemplary embodiment of the inventive concept, illustrates a time sequence when a verification result is transmitted in parallel; Fig. Figure 13 is a table illustrating verification results that are to be transferred in parallel in accordance with an exemplary embodiment of the inventive concept; Fig. Figure 14 is a time diagram illustrating the sequence of events when verification results are transferred in accordance with an exemplary embodiment of the inventive concept; Fig. Figure 15 is a table illustrating verification results, which are to be transferred serially, in accordance with an exemplary embodiment of the inventive concept; Fig. 16 and Fig. 17 are timing diagrams illustrating a method for operating a test apparatus in accordance with an exemplary embodiment of the inventive concept; Fig. Figure 18 is a conceptual representation of a storage system in accordance with another exemplary embodiment of the inventive concept; Fig. Figure 19 illustrates a circuit block of a storage device in accordance with another embodiment of the inventive concept; Fig. 20 and Fig. 21 are timing diagrams illustrating the operation of a storage device in accordance with exemplary embodiment of the inventive concept; Fig. Figure 22 is a flowchart illustrating a method for operating a storage device according to an exemplary embodiment of the inventive concept; Fig. Figure 23 is a representation illustrating optical connections of a storage system in accordance with an exemplary embodiment of the inventive concept; Fig. Figure 24 illustrates layered chips with through-silicon vias (TSV) to which a memory system is applied in accordance with an exemplary embodiment of the inventive concept; Fig. Figure 25 illustrates various interfaces of a storage system in accordance with an exemplary embodiment of the inventive concept; and Fig. 26 and Fig. 27 are diagrams illustrating system connections of a storage system in accordance with exemplary embodiments of the inventive concept. DETAILED DESCRIPTION OF THE EXECUTION FORMS

[0064] Several embodiments will now be described in more detail with reference to the accompanying drawings, in which some embodiments are shown. However, the inventive concept can be implemented in various forms and should not be considered limited to the embodiments described herein. Rather, these embodiments are intended to ensure that this disclosure is thorough and complete, and fully conveys the inventive concept to those skilled in the art. In the drawings, similar reference numerals denote similar elements, and the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0065] The terminology used herein is solely for the purpose of describing certain embodiments and is not intended to be limiting to the present inventive concept. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, it will be understood that the words "indicates" and / or "indicating," when used in this description, specify the presence of the features, integers, steps, operations, elements, and / or components mentioned, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0066] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by a person skilled in the art in the field to which this inventive concept belongs. It is further understood that terms such as those defined in commonly used dictionaries are to be interpreted as having the meaning consistent with their meaning in the context of the relevant or applicable field, and they are not to be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0067] The Fig. Figures 1-4 are conceptual representations of storage systems in accordance with embodiments of the inventive concept.

[0068] Referring to Fig. Figure 1 comprises a storage system with a test device 100 and a storage device 200. The test device 100 transmits a control signal containing an error address, an instruction commanding the storage device 200 to operate, and data DQ. Although not shown, the test device 100 may be contained within a memory controller, a memory control device, or test equipment. The storage device 200 comprises dynamic random access memory (DRAM), which is volatile memory. Alternatively, the storage device 200 may comprise non-volatile memory, such as magnetoresistive RAM (MRAM), resistive RAM, phase-change RAM (PRAM), or NAND flash memory. The storage device 200 comprises a non-volatile memory device that incorporates an anti-fuse arrangement.The non-volatile memory device is used to store the error address. The non-volatile memory device can be MRAM, RRAM, PRAM, NAND flash memory, or similar. Memory device 200 operates according to the control signal and transmits the data DQ to test device 100.

[0069] Referring to Fig. In Figure 2, a test device 100 includes an error correction code (ECC) machine. The ECC machine detects an error bit and an error address from data DQ received from a storage device 200 and corrects the error bit. The storage device 200 has an anti-fuse arrangement and stores the error address received from the test device 100. An error memory cell is repaired based on the stored error address.

[0070] Referring to Fig. 3. Test device 100 has a built-in self-test (BIST) unit. The BIST unit tests either test device 100 or storage device 200. To test storage device 200, test data is generated and transferred to storage device 200. A faulty memory cell is detected by writing test data to a memory cell and then reading the test data from the memory cell. An error address, which is the address of the faulty or failed memory cell, is temporarily stored in test device 100 and then transferred to storage device 200. The transferred error address is stored in an anti-fuse arrangement to repair the faulty memory cell.

[0071] Referring to Fig. Figure 4 includes a test device 100 comprising a BIST unit and an ECC machine. A storage device 200 is tested using the BIST unit, and an error address is stored in an anti-fuse arrangement contained within the storage device 200. The error address, which is the address of an error bit occurring during operation of the storage device 200, is captured using the ECC machine and stored in the anti-fuse arrangement of the storage device 200. When the storage device 200 is not operating, it can be tested using the BIST unit according to a test instruction issued by a central processing unit (CPU). While the storage device 200 is operating, the error address can be captured using the ECC machine.

[0072] Fig. Figure 5 illustrates a circuit block of a test device 100 in accordance with an embodiment of the inventive concept.

[0073] Referring to Fig. The test device 100 comprises a fault address memory 110, an ECC machine (or BIST unit) 120, a control unit 130, an address output buffer 140, a control output unit 150, and an input / output (I / O) data buffer 160. The fault address memory 110 stores a fault address ADD 141, which is detected by the ECC machine (or BIST unit) 120. The fault address memory 110 can be implemented as a register, a static random access memory (SRAM), or non-volatile memory. The address output buffer 140 is connected to the error address memory 110 and transmits the error address ADD 141 to the storage device 200. The control output unit 150 transmits a control signal 151, which includes a read instruction, a write instruction, a pre-charge command, a mode register setting instruction, and the like, to the storage device 200.The control output unit 150 is connected to and controlled by a control unit 130. The I / O data buffer 160 is controlled by the control unit 130 and receives or transmits input / output (I / O) data. The I / O data may only contain test data for testing the storage device 200. Data received by the storage device 200 is transferred to the ECC machine (or BIST unit) 120 via the I / O data buffer 160. The control unit 130 is connected to the ECC machine (or BIST unit) 120, the fault address memory 110, the address output unit 140, the control output buffer 150, and the I / O data buffer 160. The control unit 130 receives a test instruction from a CPU. The test command can include a test start command, a test end command, a command that orders the transmission of the error address ADD to start, and a command that orders the transmission of the error address ADD to stop.The fault address ADD 141, which is detected by the ECC machine (or BIST unit) 120, is controlled so that it is stored in the fault address memory 110 according to the received test command. Likewise, the transmission of the fault address ADD 141 and the control signal 151 are controlled using the address output unit 140 and the control output unit 150.

[0074] Fig. Figure 6A is a representation illustrating a system-on-chip (SOC) 1100 which includes a test device 100 in accordance with an embodiment of the inventive concept.

[0075] Referring to Fig. 6A, the SOC 1100 has a CPU 1120, a memory controller 1110, and an interface 1130. The memory controller 1100 has the test device 100. The test device 100 has an ECC machine (or BIST unit) 120, a fail address memory (FAM) 110, a control unit, etc., which elements of the test device 100, which in Fig. As illustrated in Figure 5, the memory controller 1110 is connected to the CPU 1120 to receive a test instruction Com from the CPU 1120. The test instruction Com can contain a test start instruction, a test end instruction, an instruction to start a transmission of an error address, and an instruction to stop the transmission of the error address. An error address, a control signal, and data are transmitted to the storage device 200 via interface 1130.

[0076] Fig. Figure 6B is a representation illustrating a test equipment 1200 which uses a test device 100 in accordance with an embodiment of the inventive concept.

[0077] Referring to Fig. Test equipment 6B comprises test device 100, a sample generator 1210, a test card 1220, and a socket or connector 1230. The sample generator 1210 generates various test data for the test storage device 200. The test card 1220 contacts a test pad of the storage device 200 directly via a test probe to transfer the test data.

[0078] The socket or connector 1230 secures the storage device 200 during a test of the storage device 200.

[0079] Fig. Figure 7 illustrates a circuit block of a storage device 200 in accordance with an embodiment of the inventive concept.

[0080] Referring to Fig. 7 The storage device 200 comprises an address buffer 210, a control buffer 220, a data buffer 230, a decode unit 240, a repair address register 250, a comparator unit 251, a multiplexer (Mux) 252, a temporary fault address memory 260, a control unit 270, an anti-fuse arrangement 280, which is a non-volatile storage device, and a memory cell arrangement 290.

[0081] An error address is received via the address buffer 210 and temporarily stored in the temporary error address memory 260. The temporary error address memory 260 can be implemented as a register array, SRAM, or non-volatile memory. The decoder 240 receives a control signal via the control buffer 220, performs decoding, and generates a mode activation signal. The control signal includes a read command, a write command, a pre-charge command, a mode register setting signal, and the like. The control unit 270 is activated according to the mode activation signal and stores the error address in the anti-fuse array 280, which is a non-volatile memory array. The control unit 270 samples the stored error address to verify that the error address has been programmed correctly.A programming result (verification result) is transmitted to the test device 100 via a data output pin. The anti-fuse arrangement 280, which is a non-volatile memory device, is connected to the repair address register 250, which is configured to store the fault address. The repair address register 250 is connected to the comparator unit 251, which is configured to compare the fault address with an external address. The comparator unit 251 is connected to the multiplexer (Mux) 252, which is configured to select one of the fault address and the external address. Data received via the I / O data buffer 230 can be used as a chip selection signal (component designation) to select a chip on a memory module.

[0082] Fig. Figure 8 is a representation illustrating a non-volatile storage device 1000 in accordance with an embodiment of the inventive concept.

[0083] Referring to Fig. Figure 8 of the non-volatile storage device 1000 comprises a fuse assembly 1100, on which a plurality of fuses 1110 are arranged, level shifters 1200_1 to 1200_m, which generate a high voltage to change the resistance states of the plurality of fuses 1110, and a read amplifier 1300, which samples / amplifies information stored in the fuse assembly 1100. The non-volatile storage device 1000 further comprises a first register unit 1400 and a second register unit 1500 for storing fuse data that is generated when information stored in the anti-fuse assembly 1100 is read. Each of the first register unit 1400 and the second register unit 1500 can be implemented as a shift register comprising a plurality of registers.

[0084] The fuse assembly 1100 comprises a plurality of fuses 1110 in which information is stored. The fuse assembly 1100 can comprise laser fuses whose connections are controlled by laser radiation, or it can comprise electrical fuses whose connections are controlled according to an electrical signal. Alternatively, the fuse assembly 1100 can comprise anti-fuses whose states are changed from a high-resistance state to a low-resistance state according to an electrical signal, for example, a high-voltage signal. The fuse assembly 1100 can comprise any type of fuse from the various types of fuses described above. In the following embodiment, the fuse assembly 1100 is assumed to be an anti-fuse assembly comprising anti-fuses.Likewise, information stored in the anti-fuses, or data read from the anti-fuses, will be referred to below as fuse data.

[0085] The anti-fuse arrangement 1100 has an array structure in which the majority of fuses 1100 are arranged at the intersections of a majority of rows and a majority of columns. For example, if the anti-fuse arrangement 1100 has m rows and n columns, then the anti-fuse arrangement 1100 has m x n anti-fuses 1110. The anti-fuse arrangement 1110 has m word lines WL1 to WLm for accessing the anti-fuses 1110, which are arranged in the m rows, and n bit lines BL1 to BLn, which are arranged to correspond to the n columns, so that they provide information that is read from the majority of anti-fuses 1110.

[0086] The anti-fuse arrangement 1100 stores various pieces of information related to the operation of the non-volatile storage device 1000. For example, the anti-fuse arrangement 1100 can store multiple settings for configuring the operating environment of the non-volatile storage device 1000. These settings are programmed by changing the states of multiple anti-fuses 1100 through the application of voltage signals WLP1 to WLPm, which are provided by the level shifters 1200_1 to 1200_m to the anti-fuse arrangement 1100. In most Anti-Fuses 1110, information is stored by programming the majority of Anti-Fuses 1110 from the high-resistance state to the low-resistance state, in contrast to a general fuse circuit, such as a laser fuse circuit or an electrical fuse circuit.Most 1110 anti-fuses can have a structure in which a dielectric layer is positioned between two conductive layers, i.e., a capacitor structure. Most 1110 anti-fuses are programmed by breaking the dielectric layer through the application of a high voltage between the two conductive layers.

[0087] After the anti-fuse assembly 1100 is programmed, a read operation is performed on the anti-fuse assembly 1100, simultaneously with the start of operation of the non-volatile storage device 1000. The read operation can be performed on the anti-fuse assembly 1100 either concurrently with its operation or at a predetermined time after the non-volatile storage device 1000 has been operated. In the anti-fuse assembly 1100, a word line selection signal is provided via word lines WL1 to WLm, and information stored in a selected anti-fuse 1110 is made available to the read amplifier 1300 via bit lines BL1 to BLn. According to the characteristics of the arrangement structure, the information stored in the anti-fuse arrangement 1100 can be accessed randomly by driving the word lines WL1 to WLm and the bit lines BL1 to Bln.

[0088] Since, for example, the word lines WL1 to WLm are operated sequentially, the majority of antifuses 1110 are accessed sequentially from the first line to the mth line in the antifuse arrangement 1100. The information accessed sequentially by the majority of antifuses is provided to the read amplifier 1300. The read amplifier 1300 has one or more read amplifier circuits. For example, if the antifuse arrangement 1100 has n columns, the read amplifier 1300 has n read amplifier circuits corresponding to the n columns. The n read amplifier circuits are each connected to the n bit lines BL1 to BLn. Fig. Figure 1 illustrates a case in which two read amplifier circuits are arranged such that they correspond to each of the n bit lines BL1 to BLn. For example, an odd-numbered read amplifier circuit and an even-numbered read amplifier circuit are arranged such that they correspond to a first bit line BL1. The odd-numbered read amplifier circuit samples, amplifies, and outputs information stored in the antifuses 1110 connected to the odd-numbered word lines WL1, WL3, WL5, ... The even-numbered read amplifier circuit samples, amplifies, and outputs information stored in the antifuses 1110 connected to the even-numbered word lines WL2, WL4, WL6, ... However, the inventive concept is not limited to this, and read amplifier circuits can be arranged in any number of different configurations.For example, only one read amplifier circuit can be arranged to correspond to one bit line, or three or more read amplifier circuits can be arranged to correspond to one bit line.

[0089] The read amplifier 1300 samples / amplifies and outputs the information accessed by the anti-fuse arrangement 1100. The sampled / amplified information consists of fuse data OUT1 to OUTn, which is actually or currently used to set or configure the operating environment of the volatile storage device 1000. As described above, since Fig. Figure 1 illustrates a case in which two read amplifier circuits are arranged so that they correspond to each bit line, currently or actually have fuse data, for example first fuse data OUT1, odd-numbered fuse data and even-numbered fuse data.

[0090] The fuse data OUT1 to OUTn, output by the read amplifier 1300, are intended for the first register unit 1400. The first register unit 1400 can be implemented as a shift register, in which a plurality of registers are connected in series to provide a signal sequentially. Likewise, the number of registers contained in the first register unit 1400 is less than the plurality of antifuses 1110 contained in the antifuse assembly 1100. The number of registers contained in the first register unit 1400 can also be determined based on the number of columns contained in the antifuse assembly 1100. For example, if the antifuse assembly 1100 has n columns, the first register unit 1400 can have n registers.Otherwise, as described above, if two read amplifier circuits are arranged so that they correspond to each bit line, the first register unit can have 1400 2xn registers.

[0091] The first register unit 1400 receives the fuse data OUT1 to OUTn in units of the rows in the anti-fuse array 1100. For example, when a row is selected from the rows of the anti-fuse array 1100, fuse data OUT1 to OUTn, which are stored in anti-fuses 1110 connected to a word line of the selected row, are allocated in parallel to the first register unit 1400. The first register unit 1400 provides the fuse data OUT1 to OUTn to the second register unit 150 by shifting the allocated fuse data OUT1 to OUTn in units of bits. The second register unit 1500 can be implemented as a shift register in which a plurality of registers are connected in series to deliver a signal sequentially.The number of registers contained in the second register unit 1500 can be equal to the number of antifuses 1110 contained in the antifuse arrangement 1100. Fuse data OUT1 to OUTn, stored in the second register unit 1500, can be used to configure the operating environment of the non-volatile memory device 1000. For example, some of the fuse data OUT1 to OUTn stored in the second register unit 1500 can be used as Info_FA information to replace a memory cell (not shown) contained in the non-volatile memory device 1000 with a redundant memory cell, and some of the fuse data OUT1 to OUTn can be used as trimming information Info_DC to adjust a voltage generated in the non-volatile memory device 1000.

[0092] To store the fuse data OUT1 to OUTn from the anti-fuse arrangement 1100, registers connected to the read amplifier 1300 for temporary storage of the fuse data OUT1 to OUTn, and registers located adjacent to various circuit blocks of the non-volatile storage device 1000 that use the fuse data OUT1 to OUTn, such as a row and column decoder or a DC voltage generator, are required to provide fuse data OUT1 to OUTn for the circuit blocks.

[0093] In accordance with exemplary embodiments of the inventive concept, the first register unit 1400 receives the fuse data OUT1 to OUTn from the read amplifier 1300 and transmits the fuse data OUT1 to OUTn to the second register unit 1500, which is arranged adjacent to these circuit blocks. In particular, the anti-fuse arrangement 1100 has the arrangement structure, and the first register unit 1400 has registers whose number corresponds to the number of columns contained in the anti-fuse arrangement 1100. Accordingly, the number of registers contained in the first register unit 1400 is less than the number of anti-fuses 1100 contained in the anti-fuse arrangement 1100. For example, if a read amplifier circuit is arranged such that it corresponds to each bit line, the first register unit 1400 has n read amplifier circuits.Therefore, the number of registers in the first register unit 1400, which relates to the fuse data OUT1 to OUTn, need not be mxn and can therefore be n. In particular, even if a large number of antifuses 1110 are contained in the antifuse arrangement 1100, the number of registers contained in the first register unit 1400 can be limited to n, according to the structure of the antifuse arrangement 1100. Consequently, it can be prevented that the number of registers contained in the first register unit 1400 increases proportionally.

[0094] Fig. Figure 9 illustrates a structure of a module 2200 in accordance with an embodiment of the inventive concept.

[0095] Referring to Fig. 9. Module 2200 includes a memory which comprises a storage device in accordance with an exemplary embodiment of the inventive concept. For example, Module 2200 includes eight DRAMs. Each DRAM includes an anti-fuse arrangement, which is a non-volatile storage device. When an error address is stored in DRAM5, a memory controller can select DRAM5 by transferring data "0" to only DRAM5. The anti-fuse arrangement contained in each of the DRAMs is used to store a generated error address in the DRAM. An instruction and an address are shared among the eight DRAMs.

[0096] The Fig. 10 and Fig. 11 are timing diagrams or time sequence diagrams which illustrate a time sequence or timing in accordance with embodiments of the inventive concept when an error address is transmitted.

[0097] Referring to Fig. 10. A mode setting register command MRS, an activation command ACT, a read command RD, and a write command WR are received via a command line CMD. A row error address F-RA and a column error address F-CA are received via an address line ADD. In module 2200 of the Fig. 9. DRAM5 can be selected among the eight DRAMs by receiving only data "0" (logical low) via a data pin DQ. Since data received via data pins DQ0 to DQ7 is all logically "low", an error address is stored in the anti-fuse arrangement, a non-volatile memory device contained within DRAM5. After the mode register setting instruction MRS, the enable instruction ACT, and the write instruction WR are sequentially supplied, and the row error address F-RA and column error address F-CA are supplied, data "0" is provided as the final chip selection data via data pin DQ, and the error address is stored in the anti-fuse arrangement. This section is an error address transmission section.A section between when the programmed error address is read according to the RD read instruction and when another mode register setting instruction (MRS) is received is a verification section. A verification operation is completed when the other mode register setting instruction (MRS) is fed after the read instruction has been received.

[0098] The time sequence diagram of the Fig. 11 is similar to the time sequence diagram of the Fig. 10, except that a memory cell corresponding to an error address is repaired by receiving only one row error address F-FA via an address line ADD. Likewise, if a verification operation is performed to reread the error address, the verification operation is completed according to a pre-charge command, and the current mode is exited.

[0099] Fig. Figure 12 is a time sequence diagram illustrating a time progression when verification results are transferred in parallel in accordance with an exemplary embodiment of the inventive concept.

[0100] Referring to Fig. When a mode register setting instruction MRS, an activation instruction ACT, and a write instruction WR are supplied via a command line CMD, a row error address F-RA and a column error address F-CA are stored in an anti-fuse arrangement, which is a non-volatile memory device. The states of the stored row error address F-RA and column error address F-CA are then checked by reading them, and the resulting verification results are transmitted to the test device 100 via data pins DQ0, DQ1, and DQ2. For example, verification results that are logic low ("L") are transmitted in parallel via data pins DQ0, DQ1, and DQ2. Values ​​transmitted to the other data pins DQ3, ..., DQ7 are not recognized by a memory controller.

[0101] Fig. Figure 13 is a table illustrating which verification results are to be transferred in parallel, according to an exemplary embodiment of the inventive concept.

[0102] Referring to Fig. 13. The states of the verification results can be checked by reading the verification results, which are stored in an anti-fuse arrangement, a non-volatile memory. If the verification results transmitted via data pins DQ0, DQ1, and DQ2 are all logically low (Case 1), this means that programming has completed normally and an error bit has been replaced by row-redundant cells. If the verification results transmitted via data pins DQ0, DQ1, and DQ2 are logically low, low, and high respectively (Case 2), this means that programming has completed normally and an error bit has been replaced by column-redundant cells. If the verification results transmitted via data pins DQ0, DQ1, and DQ2 are logically low, high, and low respectively (Case 3), this means that programming has completed normally and an error bit has been replaced by a single redundant cell.If the verification results transmitted via data pins DQ0, DQ1, and DQ2 are logically low, high, and high respectively (Case 4), this means that there is no particular significance for future use. Cases 5 through 8 each indicate that programming has been incomplete. If the verification results transmitted via data pins DQ0, DQ1, and DQ2 are logically high, low, and low respectively (Case 5), this means that a termination process being performed on a memory cell has encountered a problem. If the verification results transmitted via data pins DQ0, DQ1, and DQ2 are logically high, low, and high respectively (Case 6), this means that the termination process is still in progress. In this case, verification may be temporarily delayed and then requested again using a read command (RD).If the verification results transmitted via data pins DQ0, DQ1, and DQ2 are logically high, high, and low respectively (Case 7), this means that no redundant memory cell is available. Therefore, an error bit cannot be repaired and should be replaced by another memory cell. If the verification results transmitted via data pins DQ0, DQ1, and DQ2 are all logically high (Case 8), this means that no current chip is selected. The verification results are transmitted in parallel to test device 100 via data pins DQ0, DQ1, and DQ2.

[0103] Fig. Figure 14 is a time sequence diagram illustrating a time progression when verification results are transferred in accordance with an exemplary embodiment of the inventive concept.

[0104] Referring to Fig. 14. The verification results, which are in Fig. Figure 13 illustrates how data is transmitted serially. For example, a 3-bit verification result is transmitted serially via a data pin DQ0. The same 3-bit verification result can be transmitted to test device 100 via a data pin DQ7.

[0105] Fig. Figure 15 is a table illustrating verification results that are to be transferred serially in accordance with an exemplary embodiment of the inventive concept.

[0106] Referring to Fig. Case 1 (LLL) is defined as follows: an error bit is replaced by row-redundant cells. For example, a 3-bit verification result is transmitted serially to test device 100 via data pin DQ. Case 6 (HLH) indicates that a termination process is still in progress, during which a 3-bit verification result is transmitted serially to test device 100 via data pins DQ0, DQ1, DQ2, and DQ3.

[0107] The Fig. 16 and Fig. Figure 17 are time sequence diagrams illustrating a method for operating a test apparatus according to an exemplary embodiment of the inventive concept.

[0108] Referring to Fig. 16. A test device performs fault address acquisition and transmission as described below. First, a fault address is acquired using an ECC machine or BIST unit (Operation S100). Then, the acquired fault address is stored in a Fail Address Memory (FAM) (Operation S105). Next, a fault address transmission mode is entered according to a test instruction issued by a CPU (Operation S110). The test instruction includes a test start instruction, a test end instruction, an instruction to start the transmission of the fault address, and an instruction to stop the transmission of the fault address. Then, a mode register setting instruction, a chip select signal, and the fault address are transmitted (Operation S120).

[0109] Referring to Fig. 17. A memory device receives the mode register setting instruction, a write instruction, the chip selection signal, and the error address (Operation S130). The error address is then stored in a temporary error address memory (Operation S140). Next, the device enters a programming mode for a non-volatile memory device (Operation S150). Then, a memory location of an anti-fuse arrangement, which is a non-volatile memory device, is checked (Operation S160) (Add OK?). The anti-fuse arrangement, which is a non-volatile memory device, is then programmed (Operation S170). The programmed data is then read to verify the stored error address (Operation S180). The state of the stored data is then checked, and a verification result is transmitted externally (Operation S190). Finally, the error bit is replaced by another memory cell (Operation S200).

[0110] Fig. Figure 18 is a conceptual representation of a storage system in accordance with another exemplary embodiment of the inventive concept.

[0111] Referring to Fig. The storage system comprises a test device 100 and a storage device 200. The test device 100 transmits an error address Addr, a control signal, and data DQ. The storage device 200 comprises a BIST unit and an anti-fuse arrangement, which is a non-volatile memory. The BIST unit tests the storage device 200 according to a test command received from the test device 100 and stores the error address in the anti-fuse arrangement, which is a non-volatile memory.

[0112] Fig. Figure 19 illustrates a circuit block of a storage device 300 in accordance with another exemplary embodiment of the inventive concept.

[0113] Referring to Fig. 19 The storage device 300 comprises a fuse assembly 340, which is a non-volatile memory designed to store a fault address as program data, a temporary fault address memory (FAM) 330, a fuse assembly information memory 350 configured to store information about a fuse, a control unit 360 configured to control the fuse assembly 340 and the fuse assembly information memory 350, a BIST unit 310 configured to detect a fault address, and a memory cell assembly 320. The BIST unit 310 receives a test command Control and test data DQ from a test device and detects a fault address by writing the test data DQ to the memory cell assembly 320 and then reading the test data DQ from the memory cell assembly 320.When an error bit occurs, an error flag and an error address corresponding to the error bit are transferred to FAM 330. FAM 330 can be implemented as a register containing multiple error address arrangements FAM 1,... FAMn. The control unit 360 can check a space or location of the fuse arrangement 340 using the fuse arrangement information memory 350. The control unit 360 can also control a programming instruction and a programming address to be stored in the fuse arrangement 340, which is a non-volatile memory device. The test instruction is provided to the test device according to the control signal, and the BIST unit 310 is activated accordingly. Likewise, the error address stored in FAM 330 is transferred to the fuse arrangement 340 according to the control signal.

[0114] The Fig. 20 and Fig. Figure 21 are time sequence diagrams illustrating the operation of a storage device in accordance with exemplary embodiments of the inventive concept.

[0115] Referring to Fig. 20. An activation command ACT and a read command RD are supplied via a command line CMD. Test data EDQ is supplied via a data pin DQ. The test data EDQ is written to a memory cell array, and read data RDQ is generated by reading the test data EDQ, which is stored in the memory cell array, according to the read command RD. If an error flag signal changes from a logical high to a logical low, an Nth line address is written to an error address memory FAM #1. If the error flag occurs again, an (N+1)th line address is written to an error address memory FAM #2. Such a command and data are supplied in synchronization with a clock signal CLK, and a clock activation signal CKE and a chip selection signal are also supplied in synchronization with the clock signal CLK.

[0116] Referring to Fig. 21. An activation command ACT, a read command RD, and a pre-charge command Pre are fed via a command line CMD. The timing diagram of the Fig. 21 is essentially similar to that of the Fig. 20 except that an Nth line address is transferred to an error address memory FAM #1 when the preload instruction Pre is supplied, and an (N+1)th line address is transferred to an error address memory #2 when the preload instruction Pre is supplied again. The FAM 330 of the Fig. 19 can be implemented as a register, an SRAM, or the like.

[0117] Fig. Figure 22 is a flowchart illustrating a method for operating a storage device according to an exemplary embodiment of the inventive concept.

[0118] Referring to Fig. 22. The storage device receives an activate command, a write command, and a read command from a test device (Operation S300). Then, a BIST unit of the storage device is activated according to a command (Operation S310). Then, an error address is detected, an error flag is generated, or a preload command is received (Operation S320). Then, the error address is stored in an error address memory according to the error flag of the preload command (Operation S330). Then, a fuse assembly enters a programming mode to program the error address (Operation S340). Then, the capacity of a fuse memory is checked (Operation S350). Then, the fuse assembly is programmed (Operation S360). After that, an error bit is repaired (Operation S370).

[0119] Fig. Figure 23 is a representation illustrating optical connections of a storage system in accordance with an exemplary embodiment of the inventive concept.

[0120] Referring to Fig. Figure 23 of the memory system comprises a controller 8100 and a memory device 8200. The controller 8100 comprises a control unit 8110, a controller transmitter 8121, and a controller receiver 8122. The control unit 8110 comprises an ECC machine or a BIST unit. The controller transmitter 8121 comprises an I / O device that converts an electrical signal into an optical signal. The controller receiver 8122 comprises an O / E device that converts an optical signal into an electrical signal. The memory device 8200 comprises an anti-fuse assembly 8221, which is a non-volatile memory device, a BIST unit 8222, a DRAM core 8223, a transmitter 8312, and a receiver 8211. Transmitter 8312 has an E / O device which converts an electrical signal into an optical signal. Receiver 8211 has an O / E device which converts an optical signal into an electrical signal.The controller 8100 and the storage device 8200 are connected via an optical link 0 8500 and an optical link 1 8501 to transmit and receive data. In accordance with another exemplary embodiment of the inventive concept, data can be transmitted and received via an optical link. An I / O circuit 8120 of the controller 8100 and an I / O circuit 8210 of the storage device 8200 are connected via optical link 0 8500 and optical link 1 8501.

[0121] Fig. Figure 24 shows stacked or layered chips with silicon through-silicon vias (TSV = Through-Silicon-Via) to which a memory system is applied in accordance with an exemplary embodiment of the inventive concept.

[0122] Referring to Fig. 24 is an interface chip 3100 arranged as a bottom layer, and memory chips 3200, 3300, 3400, and 3500 are arranged sequentially on the interface chip 3100. The interface chip 3100 may include an ECC machine or a BIST unit, a memory controller, and a CPU. The memory chips 3200, 3300, 3400, and 3500 have anti-fuse assemblies 3601, 3602, 3603, and 3604, which are non-volatile memory devices, and BIST units 3801, 3802, 3803, and 3804. A fault address of a memory chip is detected using a test device (not shown) of the interface chip 3100 and is stored in an anti-fuse assembly of the memory chip. These chips are connected via microbumps, uBumps, and TSVs formed within them (3701, 3702, 3703, and 3704). For example, the number of layered chip(s) can be one or more.

[0123] Fig. Figure 25 illustrates various interfaces of a storage system in accordance with an exemplary embodiment of the inventive concept.

[0124] Referring to Fig. 25(a) A storage system comprises a controller 4000 and a storage device 5000. The controller 4000 comprises a control unit 4100 and an I / O circuit 4200. The control unit 4100 may be an ECC machine or a BIST unit. The storage device 5000 comprises a DRAM core 5300, an anti-fuse assembly 5100 (which is a non-volatile storage device), a BIST unit 5400, and an I / O circuit 5200. The I / O circuit 4200 of the controller 4000 has an interface through which an instruction, a control signal, an address, and a data strobe DQS are transmitted to the storage device 5000, and data DQs are transmitted to and received from the storage device 5000. An error address is transmitted via the interface.

[0125] Referring to Fig. 25 (b) An I / O circuit 4200 of a controller 4000 has an interface through which a chip selection signal CS and an address are transmitted to a storage device 5000 using a packet, and data DQ are transmitted to and received from the storage device 5000. An error address is transmitted through the interface.

[0126] Referring to Fig. 25 (c) An I / O circuit 4200 of a controller 4000 has an interface via which a chip selection signal CS, an address and write data wData to a storage device 5000 are transmitted using a packet and read data rData is received from the storage device 5000. An error address is transmitted via the interface.

[0127] Referring to Fig. 25 (d) An I / O circuit 4200 of a controller 4000 has an interface through which a command, an address and data DQ are transmitted to and received from a storage device 5000, and a chip selection signal CS is received from the storage device 5000. An error address is transmitted through the interface.

[0128] The Fig. 26 and Fig. Figure 27 are illustrations that demonstrate system connections of a storage system in accordance with exemplary embodiments of the inventive concept.

[0129] Referring to Fig. 26 are a memory 7300, which has an anti-fuse arrangement 7301, which is a non-volatile memory, and a BIST unit 7302, a CPU 7100, which has a BIST unit or an ECC machine 7101, and a user interface 7200 connected via a system bus 7110.

[0130] Referring to Fig. 27 are a storage system 6500, which includes a memory 6520, which has an anti-fuse arrangement and a BIST unit, and a storage controller 6510, which has a BIST or ECC machine; a CPU 6100, a read / write memory (RAM = Random Access Memory) 6200, a user interface 6300 and a modem 6400 connected via a system bus 6110.

[0131] A memory test device, a method, and a system according to an exemplary embodiment of the inventive concept can detect a fault address of a fault memory cell contained in a memory device and repair the fault memory cell. Even during chip operation or after chip packaging, a memory device can be tested and repaired using a test device. Consequently, malfunctions of the memory device due to a fault cell can be reduced, thereby improving the operational reliability of the memory device.

Claims

[1] Storage system comprising the following: a storage device (200, 300, 5000, 8200) comprising a non-volatile storage device (340, 1000, 3601-3604, 5100, 7301, 8221) having a matrix arrangement structure of at least NxM, where N and M are integers equal to or greater than 2; and a test device (100) which is configured to test the storage device (200, 300, 5000, 8200), wherein an error address, which is detected by the test device (100), is transferred to the storage device (200, 300, 5000, 8200) and stored in the non-volatile storage device (340, 1000, 3601-3604, 5100, 7301, 8221), the test device includes a semiconductor chip, wherein the semiconductor chip has an error correction code, ECC, machine or a built-in self-test, BIST, unit and an error address memory (110, 260) configured to the error address, wherein the error address memory (110, 260) is controlled by a control unit (130, 270, 360, 4100, 8110), wherein the control unit (130, 270, 360, 4100, 8110) is configured to check or control the fault address to be stored in the fault address memory (110, 260) and transmitted according to a test command. [2] Storage system according to claim 1, wherein the semiconductor chip comprises the error correction code (ECC) machine, and the non-volatile storage device (340, 1000, 3601-3604, 5100, 7301, 8221) has an anti-fuse arrangement (280, 1100, 3601-3604, 5100, 8221) which has a matrix arrangement structure of at least NxM, where N and M are integers equal to or greater than 2. [3] Storage system according to claim 1, wherein the semiconductor chip has the built-in self-test, BIST, unit, and the non-volatile storage device (340, 1000, 3601-3604, 5100, 7301, 8221) has an anti-fuse arrangement (280, 1100, 3601-3604, 5100, 8221) which has a matrix arrangement structure of at least NxM, where N and M are integers equal to or greater than 2. [4] Storage system according to claim 3, wherein the BIST unit is connected to the ECC machine. [5] Storage system according to claim 1, wherein the semiconductor chip comprises an address output unit (140), a control output unit (150), a data buffer (230) and the control unit (130, 270, 360, 4100, 8110). [6] Storage system according to claim 5, wherein the control output unit controls the operation of the ECC machine or the BIST unit, the fault address memory (110, 260), the data buffer (230) and the control unit (130, 270, 360, 4100, 8110). [7] Storage system according to claim 1, wherein the semiconductor chip is contained in a storage controller and is connected to a central processing unit, CPU. [8] Storage system according to claim 7, wherein the CPU provides the test instruction for the storage device (200, 300, 5000, 8200). [9] Storage system according to claim 8, wherein the test instruction comprises a test start instruction, a test end instruction or an error address transfer instruction. [10] Storage system according to claim 1, wherein the test device (100) is included in a test set. [11] Storage system according to claim 10, wherein the test equipment comprises a sample generator (1210), a test card (1220) and a socket (1230). [12] Storage system according to claim 1, wherein the non-volatile storage device (340, 1000, 3601-3604, 5100, 7301, 8221) has an anti-fuse arrangement (280, 1100, 3601-3604, 5100, 8221) which has a matrix arrangement structure of at least NxM, where N and M each denote an integer equal to or greater than 2. [13] Storage system according to claim 12, further comprising a preliminary fault address memory (110, 260) which is configured to store the fault address. [14] Storage system according to claim 13, wherein the fault address is stored in the anti-fuse arrangement (280, 1100, 3601-3604, 5100, 8221) under the control of the control unit (130, 270, 360, 4100, 8110). [15] Storage system according to claim 14, wherein the control unit (130, 270, 360, 4100, 8110) is activated in response to a mode activation signal received from a decoding unit (240). [16] Storage system according to claim 14, wherein the control unit (130, 270, 360, 4100, 8110) controls or verifies the fault address to be written to or read from the anti-fuse arrangement (280, 1100, 3601-3604, 5100, 8221) and a verification result to be transmitted outside the storage device (200, 300, 5000, 8200). [17] Storage system according to claim 13, wherein the anti-fuse arrangement (280, 1100, 3601-3604, 5100, 8221) is connected to a repair address memory (250) which is configured to store the fault address, wherein the repair address memory (250) is connected to a comparator unit (251) which is configured to compare the fault address with an external address, wherein the comparator (251) is connected to a multiplexer (252) which is configured to select one of the fault address and the external address. [18] Storage device comprising the following: a temporary fault address memory (260) for temporarily storing the fault address; a non-volatile storage device (340, 1000, 3601-3604, 5100, 7301, 8221) having a matrix arrangement structure of at least NxM to store the error address, where N and M are each an integer equal to or greater than 2; and a control unit (130, 270, 360, 4100, 8110) which is configured to control a transfer of the fault address which is stored in the temporary fault address memory (260) to the non-volatile storage device (340, 1000, 3601-3604, 5100, 7301, 8221), wherein the non-volatile storage device (340, 1000, 3601-3604, 5100, 7301, 8221) has an anti-fuse arrangement (280, 1100, 3601-3604, 5100, 8221), and wherein, in order to determine whether the error address is written correctly, the control unit (130, 270, 360, 4100, 8110) controls or verifies the error address to be read from the anti-fuse arrangement (280, 1100, 3601-3604, 5100, 8221) and a verification result to be transmitted outside the storage device (200, 300, 5000, 8200). [19] Storage device according to claim 18, wherein the control unit (130, 270, 360, 4100, 8110) controls or checks the anti-fuse arrangement (280, 1100, 3601-3604, 5100, 8221) to be sampled or programmed. [20] Storage device according to claim 18, wherein the anti-fuse arrangement (280, 1100, 3601-3604, 5100, 8221) is connected to a repair address memory (250) which is configured to store the fault address, wherein the repair address memory (250) is connected to a comparator unit (251) which is configured to compare the fault address with an external address, and wherein the comparator (251) is connected to a multiplexer (252) which is configured to select one of the fault address and the external address. [21] Storage device according to claim 18, wherein the temporary error address memory (260) is connected to an address buffer (210) which is configured to receive an external address. [22] Storage device according to claim 18, wherein the control unit (130, 270, 360, 4100, 8110) is activated according to a mode activation signal generated by a decoding unit (240). [23] Storage device according to claim 19, wherein the decoding unit (240) is connected to the address buffer (210) and a control buffer (220) which is configured to receive a control signal. [24] Test apparatus comprising the following: an error correction code (ECC) circuit configured to detect and correct an error bit; an error address memory (110, 260) configured to store an error address of the error bit; and a control unit (130, 270, 360, 4100, 8110) which is configured to check or control the error address to be stored in the error address memory (110, 260) and transmitted externally according to a test command. [25] Test apparatus according to claim 24, wherein the ECC circuit is connected to a data buffer (230) which is configured to receive the error bit. [26] Test device according to claim 24, wherein the test instruction comprises a test start instruction, a test end instruction or an error address transfer instruction. [27] Test apparatus according to claim 24, wherein the ECC circuit has a built-in self-test, BIST, unit. [28] Test device according to claim 24, wherein the test device (100) is contained in a memory controller and is connected to a central processing unit, CPU. [29] Test apparatus according to claim 24, wherein the test apparatus (100) is included in a test set. [30] Test apparatus according to claim 29, wherein the test equipment further comprises a sample generator (1210), a test card (1220) and a base (1230). [31] Method for operating a test device (100) to transmit a fault address, the method comprising: a detection of the error address using an error correction code (ECC) circuit; storing the error address in an error address memory (110, 260); an entry into an error address transmission mode according to a test command; a transmission of a transmission signal which includes a mode register setting instruction; and a transfer of the error address. [32] Method according to claim 31, wherein the fault address is detected by an ECC machine or a built-in self-test, BIST, unit. [33] Method according to claim 31, wherein the transmission signal further comprises a write command and a chip selection signal. [34] Method according to claim 31, wherein the test instruction comprises an instruction which commands to start a transmission of the error address or an instruction which commands to stop the transmission of the error address, and which is given by a central processing unit, CPU. [35] Method for operating a storage device to write an error address to the storage device (200, 300, 5000, 8200), the method comprising: a receiving of the error address according to a mode register setting command; storing the error address in a temporary error address memory (110, 260); and a storage of the error address in a non-volatile memory device (340, 1000, 3601-3604, 5100, 7301, 8221) which has a matrix arrangement structure of at least NxM, where N and M each denote an integer equal to or greater than 2. [36] Method according to claim 35, further comprising checking a memory location of the non-volatile memory device (340, 1000, 3601-3604, 5100, 7301, 8221) before the fault address is stored in the non-volatile memory device (340, 1000, 3601-3604, 5100, 7301, 8221). [37] Method according to claim 35, further comprising reading the stored fault address after the fault address is stored in the non-volatile storage device (340, 1000, 3601-3604, 5100, 7301, 8221). [38] Method according to claim 37, further comprising transmitting a verification result indicating a state of the read error address to the outside in series or in parallel after the stored error address has been read. [39] Method for operating a test device (100) to transfer a fault address to a storage device (200, 300, 5000, 8200), the method comprising: a detection of the error address by an error correction code, ECC, circuit; storing the error address in an error address memory (110, 260); an entry into an error address transmission mode according to a test command; a transmission of a transmission signal which includes a mode register setting instruction; a transfer of the error address; a reception of the error address according to the mode register setting signal; a storage of the error address in a temporary error address memory (260); and a storage of the error address in a non-volatile memory device (340, 1000, 3601-3604, 5100, 7301, 8221) which has a matrix arrangement structure of at least NxM, where N and M each denote an integer equal to or greater than 2. [40] Method according to claim 39, further comprising checking a memory location of the non-volatile memory device (340, 1000, 3601-3604, 5100, 7301, 8221) before the fault address is stored in the non-volatile memory device (340, 1000, 3601-3604, 5100, 7301, 8221). [41] Storage system comprising the following: a test device (100) which is configured to provide test data for a storage device (200, 300, 5000, 8200); wherein the storage device (200, 300, 5000, 8200) has the following: a built-in self-test (BIST) unit configured to test the storage device (200, 300, 5000, 8200); and a non-volatile storage device (340, 1000, 3601-3604, 5100, 7301, 8221) which has a matrix arrangement structure of at least NxM, where N and M each denote an integer equal to or greater than 2, wherein an error address, which is generated by testing the storage device (200, 300, 5000, 8200) by the BIST unit, is stored in the non-volatile storage device (340, 1000, 3601-3604, 5100, 7301, 8221), wherein the non-volatile storage device (340, 1000, 3601-3604, 5100, 7301, 8221) comprises an anti-fuse arrangement (280, 1100, 3601-3604, 5100, 8221) having a matrix arrangement structure of at least NxM, where N and M are integers equal to or greater than 2, and wherein the storage device (200, 300, 5000, 8200) further comprises at least two fault address register arrangements configured to temporarily store the fault address. [42] Storage system according to claim 41, wherein the BIST unit transfers the error address to the at least two error address memory registers according to an error flag. [43] Storage system according to claim 42, wherein the fault generation flag can be replaced by a preload command. [44] Storage system according to claim 1, wherein the test device (100) is configured to be connected to the storage device (200, 300, 5000, 8200) by silicon vias, TSVs, or microbumps. [45] Storage system according to claim 1, wherein the test device (100) is configured to be connected to the storage device (200, 300, 5000, 8200) by optical links.

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