ARRAY SUBSTRATE AND DISPLAY DEVICE

Abstract

An array substrate and a display device are provided. In the array substrate, each of the first shift register units and each of the second shift register units is electrically connected to a scanning line. Scanning lines electrically connected to the first shift register units on the same stage or to the second shift register units on the same stage are arranged in the same row. Clock signal input terminals of the first shift register units on the same stage or the second shift register units on the same stage receive the same clock signal. Enable signal input terminals of the first shift register units on the first stage or the second shift register units on the first stage receive the same enable signal, wherein an anti-false shutdown signal can remove a charge on a scanning line (101) after a display is abnormally turned off.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to display techniques, and more particularly to an array substrate and a display device. BACKGROUND

[0002] Due to the continuous development of electronic technology, a screen has become widely used as one of the interfaces for interactions between a user and an electronic device.

[0003] A display panel, a core component of the display screen in the prior art, comprises a display area and a non-display area surrounding the display area. The display area is usually shaped as a regular rectangle and equipped with a plurality of parallel scan lines. In an extending direction of the plurality of scan lines, non-display areas on two sides of the display area may both be equipped with a scan control circuit having cascade-connected shift register units. Each shift register unit is electrically connected to a corresponding scan line and supplies a scan control signal to the corresponding scan line. However, in a specially shaped display screen, namely a display screen with at least one notch along one edge extending parallel to the scan lines, each scan line is divided into a plurality of segments by the at least one notch.In this case, if the scanning control circuit is nevertheless configured in the original manner, parts of the scanning lines are not electrically connected to the shift register units. As a result, no scanning control signal is received, and the screen does not display properly. US 2016 / 0 111 040 A1 discloses a display device with a reduced edge area, wherein the display device comprises a cutout area on which an electronic component is to be placed and a display panel for displaying an image. SUMMARY

[0004] The present disclosure provides an array substrate according to claim 1 and a display device according to claim 11 for obtaining the normal display of a screen having a particular shape.

[0005] According to a first aspect, an embodiment of the present disclosure provides an array substrate. The array substrate has a display region and a non-display region surrounding the display region. The display region has a plurality of scanning lines extending in a first direction.

[0006] The array substrate has at least one notch arranged on an edge of the array substrate extending in the first direction.

[0007] The non-display region forms a first non-display region and a second non-display region on two opposite sides of the display region in the first direction. The non-display region adjacent to a first side of each notch forms a third non-display region, the non-display region adjacent to a second side of each notch forms a fourth non-display region, and the first side of each notch is closer to the first non-display region than the second side of each notch. The first non-display region and the fourth non-display region are provided with cascade-connected first shift register units therein. The second non-display region and the third non-display region are provided with cascade-connected second shift register units therein. Each of the first shift register units and the second shift register units is electrically connected to one of the plurality of scanning lines, respectively.The scanning lines electrically connected to the first shift register units on the same stage are in the same row, and the scanning lines electrically connected to the second shift register units on the same stage are in the same row.

[0008] The same clock signal is input to the clock signal input terminals of the first shift register units on the same stage, and the same clock signal is input to the clock signal input terminals of the second shift register units on the same stage. The same enable signal is input to the enable signal input terminals of the first shift register units on the same stage, and the same enable signal is input to the enable signal input terminals of the second shift register units on the same stage.

[0009] According to a second aspect, an embodiment of the present disclosure provides a display device. The display device comprises the array substrate described in the first aspect.

[0010] The array substrate provided by embodiments of the present disclosure includes the display region and the non-display region surrounding the display region. The display region includes the plurality of scanning lines extending in the first direction. The array substrate includes at least one notch disposed on the edge of the array substrate extending in the first direction. The non-display region forms the first non-display region and the second non-display region on two opposite sides of the display region in the first direction. The non-display region adjacent to a first side of each notch forms a third non-display region, the non-display region adjacent to a second side of each notch forms a fourth non-display region, and the first side of each notch is closer to the first non-display region than the second side of each notch.The first non-display region and the fourth non-display region are provided with cascade-connected first shift register units therein. The second non-display region and the third non-display region are provided with cascade-connected second shift register units therein. Each of the first shift register units and the second shift register units is electrically connected to one of the plurality of scanning lines, respectively. The scanning lines electrically connected to the first shift register units on the same stage are in the same row, and the scanning lines electrically connected to the second shift register units on the same stage are in the same row.The same clock signal is input to the clock signal input terminals of the first shift register units on the same stage, and the same clock signal is input to the clock signal input terminals of the second shift register units on the same stage. The same enable signal is input to the enable signal input terminals of the first shift register units on the same stage, and the same enable signal is input to the enable signal input terminals of the second shift register units on the same stage. With such a configuration, the scanning lines can each receive the corresponding scanning control signal, thereby achieving normal display of a specially shaped screen. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Further features, objects and advantages of the present disclosure will become more apparent from a detailed description of non-limiting embodiments with reference to the following drawings: Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure; Fig. 2 is an enlarged partial view corresponding to a rectangular dashed field of Fig. 1 corresponds; Fig. 3 is a further enlarged partial view corresponding to a rectangular dashed field of Fig. 1 corresponds; Fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure; Fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure; and Fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] In order to further describe the technical solutions and effects of the present disclosure for achieving the intended use, specific embodiments, structures, features and effects of a display panel and a method of manufacturing the same provided according to the present disclosure will be described below with reference to the accompanying drawings and preferred embodiments.

[0013] One embodiment of the present disclosure provides an array substrate. The array substrate includes a display region and a non-display region surrounding the display region. The display region includes a plurality of scan lines extending in a first direction.

[0014] The array substrate has at least one notch arranged on an edge of the array substrate extending in the first direction.

[0015] The non-display region forms a first non-display region and a second non-display region on two opposite sides of the display region in the first direction. The non-display region adjacent to a first side of each notch forms a third non-display region, the non-display region adjacent to a second side of each notch forms a fourth non-display region, and the first side of each notch is closer to the first non-display region than the second side of each notch is to the first non-display region. The first non-display region and the fourth non-display region are provided with cascade-connected first shift register units therein. The second non-display region and the third non-display region are provided with cascade-connected second shift register units therein. Each of the first shift register units and the second shift register units is electrically connected to one of the plurality of scan lines, respectively.The scanning lines electrically connected to the first shift register units on the same stage are in the same row, and the scanning lines electrically connected to the second shift register units on the same stage are in the same row.

[0016] The same clock signal is input to the clock signal input terminals of the first shift register units on the same stage, and the same clock signal is input to the clock signal input terminals of the second shift register units on the same stage. The same enable signal is input to the enable signal input terminals of the first shift register units on the same stage, and the same enable signal is input to the enable signal input terminals of the second shift register units on the same stage.

[0017] The array substrate provided by embodiments of the present disclosure includes the display region and the non-display region surrounding the display region. The display region includes the plurality of scanning lines extending in the first direction. The array substrate includes at least one notch disposed on the edge extending in the first direction of the array substrate. The non-display region forms the first non-display region and the second non-display region on two opposite sides of the display region in the first direction. The non-display region adjacent to a first side of each notch forms a third non-display region, the non-display region adjacent to a second side of each notch forms a fourth non-display region, and the first side of each notch is closer to the first non-display region than the second side of each notch.The first non-display region and the fourth non-display region are provided with cascade-connected first shift register units therein. The second non-display region and the third non-display region are provided with cascade-connected second shift register units therein. Each of the first shift register units and the second shift register units is electrically connected to one of the plurality of scanning lines, respectively. The scanning lines electrically connected to the first shift register units on the same stage are in the same row, and the scanning lines electrically connected to the second shift register units on the same stage are in the same row.The same clock signal is input to the clock signal input terminals of the first shift register units on the same stage, and the same clock signal is input to the clock signal input terminals of the second shift register units on the same stage. The same enable signal is input to the enable signal input terminals of the first shift register units on the same stage, and the same enable signal is input to the enable signal input terminals of the second shift register units on the same stage. With such a configuration, the scanning lines can each receive the corresponding scanning control signal, thereby achieving normal display of a specially shaped screen.

[0018] The foregoing is the concept of the present disclosure. The technical solutions in the embodiments of the present disclosure are clearly and comprehensively described together with the accompanying drawings in the embodiments of the present disclosure. It is obvious that only some, and not all, embodiments of the present disclosure are described here. According to embodiments of the present disclosure, all other embodiments obtained without inventive step by those skilled in the art fall within the scope of the present disclosure.

[0019] In the following description, numerous details are set forth to facilitate a thorough understanding of the disclosure; however, the present disclosure may be embodied in other embodiments other than those described herein. Those skilled in the art may make similar generalizations without departing from the spirit of the disclosure. The present disclosure is not limited to the specific embodiments disclosed below.

[0020] The present invention will be further described in detail with reference to the accompanying drawings. In the detailed description of embodiments of the present disclosure, for ease of explanation, the schematic diagrams showing structures of devices and apparatuses are partially enlarged not in accordance with the general proportions. These schematic diagrams are for illustrative purposes only and should not be construed as limiting the scope of the disclosure. In actual manufacturing, three-dimensional dimensions such as length, width, and height are to be taken into account.

[0021] Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure. As in Fig. 1, the array substrate includes a display region 10 and a non-display region 20 surrounding the display region 10. The display region 10 has a plurality of scan lines 101 extending in a first direction X. The array substrate has at least one notch 30. The notch 30 is arranged on an edge of the array substrate extending in the first direction X. In the first direction, the non-display regions 20 on two opposite sides of the display region 20 are a first non-display region 20 / 1 and a second non-display region 20 / 2. The non-display region 20 on a side of each notch 30 closer to the first non-display region 20 / 1 is a third non-display region 20 / 3. The non-display region 20 on a side of each notch 30 closer to the second non-display region 20 / 2 is a fourth non-display region 20 / 4.Cascade-connected first shift register units 201 are arranged in the first non-display area 20 / 1 and the fourth non-display area 20 / 4. Cascade-connected second shift register units 202 are arranged in the second non-display area 20 / 2 and the third non-display area 20 / 3. Each of the first shift register units 201 and the second shift register units 202 is electrically connected to a corresponding scanning line 101. The scanning lines 101 electrically connected to the first shift register units 201 located on the same stage are arranged in the same row, and the scanning lines 101 electrically connected to the second shift register units 202 located on the same stage are arranged in the same row.

[0022] Fig. 2 is an enlarged partial view corresponding to a rectangular dashed field of Fig. 1. As in Fig. 2, each of the first shift register units 201 and the second shift register units 202 has a clock signal input terminal 211. The first shift register units 201 on the first stage and the second shift register units 202 on the first stage also each have an enable signal input terminal. The same clock signal is input to the clock signal input terminals 211 of the first shift register unit 210 on the same stage, and the same clock signal is input to the second shift register unit 220 on the same stage. The same enable signal is input to the enable signal input terminals 212 of the first shift register units 201 on the first stage, and the same enable signal is input to the enable signal input terminals 212 of the second shift register units 202 on the first stage.

[0023] Note that the clock signal input terminals 211 receive the clock signal for synchronizing the operation between the first shift registers 201 and other components in the display, or between the second shift registers 202 and other components in the display. The enable signal input terminals 212 receive the enable signal for triggering the cascade-connected first shift register units 201 or the cascade-connected second shift register units 202 to start operation.It should be noted that during normal operation of the cascaded shift register units, a trigger signal output terminal 214 of the shift register unit at a corresponding stage can sequentially output a forward trigger signal to a forward trigger signal input terminal 213 of the shift register unit at a lower stage, so that the shift register units at the corresponding stages start operating sequentially, and then corresponding scan lines are scanned sequentially. The enable signal input terminal 212 of each shift register unit also serves as its forward trigger signal input terminal 213. However, the enable signal input terminal 212 receives a trigger signal from a control chip 230, not the forward trigger signal output from the shift register unit at a higher stage.

[0024] It should also be noted that for the cascade-connected shift register units, the cascade-connected shift register units can operate well if the shift register unit at the first stage receives the enable signal and the shift register units at the respective stages can receive the corresponding clock signals. In the present embodiment, the clock signal input terminals 211 of the first shift register units 201 at the same stage are configured to receive the same clock signal, and the clock signal input terminals 211 of the second shift register units 202 at the same stage are configured to receive the same clock signal.The enable signal input terminals 212 of the first shift register units 201 on the first stage are configured to receive the same enable signal, and the enable signal input terminals 212 of the second shift register units 202 on the first stage are configured to receive the same enable signal. Due to such configurations, the cascade-connected first shift register units 201 in the first non-display area 20 / 1 and the fourth non-display area 20 / 4 can operate normally, and the cascade-connected second shift register units 202 in the second non-display area 20 / 2 and the third non-display area 20 / 3 can operate normally.On the other hand, it is ensured that the cascade-connected first shift register units 201 in the first non-display area 20 / 1 and in the fourth non-display area 20 / 4 have the same time order and the cascade-connected second shift register units 202 in the second non-display area 20 / 2 and in the third non-display area 20 / 3 have the same time order, thereby maintaining the normal display of the screen.

[0025] It should also be noted that Fig. 1 merely illustrates an example in which the array substrate has a notch 30 and does not represent a limitation on the number and positions of the notches 30. It should be understood that in further implementations of the present embodiment, the number of notches 30 included in the array substrate may be two or more, and the positions of the notches 30 may be appropriately designed by the operator, provided that at least one notch 30 is arranged on an edge of the array substrate extending in the first direction.

[0026] The array substrate provided by the present embodiment includes the display region 10 and the non-display region 20 surrounding the display region 10. The display region 10 has the plurality of scanning lines 101 extending in the first direction X. The array substrate has at least one notch 30 arranged on the edge of the array substrate extending in the first direction X. In the first direction, non-display regions 20 on two opposite sides of the display region 10 form the first non-display region 20 / 1 and the second non-display region 20 / 2. The non-display region 20 on the side of each notch 30 closer to the first non-display region 20 / 1 is the third non-display region 20 / 3. The non-display region 20 on the side of each notch 30 closer to the second non-display region 20 / 2 is the fourth non-display region 20 / 4.Cascade-connected first shift register units 201 are arranged in the first non-display area 20 / 1 and the fourth non-display area 20 / 4. Cascade-connected second shift register units 202 are arranged in the second non-display area 20 / 2 and the third non-display area 20 / 3. Each of the first shift register units 201 and the second shift register units 202 is electrically connected to a scanning line 101. The scanning lines 101 electrically connected to the first shift register units 201 located on the same stage are arranged in the same row, and the scanning lines 101 electrically connected to the second shift register units 202 located on the same stage are arranged in the same row.The same clock signal is input to the clock signal input terminals 211 of the first shift register units 210 on the same stage or the second shift register units 220 on the same stage. The same enable signal is input to the enable signal input terminals 212 of the first shift register units 201 on the first stage or the second shift register units 202 on the first stage. Such a configuration allows each scanning line 101 to receive the corresponding scanning control signal, thereby maintaining the normal display of the specially shaped screen.

[0027] As in Fig. 1, the scanning lines 101 electrically connected to the first shift register units 201 and the scanning lines 101 electrically connected to the second shift register units 202 may be alternately arranged in a second direction Y perpendicular to the first direction X. Such a configuration is similar to the configuration of the cascade-connected shift register units of the conventional scanning control circuit, thereby improving compatibility with the prior art and simplifying the design process compared to other approaches.

[0028] In an embodiment described in Fig. 2, one and the same anti-misfire signal can be input to anti-misfire signal input terminals 215 of the first shift register units 201 electrically connected to scanning lines in the same row, or the second shift register units 202 electrically connected to scanning lines 101 in the same row. With such a configuration, the connection ratio of the anti-misfire signal input terminals 215 increases, and it is ensured that the timing orders of the cascade-connected first shift register units 201 in the first non-display area 20 / 1 and the fourth non-display area 20 / 4 remain the same, and the timing orders of the cascade-connected second shift register units 202 in the second non-display area 20 / 2 and the third non-display area 20 / 3 remain the same.It should be noted that the anti-false shutdown signal input terminal 215 receives the anti-false shutdown signal, and the anti-false shutdown signal can eliminate the charge on the scanning line 101 after the display is abnormally turned off to prevent any remaining charge on the scanning line 101.

[0029] Furthermore, with reference to Fig. 1 and Fig. 2, an inversion trigger signal input terminal 219 of the first shift register unit a at the n-th stage as the last stage in the fourth non-display area 20 / 4 is connected to a secondary signal trigger terminal 216 of the first shift register unit b at the (n+1)-th stage in the first non-display area 20 / 1, and the inversion trigger signal input terminal 219 of the second shift register unit c at the n-th stage as the last stage in the third non-display area 20 / 3 is connected to the secondary signal trigger terminal 216 of the second shift register unit d at the (n+1)-th stage in the second non-display area 20 / 2.One and the same forward scanning signal is input to the forward scanning signal input terminals 217 of the first shift register units 201 electrically connected to the scanning lines 101 in one and the same row or the second shift register units 202 electrically connected to the scanning lines 101 in one and the same row.

[0030] It should be noted that with such a configuration, it is possible to supply a reverse trigger signal output from the secondary signal trigger terminal 216 of the first shift register unit B to the reverse trigger signal input terminal 219 of the first shift register unit A and supply the reverse trigger signal output from the secondary signal trigger terminal 216 of the second shift register unit D to the reverse trigger signal input terminal 219 of the second shift register unit C, thereby achieving the reverse scanning of each scanning line 101.

[0031] It should also be noted that when the forward scanning signal output from the control chip 230 is input to the forward scanning signal input terminal 217 of each first shift register unit 201 and the forward scanning signal input terminal 217 of each second shift register unit 202, the cascade-connected first shift register units 201 and the cascade-connected second shift register units 202 output scanning signals sequentially from top to bottom to the corresponding scanning lines, so that the forward scanning of the screen is obtained.When the reverse scanning signal output from the control chip 230 is input to the reverse scanning signal input terminal 218 of each first shift register unit 201 and the reverse scanning signal input terminal 218 of each second shift register unit 202, the cascade-connected first shift register units 201 and the cascade-connected second shift register units 202 output scanning signals sequentially from bottom to top to the corresponding scanning lines, so that the reverse scanning of the screen is obtained.

[0032] Fig. 3 is an enlarged partial view corresponding to a rectangular dashed field of Fig. 1. Corresponds. As in Fig. 3, the array substrate has a notch 30, a common signal input terminal of the first shift register unit 201 at each stage in the first non-display region 20 / 1 is connected to a corresponding common signal input terminal of the second shift register unit 202 in the third non-display region 20 / 3, which is at the same stage as the first shift register unit 201 at the each stage in the first non-display region 20 / 1, and a common signal input terminal of the second shift register unit 202 at the each stage in the second non-display region 20 / 2 is connected to a corresponding common signal input terminal of the first shift register unit 201 in the fourth non-display region 20 / 4, which is at the same stage as the second shift register unit 202 at the each stage in the second non-display region 20 / 1.The general signal input terminal includes the enable signal input terminal 212, the forward scan signal input terminal 217, the reverse scan signal input terminal 218, and the anti-false shutdown signal input terminal 215.

[0033] Note that the common signal input terminal refers to a signal input terminal that receives the same signal from the first shift register unit and the second shift register unit. To reduce the length of the connection lines, one embodiment may adopt a configuration in which one connection line is connected to the nearest connection line.The common signal input terminal of the first shift register unit 201 at each stage in the first non-display area 20 / 1 is connected to the corresponding common signal input terminal of the second shift register unit 202 in the third non-display area 20 / 3, which is at the same stage as the first shift register unit 201 at each stage in the first non-display area 20 / 1, and the common signal input terminal of the second shift register unit 202 at each stage in the second non-display area 20 / 2 is connected to the corresponding common signal input terminal of the first shift register unit 201 in the fourth non-display area 20 / 4, which is at the same stage as the second shift register unit 202 at the respective stage in the second non-display area 20 / 2.Furthermore, with such a configuration, the amount of connecting conductors between the third non-display area 20 / 3 and the fourth non-display area 20 / 4 can be effectively reduced, and it facilitates the realization of the narrow bezel of the screen.

[0034] In one embodiment, the shape of the notch 30 may include a trapezoid, a rectangle, a triangle, and the like. The present embodiment is not specifically limited to one shape, and operators can appropriately design the shape according to actual needs.

[0035] Fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure. Fig. The array substrate shown in Figure 4 is similar to the one shown in Fig. 1. The difference is that the number of notches 30 formed on the edge of the array substrate extending in the direction X is Fig. 4, is more than one.

[0036] It should be noted that in order to simplify the wiring layout of the array substrate for a clearer illustration of the technical solution Fig. 4 illustrates a connection configuration of the signal input terminals of the first shift register units 201 on the first stage. The connection configurations of signal input terminals of the first shift register units 201 on other stages correspond to the connection configuration of signal input terminals of the first shift register units 201 on the first stage, except for the enable signals specific to the first shift register units 201 on the first stage. The connection configuration of the signal input terminals of the second shift register units 202 on the respective stage corresponds to the connection configuration of the signal input terminals of the first shift register units 201 on the same stage as the second shift register units 202 on the respective stage.

[0037] As in Fig. 4, clock signal input terminals 211 of the first shift register units 201, which are electrically connected to the scanning lines 101 in one and the same row, are sequentially connected via a first connection line 221, which is correspondingly arranged in the non-display area 20. The enable signal input terminals 212 of the first shift register units 201 on the first stage are sequentially connected via a second line 222, which is correspondingly arranged in the non-display area 20. The anti-misfire signal input terminals 215 of the first shift register units 201, which are electrically connected to the scanning lines 101 in one and the same row, are sequentially connected via a third connection line 223, which is correspondingly arranged in the non-display area 20.

[0038] Furthermore, the clock signal input terminals of the second shift register units 202, which are electrically connected to the scanning lines 101 in one and the same row, are sequentially connected in the same manner as those of the first shift register units via another connection line, which is correspondingly arranged in the non-display area 20. Enable signal input terminals of the second shift register units 202 on the first stage are sequentially connected via another second connection line, which is correspondingly arranged in the non-display area 20. The anti-misfire signal input terminals of the second shift register units 202, which are electrically connected to the scanning lines 101 in one and the same row, are sequentially connected via another third connection line 223, which is correspondingly arranged in the non-display area 20 (in Fig. 4 not shown).

[0039] It should be noted that as in Fig. As shown in Figure 4, the signal output terminals of the control chip 230 are electrically connected to corresponding signal input terminals of the first shift register units 201 at the respective stages in the first non-display area 20 / 1 and to corresponding signal input terminals of the second shift register units 202 at the respective stages in the second non-display area 20 / 2. Such a configuration is more compatible with the prior art.

[0040] It should also be noted that in Fig. 4, each first shift register unit 201 only needs to be equipped with a connecting line between the first shift register unit 201 and the adjacent first shift register unit 201 on one and the same level. Likewise, each second shift register unit 202 only needs to be connected with a connecting line between the second shift register unit 202 and the adjacent second shift register unit 202 on one and the same level (in Fig. 4 not shown). In contrast to other configurations of the connecting lines, such a configuration minimizes the number of connecting lines between adjacent first shift register units on the same level and the connecting lines between adjacent second shift register units on the same level, thus simplifying the narrow border of the screen.

[0041] Fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure. Fig. The array substrate shown in Figure 5 is similar to the structure Fig. 4 similar, with the exception that in Fig. 5, the clock signal input terminal 211 of each first shift register unit 201 in the fourth non-display areas 20 / 4 is connected via a respective fourth connecting line 224, which is correspondingly arranged in the non-display area 20, to the clock signal input terminal 211 of the first shift register unit 201 at the same stage in the first non-display area 20 / 1. The enable signal input terminal 212 of each first shift register unit 201 at the first stage in the fourth non-display area 20 / 4 is connected via a respective sixth connecting line 225, which is correspondingly arranged in the non-display area 20, to the enable signal input terminal 212 of the first shift register unit 201 at the first stage in the first non-display area 20 / 1.The anti-mis-shutdown signal input terminal 215 of each first shift register unit 201 in the fourth non-display area 20 / 4 is connected to the anti-mis-shutdown signal input terminal 215 of the first shift register unit 201 on the same stage in the first non-display area 20 / 1 via a respective eighth connecting line 226 arranged accordingly in the non-display area 20.

[0042] It should be noted that in order to simplify the wiring layout of the array substrate for a clearer illustration of the technical solution Fig. 5 illustrates a connection configuration of the signal input terminal of the first shift register units 201 on the first stage. Similar to Fig. 4, the connection configurations of signal input terminals of the first shift register units 201 at other stages correspond to the connection configurations of signal input terminals of the first shift register units 201 at the first stage, except for the enable signals specific to the first shift register units 201 at the first stage. The connection configurations of the signal input terminals of the second shift register units 202 at each stage correspond to the connection configurations of the signal input terminals of the first shift register units 201 at the same stage as the second shift register units 202 at each stage.

[0043] It can be seen that the clock signal input terminal 211 of each second shift register unit 202 in the third non-display area 20 / 3 is connected to the clock signal input terminal 211 of the second shift register unit 202 at the same stage in the second non-display area 20 / 2 via a respective fifth connecting line, which is correspondingly arranged in the non-display area 20. The enable signal input terminal 212 of each second shift register unit 202 at the first stage in the third non-display area 20 / 3 is connected to the enable signal input terminal 212 of the second shift register unit 202 at the first stage in the second non-display area 20 / 2 via a respective seventh connecting line, which is correspondingly arranged in the non-display area 20.The anti-mis-shutdown signal input terminal 215 of each second shift register unit 202 in the third non-display area 20 / 3 is connected to the anti-mis-shutdown signal input terminal 215 of the second shift register unit 202 on the same stage in the second non-display area 20 / 2 via a respective ninth connecting line arranged accordingly in the non-display area 20 (in . Fig. 5 not shown).

[0044] It should also be noted that the connection design from Fig. 5, the numerous signal input terminals of each first shift register unit 201 in the fourth non-display area 20 / 4 are all electrically connected via connecting lines directly to corresponding signal input terminals of the first shift register unit 201 on the same level in the first non-display area 20 / 1. Furthermore, the numerous signal input terminals of each second shift register unit 202 in the third non-display area 20 / 3 are all electrically connected via connecting lines directly to corresponding signal input terminals of the second shift register unit 202 on the same level in the second non-display area 20 / 2 (in Fig. 5 not shown). With such a configuration, the fidelity of the signal can be improved due to the single-line transmission of the signal.

[0045] Furthermore, with reference to Fig. 5, the array substrate further comprises a control chip 230. The control chip 230 may be arranged in the non-display area 20 on one side of the display area 10 in the second direction Y, which is perpendicular to the first direction X. As shown in Fig. 3, the at least one notch 30 may also be arranged on a side of the display area 10 that is farther away from the control chip 230. Since the side of the non-display area 20 where the control chip 230 is located includes a plurality of connection lines for connecting the control chip 230 and conductors in the display area 10, as well as functional conductors such as ground conductors, the at least one notch 30 is arranged on the side opposite the control chip 230 in one embodiment to prevent the above-mentioned connection lines and functional conductors from twisting and easily breaking.

[0046] It should be noted that the connection configuration of the signal terminals of first shift register units 201 on one and the same stage or the second shift register units 202 on one and the same stage in Fig. 4 and Fig. 5, taking the clock signal input terminals 211, the enable signal input terminals 212, and the anti-false shutdown signal input terminals 215 as examples. It should be understood that for a display capable of simultaneously performing forward scanning and reverse scanning of the scanning lines, the connection configurations of the forward scanning signal input terminals and the reverse scanning signal input terminals should be determined taking into account the Fig. 4 and Fig. 5 shown connection design.

[0047] Fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As in Fig. 6, a display device 60 includes an array substrate 61 according to one embodiment of the present disclosure. The display device further includes a counter substrate opposite the array substrate 61. Note that when the display device 60 is a liquid crystal display device, the counter substrate is a color filter substrate. When the display device 60 is an organic light-emitting display device, the counter substrate is a cover plate.

[0048] It should be noted that the foregoing merely illustrates preferred embodiments of the present disclosure and the technical principles employed. Those skilled in the art will understand that the present disclosure is not limited to the particular embodiments described herein, and that numerous changes, adaptations, combinations, and substitutions may be made by those skilled in the art without departing from the scope of the present disclosure. Thus, although the present disclosure has been described in detail with reference to the above embodiments, the present disclosure is not limited to the above embodiments, but may include other equivalent embodiments without departing from the spirit of the invention, the scope of the present disclosure being determined by the appended claims.

Claims

[1] Array substrate comprising: a display area (10) and a non-display area (20) surrounding the display area (10), the display area (10) having a plurality of scanning lines (101) extending in a first direction (X); wherein the array substrate further comprises: at least one notch (30) arranged on an edge of the array substrate extending in the first direction (X), wherein the non-display area (20) has a first non-display area (20 / 1) and a second non-display area (20 / 2) in the first direction on two opposite sides of the display area.forming a second non-display region (20 / 2), wherein the non-display region adjacent to a first side of each notch (30) forms a third non-display region (20 / 3), the non-display region adjacent to a second side of each notch forms a fourth non-display region (20 / 4), and the first side of each notch (30) is closer to the first non-display region (20 / 1) than the second side of each notch (30), wherein the first non-display region (20 / 1) and the fourth non-display region (20 / 4) are provided with cascade-connected first shift register units (201) therein, the second non-display region (20 / 2) and the third non-display region (20 / 3) are provided with cascade-connected second shift register units (202) therein, and each of the first shift register units (201) and the second shift register units (202) is electrically connected to one of the plurality of scanning lines (101), respectively;. wherein, among the plurality of scanning lines (101), scanning lines (101) electrically connected to the first shift register units (201) on one and the same stage are arranged in one and the same row, and scanning lines (101) electrically connected to the second shift register units (202) on one and the same stage are arranged in one and the same row; wherein one and the same clock signal is input to clock signal input terminals (211) of the first shift register units (201) at one and the same stage and one and the same clock signal is input to clock signal input terminals (211) of the second shift register units (202) at one and the same stage; wherein one and the same enable signal is input to enable signal input terminals (212) of the first shift register units (201) at a first stage and one and the same enable signal is input to enable signal input terminals (212) of the second shift register units (202) at a first stage, wherein one and the same anti-misturn-off signal is input to anti-misturn-off signal input terminals (215) of the first shift register units (201) which are electrically connected to scanning lines in one and the same row, and one and the same anti-misturn-off signal is input to anti-misturn-off signal input terminals (215) of the second shift register units (202) which are electrically connected to scanning lines in one and the same row, wherein the anti-false shutdown signal can remove a charge on a scanning line (101) after a display is abnormally turned off, and wherein an anti-misturn-off signal input terminal (215) of each first shift register unit (201) in the fourth non-display area (20 / 4) is connected via a respective eighth connecting line (226) correspondingly arranged in the non-display area to an anti-misturn-off signal input terminal (215) of the first shift register unit (201) on one and the same stage in the first non-display area (20 / 1), and an anti-misturn-off signal input terminal (215) of each second shift register unit (202) in the third non-display area (20 / 3) is connected via a respective ninth connecting line correspondingly arranged in the non-display area to an anti-misturn-off signal input terminal (215) of a second shift register unit (202) on one and the same stage in the second non-display area (20 / 2). [2] The array substrate according to claim 1, wherein scanning lines electrically connected to the first shift register units (201) and scanning lines electrically connected to the second shift register units (202) are alternately arranged in a second direction (Y) perpendicular to the first direction. [3] The array substrate according to claim 1, wherein clock signal input terminals (211) of the first shift register units (201) electrically connected to scanning lines (101) in one and the same row are connected via a first connection line (221) arranged correspondingly in the non-display area (20), and clock signal input terminals (211) of the second shift register units (202) electrically connected to scanning lines (101) in one and the same row are connected via another first connection line (221) arranged correspondingly in the non-display area (20); wherein enable signal input terminals (212) of the first shift register units (201) on the first stage are connected via a second connecting line (222) correspondingly arranged in the non-display area (20), and enable signal input terminals (212) of the second shift register units (202) on the first stage are connected via another second connecting line (222) correspondingly arranged in the non-display area (20); and Anti-misturn-off signal input terminals (215) of the first shift register units (201) which are electrically connected to scanning lines (101) in one and the same row are connected via a third connecting line (223) arranged correspondingly in the non-display area (20), and anti-misturn-off signal input terminals (215) of the second shift register units (202) which are electrically connected to scanning lines in one and the same row are connected via another third connecting line (233) arranged correspondingly in the non-display area (20). [4] The array substrate according to claim 1, wherein a clock signal input terminal (211) of each first shift register unit (201) in the fourth non-display region (20 / 4) is connected to a clock signal input terminal (211) of a first shift register unit (201) on one and the same stage in the first non-display region (20 / 1) via a respective fourth connection line (224) correspondingly arranged in the non-display region (20), and a clock signal input terminal (211) of each second shift register unit (202) in the third non-display region (20 / 3) is connected to a clock signal input terminal (211) of a second shift register unit (202) on one and the same stage in the second non-display region (20 / 2) via a respective fifth connection line correspondingly arranged in the non-display region (20). [5] The array substrate according to claim 1, wherein an enable signal input terminal (212) of each first shift register unit (201) on the first stage in the fourth non-display region (20 / 4) is connected to an enable signal input terminal (212) of a first shift register unit (201) on the first stage in the first non-display region (20 / 1) via a respective sixth connection line (225) correspondingly arranged in the non-display region (20), and an enable signal input terminal (212) of each second shift register unit (202) on the first stage in the third non-display region (20 / 3) is connected to an enable signal input terminal (212) of a second shift register unit (202) on the first stage in the second non-display region (20 / 2) via a respective seventh connection line correspondingly arranged in the non-display region (20). [6] The array substrate according to claim 1, further comprising a control chip (230) arranged in the non-display area on one side of the display area in a second direction (Y) perpendicular to the first direction (X). [7] The array substrate according to claim 8, wherein the at least one notch (30) is arranged on a side of the display area that is farther from the control chip (230). [8] An array substrate according to claim 7, wherein a reverse trigger signal input terminal (219) of a first shift register unit (201) at the n-th stage as the last stage in the fourth non-display area (20 / 4) is connected to a secondary signal trigger terminal (216) of a first shift register unit (201) at an (n+1)-th stage in the first non-display area (20 / 1), a reverse trigger signal input terminal (219) of the second shift register unit (202) at the n-th stage as the last stage in the third non-display area (20 / 3) is connected to a secondary signal trigger terminal (216) of a second shift register unit (202) at the (n+1)-th stage in the second non-display area (20 / 2), and one and the same forward scanning signal is input to forward scanning signal input terminals (217) of first shift register units (201) which are electrically connected to scanning lines in one and the same row, and one and the same backward scanning signal is input to backward scanning signal input terminals (218) of first shift register units (201) which are electrically connected to scanning lines in one and the same row, and one and the same forward scanning signal is input to forward scanning signal input terminals (217) of second shift register units (202) which are electrically connected to scanning lines in one and the same row, and one and the same backward scanning signal is input to backward scanning signal input terminals (218) of second shift register units (202) which are electrically connected to scanning lines in one and the same row. [9] The array substrate according to claim 8, wherein the array substrate has a notch (30), a common signal input terminal of a first shift register unit (201) at a respective stage in the first non-display region (20 / 1) is connected to a corresponding common signal input terminal of a second register unit (202) in the third non-display region (20 / 3) which is at one and the same stage as the first shift register unit at the respective stage in the first non-display region (20 / 1), and a common signal input terminal of a second shift register unit (202) at the respective stage in the second non-display region (20 / 2) is connected to a corresponding common signal input terminal of a first register unit (201) in the fourth non-display region (20 / 4) which is at one and the same stage as the second shift register unit (202) at the respective stage in the second non-display region (20 / 2),and wherein the general signal input terminal comprises an enable signal input terminal (212), a forward scan signal input terminal (217), a reverse scan signal input terminal (218), and an anti-misfire signal input terminal (215). [10] The array substrate according to claim 1, wherein a shape of the at least one notch (30) comprises a trapezoid, a rectangle and / or a triangle. [11] A display device comprising an array substrate according to any one of claims 1 to 10.

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