Out-of-band communication in a serial communication environment

Abstract

Serializer that features the following: a conversion circuit (302, 308) configured for this purpose: to receive a parallel sequence of information (252.1, ..., 252.k) in a parallel format from a first group of input ports among a multitude of input ports and to convert the parallel sequence of information (252.1, ..., 252.k) from the parallel format into a serial format according to a clock signal (258) in order to create a serial sequence of information (256) and the clock signal (258) of a first to provide a group of output ports among multiple output ports; and a pass-through circuit (304, 310) configured for this purpose: to receive control information (254, 260, 264) from a second input port among the multitude of input ports and to forward the control information (254, 260, 264) from the second input port to a second output port among the multiple output ports, wherein the control information (254, 260, 264) includes one or more connection pulses to optimize the electrical performance of a PHY (physical layer / bit layer) device (110.1, ..., 110.n, 112.1, ..., 112.n) by unilateral and / or bilateral exchange of the control information (254, 260, 264).

Description

[0001] The present disclosure relates generally to a serial communication environment and includes out-of-band communication for the communication of control information within the serial communication environment.

[0002] Link training is a technique used in high-speed serializer-deserializer (SERDES) communication and is part of the specifications of Ethernet standards (e.g., IEEE 802.3). Link training provides a protocol for a device to communicate over a point-to-point link using in-band information with a remote link partner (LP) to jointly improve the bit error rate (BFR) over the link and / or reduce interference on adjacent channels caused by the link. Existing link training solutions perform link training only once during link startup or initialization, and as a result, their applications are limited.

[0003] Publication US 2003 / 0179771 A1 discloses a physical layer device (PLD) comprising a first serializer-deserializer device (SERDES) and a second SERDES device, each SERDES device having an analog portion with a serial port configured for communicating serial data with various network devices, and a digital portion configured for communicating parallel data with various other network devices.

[0004] Publication US 2009 / 0097500 A1 discloses methods and systems for using a reserved and / or out-of-band channel to maintain a network connection.

[0005] Document US 2006 / 0047899 A1 describes a storage device control device comprising a channel control unit for issuing an I / O request to a storage device, a CPU for receiving a data input / output request in a file unit, and an I / O processor for issuing the I / O request in accordance with the data input / output request in the file unit in response to an instruction from the CPU.

[0006] The present invention is defined by the attached independent claims, the dependent claims relating to particular embodiments of the invention.

[0007] Advantageously, the parallel sequence of information includes the following: a read command to read register data from one or more registers of an electronic device that is communicatively coupled to the serializer; or a write command to read register data from one or more registers of the electronic device.

[0008] Advantageously, the tax information includes the following: one or more link pulses to train a first PHY (physical layer / bit transmission layer) device to communicate with a second PHY device via a communication channel.

[0009] The communication channel advantageously has the following features: a copper cable, a fiber optic cable, or a copper backplane.

[0010] Advantageously, the single connection pulse or the multiple connection pulses train a second serializer of the first PHY device to communicate with a deserializer of the second PHY device.

[0011] Advantageously, the conversion circuit is configured to receive the parallel sequence of information from a host device, and the pass-through circuit is configured to receive the control information from the host device.

[0012] Advantageously, the pass-through circuit is configured to simultaneously pass through the control information when the conversion circuit provides the serial sequence of information and the clock signal.

[0013] Advantageously, the pass-through circuit is configured to receive the control information simultaneously with the conversion circuit receiving the parallel sequence of information.

[0014] Advantageously, the serial sequence of information includes: a read command to read register data from one or more registers of an electronic device that is communicatively coupled to the deserializer; or a write command to read register data from the one or more registers of the electronic device.

[0015] Advantageously, the tax information includes the following: one or more link pulses to train a first PHY (physical layer / bit transmission layer) device to communicate with a second PHY device via a communication channel.

[0016] The communication channel advantageously has the following features: a copper cable, a fiber optic cable, or a copper backplane.

[0017] Advantageously, the single connection pulse or the multiple connection pulses train a second deserializer of the first PHY device to communicate with a serializer of the second PHY device.

[0018] Advantageously, the conversion circuit is configured to receive the serial sequence of information from a host device via a serial interface, and the pass-through circuit is configured to receive control information from the host device via the serial interface.

[0019] Advantageously, the pass-through circuit is configured to simultaneously pass through the control information when the conversion circuit provides the parallel sequence of information.

[0020] Advantageously, the pass-through circuit is configured to receive the control information simultaneously with the conversion circuit receiving the serial sequence of information.

[0021] In accordance with one aspect, a first electronic device is provided which has the following features: a host device with a first serializer, the first serializer being configured to do: to receive an initial sequence of information in a parallel format from a first group of input ports under a first multitude of input ports, and control information from a second input port under the first multitude of input ports, to convert the first sequence of information in the parallel format into a serial format according to a clock signal in order to provide a second sequence of information in the serial format and the clock signal of a first group of output ports under a first plurality of output ports, and to route the control information from the second input port to a second output port among the first plurality of output ports; and a PHY (physical layer / bit layer) device comprising a first deserializer and a second serializer, the first deserializer being configured to: to receive the second sequence of information in serial format and the clock signal from a first group of input ports under a second multitude of input ports, and the control information from a second input port under the second multitude of input ports, to convert the second sequence of information in serial format into parallel format according to the clock signal, in order to provide a third sequence of information in parallel format and the clock signal of a first group of output ports under a second plurality of output ports, and to route the control information from the second input port to a second output port among the second multitude of output ports, and where the second serializer is configured for this purpose: to receive the third sequence of information in the parallel format from a first group of input ports under a third multitude of input ports and the control information from a second input port under the third multitude of input ports, to convert the first sequence of information in the parallel format into the serial format according to the clock signal, in order to provide a fourth sequence of information in the serial format and the clock signal of a first group of output ports under a third plurality of output ports, and to route the control information from the second input port to a second output port among the third multitude of output ports.

[0022] Advantageously, the control information includes the following: one or more link pulses to train a second deserializer to communicate with the second serializer via a communication channel.

[0023] Advantageously, the second serializer is further configured to provide the fourth sequence of information to a second electronic device via a communication channel in accordance with a version of an Ethernet communication standard or Ethernet communication protocol.

[0024] Advantageously, the version of the Ethernet communication standard or Ethernet communication protocol includes the following: 50G Ethernet, 100G Ethernet, 200G Ethernet or 400G Ethernet. BRIEF DESCRIPTION OF THE DRAWINGS / FIGURES

[0025] Embodiments of the disclosure are described with reference to the accompanying drawings. In the drawings, identical reference numerals denote identical or functionally similar elements. Furthermore, the leftmost position(s) of a reference numeral identifies the drawing in which the reference numeral first appears. The accompanying drawings illustrate: Fig. 1 a first communication environment in accordance with an exemplary embodiment of the present disclosure; Fig. 2 a serial interface within the serial communication environment in accordance with an exemplary embodiment of the present disclosure; Fig. 3A a block diagram of an exemplary serializer within the serial communication environment in accordance with an exemplary embodiment of the present disclosure; Fig. 3B a block diagram of an exemplary serializer within the serial communication environment in accordance with an exemplary embodiment of the present disclosure; and Fig. 4 a second communication environment in accordance with an exemplary embodiment of the present disclosure.

[0026] The revelation will now be described with reference to the accompanying drawings. In the drawings, identical reference symbols generally denote identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost position(s) in the reference drawing. DETAILED DESCRIPTION OF THE REVELATION OVERVIEW

[0027] The present disclosure describes a serializer and a deserializer. The serializer can receive a sequence of information in a parallel format and control information via a serial interface from a host device. The serializer converts the sequence of information in the parallel format to a sequence of information in a serial format to be provided to the deserializer, which then converts the sequence of information in the serial format back into a sequence of information in the parallel format. The serializer passes the control information to the deserializer, which similarly passes it on. The control information may consist of one or more control packets and / or one or more connection pulses.Link Pulses are included to train one or more other serializers and / or one or more other deserializers to communicate with each other via a communication channel. FIRST SERIAL COMMUNICATION ENVIRONMENT

[0028] Fig. Figure 1 illustrates a first communication environment in accordance with an exemplary embodiment of the present disclosure. A serial communication environment 100, such as a data center or computer center or a company site, to name a few examples, provides serial communication of information between a first electronic device 102 and a second electronic device 104 via a communication channel 106, such as a copper cable, a fiber optic cable, or a copper backplane, to name a few examples. As shown in Fig. As illustrated in Figure 1, the first electronic device 102 has a host device 108 and PHY (physical layer / bit layer) devices 110.1 to 110.n, and the second electronic device 104 has PHY devices 112.1 to 112.n and a host device 114.

[0029] The host device 108 of the first electronic device 102 communicates information with the PHY devices 110.1 to 110.n in serial format via a first serial interface 116. In the exemplary embodiment shown in Fig. As illustrated in Figure 1, the host device 108 includes SERDES devices 118.1 to 118.n, each of which has a serializer 120 and a deserializer 122. The serializer 120 converts information received from the host device 108 in a parallel format into the serial format for communication with a corresponding PHY device among the PHY devices 110.1 to 110.n. Similarly, the deserializer 122 converts information received in serial format from the corresponding PHY device among the PHY devices 110.1 to 110.n into the parallel format for feeding to the host device 108. In an exemplary embodiment, the host device 108 can be a network switch ora switching center, an application-specific integrated circuit (NIC), a network interface controller (NIC), a network processor, a storage device or any other suitable device which will be obvious to those skilled in the art in the relevant field(s) without departing from the inventive concept and the scope of protection of the present disclosure.

[0030] The PHY devices 110.1 to 110.n of the first electronic device 102 communicate information between the host device 108 and the PHY devices 112.1 to 112.n of the second electronic device 104 in serial format. In an exemplary embodiment, the information is communicated between the PHY devices 110.1 to 110.n and the PHY devices 112.1 to 112.n in accordance with a version of an IEEE (Institute of Electrical and Electronics Engineers) 802.3 communication standard or protocol, also known as Ethernet, such as 50G Ethernet, 100G Ethernet, 200G Ethernet, and / or 400G Ethernet, to name a few examples. In this exemplary embodiment, the information between PHY devices 110.1 to 110.n and PHY devices 112.1 to 112.n is transmitted as one or more Ethernet packets, which has Ethernet cell headers and Ethernet frames.have communicated.

[0031] In the exemplary embodiment shown in Fig. As illustrated in Figure 1, each of the PHY devices 110.1 to 110.n has a deserializer 124, a serializer 126, a deserializer 129, and a serializer 130. The deserializer 124 converts information received in serial format from a corresponding SERDES device among the SERDES devices 118.1 to 118.n via the first serial interface 116 into the parallel format for transmission to the serializer 126. The serializer 126 then converts the information received in parallel format from the deserializer 124 into the serial format for communication with a corresponding PHY device among the SERDES devices 112.1 to 112.n via the communication channel 106. Similarly, the deserializer 128 converts information that it receives in serial format from the corresponding PHY device among the PHY devices 112.1 to 112.The deserializer 128 converts the information received via communication channel 106 into the parallel format for feeding to the serializer 130. The serializer 130 then converts the information it received in parallel format from the deserializer 128 into the serial format for communication between the corresponding SERDES devices 118.1 to 118.n via the first serial interface 116.

[0032] The PHY devices 112.1 to 112.n of the second electronic device 104 communicate information between the PHY devices 110.1 to 110.n of the first electronic device 102 and the host device 114 in serial format. In an exemplary embodiment, the information is communicated between the PHY devices 112.1 to 112.n and the PHY devices 110.1 to 110.n according to a version of an IEEE (Institute of Electrical and Electronics Engineers) 802.3 communication standard or protocol, also known as Ethernet, such as 50G Ethernet, 100G Ethernet, 200G Ethernet, and / or 400G Ethernet, to name a few examples. In this exemplary embodiment, the information between the PHY devices 112.1 to 112.n and the PHY devices 110.1 to 110.n is transmitted as one Ethernet packet or as several Ethernet packets, which has the Ethernet cell header(s) and Ethernet frame(s).have communicated.

[0033] In the exemplary embodiment shown in Fig. As illustrated in Figure 1, each of the PHY devices 112.1 to 112.n has a deserializer 132, a serializer 134, a deserializer 136, and a serializer 138. The deserializer 132 converts information received in serial format from a corresponding PHY device (PHY devices 110.1 to 110.n) via communication channel 106 into parallel format for transmission to serializer 134. Serializer 134 then converts the information received in parallel format from deserializer 132 into serial format for communication with a corresponding SERDES device (SERDES devices 142.1 to 142.n) via a second serial interface 140. Similarly, the deserializer 136 converts information that it receives in serial format from the corresponding SERDES device among the SERDES devices 142.1 to 142.The data received via the second serial interface 140 is converted into the parallel format for feeding to the serializer 138. The serializer 138 then converts the information it received in parallel format from the deserializer 136 into the serial format for communication to the corresponding PHY device among the PHY devices 110.1 to 110.n via communication channel 106.

[0034] The host device 114 of the second electronic device 104 communicates information with the PHY devices 112.1 to 112.n in serial format via the second serial interface 140. In the exemplary embodiment shown in Fig. As illustrated in Figure 1, the host device 114 comprises SERDES devices 142.1 to 142.n, each of which includes a deserializer 144 and a serializer 146. The deserializer 144 converts information received in serial format from the corresponding PHY device among the PHY devices 112.1 to 112.n into the parallel format for transmission to the host device 114. Similarly, the serializer 146 converts information received from the host device 114 in parallel format into the serial format for communication to a corresponding PHY device among the PHY devices 112.1 to 112.n. In an exemplary embodiment, the host device 114 can be a network switch ora switching center, an application-specific integrated circuit (NIC), a network interface controller (NIC), a network processor, a storage device or any other suitable device which will be obvious to those skilled in the art in the relevant field(s) without departing from the inventive concept and the scope of protection of the present disclosure. EXAMPLE SERIAL INTERFACE

[0035] Fig. Figure 2 illustrates a serial interface within the serial communication environment in accordance with an exemplary embodiment of the present disclosure. A serializer 202 converts information received in the parallel format into a serial format for communication with a deserializer 204 via a serial interface 206. The deserializer 204 converts the information received by the serializer 202 in the serial format into the parallel format. The serializer 202 can be an exemplary embodiment of serializer device 120, serializer device 130, serializer device 134, serializer device 146, serializer device 412, and / or serializer device 414.The deserializer 204 can represent an exemplary embodiment of the deserializer device 122, the deserializer device 124, the serializer device 136, the deserializer device 144, the deserializer device 140 and / or the deserializer device 416. The deserializer device 410, the serializer device 412, the serializer device 414 and the deserializer device 416 are described below. Fig. 4 will be described in more detail. The serial interface 206 can represent an exemplary embodiment of the first serial interface 116 and / or the second serial interface 140.

[0036] The serializer 202 receives a parallel sequence of information 252.1 to 252.k from a first electronic device, such as the host device 108, the deserializer device 128, the deserializer device 132, and / or the host device 114, to name a few examples. The parallel sequence of information 252.1 to 252.k can comprise one or more data packets to be transmitted to the deserializer 204. In an exemplary embodiment, the parallel sequence of information 252.1 to 252.k can consist of...k includes a read command to read register data from one or more registers of the deserializer 204 and / or the other electronic devices that are communicatively coupled with the deserializer 204, and / or a write command to write register data to the one or more registers of the deserializer 204 and / or the other electronic devices that are communicatively coupled with the deserializer 204.In this exemplary embodiment, the read instruction and / or the write instruction may include: (1) preambles of thirty-two (32) bits with a logic one; (2) sixteen (16) control bits for identifying: the starts of the read instruction and / or the write instruction, the read instruction and / or the write instruction, an address of a host device, such as host device 108 or host device 114, to name a few examples, the request for the read instruction and / or the write instruction, one or more addresses of the one or more registers; and (3) sixteen (16) bits of the register data.

[0037] Similarly, the serializer 202 receives control information 254 from the first electronic device. The control information 254 may include one or more control packets and / or one or more link pulses, such as one or more fast link pulses (FLPs) or one or more normal link pulses (NLPs), to name a few examples, to identify the configuration and / or operation of the deserializer 204 and / or other electronic devices that are communicatively coupled to the deserializer 204, such as the PHY devices 110.1 to 110.n, the PHY devices 112.1 to 112.n, the SERDES devices 118.1 to 118.n, and / or the SERDES devices 142.1 to 142.n, to name a few examples. In some situations, one or more link pulses can also be one or more link codewords.Link Code Words (LCWs) are included. In an exemplary embodiment, the control information 254 can be used to implement an autonegotiation procedure to allow connected devices, such as the PHY devices 110.1 to 110.n and the PHY devices 112.1 to 112.n, to name one example, to select common communication parameters such as speed, error correction, duplex mode and / or flow control, to name a few examples, in order to establish one or more communication connections or communication links for communicating information over a communication channel, such as the communication channel 106.

[0038] In some situations, the control information 254 can be used to train the PHY devices 110.1 to 110.n to communicate with the PHY devices 112.1 to 112.n via communication channel 106, and / or to train the PHY devices 112.1 to 112.n to communicate with the PHY devices 110.1 to 110.n via communication channel 106. In these situations, the PHY devices 110.1 to 110.n configure their corresponding serializer device 126 and / or the PHY devices 112.1 to 112.n configure their corresponding deserializer device 132 and / or the PHY devices 112.1 to 112.n configure their corresponding serializer device 138 and / or the PHY devices 110.1 to 110.n configure their corresponding deserializer device 128 so that they optimize their electrical performance by means of a unilateral and / or bilateral exchange of the control information 254.

[0039] Furthermore, the control information 254 can be used to control and / or configure one or more advanced features or sophisticated properties of a serial communication environment, such as the serial communication environment 100, to name one example. These advanced features include features supported by the FlexE (Flexible Ethernet) communication protocol, such as bonding (combining) multiple communication links within the communication channel 106, sub-rating (using only part of a link) of communication links within the communication channel 106, and / or channelization of communication links within the communication channel 106, to name a few examples.These extended features also include features supported by the MAC security standard (MACsec), such as Secure Connectivity Associations and / or Security Associations, including Security Association Keys (SAKs), to name a few examples.

[0040] The serializer 202 then converts the parallel sequence of information 252.1 to 252.k from the parallel format to the serial format according to a clock signal, in order to provide a serial sequence of information 256 and a clock signal 258 to the deserializer 204. In some situations, the serializer 202 may be implemented as an embedded clock device to serialize the parallel sequence of information 252.1 to 252.k and the clock signal into the serial sequence of information 256. In these situations, the serializer 202 does not provide the clock signal 258. Furthermore, the serializer 202 routes the control information 254 to provide control information 260 to the deserializer 204.In an exemplary embodiment, the serializer 202 can simply pass through the control information 254 to provide the control information 260 to the deserializer 204 without further processing the control information 254.

[0041] In an exemplary embodiment, the serial sequence of information 256 can be characterized as in-band communication, and the control information 260 can be characterized as out-of-band communication with respect to the serial sequence of information 256. In this exemplary embodiment, the host device 108 or the host device 114 can simultaneously or almost simultaneously identify the configuration and / or operation of the deserializer 204 and / or the other electronic devices that are communicatively coupled to the deserializer 204, such as the PHY devices 110.1 to 110.n, the PHY devices 112.1 to 112.n, the SERDES devices 118.1 to 118.n and / or the SERDES devices 142.1 to 142.n, to name a few examples, and send the parallel sequence of information 252.1 to 252.k via the serializer 202.For example, the host device 108 or the host device 114 can simultaneously or almost simultaneously train the PHY devices 112.1 to 112.n via the serializer 202 to communicate with the PHY devices 110.1 to 110.n via the communication channel 106, and / or train the PHY devices 110.1 to 110.n to communicate with the PHY devices 112.1 to 112.n via the communication channel 106, and send the parallel sequence of information 252.1 to 252.k.

[0042] The deserializer 204 receives the serial sequence of information 256, the clock signal 258, and the control information 260 from the serializer 202 via the serial interface 206. The deserializer 204 then converts the serial sequence of information 256 from serial format to parallel format according to the clock signal 258 to provide a parallel sequence of information 262.1 to 262.m. Furthermore, the deserializer 204 routes the control information 260 to provide control information 264 to a second electronic device, such as the host device 108, the host device 114, the serializer device 126, and / or the serializer device 138, to name a few examples.In an exemplary embodiment, the deserializer 204 can simply pass through the control information 260 to provide the control information 264 to the second electronic device without further processing the control information 254. EXEMPLARY SERIALIZER

[0043] Fig. Figure 3A illustrates a block diagram of an exemplary serializer within the serial communication environment in accordance with an exemplary embodiment of the present disclosure. A serializer 300 converts information received in parallel format into serial format for communication with a deserializer, such as deserializer 204, for example, via a serial interface, such as serial interface 206, for example. Similarly, the serializer 300 passes control information to the deserializer via the serial interface. In the exemplary embodiment shown in Figure 3A, the serializer 300 is a block diagram of an exemplary embodiment of a serializer 204, for example. Fig. As illustrated in Figure 3A, serializer 300 has a conversion circuit 302 and a pass-through circuit 304. Serializer 300 can represent an exemplary embodiment of serializer 202.

[0044] Conversion circuit 302 receives the parallel sequence of information 252.1 to 252.k from a first group of input ports. It then converts this sequence to serial format according to a clock signal, providing the serial sequence of information 256 and the clock signal 258 to a first group of output ports. In some situations, conversion circuit 302 may serialize the parallel sequence of information 252.1 to 252.k and the clock signal into the serial sequence of information 256. In these situations, conversion circuit 302 does not provide the clock signal 258.

[0045] The pass-through circuit 304 receives the control information 254 from a second input port among the multiple input ports. The pass-through circuit 304 routes the control information 254 to provide the control information 260 to a second output port among the multiple output ports. In an exemplary embodiment, the serializer 202 can simply pass through the control information 254 to provide the control information 260 to the second output port without further processing the control information 254. EXEMPLARY DESERIALIZER

[0046] Fig. Figure 3B illustrates a block diagram of an exemplary serializer within the serial communication environment in accordance with an exemplary embodiment of the present disclosure. A deserializer 306 converts information received in serial format into the parallel format for communication to a serializer, such as serializer 202, for example, via a serial interface, such as serial interface 206, for example. Similarly, the deserializer 306 passes control information to the serializer via the serial interface. In the exemplary embodiment shown in Figure 3B, the deserializer 306 is a block diagram of an exemplary serializer. Fig. As illustrated in Figure 3B, the deserializer 306 has a conversion circuit 308 and a pass-through circuit 310. The deserializer 306 can represent an exemplary embodiment of the deserializer 204.

[0047] The conversion circuit 308 receives the serial sequence of information 256 and the clock signal 258 from a first group of input ports. The conversion circuit 308 then converts the serial sequence of information 256 from serial format to parallel format according to the clock signal 258, in order to provide the parallel sequence of information 262.1 to 262.m to a first group of output ports.

[0048] The pass-through circuit 310 receives the control information 260 from a second input port among the multiple input ports. The pass-through circuit 310 routes the control information 260 to provide the control information 264 to a second output port among the multiple output ports. In an exemplary output form, the serializer 202 can simply pass through the control information 260 to provide the control information 264 to the second output port without further processing the control information 260. SECOND EXEMPLARY COMMUNICATION ENVIRONMENT

[0049] Fig. Figure 4 illustrates a second communication environment in accordance with an exemplary embodiment of the present disclosure. A serial communication environment 400, such as a data center or computer center or a company site, to name a few examples, provides serial communication of information between a first electronic device 402 and a second electronic device 404 via the communication channel 106. As shown in Fig. As illustrated in Figure 4, the first electronic device 402 comprises the host device 108 and simplex devices 406.1 to 406.n, and the second electronic device 104 comprises simplex devices 408.1 to 408.n and the host device 114. As will be discussed below, a simplex device, such as one of the simplex devices 406.1 to 406.n and / or the simplex devices 408.1 to 408.n, comprises a serializer without a corresponding deserializer and a deserializer without a corresponding serializer. In contrast, a PHY device, such as one of the PHY devices 110.1 to 110.n and / or of the PHY devices 112.1 to 112.nn, has a serializer with a corresponding deserializer and a deserializer with a corresponding serializer. But the experts at the respective...Those in the relevant field(s) will recognize that the first electronic device 402 and the second electronic device 404 are each the PHY devices 110.1 to 110.n and the PHY devices 112.1 to 112.n as described above in . Fig. 1 discussed can include without deviating from the inventive concept and the scope of protection of the present disclosure.

[0050] The host device 108 of the first electronic device 402 communicates information with the simplex devices 406.1 to 406.n in serial format via the first serial interface 116 in an essentially similar manner to how the host device 108 of the first electronic device 402 communicates information with the PHY devices 110.1 to 110.n, as described above. Fig. 1 has been described.

[0051] The simplex devices 406.1 to 406.n of the first electronic device 402 communicate information between the host device 108 and the simplex devices 408.1 to 408.n of the second electronic device 404. In the exemplary embodiment shown in Fig. As illustrated in Figure 4, each of the simplex devices 406.1 to 406.n has a deserializer 410 and a serializer 412. The deserializer 410 converts information received in serial format from a corresponding SERDES device among the SERDES devices 118.1 to 118.n via the first serial interface 116 into the parallel format for input to a corresponding simplex device among the simplex devices 408.1 to 408.n. Similarly, the serializer 412 converts information received from the corresponding simplex device among the simplex devices 408.1 to 408.n via communication channel 106 into the serial format for communication to a corresponding SERDES device among the SERDES devices 118.1 to 118.n via the first serial interface 116.

[0052] As above in Fig. As discussed in section 2, the serializer 202 and the deserializer 204 can each represent exemplary embodiments of the serializer 414 and the deserializer 410, respectively. Thus, the deserializer 410 receives the control information 254, such as one or more control packets and / or one or more link pulses, as described above in section 2. Fig. As described in Section 2, the host device 108 receives control information 260 to identify the configuration and / or operation of the simplex devices 408.1 to 408.n. Furthermore, the deserializer 410 routes the control information 260 to provide the control information 264 for delivery to a corresponding simplex device among the simplex devices 408.1 to 408.n. In an exemplary embodiment, the deserializer 410 can simply pass the control information 260 through to provide the control information 264 to the corresponding simplex device among the simplex devices 408.1 to 408.n without further processing the control information 264. In some situations, the control information 260 can be used to train the simplex devices 406.1 to 406.n, with the simplex devices 408.1 to 408.to communicate with the simplex devices 408.1 to 408.n via communication channel 106, and / or to train the simplex devices 406.1 to 406.n to communicate with the simplex devices 406.1 to 406.n via communication channel 106. In these situations, the simplex devices 406.1 to 406.n configure their corresponding deserializer 401 and / or the simplex devices 408.1 to 408.n configure their corresponding serializer device 414 so that they optimize their electrical performance through a unilateral and / or bilateral exchange of the control information 260.

[0053] The simplex devices 408.1 to 408.n of the second electronic device 404 communicate information between the host device 114 and the simplex devices 406.1 to 406.n of the first electronic device 402. In the exemplary embodiment shown in Fig. As illustrated in Figure 4, each of the simplex devices 408.1 to 408.n has a serializer 414 and a deserializer 416. The serializer 414 converts information received from a corresponding simplex device among the simplex devices 406.1 to 406.n via communication channel 106 into the serial format for communication with a corresponding SERDES device among the SERDES devices 142.1 to 142.n via a second serial interface 140. The deserializer 124 converts information received in serial format from the corresponding SERDES device (SERDES devices 142.1 to 142.n) via the second serial interface 140 into the parallel format for feeding into a corresponding simplex device (simplex devices 406.1 to 406.n).

[0054] As above in Fig. As discussed in section 2, serializer 202 and deserializer 204 can each represent exemplary embodiments of serializer 414 and deserializer 416, respectively. Thus, deserializer 416 receives the control information 254, such as one or more control packets and / or one or more link pulses, as described above in Fig. As described in Section 2, the host device 114 receives control information 260 to identify the configuration and / or operation of the simplex devices 406.1 to 406.n. Furthermore, the deserializer 416 routes the control information 260 to provide the control information 264 for delivery to a corresponding simplex device among the simplex devices 406.1 to 406.n. In an exemplary embodiment, the deserializer 416 can simply pass the control information 260 through to provide the control information 264 to the corresponding simplex device among the simplex devices 406.1 to 406.n without further processing the control information 264. In some situations, the control information 260 can be used to train the simplex devices 406.1 to 406.n, to communicate with the simplex devices 408.1 to 408.n via communication channel 106, and / or to control the simplex devices 408.1 to 408.n to train, to communicate with the simplex devices 406.1 to 406.n via communication channel 106. In these situations, the simplex devices 406.1 to 406.n configure their corresponding serializer 412 and / or the simplex devices 408.1 to 408.n configure their corresponding deserializer device 416 so that they optimize their electrical performance through a unilateral and / or bilateral exchange of control information 260.

[0055] The host device 114 of the second electronic device 404 communicates information with the simplex devices 408.1 to 408.n in serial format via the second serial interface 140 in a substantially similar manner to how the host device 114 of the second electronic device 104 communicates information with the PHY devices 112.1 to 112.n, as described above. Fig. 1 has been described.

[0056] Any feature, structure, or characteristic described in connection with an exemplary embodiment can be included independently or in any combination with features, structures, and characteristics of other exemplary embodiments, whether explicitly described or not. The disclosure has been described using functional modules that illustrate the implementation of specific functions and their relationships. The boundaries of these functional modules have been arbitrarily defined here for the sake of clarity. Alternative boundaries may be defined as long as the specified functions and their relationships are appropriately realized.

Claims

[1] Serializer which has the following features: a conversion circuit (302, 308) configured for this purpose: to receive a parallel sequence of information (252.1, ..., 252.k) in a parallel format from a first group of input ports among a multitude of input ports and to convert the parallel sequence of information (252.1, ..., 252.k) from the parallel format into a serial format according to a clock signal (258) in order to create a serial sequence of information (256) and the clock signal (258) of a first to provide a group of output ports among multiple output ports; and a pass-through circuit (304, 310) configured for this purpose: to receive control information (254, 260, 264) from a second input port among the multitude of input ports and to forward the control information (254, 260, 264) from the second input port to a second output port among the multiple output ports, wherein the control information (254, 260, 264) includes one or more connection pulses to optimize the electrical performance of a PHY (physical layer / bit layer) device (110.1, ..., 110.n, 112.1, ..., 112.n) by unilateral and / or bilateral exchange of the control information (254, 260, 264). [2] Serializer according to claim 1, wherein the control information (254, 260, 264) comprises one or more link pulses to identify a configuration of the PHY (physical layer / bit layer) device (110.1, ..., 110.n, 112.1, ..., 112.n). [3] Serializer according to claim 1 or 2, wherein the parallel sequence of information (252.1, ..., 252.k) comprises: a read command to read register data from one or more registers of an electronic device (102, 104, 402, 404) that is communicatively coupled to the serializer (120, 126, 130, 134, 138, 146, 202, 412, 414, 300, 412, 414); or a write command to write register data to one or more registers of the electronic device (102, 104, 402, 404). [4] Serializer according to claim 1, wherein the control information (254, 260, 264) comprises the following: one or more further connection pulses to train a first PHY (physical layer / bit layer) device (110.1, ..., 110.n) to communicate with a second PHY device (112.1, ..., 112.n) via a communication channel (106). [5] Serializer according to claim 4, wherein the communication channel (106) comprises: a copper cable, a fiber optic cable, or a copper backplane. [6] Serializer according to claim 4 or 5, wherein one or more connection pulses train a second serializer (120, 126, 130, 134, 138, 146, 202, 412, 414, 300, 412, 414) of the first PHY device (110.1, ..., 110.n) to communicate with a deserializer (122, 124, 128, 129, 123, 128, 132, 136, 140, 144, 204, 208, 306, 401, 410, 416) of the second PHY device (112.1, ..., 112.n). [7] Serializer according to any of the preceding claims, wherein the conversion circuit (302, 308) is configured to receive the parallel sequence of information (252.1, ..., 252.k) from a host device (108, 114), and wherein the pass-through circuit (304, 310) is configured to receive the control information (254, 260, 264) from the host device (108, 114). [8] Deserializer configured for this purpose: to receive a serial sequence of information (256) in a serial format and a clock signal (258) from a first group of input ports among a plurality of input ports, and to convert the serial sequence of information (256) from the serial format into a parallel format according to the clock signal (258) in order to provide a parallel sequence of information (252.1, ..., 252.k) to a first group of output ports among multiple output ports, and Receiving tax information (254, 260, 264) from a second input port among the multitude of input ports and to pass the control information (254, 260, 264) from the second input port to a second output port among the multiple output ports, wherein the control information (254, 260, 264) includes one or more connection pulses to optimize the electrical performance of a PHY (physical layer / bit layer) device (110.1, ..., 110.n, 112.1, ..., 112.n) by unilateral and / or bilateral exchange of the control information (254, 260, 264). [9] Deserializer according to claim 8, wherein the control information (254, 260, 264) includes one or more further connection pulses to identify a configuration of the PHY (physical layer / bit layer) device (110.1, ..., 110.n, 112.1, ..., 112.n). [10] Deserializer according to claim 8 or 9, wherein the PHY (physical layer / bit layer) device (110.1, ..., 110.n, 112.1, ..., 112.n) is communicatively coupled to the deserializer (122, 124, 128, 129, 123, 128, 132, 136, 140, 144, 204, 208, 306, 401, 410, 416).

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