Wireless communication with peripheral devices

Abstract

System (100, 200, 300, 400, 900) that features: a wireless transceiver (413, 424, 914, 915); a storage device (220, 306) for storing a set of instructions; and a hardware processor (402) trained to execute the set of instructions to perform: Receiving an initial indication of a host device clock signal (504) from a host device (412), wherein the system (100, 200, 300, 400, 900) and the host device (412) are connected via a wired connection; Determining a phase relationship between the host device clock signal (504) and an endpoint device clock signal based on the first cue and a second cue of the endpoint device clock signal; Determining a first time point for transmitting a sensor data request to a peripheral device (404) of a computer (110, 460, 960) at least on the basis of the phase relationship; Transmitting the sensor data request to the peripheral device (404) at the first time using the wireless transceiver (413, 424, 914, 915); Receiving the requested sensor data from the peripheral device (404); and providing the requested sensor data to the host device (412) via the wired connection as input data to the computer (110, 460, 960), with the first indication of the host device clock signal (504) being received at a second time; and wherein the first time for transmitting the sensor data request is determined based on the second time and a predetermined delay between the time at which the system (100, 200, 300, 400, 900) begins to obtain the sensor data and the time at which the sensor data becomes available at the system (100, 200, 300, 400, 900) for transmission via the wired connection.

Description

BACKGROUND

[0001] Peripherals can serve as an interface between humans and computers. Some common peripherals include keyboards, computer mice, image scanners, speakers, microphones, webcams, and others. These peripherals can be connected to a computer processor via a wired connection, such as a Universal Serial Bus (USB), DisplayPort, etc. To enable communication between the computer processor and the peripherals, a wired connection can be provided between a peripheral device and the interface ports of the high-speed serial connection.

[0002] The introduction of wireless technology enables the replacement of wired connections with reliable, high-bandwidth radio channels. For example, a USB dongle can be provided that allows a wireless peripheral (e.g., a wireless computer mouse) to communicate wirelessly with a computer processor. The USB dongle can have a radio interface for communicating with the wireless peripheral. The USB dongle can further connect to a USB interface of the computer and communicate with the computer processor via a USB host device and a USB bus. The wireless peripheral can then communicate with the computer processor via the USB dongle.

[0003] A wireless connection between peripherals and computers can further enhance the usability of peripherals. For example, a wired connection can hinder the movement of a computer mouse. By eliminating the wired connection, a wireless computer mouse can move more freely and requires less effort to operate. It can also increase the speed with which the computer adjusts the display (e.g., mouse pointer position, response to user mouse selections, etc.), which can be critical for software applications that require immediate interaction between the user (e.g., games, device control, etc.) and the system. All of this can improve both user productivity and the user experience.

[0004] US 2012 / 0 066 418 A1 discloses a method for synchronizing a plurality of USB connections of different speeds, wherein the USB connections are grouped by speed and synchronized within the groups.

[0005] DE 11 2016 000 777 T5 discloses a controller of a memory system which provides data via a bus at a clock rate such that the data can be read at a clock rate of a peripheral device.

[0006] US 10 430 225 B1 discloses a server that manages a plurality of bus connections, wherein the server can block, filter and forward requests sent via the bus connections.

[0007] US 5 339 395 A discloses an interface between a microprocessor and a peripheral device to enable data transmission between the microprocessor and the peripheral device.

[0008] US 2012 / 0 197 729 A1 discloses a system for distributing promotional messages, wherein promotional messages are sent to a peripheral device in a personalized manner in association with an identifier.

[0009] US 2005 / 0 210 128 A1 discloses an adaptive query system in which future events to be queried are predicted.

[0010] US 2017 / 0 075 852 A1 discloses an integrated circuit that can process inputs and outputs for communication with a peripheral device without using the central processing unit. SHORT DESCRIPTION

[0011] A system is proposed having the features defined in independent claims 1, 12, and 16. Advantageous embodiments of the system have the features defined in dependent claims 2 to 11, 13 to 15, and 17. In some examples, a system comprises a wireless transceiver, a memory device for storing a set of instructions, and a hardware processor.The hardware processor is configured to execute the set of instructions to perform: receiving a first indication of a host device clock signal from a host device, wherein the system and the host device are connected via a wired connection; determining a phase relationship between the host device clock signal and an endpoint device clock signal based on the first indication and a second indication of the endpoint device clock signal; determining a first time to transmit a sensor data request to a peripheral device of a computer based at least on the phase relationship; transmitting the sensor data request to the peripheral device at the first time using the wireless transceiver; receiving the requested sensor data from the peripheral device; and providing the requested sensor data to the host device via the wired connection as input data to the computer.

[0012] In some aspects, the hardware processor is configured to perform the following: determining a second time at which the system is to receive a read request for the sensor data from the host device based on the host device clock signal, wherein the first time for obtaining the sensor data is determined by the peripheral device such that the sensor data is obtained by the system before the second time.

[0013] In some aspects, the first indication of the host device clock signal is received at a third time. The first time to transmit the sensor data request is determined based on the third time and a predetermined delay between the time the system begins acquiring the sensor data and the time the sensor data becomes available at the system for transmission over the wired connection.

[0014] In some aspects, transmitting the sensor data request to the peripheral device comprises transmitting a query request by the system to the peripheral device using the wireless transceiver. The hardware processor is further configured to perform the following: receiving a query response containing the sensor data from the peripheral device using the wireless transceiver; and processing the query response to extract the sensor data.

[0015] According to some aspects, transmitting the query request to the peripheral device at the first time may enable the peripheral device to determine a third time for obtaining the next sensor data and / or a fourth time for waiting for a next query request for transmitting the next sensor data from the peripheral device.

[0016] In some aspects, the polling request further includes information about the accuracy of the host device clock signal to determine the third time to obtain the next sensor data from and / or the fourth time to wait for a next polling request at the peripheral device.

[0017] In some aspects, the hardware processor is further configured to perform the following: determining a change in the phase relationship between the host device clock signal and the endpoint device clock signal, and if the change in the phase relationship is determined to exceed a threshold: generating an instruction containing information about the change in the phase relationship and transmitting the instruction to the peripheral device using the wireless transceiver so that the peripheral device can update the third time point for obtaining the next sensor data from and / or the fourth time point for waiting for a next polling request at the peripheral device.

[0018] In some aspects, the instruction further includes information about the accuracy of the host device clock signal and indicates when to update the third time point for obtaining the next sensor data from and / or the fourth time point for waiting for a next polling request at the peripheral device.

[0019] In some aspects, the hardware processor is further configured to perform: receiving a request from the peripheral device to establish a radio channel using the wireless transceiver; and sending an acknowledgment to the peripheral device using the wireless transceiver at a second time determined based on a third time at which the first indication of the host device clock signal is received.

[0020] In some aspects, the hardware processor is further configured to perform: determining a second time to begin obtaining second sensor data from a second peripheral, wherein the second time is also determined based on the phase relationship between the host device clock signal and the endpoint device clock signal; and beginning to obtain the second sensor data from the second peripheral at the determined second time.

[0021] In some aspects, the first indication of the host device clock signal comprises an interrupt signal. In some aspects, the wired connection comprises one or more Universal Serial Buses (USB).

[0022] In some examples, a system includes a wireless transceiver, a sensor, a storage device for storing a set of instructions, and a hardware processor configured to execute the set of instructions to perform: receiving a sensor data request from an endpoint device connected to a computer at a first time using the wireless transceiver; determining a second time to receive a next sensor data request based on the first time; determining a delay associated with obtaining sensor data from a sensor; determining a third time to begin obtaining sensor data based on the delay and the second time; obtaining the sensor data from the sensor at the third time; and transmitting the sensor data to the endpoint device using the wireless transceiver as input to the computer.

[0023] In some aspects, the endpoint device is connected to a host device via a wired connection. The first time is determined based on a phase relationship between a host device clock signal provided to the host device and an endpoint device clock signal provided to the endpoint device.

[0024] In some aspects, the hardware processor is further configured to perform: receiving an instruction containing information about a change in the phase relationship from the endpoint device; and determining the third time to begin obtaining sensor data from the sensor based on the instruction.

[0025] In some aspects, the instruction further includes information regarding the accuracy of the host device clock signal. The third time to begin obtaining the sensor data is determined based on the accuracy information.

[0026] In some aspects, the first time is determined based on when the endpoint device is expected to receive a read request for the sensor data from a host device.

[0027] In some examples, a system includes a dongle connected to a host device of a computer via a wired connection and a peripheral device. The dongle is configured to: receive a first indication of a host device clock signal from the host device; determine a phase relationship between the host device clock signal and an endpoint clock signal based on the first indication and a second indication of the endpoint clock signal; determine a first time to transmit a sensor data request to a peripheral device of a computer based at least on the phase relationship; and wirelessly transmit the sensor data request to the peripheral device at the first time.The peripheral device is configured to: acquire sensor data at a second time, determined based on a delay associated with acquiring the sensor data and based on when the dongle's sensor data request is expected to arrive; receive the sensor data request wirelessly from the dongle; and transmit the requested sensor data wirelessly in response to the sensor data request. The dongle is further configured to wirelessly receive the requested sensor data from the peripheral device and provide the requested sensor data to the host device via the wired connection as input data for the computer.

[0028] In some examples, the dongle is configured to send a query request to the peripheral device, receive a query response containing the sensor data from the peripheral device, and process the query response to extract the sensor data.

[0029] In some examples, the dongle is further configured to perform the following: determining a change in the phase relationship between the host device clock signal and the endpoint device clock signal; if the change in the phase relationship is determined to exceed a threshold: generating an instruction containing information about the change in the phase relationship; and transmitting the instruction to the peripheral device so that the peripheral device can update the third time point for obtaining the next sensor data and / or the fourth time point for waiting for a next polling request from the peripheral device.

[0030] In some examples, a method comprises: receiving a first indication of a host device clock signal from a host device using an endpoint device, the endpoint device and the host device being connected via a wired connection; determining a phase relationship between the host device clock signal and an endpoint clock signal using the endpoint device and based on the first indication and a second indication of the endpoint device clock signal; determining a first time to transmit a sensor data request to a peripheral device of a computer using the endpoint device and at least based on the phase relationship; transmitting the sensor data request to the peripheral device at the first time over a wireless channel using the endpoint device; receiving the requested sensor data from the peripheral device using the endpoint device;and providing the requested sensor data to the host device using the endpoint device over the wired connection as input data to the computer.;

[0031] In some examples, a method for controlling multiple peripheral devices of a computer comprises: establishing a first radio channel to a first peripheral device using a first transceiver of a first endpoint device, the first endpoint device connected to a host device via a first connection; establishing a second radio channel to a second peripheral device using a second transceiver of a second endpoint device, the second endpoint device connected to the host device via a second connection; receiving first sensor data over the first radio channel using the first endpoint device using the first transceiver; receiving second sensor data over the second radio channel using the second endpoint device using the second transceiver;providing the first sensor data and the second sensor data to the host device over the first connection using the first endpoint device; and providing the first sensor data and the second sensor data to the host device over the second connection using the second endpoint device.

[0032] In some aspects, the first endpoint device and the second endpoint device are the same endpoint device. The first connection and the second connection represent the same connection.

[0033] In some aspects, the first transceiver is controlled to establish the first radio channel using a first radio protocol. The second transceiver is controlled to establish the second radio channel using a second radio protocol.

[0034] In some aspects, the first radio protocol and the second radio protocol are the same radio protocol.

[0035] In some aspects, the first sensor data and the second sensor data are received by the endpoint device within a transmission period. The first radio channel and the second radio channel are configured such that the first sensor data is received at a different radio carrier frequency than the second sensor data at each time point during the transmission period.

[0036] In some aspects, the first sensor data is received wirelessly using a first carrier, wherein a radio frequency of the first carrier is changed within the transmission period based on a first radio frequency hopping method. The second sensor data is received wirelessly using a second carrier, wherein a radio frequency of the second carrier is changed within the transmission period based on a second radio frequency hopping method.

[0037] In some aspects, the first sensor data is transmitted wirelessly using a first carrier at a fixed first frequency within the transmission period. The second sensor data is transmitted wirelessly using a second carrier at a fixed second frequency within the transmission period.

[0038] In some aspects, the first sensor data and the second sensor data are received by the endpoint device within different transmission periods. The first sensor data and the second sensor data may be wirelessly received at an identical carrier frequency.

[0039] In some aspects, the method further comprises: transmitting information about the first radio channel using the first endpoint device to the second endpoint device; and determining the second radio channel at the second endpoint device and based on the information about the first radio channel.

[0040] In some aspects, the information about the first radio channel indicates a first frequency hopping sequence to be implemented on the first transceiver. The second radio channel is established based on a second frequency hopping sequence determined based on the information.

[0041] In some aspects, the information is transferred from the first endpoint device to the second endpoint device upon startup of the first endpoint device.

[0042] In some aspects, the information is transmitted from the first endpoint device to the second endpoint device after the first endpoint device receives the first sensor data over the first radio channel. BRIEF DESCRIPTION OF THE CHARACTERS

[0043] The detailed description is given with reference to the attached figures. Fig. Figure 1 shows a typical implementation of a system using the disclosed techniques. Fig. 2 shows a system for controlling a peripheral device according to certain examples of the present disclosure. Fig. 3 shows a system for operating a host computing device according to certain examples of the present disclosure. Fig. 4 illustrates a system for communication between a host computing device and a peripheral device according to certain examples of the present disclosure. Fig. Figure 5 shows the generation of local internal clock signals for the communication system of Fig. 4, according to certain examples of the present disclosure. Fig. Figures 6A to 6C show examples of wireless and wired data transmission. Fig. 7A to 7B show synchronized wireless and wired data transmission using the communication system of Fig. 4, according to certain examples of the present disclosure. Fig. 8 illustrates a time division multiplexing method used for wireless and wired data transmission according to certain examples of the present disclosure. Fig. 9 illustrates a system for communication between a host computing device and multiple peripheral devices according to certain examples of the present disclosure. Fig. 10 shows the processes in the communication system of Fig. 9 according to certain examples of the present disclosure. Fig. 11 and Fig. 12 illustrate flowcharts of operations on a computer system according to certain examples of the present disclosure. DETAILED DESCRIPTION

[0044] Aspects of the present disclosure relate to peripheral devices in general and to wireless peripheral control in particular, according to certain examples.

[0045] The following description describes various examples of a wireless peripheral device controller. To provide a thorough understanding of the embodiments, the descriptions are based on setting forth specific configurations and details. However, it will be apparent to one skilled in the art that certain embodiments may be practiced or implemented without each of the disclosed details. Furthermore, well-known features may be omitted or simplified to more clearly illustrate the novel features described herein.

[0046] Despite the improvements enabled by wireless technology, bottlenecks remain that can cause delays in transferring data from peripherals to the computer, impairing the user experience. For example, there is a lack of synchronization between wireless data transmission over the wireless connection and data transmission over the wired connection. As a result, the delay in data transmission between the wireless peripheral and the computer processor can increase.There is therefore a need for new developments that improve the synchronization between wireless data transmission and data transmission over a wired connection in order to reduce the delay in data transmission between a wireless peripheral device and a computer processor, thereby making the peripheral device easier to handle and improving usability. Conceptual overview of specific embodiments

[0047] Examples of the present disclosure relate to a wireless peripheral controller. The wireless peripheral controller may provide an interface between the host device and one or more wireless peripherals. The wireless peripheral controller may be connected to the host device via a wired connection and to the one or more wireless peripherals via one or more radio channels. The wireless peripheral controller may receive sensor data (e.g., detecting the X / Y movement of a computer mouse, detecting a key press on a keyboard, detecting audio signals from a microphone, etc.) from one or more wireless peripherals via the one or more radio channels and transmit the received sensor data to the host device via the wired connection.The wireless peripheral controller may synchronize wireless data transmissions from one or more of the wireless peripherals with the transmission of sensor data to a host device.

[0048] With a wireless peripheral controller according to the disclosed techniques, the synchronization between the wireless data transmission and the data transmission over the wired connection can be improved. The improved synchronization can reduce the data transmission delay between the wireless peripheral and the computer processor. For example, the disclosed techniques can reduce the latency between a user's keystroke or actuation on a peripheral and the execution of a corresponding action on a computer (which receives the user's action information wirelessly from the peripheral). This is particularly important for improving the user experience in applications that require rapid interactions between the user (e.g., games, device control, etc.) and the system, such as games, flight simulators, etc.

[0049] Specifically, the radio peripheral controller may receive indications of a continuously bi-level host device clock signal that controls the timing at which the host device requests data from the radio peripheral controller. The indications may be in the form of interrupts, where each interrupt corresponds to an edge (e.g., a rising edge) of the host device clock signal. In some examples, the interrupt may include, for example, a start-of-frame (SOF) interrupt. The radio peripheral controller may determine when the next data request from the host device is expected to arrive based on the timing of the indication of a current host device clock signal cycle.To ensure that the sensor data is available when the next data request from the host device arrives, the wireless peripheral controller may also synchronize the retrieval of sensor data from the wireless peripheral with the host device's clock signal, for example, by initiating the retrieval at a time determined based on the timing of the receipt of the indication of the host device's clock signal. In some examples, the wireless peripheral controller may initiate the retrieval of sensor data by sending a request (e.g., a polling request) to the wireless peripherals or simply by waiting for the sensor data at the specified time.

[0050] There are various ways the wireless peripheral controller can determine when to initiate sensor data acquisition. In one example, the wireless peripheral controller can initiate sensor data acquisition after a specified amount of time has elapsed from the time the most recent indication of a host device clock signal is received. The specified amount of time can be determined based on a processing delay at the wireless peripheral controller and the time at which the next data request from the host device is expected. The processing delay can be a delay at the wireless peripheral controller to acquire and process the sensor data so that the sensor data is available at the wireless peripheral controller before the next data request from the host device arrives.

[0051] In another example, the wireless peripheral controller may use time-division multiplexing (TDMA) to initiate the acquisition of sensor data from multiple wireless peripherals at different times within a host device clock cycle. The TDMA method may be used to minimize signal interference and collisions between the wireless peripherals. Each of the different acquisition times may be determined relative to the time of receipt of the host device clock indication. The delay between each sensor data acquisition time and the time of receipt of the host device clock indication may also be determined, for example, based on a delay experienced by a wireless peripheral in acquiring and processing the sensor data and in wirelessly transmitting the sensor data to the wireless peripheral controller.However, the time for a reference to the host device clock signal from the last wireless peripheral can still be determined based on the processing delay at the radio peripheral controller, such that all sensor data obtained from the multiple wireless peripherals within the host device clock signal cycle is available at the radio peripheral controller before the next data request from the host device arrives.

[0052] In some examples, the wireless peripheral controller may also transmit information about the timing of the host device clock signals to the wireless peripheral so that the wireless peripheral can determine when the wireless peripheral controller will initiate the acquisition of the next sensor data set. Based on the information, the wireless peripheral can determine when to collect the sensor data from its local sensor to provide the most recent sensor data when the wireless peripheral controller initiates the acquisition of the next sensor data set.

[0053] There are several ways the radio peripheral controller communicates information about the timing of the host device clock signals to the wireless peripheral. For example, when the radio peripheral controller receives a request from the wireless peripheral, the radio peripheral controller may synchronize the acknowledgment with the host device clock signal indication. For example, the radio peripheral controller may send the acknowledgment to the wireless peripheral after a predetermined period of time has elapsed from the time the host device clock signal was received. Receipt of the acknowledgment at the wireless peripheral may establish the phase of the system clock signal at the wireless peripheral, allowing the wireless peripheral to synchronize its operation with the host device clock signal.In TDMA, the radio peripheral controller may acknowledge the connection request of each wireless peripheral at different times, with each acknowledgment time being set relative to the time at which the indication of the host device clock signal is received (thus synchronized with the host device clock signal) to enable synchronization of the operations at each of the wireless peripherals with that of the host device clock signal.

[0054] In some examples, the wireless peripheral controller may also detect a drift of a current host device clock signal cycle and measure the amount of drift. The drift of the host device clock signal may result in a change in the expected arrival time of the next host data request. As long as the wireless peripheral controller can adjust its reference time for the next sensor data set, as described above, based on the most recent indication of the host device clock signal, the wireless peripheral controller may transmit an instruction containing the amount of drift to the wireless peripheral so that the wireless peripheral can update an estimate for when to submit the sensor data to the wireless peripheral controller. The wireless peripheral may adjust the timing of its operations, including the timing for acquiring the sensor data from its local sensor, based on the updated estimate.In some examples, the wireless peripheral controller may also transmit other information, such as a jitter measurement of the host device clock signal, to allow the wireless peripheral to further refine the estimate of when to pass the sensor data to the wireless peripheral controller.

[0055] There are various ways the radio peripheral controller can detect a drift of a current host device clock signal cycle and measure the amount of drift. For example, the radio peripheral controller can receive or generate an internal reference clock signal that has the same nominal cycle period as the host device clock signal (e.g., based on an average cycle period of the host device clock signal, based on a design cycle period of the host device clock signal without drift, etc.). The radio peripheral controller can determine a phase delay between the host device clock signal and the internal reference clock signal (e.g., by measuring a delay between a respective host device clock signal and a corresponding clock signal edge of the internal reference clock signal).The wireless peripheral controller may record the previous phase delays and determine a drift amount by comparing a current phase delay (measured in a current host device clock cycle) with the previous phase delays. In some examples, the wireless peripheral controller may compare the drift amount to a threshold to account for random drift due to jitter, and if the drift amount exceeds the threshold, take corrective action (e.g., adjusting the timing for acquiring the next sensor data, transmitting an instruction to the wireless peripheral to adjust the expiration timing, etc.).

[0056] By synchronizing the wireless data transmission (between the wireless peripheral controller and the wireless peripheral) with the host device clock signal, the data transmission delay between the wireless peripheral and the computer processor can be reduced. For example, the wireless peripheral can acquire the sensor data just in time before a request from the wireless peripheral controller, while the wireless peripheral controller can retrieve the sensor data from the wireless peripheral just in time before the next data request arrives from the host device.With such an arrangement, the overall delay time for data transmission from the wireless peripheral to the host device (and the computer processor) can be minimized, allowing the computer processor to respond more quickly to user input (captured via the peripheral), thereby improving both user experience and system performance.

[0057] In some examples, the wireless peripheral controller may include multiple wireless transceivers (and antennas) to better communicate with multiple wireless peripherals. Each of the multiple wireless transceivers may be dedicated to communicating with a particular wireless peripheral (or group of wireless peripherals). In one illustrative example, a wireless peripheral controller including two wireless transceivers may assign communication with a computer mouse to one of the wireless transceivers, while the other of the wireless transceivers may assign communication with a keyboard and microphone. The wireless peripheral controller may obtain sensor data from both wireless transceivers and transmit the sensor data to the host device over the connection.

[0058] The wireless peripheral controller may also coordinate the acquisition of sensor data among the wireless transceivers to minimize signal collisions and interference. In some examples, different frequency channels may be assigned to the wireless transceivers for performing wireless data transmission with the respective wireless peripherals at different times (e.g., by providing different sequences of frequency hopping patterns). In some examples, the wireless transceivers may operate according to a TDMA scheme, in which the wireless transceivers alternately acquire sensor data from the respective wireless peripheral(s).In one example of a TDMA scheme, each wireless transceiver may be assigned a time slot for obtaining sensor data from its respective wireless peripherals. During each assigned time slot, only one of the wireless transceivers may be powered on, while the other wireless transceivers must be powered off during that assigned time slot. Likewise, the timing for obtaining sensor data at each wireless transceiver may be synchronized with the host device clock signal. With such arrangements, the computer processor can efficiently obtain valid sensor data from multiple peripherals, further improving both user experience and system performance. Typical system environment for specific embodiments

[0059] Fig. 1 shows a typical implementation of a system 100 in which the disclosed techniques may be utilized. The system 100 may include a computer 110, a display 120, and a plurality of peripherals, including, for example, peripheral 130 (e.g., "computer mouse 130"), peripheral 140 (e.g., "keyboard 140"), and peripheral 150 (e.g., "microphone 150"). In the system 100, as will be appreciated by one of ordinary skill in the art, the computer mouse 130, keyboard 140, and microphone 150 may be configured to control aspects of the computer 110 and the display 120. The computer 110 may be referred to as a "host computer" or a "host computing device." Each of the peripheral devices 130-150 may include one or more sensors for detecting input from a user (or input signals, such as audio signals) and generating corresponding sensor data (e.g.,Sensor data representing a path of movement of the computer mouse 130, sensor data indicating a keystroke on the keyboard 140, audio data captured by the microphone 150, etc.) The peripheral devices 130-150 can provide the sensor data to the computer 110 for controlling one or more operations of the computer 110. For example, the computer 110 can detect a user selection of an audio file in a graphical user interface displayed on the display 120 based on movement detected by the computer mouse 130 and play the selected audio file.

[0060] The computer 110 may include a machine-readable medium (not shown) configured to store computer code, such as keyboard driver software, and the like, where the computer code may be executed by a processor (e.g., processor(s) 302) of the computer 110 to affect control of the computer 110 by the peripheral devices 130, 140, and / or 150. The various examples described herein generally refer to peripheral device 130 as a computer mouse, peripheral device 140 as a keyboard, and peripheral device 150 as a microphone, although it is understood that the peripheral devices 130-150 may be any input / output (I / O) device, user interface device, control device, input unit, or the like. The peripheral devices 130-150 may also be, for example, a remote control device, a portable device (e.g.,Smartwatch, bracelet, glasses), a smartphone or the like.

[0061] The host computing device is typically a desktop or laptop computing device. However, it should be understood that the host computing device may be any suitable computing device, further including a tablet computer, a smartphone, a virtual or augmented reality interface (e.g., with 2D or 3D displays), a holographic interface, or the like. Many variations, modifications, and alternative embodiments thereof will be apparent to one of ordinary skill in the art.

[0062] Fig. 2 illustrates a system for controlling a peripheral device (e.g., one or more peripheral devices 130-150) according to certain embodiments. System 200 includes processor(s) 210, a memory array 220, a power management system 230, a communication system 240, and an input acquisition module 250. Each of system blocks 220-250 may be electrically connected to processor(s) 210 (e.g., via a bus system). System 200 may also include other systems that are not illustrated or explained herein in order to clearly illustrate the novel features described herein. System blocks 220-250 may be implemented as separate modules; alternatively, more than one system block may be implemented in a single module.

[0063] In some embodiments, the processor(s) 210 includes one or more microprocessors (µCs) and may be configured to control the operation of the system 200. Alternatively, as will be appreciated by one of ordinary skill in the art, the processor(s) 210 may include one or more microcontrollers (MCUs), digital signal processors (DSPs), or the like with supporting hardware and / or firmware (e.g., memory, programmable I / Os, etc.). The processor(s) 210 may control some or all aspects of operation of the peripheral devices 130-150 (e.g., system blocks 220-250). Alternatively or additionally, some of the system blocks 220-250 may include an additional specialized processor operable in conjunction with the processor 210. Many variations, modifications, and alternative embodiments thereof will be apparent to one of ordinary skill in the art.

[0064] The memory array 220 may be configured to store information related to one or more configurations for operation of the peripheral devices 130-150. As explained in more detail below, one or more of the configurations for operation of the peripheral devices 130-150 may include setting features of the peripheral devices 130-150, including, but not limited to, computer mouse scrolling speed, computer mouse motion sensor sensitivity, keyboard shortcut mapping, microphone sensitivity, and the like. The memory array 220 may also store other configuration information used for communication with the peripheral devices 130-150, as explained in more detail below.

[0065] Additionally, memory array 220 may store one or more software programs for execution by processors (e.g., processor(s) 210). Note that "software" may refer to sequences of instructions that, when executed on processing units (e.g., processors, processing devices, etc.), cause system 200 to perform certain functions of software programs. The instructions may be stored as firmware residing in read-only memory (ROM) and / or as applications stored in media storage that can be read into memory for processing by processing devices. Software may be implemented as a single program or as a bundle of individual programs, and it may be stored in non-volatile memory and copied, in whole or in part, to volatile memory during program execution.

[0066] The power management system 230 may be configured to handle power distribution, charging, energy efficiency, and the like for the peripheral devices 130-150. In some embodiments, the power management system 230 may include a battery (not shown), a USB-based charging system for the battery (not shown), and power management devices (e.g., low-dropout regulators - not shown). In certain embodiments, the functions available through the power management system 230 may be integrated into the processor(s) 210. The power source may be a removable battery, a rechargeable energy storage device (e.g., a supercapacitor, a lithium-polymer battery, NiMH, NiCd), or a wired power supply. The charging system may be an additional cable (dedicated to charging) or may use a USB port to charge the battery.

[0067] For example, the communication system 240 may be configured to enable wireless or wired communication between the processors 210 and one or more of the peripherals 130-150. The communication system 240 may be configured to use radio frequency (RF), Bluetooth®, BLE, Wi-Fi, infrared (IR), ZigBee®, Logitech Unifying®, or other suitable communication technology for communicating with other computing devices and / or peripherals. The communication system 240 may also provide a hardwired connection to the processors 210. The hardwired connection may be a serial connection such as Universal Serial Bus (USB), FireWire®, DisplayPort®, etc.

[0068] As an example of a communication system 240, a dongle may be provided that may enable a combination of wireless and wired communication between the processors 210 and one or more peripheral devices 130-150. For example, the dongle may include a wired interface connector (e.g., a USB plug) that may be plugged into a hard-wired interface connector (e.g., a USB port). The hard-wired interface connector, in turn, is connected to the processors 210 via a hard-wired connection (e.g., USB buses). In addition, the dongle may also include a wireless interface (e.g., a Bluetooth® radio interface) to enable wireless data transmission with the peripheral devices 130-150.The dongle can receive sensor data from peripheral devices 130-150 via the wireless interface and transmit the sensor data to processors 210 via the hardwired connection. As explained in more detail below, the present disclosure provides techniques for synchronizing wireless data transmission (via the wireless interface) with wired data transmission (via the hardwired connection), which can reduce the data transmission delay between peripheral devices 130-150 and processors 210.

[0069] The input capture module 250 may control the capture of a user's interaction with input elements located on the peripheral devices 130-150. The input capture module 250 may capture user input based, for example, on sensor data from the computer mouse 130. In some embodiments, the input capture module 250 may cooperate with the memory array 220 to generate input data for the processors 210 based on the sensor data received from the communication system 240. For example, the input capture module 250 may calculate a distance traveled by a mouse pointer on the display 120 based on scroll speed information stored in the memory array 220 and sensor data from the computer mouse 130, and pass the distance information to the processors 210 (or a renderer) to render the mouse movement on the display 120.

[0070] Although certain systems are not specifically discussed, they are considered part of system 200, as would be apparent to one of ordinary skill in the art. System 200 may, for example, include a bus system for transferring power and / or data to and from its various systems.

[0071] It should be understood that system 200 is illustrative, and variations and modifications are possible. System 200 may perform other functions not expressly described herein. Furthermore, although system 200 is described with reference to specific blocks, these blocks are defined for ease of illustration and are not intended to imply any particular physical arrangement of components. Furthermore, the blocks need not correspond to any particular physical components. The blocks may be configured to perform various functions, e.g., by programming a processor or providing appropriate control circuitry, and various blocks may or may not be reconfigured depending on how they were originally configured.

[0072] Embodiments of the present invention may be implemented in a variety of systems, including electronic devices implemented using any combination of circuitry and software. Furthermore, aspects and / or portions of system 200 may be combined with or operated in conjunction with other subsystems as required by design. For example, input acquisition module 250 and / or memory array 220 may be implemented within processor(s) 210 rather than functioning as a separate unit. Furthermore, the inventive concepts described herein may be applied to various peripheral devices and are not limited to computer mice, keyboards, or microphones. System 200 may be applied to any of the peripheral devices explicitly described, by reference, or implicitly described in the embodiments (e.g.,(if applicable to a particular peripheral device as would be apparent to a person of ordinary skill in the art). The above embodiments are not intended to be limiting, and countless applications and possibilities will become apparent to a person of ordinary skill in the art with knowledge of this disclosure.

[0073] Fig. 3 shows a system 300 for operating a host computing device (e.g., host computing device 110) according to certain embodiments. The system 300 may be used to implement the methods described herein with reference to Fig. 1, Fig. 2 and the myriad examples described herein or within the scope of this disclosure, but not necessarily explicitly described. System 300 may include one or more processors 302 that can communicate with a number of peripherals (e.g., peripheral devices) via a bus subsystem 304. These peripherals may include storage subsystem 306 (consisting of memory subsystem 308 and file storage subsystem 310), user interface peripherals 314, user interface output devices 316, and network interface subsystem 312. User peripherals 314 may be any of the peripheral types described herein (e.g., keyboard, computer mouse, remote control, etc.).User output devices 316 may be any display, including, as would be appreciated by one of ordinary skill in the art, computer monitors, displays on portable devices (e.g., smartphones, gaming systems), or the like. Alternatively or additionally, a display may also include virtual reality (VR) displays, augmented reality displays, holographic displays, and the like, as would be appreciated by one of ordinary skill in the art.

[0074] In some examples, the internal bus subsystem 304 may provide a mechanism by which the various components and subsystems of the computer system 300 may communicate with each other as intended. Although the internal bus subsystem 304 is schematically illustrated as a single bus, alternative embodiments of the bus subsystem may utilize multiple buses. One example of the internal bus subsystem 304 is USB buses. Further, the network interface subsystem 312 may serve as an interface for transmitting data between the computer system 300 and other computer systems or networks. Embodiments of the network interface subsystem 312 may include wired interfaces (e.g., Ethernet, CAN, RS232, RS485, etc.) or wireless interfaces (e.g., Bluetooth®, BLE, ZigBee®, Z-Wire®, Wi-Fi, cellular protocols, etc.).In some examples, the network interface subsystem 312 may be part of a dongle, and the dongle may connect to the internal bus subsystem 304 (e.g., USB buses) to communicate with the processors 302 as described above.

[0075] In some cases, the user interface peripherals 314 may include a keyboard (keyboard 140), a presenter, a pointing device (e.g., mouse, trackball, touchpad, etc.), a touchscreen integrated with a display, audio peripherals (e.g., speech recognition systems, microphones, etc.), human-machine interfaces (HMI), and other types of peripherals. In general, the use of the term "peripheral" is intended to include all possible types of devices and mechanisms for inputting information into the computer system 300. Additionally, the user interface output devices 316 may include a display subsystem, a printer, or non-visual displays such as audio output devices, etc. The display subsystem may be any known type of display device.In general, the use of the term “output device” is intended to encompass all possible types of devices and mechanisms for outputting information from the computer system 300.

[0076] The storage subsystem 306 may include the memory subsystem 308 and the file storage subsystem 310. The memory subsystem 308 and the file storage subsystem 310 represent non-transitory, computer-readable storage media that can store program code and / or data that provide the functionality of embodiments of the present disclosure. In some embodiments, the memory subsystem 308 may include a number of memories, including the main random access memory (RAM) 318 for storing instructions and data during program execution and the read-only memory (ROM) in which non-modifiable instructions may be stored. The file storage subsystem 310 may provide persistent (i.e., non-volatile) storage for program and data files and may include a magnetic hard disk or solid-state drive, an optical drive, along with associated removable media (e.g., CD-ROM, DVD, Blu-ray, etc.).), a removable flash memory drive or card, and / or other types of storage media known in the art.

[0077] It should be noted that computer system 300 is illustrative and not intended to limit the embodiments of the present disclosure. Many other configurations with more or fewer components than system 300 are possible. The various embodiments may further be implemented in a variety of operating environments, which in some cases may include one or more user computers, computing devices, or processing devices capable of executing multiple applications. User or client devices may include any number of general-purpose personal computers, such as desktop computers or laptop computers running a standard or non-standard operating system, as well as mobile, wireless, and wearable devices running mobile software capable of supporting a variety of networking and messaging protocols.Such a system may also include a series of workstations running a variety of commercially available operating systems and other well-known applications for purposes such as development and database management. These devices may also include other electronic devices, such as dummy terminals, thin clients, gaming systems, and other devices capable of communicating over a network.

[0078] Most embodiments utilize at least one network familiar to those skilled in the art for supporting communications using a variety of commercially available protocols, such as TCP / IP, UDP, OSI, FTP, UPnP, NFS, CIFS, and the like. The network may be, for example, a local area network, a wide area network, a virtual private network, the Internet, an intranet, an extranet, a public switched telephone network, an infrared network, a wireless network, and any combination thereof.

[0079] In embodiments employing a network server, the network server may run a variety of server or mid-tier applications, including HTTP servers, FTP servers, CGI servers, data servers, Java servers, and business application servers. The server(s) may also be capable of executing programs or scripts in response to requests from user devices, for example, by executing one or more applications, which may be implemented as one or more scripts or programs written in any programming language, including but not limited to Java®, C, C#, or C++, or a scripting language such as Perl, Python, or TCL, as well as combinations thereof. The servers may also include database servers, including but not limited to those commercially available from Oracle®, Microsoft®, Sybase®, and IBM®.

[0080] Such devices may also include, as described above, a computer-readable storage media reader, a communication device (e.g., a modem, a network card (wireless or wired), an infrared communication device, etc.), and a memory. The computer-readable storage media reader may be connected to or configured to receive a non-transitory computer-readable storage medium, which may include external storage media, local storage media, fixed storage media, and / or removable storage media, as well as storage media for temporarily and / or more permanently recording, storing, transmitting, and retrieving computer-readable information.The system and various devices typically also include a number of software applications, modules, services, or other elements residing in at least one memory device, including an operating system and application programs such as a client application or a browser. It should be noted that alternative embodiments may include numerous changes from the embodiments described above. For example, custom hardware may be used and / or certain elements may be implemented in hardware, software (including portable software such as applets), or both. In addition, connections to other computing devices, such as network input and output devices, may be used. Examples of a communication system

[0081] Fig. 4 shows an example of a communication system 400 in which the disclosed techniques may be applied. The communication system 400 may facilitate data transmission between a hardware processor 402 (e.g., processor 210 of Fig. 2, processor 302 from Fig. 3, etc.) and a peripheral device 404 (e.g., peripheral devices 130-150). The communication system 400 may include a wireless interface 406 and a wired connection 408 on the hardware processor 402 side (e.g., as part of the computer 110 and / or systems 200 and 300) and a wireless interface 410 on the peripheral device 404 side. The wired connection 408 further includes a host device 412, an endpoint device 414, and a bus 415 connecting the host device 412 to the endpoint device 414. Data may be transferred between the hardware processor 402 and the peripheral device 404 via the wireless interfaces 406 and 410 and the wired connection 408.

[0082] As in Fig. 4, the wireless interface 406 and the endpoint device 414 may be part of a dongle 450, while the hardware processor 402 and the host device 412 may be part of a computer system 460. The dongle 450 may further include a control processor 416 to control the operations of the wireless interface 406 and the endpoint device 414, including, for example, the operations for transferring data between the hardware processor 402 and the peripheral devices 404. Although Fig. While Figure 4 shows the control processor 416 as a single unit, the control processor 416 may of course also comprise multiple units, some of which may be part of the wireless interface 410. Furthermore, the peripheral device 404 may also comprise a sensor 430 for capturing user input and generating sensor data, as well as a control processor 432 for processing the sensor data and controlling the wireless interface 410 to transmit the sensor data to the dongle 450, which may then transmit the sensor data to the hardware processor 402 via the wired connection 408. A wireless network formed between the dongle 450 and the peripheral device 404 may be referred to as a piconet. A link event may occur between the wireless interfaces 406 and 410 when data packets are transferred between the interfaces.From a connection event, the control processor 416 may obtain sensor data from the peripheral device 404 and forward the sensor data to the endpoint device 414. The endpoint device 414 may transmit the sensor data to the host device 412 via the bus 415.

[0083] The wireless interface 406 may include one or more wireless transceivers 413, whereas the wireless interface 410 may further include a wireless transceiver 424. The wireless transceivers 413 and 424 may be controlled by the control processor 416 and 432, respectively, to transmit and receive radio signals to perform wireless data transmission. The wireless transceivers 413 and 424 may include, for example, antennas, power amplifiers, low-noise amplifiers, mixers, analog-to-digital converters (ADCs), etc., and may perform data transmission based on predetermined protocols, such as Bluetooth®, BLE, etc. In the Bluetooth® and BLE protocols, the radio carrier frequency for transmitting / receiving data may be changed, for example, based on a predetermined frequency hopping sequence, and various components (e.g.,Mixers) of the wireless transceivers 413 and 424 can be operated to perform data transfer upon a connection event based on the predetermined frequency hopping sequence.

[0084] In some examples, in a wireless piconet formed between the dongle 450 and the peripheral device 404, the dongle 450 may act as the master device, whereas the peripheral device 404 may act as the slave device. The control processor 416 may initiate the acquisition of sensor data via the wireless interface 406 by sending a request (e.g., a polling request) to the wireless interface 410 at predetermined time intervals, and the peripheral wireless communication device may listen for the polling request and provide sensor data in response to the polling request. In some examples, the control processor 416 may also determine when the peripheral devices 404 should transmit sensor data and transmit scheduling information to the peripheral devices 404.Based on the schedule information, the peripheral devices 404 may transmit sensor data at the scheduled times, while the wireless interface 406 may initiate the acquisition of sensor data by waiting for the sensor data from the peripheral devices 404 at the scheduled times. In either case, the application processor 422 (of the peripheral devices 404) may determine when the next connection event should occur (e.g., based on previous sensor data transmissions to the wireless interface 406, previous polling requests received from the wireless interface 406, etc.) and may acquire sensor data from the sensor 430 prior to the next connection event.

[0085] The communication system 400 also includes the wired connection 408 connected to the wireless interface 406. Sensor data received via the wireless interface 406 may be transmitted to the hardware processor 402 via the wired connection 408. The host device 412 may send a read request for data via the bus 415. After receiving the read request, the host device 412 may send the sensor data to the host device 412 via the bus 415. In some examples, the bus 415 may be a USB bus, and the dongle 450 may be configured as a USB dongle with a hardware connector (e.g., a USB plug) that can be plugged into a hardware connector (e.g., a USB port) of the computer system 460 to establish a connection. The hardware connector may be hard-wired to the USB bus 415 of the computer system 460.

[0086] Even if Fig. 4 illustrates the endpoint device 414 as separate from the computer system 460. It should be understood that the endpoint device 414 may also be an internal module of the computer system 460, such that the endpoint device 414 is not connected to the host device 412 via a hardware port (e.g., a USB port). For example, the host device 412 and the endpoint device 414 may be connected via an I2C (Inter-Integrated Circuit) bus of a motherboard. Likewise, the wireless interface 406 and the control processor 416 may also be part of the computer system 460.

[0087] The host devices 412, the dongle 450, and the peripheral device 404 may each form a synchronous system. Each of these systems may include a local internal clock signal and a set of digital sequential circuits configured as a finite state machine (FSM) clocked by the local internal clock signal, which may set the state transitions and outputs of the FSM and control the timing of operations for the respective system. The local internal clock signal may be a continuously alternating signal between two levels at a nominal frequency (excluding drift, jitter, etc.) configured to control the timing of operations for various digital sequential circuits.For example, the peripheral device 404 may have a local internal clock signal for controlling the timing at which to acquire sensor data from the sensor 430, wait for a polling request from the wireless interface 406, transmit the acquired data to the interface 406 in response to the polling request, etc. The dongle 450 may also have a local internal clock signal for controlling the timing at which to send a polling request for sensor data to the peripheral devices 404, process and store the sensor data, etc. The host device 412 may also have a local internal clock signal for controlling the timing at which to send a data read request to the endpoint device 414 of the dongle 450.

[0088] The host device 412, the dongle 450, and the peripheral device 404 may each receive or generate a local internal clock signal from a clock signal source. Fig. 5 illustrates examples of generating local internal clock signals for the host device 412, the dongle 450, and the peripheral device 404. In the example of Fig. 5, the host device 412 within the computer system 460 may receive a set of nominally periodic interrupt signals 502 (e.g., start-of-frame (SOF) interrupts in USB). The interrupt signals 502 may, for example, be provided by the hardware processor 402 and embodied as a host device clock signal 504. An SOF interrupt may cause the host device 412 to send a read request to the endpoint device 414 via the bus 415. Additionally, the dongle 450 may include a local oscillator 506 that may output an oscillator signal 507 at a relatively high frequency. The oscillator signal 507 may be processed by a frequency divider 508, which may perform frequency division of the oscillator signal 507 to generate a dongle clock signal 510 having a frequency lower than the frequency of the oscillator signal 507.The dongle reference clock signal 510 can be used to adjust the timing of operations at the wireless interface 406, the endpoint device 414, and the control processor 416. Furthermore, the peripheral device 404 can also include a local oscillator 516, which can also output an oscillator signal 517 at a relatively high frequency. The oscillator signal 517 can be processed by the control processor 432 to generate a set of nominally periodic interrupt signals 522 (e.g., radio notification interrupt signals 522), which can be embodied as the peripheral clock signal 524 and used to adjust the timing of operations at the wireless interface 410 and the sensor 430. For example, the wireless interface 410 can be controlled by the control processor 432 to enter a receiver mode (e.g.,an RX mode) to wait for a polling request from the wireless interface 406 in response to a radio message interrupt signal. Need to synchronize wireless data transmission with wired data transmission

[0089] Typically, the clock periods of the peripheral device clock signal 524, the dongle reference clock signal 510, and the host device clock signal 504 are identical, and a data transfer operation can occur in each clock cycle. Fig. 6A illustrates an example of the timing of data transfers between the peripheral device 404 and the host device 412 via the endpoint device 414. In the example of Fig. 6A, the horizontal axes represent the time axis. The peripheral clock signal 520, the dongle clock signal 510, and the host device clock signal 504 each have the same period T. For the peripheral device 404, a first cycle of the peripheral clock signal 520 may be defined by clock edges 602a and 602b arriving at times T1 and T1+T, respectively, and a second cycle of the peripheral clock signal 520 may be defined by clock edges 602b and 602c. Clock edge 602c arrives at time T1+2T. Each of the clock edges 602a, 602b, and 602c may correspond to a radio message interrupt signal. Additionally, at endpoint device 414, a first cycle of dongle clock signal 510 may be defined by clock signal edges 604a and 604b arriving at time T2 and T2+T, respectively. A second cycle of dongle clock signal 510 begins at time T2+T.Furthermore, at host device 412, a first cycle of host device clock signal 504 may be defined by clock signal edges 606a and 606b. A second cycle of host device clock signal 504 begins at time T3+T. Clock signal edges 606a and 606b may correspond to SOF interrupts.

[0090] At the peripheral device 404, the control processor 432 receives a first set of sensor data (sensor data 610) from the sensor 430 after a fixed delay d1 from time T1 (and within the first cycle of the peripheral device clock signal 520) and processes the sensor data 610 (e.g., generating data packets, etc.) in preparation for wireless transmission before the arrival of the clock signal edge 602b. Furthermore, the control processor 416 of the dongle 450 may drive the wireless interface 406 after a fixed delay d2 from time T2 (and within the first cycle of the clock signal 510) to initiate the acquisition of sensor data from the peripheral device 404, for example, by sending a polling request 612. The peripheral device 404 may receive the polling request and transmit sensor data 610 to the endpoint device 414.The control processor 416 of the dongle 450 then receives the data 610 and provides the data 610 to the endpoint device 414, which may process the sensor data 610 and store it in local memory before the clock edge 606b arrives. At time T3+T (second cycle of the host device clock signal 504), the host device 412 may send a read request to the endpoint device 414 (of the dongle 450) in response to receiving an SOF interrupt (represented by the clock edge 602b). The endpoint device 414 may receive the read request and provide the sensor data 610 to the host device 412 in response to the read request. Meanwhile, the control processor 432 of the peripheral device 404 may receive a second set of sensor data (sensor data 614) from the sensor 430 within the second cycle of the peripheral device clock signal 520.The sensor data 614 may be transmitted to the dongle 450 on a subsequent cycle of the peripheral clock signal 520.

[0091] In the example of Fig. 6A, host device 412 may obtain the sensor data received from peripheral device 404 within approximately one cycle period of host device clock signal 504, which may correspond to a minimal delay. The reduction in delay may be attributed, for example, to endpoint device 414 initiating the acquisition of sensor data from peripheral device 404 after peripheral device 404 has received the last cycle's sensor data, and endpoint device 414 receiving the read request from host device 412 after endpoint device 414 has received the last cycle's sensor data from peripheral device 404. Reducing the delay in data transmission between peripheral device 404 and host device 412 is highly desirable to enable computer system 460 to respond more quickly to user input.Without a synchronization scheme to synchronize the operations at the peripheral device 404, the dongle 450, and the host device 412, the relationship between the times at which the endpoint device 414 initiates the collection of sensor data, the peripheral device 404 receives sensor data, and the host device 412 sends read requests may change. This timing relationship may change due to uncertainties in the timing of the clock signals, such as clock jitter, clock drift, etc. As a result, the delay in data transfer between the peripheral device 404 and the host device 412 may increase, or the host device 412 may skip / miss one or more instances of sensor data. All of this may degrade the ability of the computer system 460 to track user inputs and impair the user experience.

[0092] Fig. 6B and Fig. 6C illustrate examples of uncertainties in the timing of the clock signals, which can increase the system response time or cause sensor data to be skipped. Fig. 6B illustrates an example of how the host device 412 skips one or more instances of sensor data. In the example of Fig. 6B, an SOF interrupt (represented by clock edge 606b) may arrive at T3+T', which is before T3+T. The early arrival of the SOF interrupt causes host device 412 to send a sensor data read request at a time when dongle 450 cannot process the read request. For example, endpoint device 414 may be receiving data 610 from control processor 416 at time T3+T', so it cannot respond to the read request. Host device 412 may therefore skip sensor data 610. If subsequent SOF interrupts (and host device read requests) continue to arrive at times when endpoint device 414 is unable to process host device 412 read requests, host device 412 may also skip additional sensor data (e.g., sensor data 614) received from peripheral device 404 later.

[0093] Fig. Figure 6C illustrates an example of an increase in system response time. In the example of Fig. 6C, an SOF interrupt (represented by clock signal edge 606b) may arrive at T3+T'', i.e., after T3+T. Endpoint device 414 does not receive a read request at time T3+T (and in a second cycle of dongle clock signal 510) and may send another poll request 622 to peripheral device 404 and obtain sensor data 614. Endpoint device 414 may also add sensor data 614 to the sensor data stored in local memory. If endpoint device 414 receives a read request at time T3+T'', it may transfer both sensor data 610 and sensor data 614 to host device 412.

[0094] In the two examples of Fig. 6B and Fig. 6C, the hardware processor 402 may respond late or not at all to the user inputs captured by the sensor data 610, both of which are undesirable. In the example of Fig. 6B, for example, the host device 412 skips / misses the sensor data 610 and cannot provide the sensor data 610 to the hardware processor 402, so that the hardware processor misses the user inputs captured by the sensor data 610. In the example of Fig. 6C, although the hardware processor 402 receives sensor data 610 (and sensor data 614), the delay between the time the sensor data 610 is received from the peripheral device 404 and the time the sensor data 610 is received by the hardware processor 402 is compared to Fig. 6A is larger. As a result, the response of the hardware processor 402 to the user input may be delayed. Both of these factors impair the speed with which the computer system responds to the user input. Synchronization of a wireless data transmission with a wired data transmission

[0095] Fig. Figure 7A illustrates an example of synchronization between the dongle 450 and the host device 412. In the example of Fig. 7A, the endpoint device 414 may synchronize the retrieval of sensor data from the peripheral device 404 with both the dongle clock signal 510 and the host device clock signal 504 (or SOF interrupts 502) so that sensor data may be retrieved and made available to service a subsequent read request from the host device 412 in a subsequent cycle of the host device clock signal 504.

[0096] Specifically, the control processor 416 may obtain information about the host device clock signal 504, for example, based on SOF interrupt signals 502, data packets (e.g., SOF packets), etc., that the endpoint device 414 receives from the host device 412. The control processor 416 receives an indication from the endpoint device 414 that an SOF interrupt signal or an SOF packet is received and, based on the indication, may derive the timing of the clock signal edge 706a of the host device clock signal 504. Assuming that the control processor 416 determines that the clock edge 706a arrives at time T3 within a first cycle of the dongle clock signal 510 (defined by the clock edges 704a and 704b at times T2 and T2+T), the control processor 416 may synchronize the transmission of certain signals to the peripheral device 404 relative to time T3. For example, the control processor 416 may control the endpoint device 414 to transmit a (in Fig. 7A) to the peripheral device 404 to establish a wireless connection with the peripheral device. As another example, the control processor 416 may initiate the acquisition of sensor data by, for example, sending a polling request to the peripheral device 404. Both the transmission of the connection request acknowledgment and the polling request may occur after a predetermined delay 710 from the clock signal edge 706a, such that the transmission of the connection request acknowledgment and the polling request are synchronized with the clock signal edge 706a (and with the host device clock signal 504).

[0097] In some examples, the delay 710 may be determined, for example, based on the duration of a processing time 720 that includes sending a polling request 712 to the peripheral device 404, receiving sensor data 714 from the peripheral device 404, and processing and storing sensor data 714 at the endpoint device 414. The delay 710 may also be determined based on when the next clock signal edge 704b of the dongle clock signal 510 is expected. In the example of Fig. 7A, the control processor 416 may determine a period 740 elapsed between the clock edge 706a of the host device clock signal 504 and the clock edge 704b of the dongle clock signal 510 and obtain a delay 710 based on the following equation: Delay 710 = Period 740 − Processing time 720

[0098] In such arrangements, the control processor 416 may adjust the timing of transmission of a polling request to account for a change in the timing of the host device clock signal 504, thereby allowing the wired data transfer between the endpoint device 414 and the host device 412 to be synchronized with the host device clock signal 504. For example, the endpoint device 414 may send a polling request at a predetermined time, the timing being determined so that sensor data can be collected and processed before the next read request is received from the host device 412 when the clock signal edge 706b of the host device clock signal 504 arrives at time T3+T.Furthermore, by determining the delay 710 also with respect to the dongle clock signal 510 (based on the determination of the time period 740), the transmission of the polling request can also be synchronized with the dongle clock signal 510, which determines the timing for other operations of the dongle 450 (e.g., wireless interface 406), thereby supporting correct operations on the dongle 450.

[0099] In addition, the control processor 416 may also control the peripheral device 404 to synchronize acquisition of sensor data from the sensor 430 with the host device clock signal 504. Through such arrangements, the peripheral device 404 may provide the most recent sensor data when the endpoint device 414 initiates the acquisition of sensor data, the timing of which is also synchronized with the host device clock signal 504 as described above. In the example of Fig. 7A, the control processor 416 may control the peripheral device 404 to initiate the process 760 for obtaining and processing sensor data from the sensor 430 in the period 750 prior to the expected receipt of the polling request 712 at time T1, which may correspond to the clock edge 702a of the peripheral device clock signal 524. Because the transmission of the polling request 712 is synchronized with the host device clock signal 504 (e.g., delayed by a period 710 from the clock edge 706a of the host device clock signal 504), the timing of the process 760 at the peripheral device 404 may thereby also be synchronized with the host device clock signal 504. In some examples, the period 750 may be determined based on, for example, the total time required for the peripheral device 404 to obtain sensor data from the sensor 730 and prepare the sensor data for transmission (e.g.,Processing delay, time to generate packets for wireless transmission, etc.).

[0100] There are various ways in which the control processor 416 can control the peripheral device 404 to synchronize the acquisition of sensor data from the sensor 430 with the clock signal edge 706a of the host device clock signal 504. In some examples, the control processor 432 of the peripheral device 404 can synchronize the generation of radio reporting interrupt signals 522 (which can be used to generate the peripheral clock signal 524) with the receipt of various signals from the endpoint device 414 based on a predetermined configuration. For example, the control processor 432 can determine the timing for the generation of radio reporting interrupts based on the times at which the connection request acknowledgment and polling requests are received from the dongle 450. The control processor 432 can trigger the generation of radio reporting interrupts upon receiving the acknowledgment message and polling requests.The control processor 432 may also predict when the dongle 450 is likely to send the next poll request based on the timing of the previous poll requests. The peripheral device 404 may generate the next radio message interrupt and wait for the next poll request at the predicted time. Furthermore, within one cycle of the peripheral device clock signal 504 (e.g., as defined by times T1-T and T1), the control processor 432 may initiate the process 760 for obtaining and processing sensor data from the sensor 430 during the period 750 prior to the time the next radio message interrupt is generated (e.g., at time T1).

[0101] Furthermore, the control processor 416 (of the dongle 450) may also transmit timing information indicating a timing adjustment value (e.g., a change in the delay time 710) to be applied to the transmission of a subsequent polling request as a standalone message over a radio channel to the peripheral device 404. Through the standalone message, the control processor 432 of the peripheral device 404 can adjust the timing at which the sensor data is obtained (e.g., by adjusting the time period 750) and the timing at which to wait for a next polling request (e.g., by adjusting when to generate the next radio message interrupt) before receiving the next polling request, thereby enabling the peripheral device 404 to respond more quickly to changes in the timing of the host device clock signal 504. As shown in Fig. For example, as shown in Figure 7A, the control processor 416 (of the dongle 450) may determine whether the timing of the clock edge 706a of the host device clock signal 504 deviates from an expected timing. The control processor 416 may also determine a timing adjustment value to be applied to the transmission of a next polling request to account for the changes in timing and transmit the timing adjustment value immediately after time T3. The control processor 432 of the peripheral device 404 may receive the timing adjustment value via the standalone message in a first cycle of the peripheral device clock signal 520 (defined by times T1-T and T1) and determine the time (T1) at which the next polling request arrives based on the timing adjustment value. The control processor 432 may also determine the start time of the process 760 (to obtain and process sensor data from the sensor 430) by subtracting the period 750 from the time T1.At time T1, the control processor 432 may control the wireless interface 410 to enter RX mode to wait for the polling request 712 and transmit the data 714 to the dongle 450.

[0102] There are various ways in which the control processor 416 can detect and measure changes in the timing of the host device clock signal 504. For example, the control processor 416 can record the timing at which the previous clock signal edges of the host device clock signal 504 (or the SOF interrupts 502) were received. The record can be stored, for example, in the memory array 220 of Fig. 2. The control processor 416 may determine a nominal or average period of the host device clock signal 504 based on the recording and predict when a future clock edge of the host device clock signal 504 (or a future SOF interrupt) is expected to arrive based on the period and the time at which the last clock edge was received. Changes in timing may be detected if the clock edge arrives at a different time than the predicted arrival time, and the control processor 416 may determine the timing adjustment value based, for example, on a difference between the actual arrival time and the predicted arrival time of the clock edge.

[0103] As another example, the control processor 416 may also monitor a phase relationship between the host device clock signal 504 and a reference clock signal. The reference clock signal may, for example, include the dongle clock signal 510 or a dedicated reference clock signal generated by the local oscillator 506 and not used by other components of the dongle 450. A dedicated reference clock signal may be provided to reduce the likelihood that the reference clock signal will be corrupted by jitter, which may affect the accuracy of the phase relationship measurement. In some examples, the control processor 416 may record a phase relationship between the host device clock signal 504 and the reference clock signal and detect changes in the timing of the host device clock signal 504 based on changes in the phase relationship.The control processor 416 may determine a timing adjustment value based, for example, on a difference between the last phase relationship between the host device clock signal 504 and the reference clock signal and a previous phase relationship between the two clock signals. The timing adjustment value may then be used in a resynchronization process to change the timing of operations on the dongle 450 and the peripheral device 404 in response to the change in the timing of the host device clock signal 504.

[0104] In some examples, the control processor 416 may also indicate in the standalone message to the peripheral device 404 when the peripheral device 404 should apply the timing adjustment value. As shown in Fig. For example, as shown in Figure 7B, clock edge 706a of host device clock signal 504 arrives after peripheral device 404 has initiated process 760 to obtain and process sensor data from sensor 430. The timing of process 760 (which has already begun) cannot be adjusted via clock edge 706a. In this case, control processor 416 may defer the timing adjustment on both dongle 450 and peripheral device 404 to the next cycle. For example, control processor 416 may determine whether clock drift is occurring based on the timing of clock edge 706a received in the first cycle of dongle clock signal 510 (between times T2 and T2+T). The clock drift may result in a change in the period of host device clock signal 504.The control processor 416 may determine a timing adjustment value Ta that accounts for the clock drift and update the estimated arrival time of the next clock edge 706b of the host device clock signal 504, e.g., T3+T+Ta. The control processor 416 may adjust the time to send a next poll request 722 in the second cycle of the dongle clock signal 510 (from time T2+T) based on the estimated arrival time of the next clock edge 706b (e.g., by adding the period 710).

[0105] In some examples, the control processor 416 may perform additional processing before resynchronizing its operations (and the operations on the peripheral device 404) with the host device clock signal 504. The additional processing may be configured to reduce the number of instances of the resynchronization processes, which may improve the stability of the operations on the dongle 450 and the peripheral device 404. In some examples, the control processor 416 may determine whether the change in the timing of the host device clock signal 504 exceeds a threshold and perform the resynchronization process (e.g., changing the timing for transmitting a polling request and transmitting the timing adjustment value to the peripheral device 404) if the change in timing exceeds the threshold.In some examples, the control processor 416 may also average a number of previous instances of changes in the timing of the host device clock signal 504 (e.g., based on a number of previous clock edges of the host device clock signal 504) and resynchronize when the average change (rather than just one instance) in timing exceeds a threshold. Such arrangements allow the system to respond only to a relatively large and long-term change in the timing of the host device clock signal 504 (e.g., caused by clock drift) while ignoring other smaller and short-term changes in the timing of the host device clock signal 504 (e.g., caused by clock jitter) to reduce disruption to the operations of the dongle 450 and peripheral 404.

[0106] Additionally, the control processor 416 may request the peripheral device 404 in the standalone message to update the timing of a new process 770 for obtaining sensor data 780 in the second cycle of the peripheral device clock signal 520 based on the timing adjustment value. After receiving the standalone message, the control processor 432 of the peripheral device 404 may update the estimate of when the polling request 722 (time T1+T) is expected to be received based on the timing adjustment value and update the timing of the process 760 to start within a period 750 prior to time T1+T at which the polling request 722 is received. At time T1+T, the control processor 432 may generate a radio message interrupt corresponding to the clock edge 702b of the third cycle of the peripheral device clock signal 520.The control processor 432 may control the wireless interface 410 to enter RX mode to receive the polling request 722 from the dongle 450 and then transmit the data 780 to the dongle 450 in response to the polling request 722.

[0107] In some examples, control processor 416 may include additional information in the message in addition to a timing adjustment value and the time at which the timing adjustment value should be applied. For example, the message may include an opcode indicating to processor 432 that the message is for peripheral device 404 (and not other peripheral devices) and containing timing adjustment information. The message may also include a measurement of random uncertainties (e.g., jitter) of host device clock signal 504 (e.g., in units of parts per million (ppm)). The measurement information may be obtained, for example, from host device 412 (and / or hardware processor 402). In some examples, control processor 416 may also perform statistical analysis on a recording of clock signal periods of host device clock signal 504 to obtain the measurement uncertainties. Synchronization of multiple peripheral devices

[0108] In some examples, the dongle 450 may be configured to receive sensor data from multiple peripheral devices and provide the sensor data to the hardware processor 402 of the computer system 460. From the example of Fig. 1 also shows that the dongle 450 can receive sensor data from a variety of peripheral devices, including, for example, the computer mouse 130, the keyboard 140, and the microphone 150, to provide the user with the ability to interact with the host computing device 110 using different methods.

[0109] In some examples, dongle 450 may be configured to communicate with computer mouse 130, keyboard 140, and microphone 150, each using a time-division multiplexing (TDMA) method, where dongle 450 establishes a wireless connection using wireless interface 406 (and wireless transceiver 413) with each peripheral simultaneously, but initiates the acquisition of sensor data at each peripheral at different times. The initiation of the acquisition of sensor data from each peripheral may also be synchronized with host device clock signal 504 and dongle clock signal 510. Fig. Figure 8 illustrates an example of a TDMA method. In Fig. 8, the dongle 450 may initiate the acquisition of sensor data from the peripheral device 802 within a first cycle of the dongle clock signal 510 (defined by T2 and T2+T) by sending a polling request 808 over a wireless connection. The transmission of the polling request 808 may occur after a delay 810 from the clock signal edge 706a (at time T3) of the host device clock signal 504. The dongle 450 may also initiate the acquisition of sensor data from the peripheral device 804 within the first cycle of the dongle clock signal 510 by sending the polling request 818 over another wireless connection. The transmission of the polling request 818 may occur after a delay 820 from the clock signal edge 706a. Both peripheral devices 802 and 804 may also interrupt their operations (e.g.,The dongle 450 may synchronize its actions (e.g., generating radio message interrupts, collecting sensor data, entering RX mode to wait for polling requests, transmitting sensor data, etc.) with the polling requests received from the dongle 450 (and with the host device clock signal 504) and transmit sensor data (e.g., sensor data 828 from the peripheral 802, sensor data 838 from the peripheral 804) back to the dongle 450 at different times in response to the respective polling requests 808 and 818. The dongle 450 may receive the data 828 and 838 and process the data before the second cycle of the dongle clock signal 510 arrives at time T2+T. The host device 412 may send a read request at time T3+T, and the dongle 450 may transmit the data 828 and 838 acquired from the peripherals 802 and 804 to the host device via the bus 415.

[0110] As explained above, delays 810 and 820 may be used to schedule the initiation of a sensor data acquisition (e.g., by sending a polling request) from each peripheral device so that the peripheral devices can each alternately transmit sensor data to the dongle 450. In the example of Fig. 8, in order to synchronize the sending of polling requests with the dongle clock signal 510 (in addition to the host device clock signal 504), the dongle 450 may determine both the delay 810 and the delay 820 based on the processing time 830 (for sending the polling request 808 and receiving data 828), the processing time 840 (for sending the polling request 818 and receiving data 838), the processing delay 850 (for processing the data 828 and 838), and the timing of the clock signal edge 704b of the dongle clock signal 510 (which initiates the second cycle of the dongle clock signal 510). For example, assuming that the clock edge 706a of the host device clock signal 504 and the clock edge 704b of the dongle clock signal 510 are separated by a period 860, the delays 810 and 820 can be determined based on the following equations: Delay 810=Period 860−Processing time 830−Processing time 840−Processing time 850 Delay 820=Period 860−Processing time 840−Processing time 850

[0111] To reduce signal interference and collisions between peripherals 802 and 804, one of the peripherals may be configured to stop transmitting radio signals when the other peripheral is communicating with dongle 450. For example, peripheral 804 may be configured to maintain radio silence and not transmit radio signals when peripheral 802 is sending data 828 to dongle 450. In some examples, the wireless interface of each peripheral may only be turned on (to enter RX mode, wait for a polling request, and send sensor data in response to the polling request) within a certain period of time after receiving the radio polling interrupt signal, and must be turned off outside of this period to avoid interference or collisions with other peripherals that are in the middle of transmitting sensor data to dongle 450.

[0112] Furthermore, the Fig. The TDMA method and polling scheme described in Figure 8 may be used to enable prioritization of peripheral devices. Prioritization may be useful for processing input data transmitted by peripheral devices associated with different applications that may have different delay requirements. For example, peripheral device 802 may be a computer mouse used to control a gaming application, which may require the computer system to respond in real time to the input data provided by peripheral device 802 and cannot tolerate higher latency for data transmission to host device 412. On the other hand, peripheral device 804 may be a speaker for an audio streaming application.The speaker may have a buffer for storing the audio data to be played and may tolerate a higher latency for data transmission from the host to the speaker (unless the buffer is emptied). In this example, the transmission of input data from the computer mouse to the host device 412 may be prioritized over the transmission of output data from the host device 412 to minimize the latency for data transmission from the peripheral device 802 to the host device 412.

[0113] To perform prioritization, within the time period 860, the polling request for peripheral 802 may be transmitted first (and synchronized with the clock signal edge 706a of the host device 412), followed by the polling request for peripheral 804. Such arrangements may reduce the delay between acquiring sensor data (e.g., data 828) at peripheral 802 and transmitting the sensor data to dongle 450. On the other hand, polling of peripheral 804 may be performed after dongle 450 has received the input data (e.g., data 828) from peripheral 802.The polling may also be synchronized with the clock signal edge 706a of the host device 412, however, the processing time 830 for polling and receiving data from the peripheral device 802 may contribute to the delay between the time the peripheral device 804 collects sensor data and the time the sensor data is transmitted to the dongle 450. A dongle with multiple transceivers

[0114] Even though the TDMA method and the query scheme of Fig. 8 allow the dongle 450 to receive sensor data from multiple peripherals, despite improving data transmission delay with the synchronized polling techniques described above, the polling scheme can pose challenges in several ways for wireless data transfer between the peripherals and the dongle.

[0115] First, the number of peripherals connected to the dongle 450 may be limited. For example, with a dongle 450, as again shown in Fig. As can be seen in Figure 8, the time period 860 between two clock edges of the host device 412 (clock edges 706a and 706b) for polling and receiving data from each peripheral is finite. Polling and receiving data requires a finite processing time for each peripheral (e.g., processing time 830 for peripheral 802, processing time 840 for peripheral 804, etc.), and the finite time period 860 may impose an upper limit on how many peripherals can be polled consecutively and data transferred to the dongle 450 within the time period 860. For example, the sum of the processing times (e.g., processing times 830, 840, 850, etc.) at each peripheral device must not exceed the period 860 so that the dongle 450 can receive and process the input data from each of the polled peripheral devices before the next clock edge (e.g., clock edge 704b) of the dongle clock signal arrives.Limiting the number of peripherals that can be wirelessly connected to the Dongle 450 can have a significant impact on the user experience. For example, the Dongle 450 may be used on a system with a very limited number of USB ports, so the system can only be connected to a single Dongle 450, which in turn can only be wirelessly connected to a limited number of peripherals. If the number of peripherals that can be wirelessly connected to the Dongle 450 is small, the user's ability to interact with the system can be severely limited, not only reducing the system's usability but also impacting the user experience.

[0116] In addition, a polling scheme can result in a delay in the data transmission of each peripheral. For example, because the peripherals must each take turns waiting for the polling signal to transmit data to the dongle 450, the time spent waiting for the polling signal contributes to the data transmission delay. The delay is acceptable for some applications, but not for others. For example, the delay may be acceptable for streaming audio and video data as long as the system can buffer sufficient amounts of data being processed by the display and / or audio player while waiting for new wireless audio / video data. However, the delay may be unacceptable for an input device (e.g., a mouse, joystick, etc.) used with applications that require extremely intensive interaction between the user and the system (e.g., gaming, instrumentation control, etc.).), may be unacceptable because, to support the extremely intensive interaction between the user and the system, the input device must send new user input data as soon as the input data has been generated.

[0117] Furthermore, the use of multiple peripherals sequentially during wireless communication using a single transceiver of the dongle 450 (e.g., in a polling scheme) can also result in the data transmission at one peripheral affecting the data transmission of other peripherals. For example, if the transceiver's bandwidth is exceeded and the data transmission of one device is prioritized over other non-priority devices (e.g., by providing a larger polling window), the data transmission delay of the non-priority devices can be affected (and increased) by the prioritized devices.For example, if a gaming mouse and audio and / or video streaming devices communicate with the single transceiver present on the Dongle 450, the data transmission latency for the audio and / or video streaming devices may increase as a result of the gaming mouse prioritizing the transmission of user input data.

[0118] In some examples, to address the above-mentioned problems of a polling scheme, a dongle may use a hybrid TDMA and frequency division multiplexing (FDMA) method to process input data from multiple peripherals. For example, a dongle may be configured to include multiple wireless transceivers, each of the wireless transceivers configured to communicate with one or more peripherals over a different frequency channel. The wireless transceivers may also be associated with different peripherals (or different groups of peripherals with different delay tolerances). For example, a first wireless transceiver may be dedicated to data transmission from a user input device (e.g., a gaming mouse, an instrumentation control device, etc.).), while a second wireless transceiver can be assigned to data transmission from video and / or audio data streaming devices.

[0119] The multiple wireless transceivers allow the dongle to poll and receive input data from multiple peripherals in parallel (via FMDA) and / or sequentially (via TDMA). Parallelism increases the number of peripherals allowed to transmit input data within each host device clock cycle, while reducing the latency and data transmission delay at each peripheral. Furthermore, by assigning specific wireless transceivers to different peripherals (or different groups of peripherals), the likelihood of prioritized devices interfering with the data transmission of non-priority devices can be reduced.

[0120] Fig. 9 illustrates an example of a communication system 900 using a hybrid TDMA and FDMA system. As in Fig. 9, the communication system 900 may facilitate data transmission between the hardware processor 402 of Fig. 4 and the peripheral devices 904a, 904b and 904c (e.g., the peripheral devices 130-150). The communication system 900 may include a wireless interface 906 and, on the hardware processor 402 side (e.g., as part of the computer 110 and / or the systems 200 and 300), a wired connection 408 (from Fig. 4). The wireless interface 906 may include multiple wireless transceivers, such as transceivers 914 and 915. Each of the peripheral devices 904a-c also includes a wireless interface (in Fig. 9 not shown) to communicate with the wireless interface 906 via transceivers 914 and 915. Each transceiver may include, for example, an antenna, power amplifiers, low-noise amplifiers, mixers, analog-to-digital converters (ADCs), etc.

[0121] Data may be transferred between the hardware processor 402 and the peripheral devices 904a-c via the wireless interface 906 and the wired connection 408. The wireless interface 906 and the endpoint device 414 may be part of a dongle 950. The dongle 450 may further include a control processor 916 to control operations at the wireless interface 906 and the endpoint device 414, including, for example, operations for transferring data between the hardware processor 402 and the peripheral devices 904a-c. The dongle 450 may form one or more piconets with the peripheral devices 904a-c and receive sensor data from each of the peripheral devices during multiple connection events.The control processor 916 may control the transceivers 914 and 915 of the wireless interface 906 to perform wireless data transmission with the peripherals 904a-c based on the same wireless protocol or different wireless protocols, such as Bluetooth®, BLE, etc. The control processor 916 may also synchronize the wireless data transmission with the host device clock signal 504 based on the techniques described above. Even if . Fig. 9 shows that the control processor 916 is a single unit, it is understood that the control processor 916 may comprise multiple units, some of which may be part of the transceiver 914 and the transceiver 915.

[0122] In some examples, the control processor 916 may control the transceivers 914 and 915 to perform wireless data transmission with at least some of the peripheral devices 904a-c in parallel. Fig. Figure 10 illustrates an example of wireless data transmission between the dongle 950 and the peripheral devices 904a-c. As shown in Fig. 10, the control processor 916 (of the dongle 950) may perform a wireless data transmission with the peripheral device 904a using the wireless transceiver 914 between times T1 and T2. The control processor 916 may also perform a wireless data transmission with the peripheral device 904b using the wireless transceiver 915 between times T1 and T2, and with the peripheral device 904c using the wireless transceiver 915 between times T2 and T3.

[0123] Further, to reduce the likelihood of signal collision and interference, control processor 916 may configure transceivers 914 and 915 to operate in an FDMA scheme using different radio carrier frequencies to perform parallel wireless data transmission between times T1 and T2. In some examples, control processor 916 may configure transceivers 914 and 915 to use different frequency hopping sequences to perform wireless data transmission, such that different radio carrier frequencies are used at transceivers 914 and 915 to perform data transmission at any given time.For example, the wireless data transmission operations may include, at dongle 950, sending a polling request and thereby receiving sensor data, at peripheral devices 904a-c, entering RX mode to wait for a polling request and sending sensor data in response to the polling request, etc. In some examples, a TDMA method may also be used, so that transceivers 914 and 915 may be used to communicate with different peripheral devices at different times over the same radio carrier frequency.

[0124] In some examples, transceivers 914 and 915 may be controlled by separate control circuits (enclosed in a single dongle) and / or may be part of two different dongles and connected to two different endpoint devices. For example, as described above, some of the components / units of control processor 916 may be incorporated into transceivers 914 and 915. The two endpoint devices may be connected to a single host device or separate host devices. The two control circuits may be configured to initiate the same frequency hopping sequences (e.g., using the same seed value to generate a set of frequency values) on the two transceivers, which may result in signal collisions and interference on the two transceivers.To efficiently reduce signal collisions and interference, the two control circuits may be synchronized with each other to determine the frequency hopping sequences for the respective transceivers before or during wireless data transmission with the peripherals via an information exchange process. For example, during commissioning, the control circuit for the transceiver 914 may transmit a frequency hopping sequence to the control circuit for the transceiver 915 to be implemented on the transceiver 914. The control circuit for the transceiver 915 may further transmit the frequency hopping sequence for the transceiver 915 to the control circuit for the transceiver 914. In some examples, the information exchange may occur wirelessly across the transceivers. In some examples, the information exchange may occur over a wired connection between the two transceivers.One of the control circuits / endpoint devices (e.g., for transceiver 914) may adjust its frequency hopping sequence based on the received information, for example, to use a frequency hopping sequence that does not overlap with the frequency hopping sequence of the other transceiver at any time, so as to reduce frequency overlap and avoid environmental interference.

[0125] In some examples, one of the control circuits / endpoint devices may further monitor for interference during wireless data transmission and, upon detecting significant interference, exchange frequency hopping sequence information with the other control circuit / endpoint device so that the other control circuit / endpoint device can update its frequency hopping sequence to reduce interference. In some examples, both the control circuit and the endpoint device may adjust their respective frequency hopping sequences based on the exchanged information to accelerate the synchronization process, allowing the respective frequency hopping sequences to be set on both transceivers to start (or restart) wireless data transmission as quickly as possible.Fast, device-independent adaptation of frequency hopping sequences on the transceivers can be critical for applications that require extremely intensive interaction between the user and the computer (e.g., game control, instrumentation control, etc.) and where tolerance for a lack of response from the computer (e.g., due to signal interference) may be low. For example, if a first transceiver is used for lower-priority applications (e.g., streaming audio / video data) and a second transceiver is used to receive input data for high-speed games, it is unfavorable if the first transceiver interrupts the second transceiver's wireless data transmission due to a collision.Through the information exchange process, the second transceiver can quickly adjust its frequency hopping sequence based on the frequency hopping sequence used by the first transceiver, so that the interruption of wireless data transmission at the second transceiver for the higher-level gaming application can be minimized.

[0126] The hybrid TDMA and FDMA method of Fig. 10 may also incorporate the techniques described above to reduce data transfer latency and enable prioritization between peripherals. For example, the sending of polling requests and the receiving of data from the peripherals, as well as the sending of data by the peripherals, may be synchronized with the host device clock signal 504. Furthermore, higher-priority peripherals may be polled first within a cycle of the host device clock signal, followed by lower-priority peripherals. Fig. 10, for example, peripherals 904a and 904b may have a higher priority than peripheral 904c, and peripherals 904a and 904b may be polled before peripheral 904c.

[0127] Compared to the TDMA method of Fig. 8, where the peripherals must communicate with the dongle sequentially via the dongle's single wireless transceiver, the parallel wireless data transmission enabled by multiple transceivers 914 and 915 can reduce the latency at each peripheral before the peripheral sends sensor data, thereby further reducing the delay in transmitting sensor data to the hardware processor 402. Such arrangements can improve the ability of a computer system to track user inputs, which can lead to a better user experience. Proceedings

[0128] Fig. 11 shows a simplified flowchart for a method 1100 for performing a wireless data transmission, according to some examples. The method 1100 may be executed using processing logic that may include hardware (circuitry, specialized logic, etc.), software running on suitable hardware (e.g., a general-purpose computer system or a specialized device), firmware (embedded software), or any combination thereof. In some examples, the method 1100 may be performed by, for example, an endpoint device (e.g., endpoint device 414) and a peripheral device (e.g., peripheral device 404) of the Fig. 4. Endpoint devices may be connected to a host device via a hardware connection, including, for example, a USB bus. The method 1100 may be implemented with the methods described above, for example, with respect to Fig. 7A, Fig. 7B and Fig. 8 - Fig. 10 described techniques can be implemented.

[0129] At step 1110, method 1100 may include receiving a first indication of a host device clock signal from the host device at an endpoint device. For example, the first indication may include a start-of-frame (SOF) signal that may be synchronized with a rising edge of the host device clock signal. The first indication may also be based on the receipt of an SOF data packet.

[0130] At step 1120, the method 1100 may include determining a phase relationship between the host device clock signal and an endpoint clock signal based on the first indication and a second indication of the endpoint clock signal. The second indication may be a first rising edge of the endpoint clock signal after the rising edge of the host device clock signal corresponding to the first indication. The phase relationship may, for example, correspond to the period 740 of Fig. 7A and Equation 11.

[0131] At step 1130, the method 1100 may include determining a first time point for transmitting a sensor data request, such as a polling request, to a peripheral device based at least on the phase relationship. By determining the first time point, the transmission of the sensor data request may be adjusted to account for the change in timing for the host device clock signal, thereby synchronizing the data transfer between the endpoint device and the host device with the host device clock signal. The first time point (e.g., delay 710 of Fig. 7A) can, for example, be based on a total processing time of the sensor data request at the peripheral device (e.g., processing time 720 of Fig. 7A) and equation 12.

[0132] At step 1140, the method 1100 may include obtaining sensor data at the peripheral device at a second time determined based on a delay associated with obtaining the sensor data and the time at which the sensor data request is expected to arrive from the endpoint device. The delay may, for example, be the period 750 from Fig. 7A. In some examples, the period 750 may also be determined based on the expected timing of the arrival of the sensor data request (e.g., polling request) from the endpoint device, so that sensor data collection may be completed prior to the arrival of the polling request to synchronize the operation of the peripheral with the endpoint device (and with the host device). For example, the expected timing of the arrival of the sensor data request may be determined based on the receipt of acknowledgment signals from the endpoint device during establishment of the wireless connection between the endpoint device and the peripheral device, if sensor data requests have been previously received from the endpoint device, etc. The period 750 may also be adjusted based on a timing adjustment value received from the endpoint device as part of a standalone message.The timing adjustment value may, for example, be a change in the time to transmit the sensor data query (e.g., delay 710 from . Fig. 7A) at the endpoint device, which is caused, for example, by the drift of the host device clock signal during synchronization between the peripheral device, the endpoint device and the host device.

[0133] At step 1150, method 1100 may include the endpoint device wirelessly transmitting the sensor data request to the peripheral device at the first time. The wireless transmission may be based, for example, on the BLE protocol, in which a wireless transceiver is connected to the endpoint device.

[0134] At step 1160, method 1100 may include receiving the sensor data request at the peripheral device. The peripheral device may enter an RX mode to wait for the sensor data request (e.g., a poll request) at the beginning of a peripheral device clock period indicated by a radio message interrupt signal and receive the sensor data request at step 1160.

[0135] At step 1170, method 1100 may include the peripheral device wirelessly transmitting the requested sensor data to the endpoint device. The wireless transmission may be based, for example, on the BLE protocol, which uses a wireless transceiver included in the endpoint device.

[0136] At step 1180, method 1100 may include receiving the requested sensor data at the endpoint device in response to the sensor data request transmitted at step 1150. The endpoint device may provide the sensor data to the host device, for example, by storing the sensor data in a register accessible by the host device at step 1190 prior to the start of the next host device clock cycle.

[0137] Fig. 12 shows a simplified flowchart for the method 1200 for performing a wireless data transfer between a computer and multiple peripheral devices, according to some examples. The method 1200 may be performed using processing logic that may include hardware (circuitry, specialized logic, etc.), software running on suitable hardware (e.g., a general-purpose computer system or a specialized device), firmware (embedded software), or any combination thereof. In some examples, the method 1200 may be performed, for example, by a single endpoint device of a single dongle (e.g., endpoint device 414 of dongle 950 of Fig. 9), and the single endpoint device is connected to a host device of the computer via a single connection (e.g., a USB bus). In some examples, the method 1200 may also be performed by multiple endpoint devices of a single dongle or multiple dongles, each of the multiple endpoint devices being connected to a host device via a connection. The method 1200 may, for example, be performed using the methods described above with reference to Fig. 7A, Fig. 7B and Fig. 8 - Fig. 10 described techniques can be implemented.

[0138] At step 1210, method 1200 may include establishing a first radio channel with a first peripheral device using a first transceiver of a first endpoint device, wherein the first endpoint device is connected to a host device via a first connection. The first radio channel may be a BLE radio channel.

[0139] At step 1220, method 1200 may include establishing a second radio channel with a second peripheral device using a second transceiver of a second endpoint device, wherein the second endpoint device is connected to the host device via a second connection. The second radio channel may also be a BLE radio channel.

[0140] In some examples, the two radio channels may be configured with the same set of carrier frequencies, and the two transceivers may be controlled to transmit and receive data over the radio channels according to a time-division multiple access (TDMA) method using a carrier frequency, wherein the first sensor data and the second sensor data are received by the endpoint device within different transmission periods. In some examples, the two radio channels may be configured using different sets of carrier frequencies. The two transceivers may be controlled to transmit and receive data over the radio channels according to a frequency-division multiple access (FDMA) method. In some examples, the two transceivers may also be controlled to transmit and receive data over the radio channels according to a hybrid TDMA and FDMA method.For example, the two transceivers can also be controlled to send and receive data over the radio channels using different frequency hopping sequences, so that the two transceivers use carriers of different frequencies to send and receive data at any given time, for example, but the two transceivers can also use carriers of the same frequency to send and receive data, albeit at different times.

[0141] In some examples, the two wireless transceivers may be controlled by a single endpoint device and / or a single control circuit such that the first endpoint device and the second endpoint device are identical, and the first connection and the second connection are identical, where the single endpoint device can coordinate the establishment of the radio channels on the two wireless transceivers to minimize overlap and interference between the two radio channels. In some examples, the two wireless transceivers may be controlled by two separate endpoint devices, and the two endpoint devices can exchange information about the respective radio channels so that at least one of the endpoint devices can adjust its respective radio channel to minimize overlap and interference.For example, the first endpoint device may transmit to the second endpoint device information about a first frequency hopping sequence to be implemented on the first wireless transceiver for the first radio channel. The second endpoint device may determine the second frequency hopping sequence for the second radio channel based on the first frequency hopping sequence to reduce or eliminate overlap and interference between the two radio channels, so that at any time within the transmission period, the first sensor data is received using a different wireless carrier frequency than the second sensor data. The information exchange may occur during commissioning and / or during wireless data transmission.

[0142] In some aspects, the first transceiver is operable to establish the first radio channel using a first wireless protocol. The second transceiver is operable to establish the second radio channel using a second wireless protocol. The first and second wireless protocols may be the same protocol or different protocols, including, for example, BLE.

[0143] At step 1230, method 1200 may include receiving first data over the first wireless channel by the first endpoint device using the first transceiver. The first data may include, for example, sensor data indicating movement of a mouse in the x and y directions.

[0144] At step 1240, method 1200 may include receiving second data over the second radio channel by the second endpoint device using the second transceiver. The second data may include, for example, audio / video stream data.

[0145] At step 1250, method 1200 may include the first endpoint device providing the first data to the host device over the first connection. For example, the first endpoint device may store the first data in a register accessible to the host device, which then retrieves the first data from the register.

[0146] At step 1260, method 1200 may include the second endpoint device providing the second data to the host device over the second connection. For example, the second endpoint device may store the second data in a register accessible to the host device, which may then retrieve the second data from the register.

[0147] In summary, the present invention provides techniques for wireless communication. A system includes a wireless transceiver and a hardware processor configured to receive a first indication of a host device clock signal from a host device. The system and the host device may be connected via a wired connection, although other connection types are possible. They may be further configured to determine a phase relationship between the host device clock signal and an endpoint device clock signal based on the first indication and a second indication of the endpoint device clock signal. They may be further configured to determine a first time for transmitting a sensor data request to a peripheral device of a computer based at least on the phase relationship.They may further be configured to transmit the sensor data request to the peripheral device at the first time using the wireless transceiver. They may also be configured to receive the sensor data from the peripheral device and provide the sensor data to the host device via the wired connection as input data for the computer.

[0148] Other variations are within the spirit of the present disclosure. While the disclosed techniques are susceptible to various modifications and alternative forms, certain embodiments of the illustrated techniques are illustrated in the figures and have been described in detail above. It should be understood, however, that the disclosure is not intended to be limited to the form(s) disclosed, but on the contrary, the intention is to cover all modifications, alternative designs, and equivalents falling within the spirit and scope of the disclosure as defined in the appended claims. For example, all embodiments, alternative embodiments, etc., and their concepts may be applied to all other embodiments described and / or within the spirit and scope of the disclosure.

[0149] The use of the terms "a" and "an" and "the" and similar references in connection with the description of the disclosed embodiments (particularly in connection with the following claims) is to be construed to cover both the singular and the plural, unless otherwise stated herein or the context clearly indicates otherwise. The terms "comprising," "having," "including," and "containing" are to be construed as non-exhaustive terms (i.e., they mean "including, but not limited to") unless otherwise specified. The term "associated" is to be construed as including, affixed to, or connected to, in whole or in part, even if there is something in between.The term "based on" should be construed as non-exhaustive and in no way limiting and is intended to be interpreted or otherwise read as "based on, at least in part," where appropriate. The citation of ranges of values ​​herein is intended merely as a shorthand way of referring individually to each value falling within the range, unless otherwise noted herein, and each value is deemed to be included in the description as if listed individually. All of the procedures described herein may be performed in any convenient order, unless otherwise noted here or the context clearly indicates otherwise. The use of any examples or exemplary phrases contained herein (e.g.,"for example, such as") is intended merely to better explain embodiments of the disclosure and does not constitute a limitation on the scope of the disclosure unless otherwise claimed. No statements in the description should be construed as identifying any unclaimed element as essential to practicing the disclosure.

Claims

[1] System (100, 200, 300, 400, 900) which has: a wireless transceiver (413, 424, 914, 915); a storage device (220, 306) for storing a set of instructions; and a hardware processor (402) configured to execute the set of instructions to perform: Receiving a first indication of a host device clock signal (504) from a host device (412), wherein the system (100, 200, 300, 400, 900) and the host device (412) are connected via a wired connection; determining a phase relationship between the host device clock signal (504) and an endpoint device clock signal based on the first indication and a second indication of the endpoint device clock signal; Determining a first time for transmitting a sensor data request to a peripheral device (404) of a computer (110, 460, 960) based at least on the phase relationship; transmitting the sensor data request to the peripheral device (404) at the first time using the wireless transceiver (413, 424, 914, 915); Receiving the requested sensor data from the peripheral device (404); and providing the requested sensor data to the host device (412) via the wired connection as input data to the computer (110, 460, 960), wherein the first indication of the host device clock signal (504) is received at a second time; and wherein the first time for transmitting the sensor data request is determined based on the second time and a predetermined delay between the time at which the system (100, 200, 300, 400, 900) begins retrieving the sensor data and the time at which the sensor data becomes available at the system (100, 200, 300, 400, 900) for transmission via the wired connection. [2] The system (100, 200, 300, 400, 900) of claim 1, wherein the hardware processor (402) is further configured to: Determining a third time at which the system (100, 200, 300, 400, 900) should receive a read request for the sensor data from the host device (412) based on the host device clock signal (504), wherein the first time for obtaining the sensor data from the peripheral device (404) is determined such that the sensor data is obtained from the system (100, 200, 300, 400, 900) before the second time. [3] The system (100, 200, 300, 400, 900) of claim 1 or 2, wherein transmitting the sensor data request to the peripheral device (404) comprises transmitting a query request (612) by the system (100, 200, 300, 400, 900) to the peripheral device (404) using the wireless transceiver (413, 424, 914, 915); wherein the hardware processor (402) is further configured to: Receiving a query response containing the sensor data from the peripheral device (404) using the wireless transceiver (413, 424, 914, 915); and Processing the query response to extract the sensor data. [4] The system (100, 200, 300, 400, 900) of claim 3, wherein the peripheral device (404) can determine at least one of the following times by transmitting the query request (612) to the peripheral device (404) at the first time: a third time for obtaining the next sensor data and a fourth time for waiting for a next query request (612) for a transmission of the next sensor data from the peripheral device (404). [5] The system (100, 200, 300, 400, 900) of claim 4, wherein the polling request (612) further comprises information about the accuracy of the host device clock signal (504) to determine the third time to obtain the next sensor data from and / or the fourth time to wait for a next polling request (612) at the peripheral device (404). [6] System (100, 200, 300, 400, 900) according to claim 4 or 5, wherein the hardware processor (402) is further configured to: Determining a change in the phase relationship between the host device clock signal (504) and the endpoint device clock signal; and, if it is determined that the change in the phase relationship exceeds a threshold, to: Generating an instruction containing information about the change in the phase relationship; and Transmitting the instruction to the peripheral device (404) using the wireless transceiver (413, 424, 914, 915) so that the peripheral device (404) can update the third time for obtaining the next sensor data from and / or the fourth time for waiting for a next polling request (612) at the peripheral device (404). [7] The system (100, 200, 300, 400, 900) of claim 6, wherein the instruction further comprises information regarding the accuracy of the host device clock signal (504) and indicates when to update the third time for obtaining the next sensor data from and / or the fourth time for waiting for a next polling request (612) at the peripheral device (404). [8] System (100, 200, 300, 400, 900) according to one of claims 1 to 7, wherein the hardware processor (402) is further configured to: Receiving a request from the peripheral device (404) to establish a radio channel using the wireless transceiver (413, 424, 914, 915); and Sending an acknowledgment to the peripheral device (404) using the wireless transceiver (413, 424, 914, 915) at a third time determined based on the second time at which the first indication of the host device clock signal (504) is received. [9] System (100, 200, 300, 400, 900) according to one of claims 1 to 8, wherein: the peripheral device (404) is a first peripheral device (904a); the sensor data is first sensor data; the hardware processor (402) is further configured to: Determining a third time for the start of a retrieval of second sensor data from a second peripheral device (904b), wherein the third time is also determined based on the phase relationship between the host device clock signal (504) and the endpoint device clock signal; and Commencing obtaining the second sensor data from the second peripheral device (904b) at the determined third time. [10] The system (100, 200, 300, 400, 900) of any of claims 1 to 9, wherein the first indication of the host device clock signal (504) comprises an interrupt signal. [11] The system (100, 200, 300, 400, 900) of any one of claims 1 to 10, wherein the wired connection comprises one or more Universal Serial Buses (USBs). [12] System (100, 200, 300, 400, 900), comprising: a wireless transceiver (413, 424, 914, 915); a sensor (430); a storage device (220, 306) for storing a set of instructions; and a hardware processor (402) configured to execute the set of instructions to perform: Receiving a sensor data request from an endpoint device (414) connected to a computer (110, 460, 960) at a first time using the wireless transceiver (413, 424, 914, 915); Determining a second time for receiving a next sensor data request based on the first time; Determining a delay associated with obtaining sensor data from a sensor; Determining a third time for starting to obtain the sensor data from the sensor (430) based on the delay and the second time; Obtaining the sensor data from the sensor (430) at the third time; Transmitting the sensor data to the endpoint device (414) using the wireless transceiver (413, 424, 914, 915) as input data for the computer (110, 460, 960); Receiving an instruction containing information about a change in a phase relationship from the endpoint device (414); and Determining the third time for starting to obtain sensor data from the sensor (430) based on the instruction. [13] The system (100, 200, 300, 400, 900) of claim 12, wherein the endpoint device (414) is connected to a host device (412) via a wired connection; and wherein the first time is determined based on a phase relationship between a host device clock signal (504) provided to the host device (412) and an endpoint device clock signal provided to the endpoint device (414). [14] The system (100, 200, 300, 400, 900) of claim 13, wherein the instruction further comprises information regarding the accuracy of the host device clock signal (504); and wherein the third time to begin obtaining the sensor data is determined based on the accuracy information. [15] The system (100, 200, 300, 400, 900) of any one of claims 12 to 14, wherein the first time is determined based on when the endpoint device (414) is to receive a read request for the sensor data from a host device (412). [16] System (100, 200, 300, 400, 900), comprising: a dongle (450, 950) connected to a host device (412) of a computer (110, 460, 960) via a wired connection (415); and a peripheral device (404); wherein the dongle (450, 950) is designed to: Receiving a first indication of a host device clock signal (504) from the host device (412); determining a phase relationship between the host device clock signal (504) and an endpoint clock signal based on the first indication and a second indication of the endpoint clock signal; Determining a first time point for transmitting a sensor data request to a peripheral device (404) of a computer (110, 460, 960) based at least on the phase relationship; and transmitting the sensor data request wirelessly to the peripheral device (404) at the first time; wherein the peripheral device (404) is designed to: Obtaining sensor data at a second time determined based on a delay associated with obtaining the sensor data and when the sensor data request from the dongle (450, 950) is expected to arrive; Receiving the sensor data request wirelessly from the dongle (450, 950); and Sending the requested sensor data wirelessly in response to the sensor data request; and wherein the dongle (450, 950) is further configured to: wirelessly receiving the requested sensor data from the peripheral device (404); providing the requested sensor data to the host device (412) via the wired connection (415) as input data to the computer (110, 460, 960) determining a change in the phase relationship between the host device clock signal (504) and the endpoint device clock signal; and if it is determined that the change in the phase relationship exceeds a threshold, to: Generating an instruction containing information about the change of phase; and Transmitting the instruction to the peripheral device (404) so that the peripheral device (404) can update the third time for obtaining the next sensor data from and / or the fourth time for waiting for a next polling request (612) at the peripheral device (404). [17] The system (100, 200, 300, 400, 900) of claim 16, wherein transmitting the sensor data request to the peripheral device (404) comprises transmitting a query request (612); wherein the dongle (450, 950) is further configured to: Receiving a query response containing the sensor data from the peripheral device (404); and processing the query response to extract the sensor data.

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