Display device with through hole

Abstract

A display device comprising: a panel (100, 1000) that has an active area (AA) in which a plurality of subpixels (SP) are arranged; a through hole (HL) formed by the active area (AA) of the panel (100, 1000); a hole surround area (HBZ) that is arranged between the through hole (HL) and the active area (AA) in such a way that it surrounds the through hole (HL); and a plurality of data lines (DL) extending from a first active area (AA1) of the active area (AA) across the hole border area (HBZ) to a second active area (AA2) of the active area (AA), wherein the plurality of data lines (DL) in the hole border area (HBZ) have a smaller line spacing than in the first active area (AA1) and the second active area (AA2), wherein a first arrangement order of the plurality of data lines (DL) arranged in the first active area (AA1) and a second arrangement order of the plurality of data lines (DL) arranged in the hole border area (HBZ) are different from each other, wherein the majority of data lines (DL) are time-division multiplexed by means of a demultiplexer matrix which is installed in the panel (100, 1000), wherein the second arrangement order of the majority of data lines (DL) in the hole border area (HBZ) is defined such that data lines from the time-division multiplexed data lines (DL) which have an identical control timing sequence and to which the data signals which have opposite polarities are applied are arranged adjacent to each other, and wherein data lines (DL) that apply green data signals in the hole border area (HBZ) apply data signals that have an identical polarity by means of two adjacent data lines.

Description

[0001] This application claims priority over Korean patent application No. KR10-2019-0091550, filed on July 29, 2019. BACKGROUND OF THE INVENTION Technical field of the invention

[0002] The present invention relates to a display device having a through-hole arranged in an active area. Discussion of the related technology

[0003] At least one optical module, such as a camera module or a sensor module, can be integrated, together with a display device, into an electronic device, such as a smartphone or a tablet personal computer (PC).

[0004] In general, each optical module is arranged in a through-hole formed by a perimeter unit of the electronic device.

[0005] However, with a decrease in the size of the border unit, there is a need for a structure in which both the optical module and the through-hole are located in an active area of ​​the display device. There is also a need for a wiring structure modified such that, when the through-hole is located in the active area of ​​the display device, image quality degradation due to the through-hole is prevented. CN 1 10 047 901 A describes a display device comprising a carrier substrate, a first non-display area, a display area at the edge of the first non-display area, a second non-display area, several data lines, and one of several scanning lines at the edge of the display area.The display area has multiple pixels, each of which has m subpixels, with each subpixel located between adjacent scanning lines and adjacent data lines, and each column of a subpixel being electrically connected to a corresponding data line. In the first non-display area, at least two data lines are laminated and insulated, with at least two data lines arranged side by side in a plane in which the substrate is arranged. The scanning lines are not interlocked. At least one scanning line has a first scanning line, with at least in one pixel row two adjacent pixels being separately connected to two first scanning lines, the first scanning lines being curved and electrically connected to the corresponding first side of each pixel.CN 1 08 831 368 A describes a display device comprising a hollowed-out area, a first non-display area at the edge of the hollowed-out area, a second non-display area at the edge of the display area, a display area with multiple subpixels, and multiple data lines arranged in a first direction, wherein the electrical connection corresponds to a column subpixel of a data line, wherein each data line overlapping the first non-display area has a first data line at the display area and a second data line at the first non-display area, wherein each first data line is coiled and extends through the edge of the hollowed-out area of ​​the first non-display area, and wherein at least two first data lines for providing data signals for subpixels of the same color in the first non-display area are arranged side by side in the orthogonal projection of the display field.US 2018 / 0129111A1 describes a display device with a display panel comprising multiple first and second signal lines extending to a peripheral, specially shaped area, as well as a first multiplexer, a second multiplexer, and multiple main lines arranged within the peripheral, specially shaped area. The multiple first and second signal lines are interconnected one-to-one by the first multiplexer, the multiple main lines, and the second multiplexer within the peripheral, specially shaped area. Different first and corresponding second signal lines connected to the same main line can be switched on sequentially at predetermined times by controlling the switching times of the switching elements of the first and second multiplexers. SUMMARY OF THE INVENTION

[0006] Accordingly, the present invention relates to a display device which essentially prevents one or more problems due to limitations and disadvantages of the related technology.

[0007] One object of the present invention is to provide a display device that can prevent a deterioration in image quality due to a through-hole.

[0008] Additional advantages, functions, and features of the invention are partly disclosed in the following description and partly are apparent to the person skilled in the art from studying the following or can be learned through application of the invention. The objectives and other advantages of the invention can be realized and achieved by means of the structure particularly highlighted in the written description and the resulting claims, as well as the attached drawings.

[0009] To achieve these tasks and other advantages, and in accordance with the objective of the invention as set forth and described in detail herein, a display device according to claim 1 is provided. Further embodiments are described in the dependent claims. A display device according to various embodiments comprises a panel having an active area in which a plurality of subpixels are arranged, a through-hole formed through the active area of ​​the panel, a hole surround area arranged between the through-hole and the active area such that it surrounds the through-hole, and a plurality of data lines extending from a first active area of ​​the active area, via the hole surround area, to a second active area of ​​the active area.wherein the majority of data lines in the hole border area have a smaller line spacing than in the first active area and the second active area, wherein a first arrangement order of the majority of data lines arranged in the first active area and a second arrangement order of the majority of data lines arranged in the hole border area are different from each other, wherein the majority of data lines are time-division multiplexed by means of a demultiplexer matrix mounted in the panel, wherein the second arrangement order of the majority of data lines in the hole border area is defined such that data lines from the time-division multiplexed data lines, which have an identical control timing sequence and to which the data signals, which have opposite polarities are applied, are arranged adjacent to each other, and wherein data lines,which create green data signals in the hole border area, by means of two adjacent data lines creating data signals that have an identical polarity.

[0010] The hole border area can have a first bridge area, which is arranged at an input end of the hole border area adjacent to the first active area, for changing the first arrangement order of the plurality of data lines to the second arrangement order, and a second bridge area, which is arranged at an output end of the hole border area adjacent to the second active area, for changing the second arrangement order of the plurality of data lines to the first arrangement order.

[0011] The majority of data lines can have data lines of a first metal layer and data lines of a second metal layer arranged in the hole border area, with the data lines of the first metal layer and the data lines of the second metal layer arranged alternately.

[0012] Adjacent data lines of the first metal layer, which are adjacent to each other in the state in which the data lines of the second metal layer are arranged in the hole border area between them, can have the identical control timing sequence and can apply the data signals which have opposite polarities.

[0013] Adjacent data lines of the second metal layer, which are arranged adjacent to each other in the state in which the data lines of the first metal layer are arranged in the hole border area between them, can have the identical control timing sequence and can apply the data signals which have opposite polarities.

[0014] The data signals fed to the adjacent data lines can be data signals of the same color.

[0015] The arrangement of the majority of data lines can be modified such that the majority of data lines in both the first active area and the second active area have the first arrangement in which the first to twelfth data lines are arranged sequentially, and such that the majority of data lines have the second arrangement in which the first to twelfth data lines in the hole border area are arranged in the order of the first data line, second data line, fourth data line, third data line, fifth data line, sixth data line, seventh data line, eleventh data line, tenth data line, twelfth data line, eighth data line and ninth data line.

[0016] The majority of data lines can be time-division multiplexed (TDM) in a 1:3 ratio during each horizontal period. Within the hole border area, during each horizontal period, for a first period, a first data line and a fourth data line, located adjacent to each other in an identical layer, can supply a first red data signal and a second red data signal, each with opposite polarities. Similarly, a seventh data line and a tenth data line, located adjacent to each other in an identical layer, can supply a third red data signal and a fourth red data signal, each with opposite polarities.During each horizontal period, for a second period, a second data line and a fifth data line, arranged in different layers, can supply a first green data signal and a second green data signal, each having opposite polarities, and an eleventh data line and an eighth data line, arranged in different layers, can supply a fourth green data signal and a third green data signal, each having opposite polarities, with the polarities of the second green data signal and the fourth green data signal being identical.During each horizontal period, for a third period, a third data line and a sixth data line, arranged adjacent to each other in an identical layer, can supply a first blue data signal and a second blue data signal, each having opposite polarities, and a twelfth data line and a ninth data line, arranged adjacent to each other in an identical layer, can supply a fourth blue data signal and a third blue data signal, each having opposite polarities.

[0017] The majority of data lines can be time-division multiplexed (TDM) at a ratio of 1:6 during each horizontal period. Within the hole border area, during each horizontal period, for a first period, a first data line and a fourth data line, located adjacent to each other in the same layer, can supply a first red data signal and a second red data signal, respectively, with opposite polarities. During each horizontal period, for a second period, a second data line and a fifth data line, located in different layers, can supply a first green data signal and a second green data signal, respectively, with opposite polarities.During each horizontal period, for a third period, a third data line and a sixth data line, located adjacent to each other in an identical layer, can supply a first blue data signal and a second blue data signal, each with opposite polarities. During each horizontal period, for a fourth period, a seventh data line and a tenth data line, located adjacent to each other in an identical layer, can supply a third red data signal and a fourth red data signal, each with opposite polarities. During each horizontal period, for a fifth period, an eleventh data line and an eighth data line, located in different layers, can supply a fourth green data signal and a third green data signal, each with opposite polarities.During each horizontal period, for a sixth period, a twelfth data line and a ninth data line, arranged adjacent to each other in an identical layer, can supply a fourth blue data signal and a third blue data signal, each having opposite polarities.

[0018] Both the first bridge region and the second bridge region can further connect a first bridge electrode configured to connect the third data line extending from the active region and the third data line having the modified arrangement sequence in the hole border region; a second bridge electrode configured to connect the eighth data line extending from the active region and the eighth data line having the modified arrangement sequence in the hole border region; a third bridge electrode configured to connect the ninth data line extending from the active region and the ninth data line having the modified arrangement sequence in the hole border region; and a fourth bridge electrode configured to connect the eleventh data line extending from the active region.and to connect the eleventh data line, which has the changed arrangement sequence in the hole border area.

[0019] The hole perimeter area can have an outer perimeter area in which a plurality of gate lines extending from a third active area of ​​the active area across the hole perimeter area to a fourth active area of ​​the active area are arranged, and an inner perimeter area in which curved sections of the plurality of data lines are arranged along the through-hole between the outer perimeter area and the through-hole, and the first bridge area can be arranged between the first active area and the outer perimeter area, and the second bridge area can be arranged between the second active area and the outer perimeter area.

[0020] It should be noted that both the preceding general description and the following detailed description of the present invention are exemplary and illustrative, and are intended to provide further explanations of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are included to provide a further understanding of the invention and which are incorporated into and form part of this application, illustrate embodiment(s) of the invention and, together with the description, serve to explain the principle of the invention. They show: Fig. 1A and Fig. 1B Views showing the structure of a display surface of a display device according to an embodiment of the present invention; Fig. 2A and Fig. 2B Cross-sectional views showing a structure in which a camera module is inserted into a through-hole of the display device according to the embodiment of the present invention; Fig. 3 a view schematically illustrating the construction of a circuit of the display device according to the embodiment of the present invention; Fig. 4 a view showing a wiring structure of a hole border area according to an embodiment of the present invention; Fig. 5 a cross-sectional view showing the areas of the hole border region according to the embodiment of the present invention, which correspond to the cutouts “A” and “B” shown in Fig. 4 are shown, correspond to; Fig. 6 a view showing a vertical spot in an active area according to an embodiment of the present invention due to a through-hole; Fig. 7 a view showing a data line change structure in the hole border area compared to the active area according to the embodiment of the present invention; Fig. 8 an equivalent circuit diagram representing a 1:3 DEMUX matrix according to an embodiment of the present invention; Fig. 9 and Fig. 10 waveform diagrams of data lines in the active area and the hole border area, which are time-division multiplexed using the 1:3 DEMUX matrix according to the embodiment of the present invention; Fig. 11 an equivalent circuit diagram representing a 1:6 DEMUX matrix according to an embodiment of the present invention; Fig. 12 and Fig. 13 Waveform diagrams of data lines in the active area and the hole border area, which are time-division multiplexed using the 1:6 DEMUX matrix according to the embodiment of the present invention; Fig. 14 a top view showing a wiring structure of a bridge area of ​​the hole border area according to the embodiment of the present invention; and Fig. 15 a cross-sectional view along a line II' of the Fig. 14 of the bridge area according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0022] Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

[0023] Fig. 1A and Fig. 1B are views that depict the structure of a display surface of a display device according to an embodiment of the present invention, and Fig. 2A and Fig. Figure 2B shows cross-sectional views of a structure in which a camera module is inserted into a through-hole of the display device according to the embodiment of the present invention.

[0024] Referring to Fig. 1A and Fig. 1B The display device according to the embodiment of the present invention comprises an active area AA in which a plurality of subpixels are arranged, and a non-active area NA in which no subpixels are arranged, wherein the non-active area NA surrounds the active area AA. The active area AA can be referred to as a display area or a pixel matrix area, and the non-active area NA can be referred to as a non-display area or a border area. The display device can further comprise a touchscreen configured to overlap the entire active area AA in order to detect touch input.

[0025] The display device has at least one through-hole HL formed through the active area AA and at least one hole surround area HBZ arranged between each through-hole HL and the active area AA. For example, according to the embodiment of the present invention, the display device can have a through-hole HL formed through the active area AA and a hole surround area HBZ as shown in Fig. 1A shown, or can have a plurality of through holes HL formed through the active area AA and a plurality of hole border areas HBZ surrounding the plurality of through holes HL, as shown in Fig. Figure 1B shows the number of through holes HL arranged in the active area AA, which can be changed as needed.

[0026] Each hole border region HBZ is a region having a structure surrounding a corresponding through-hole HL, which in turn has a structure surrounded by subpixels of the active region AA, and in which no subpixel is arranged. Each hole border region HBZ is a section through which a plurality of conductors extending from one region to another of the active region AA pass, and the conductors arranged in the hole border region HBZ have a smaller conductor spacing than in the active region AA. To compensate for a capacitance coupling effect due to the smaller conductor spacing in the hole border region HBZ, a hole border region HBZ according to one embodiment of the present invention has a conductor arrangement structure (order) that differs from that of the active region AA, the detailed description of which follows.

[0027] An optical module can be inserted into and mounted in any through-hole HL formed by the active area AA of the display device. The optical module can be a camera module configured to transmit and receive light through the through-hole HL of the display device, or a sensor module comprising various sensors, such as an infrared module and an ambient light sensor. Furthermore, each through-hole HL formed by the active area AA of the display device can be used for various purposes as needed, and another module, different from the optical module, can be inserted into and mounted in the through-hole.

[0028] Various types of display devices, such as liquid crystal displays and electroluminescent displays, can be used as the display device that has the through-hole in the active area AA. An organic light-emitting diode (OLED) display, a quantum dot light-emitting diode display, or an inorganic light-emitting diode display can be used as the electroluminescent display.

[0029] For example, as in Fig. As shown in Figure 2A, the display device is a liquid crystal display comprising a liquid crystal panel 100 and a backlight unit 110, and a cover substrate 104 can be arranged on the liquid crystal panel 100. Each through-hole HL can be formed through the active area AA of the liquid crystal panel 100 and the backlight unit 110 beneath the liquid crystal panel 100. A camera module 160 can be inserted into each through-hole HL and can be arranged such that it overlaps the cover substrate 104.

[0030] The liquid crystal panel 100 comprises a first substrate in which a thin-film transistor (TFT) matrix is ​​arranged, a second substrate in which a color filter matrix is ​​arranged, a liquid crystal layer arranged between the first and second substrates, which are layered by means of a sealant, and a polarizing plate arranged on the outer surface of both the first and second substrates. The backlighting unit 110 comprises a light guide plate and a plurality of optical films stacked sequentially on a lower cover beneath the liquid crystal panel 100, and further comprises a light source arranged such that it faces a light-incident surface of the light guide plate.

[0031] Another example is how in Fig. As shown in Figure 2B, the display device is an OLED display comprising an OLED panel 1000, and a cover substrate 104 can be arranged on the OLED panel 1000. Each through-hole HL can be formed through the active area AA of the OLED panel 1000. A camera module 160 can be inserted into each through-hole HL and can be arranged such that it overlaps the cover substrate 104.

[0032] The OLED panel 1000 can comprise a TFT matrix and an OLED matrix stacked sequentially on a substrate, and an encapsulation structure arranged to encapsulate the OLED and TFT matrices. A touch sensor matrix and an optical layer, such as a polarizing plate designed to reduce reflection of external light, can also be arranged on the encapsulation structure.

[0033] Fig. Figure 3 is a view that schematically illustrates the construction of a circuit of the display device according to the embodiment of the present invention.

[0034] Referring to Fig. 3. According to the embodiment of the present invention, the display device can comprise a liquid crystal panel 100 and a panel control unit. The panel control unit can comprise gate drivers 130 and 140, which are configured to drive a plurality of gate lines GL1 to GLn of the liquid crystal panel 100, a control integrated circuit (IC) 200, which is configured to drive a plurality of data lines DL1 to DLM of the liquid crystal panel 100, and a demultiplexer (hereinafter referred to as DEMUX) matrix 150. The control IC 200 can have a timing control and can control the gate drivers 130 and 140 and the DEMUX matrix 150.

[0035] The liquid crystal panel 100 has an active region AA, non-active regions NA1 to NA4, at least one through-hole HL formed through the active region AA, and at least one hole surround region HBZ surrounding the at least one through-hole HL in the active region AA. The liquid crystal panel 100 may further have a touchscreen configured to overlap the active region AA, or a common electrode may be subdivided to serve as a touch electrode.

[0036] A plurality of subpixels forming the active area AA can include a red subpixel, a green subpixel, and a blue subpixel, and may additionally include a white subpixel configured to enhance brightness. Each subpixel SP has a TFT connected to the gate line GL and the data line DL, and a liquid crystal capacitor Clc and a storage capacitor Cst connected in parallel to the TFT. An amorphous silicon (a-Si) TFT, a polysilicon (poly-Si) TFT, an oxide TFT, or an organic TFT can be used as the TFT. The liquid crystal capacitor Clc charges a differential voltage between a data signal fed through the TFT to a pixel electrode and a common voltage Vcom applied to a common electrode, and controls liquid crystals to adjust light transmittance based on the charged differential voltage.The liquid crystal layer can be driven in a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in-plane switching type (IPS) mode, or a stray field switching (FFS) mode.

[0037] For example, the pixel electrode and the common electrode of each subpixel on a TFT matrix substrate can overlap in the state where a dielectric layer is inserted between them, can have a plurality of slits through which one of the pixel electrodes and the common electrode overlaps the other, and can apply an electric stray field to the liquid crystals to control them. In this configuration, the common electrode can be subdivided and arranged in the active region AA such that it is divided by the plurality of subpixels, and can also be used as a contact electrode.

[0038] Gate drivers 130 and 140 are configured by means of a shift register located in the inactive areas NA2 and NA3 of panel 100 such that they sequentially drive the majority of gate lines GL1 to GLn of the active area AA. Gate drivers 130 and 140 can receive gate control signals from the driver IC 200 via transmission lines GTL1 and GTL2. During an active period, gate drivers 130 and 140 apply a sampling pulse of a gate-on voltage, which is the turn-on voltage of the TFT, to each gate line GL1. During an inactive period, they apply a gate-off voltage, which is the turn-off voltage of the TFT, to each gate line GL1.The gate drivers 130 and 140 can be formed in the same process together with a TFT matrix of the active area AA on the first substrate and can thus be arranged in the non-active areas NA2 and NA3 of the liquid crystal panel 100 in a gate-in-panel (GIP) type.

[0039] For example, the first gate driver 130 and the second gate driver 140 can be arranged at their ends in the second inactive region NA2 and the third inactive region NA3, respectively, which are located on the left and right sides of the active region AA, to simultaneously drive the majority of gate lines GL1 to GLn. This makes it possible to reduce the RC delay of the sampling pulse supplied to each gate line GL and to reduce capacitance coupling effects. One of the first gate drivers 130 and one of the second gate drivers 140 can be located in one of the second inactive region NA2 and the third inactive region NA3.

[0040] The control IC 200 can be arranged on a circuit film 300 and can be connected to the liquid crystal panel 100 through a pad unit located in the first non-active area NA1 of the first substrate of the liquid crystal panel 100, or can be placed directly on the first non-active area NA1 of the first substrate.

[0041] The control IC 200 converts digital data, which is a video signal, into a positive or negative analog data signal using multiple gamma voltages and outputs the converted data signal to the DEMUX matrix 150 via multiple output channels CH1 to CHk. The control IC 200 may include integrated timing control and can control the gate drivers 130 and 140 and the DEMUX matrix 150.

[0042] The DEMUX matrix 150 can be arranged between the control IC 200 and the active area AA in the first non-active area NA1 of the first substrate of the liquid crystal panel 100 and can be formed in the same process together with the TFT matrix of the active area AA and the gate drivers 130 and 140 of the non-active areas NA2 and NA3 on the first substrate.

[0043] The DEMUX matrix 150 divides the data signal output by k output channels CH1 to CHk (where k is a positive integer) of the control IC 200 into time intervals in a ratio of 1:j (where j is an integer of 2 or more) and distributes the time-divided data signals to m data lines DL1 to DLm (where m = k × j and m is a positive integer). In other words, in response to j control signals supplied by the control IC 200, the DEMUX matrix 150 can divide a data signal from each output channel CH into time intervals in a ratio of 1:j and can sequentially supply the j time-divided data signals to j data lines. Consequently, the number k of output channels CH1 to CHk of the control IC 200 can be reduced by a factor of 1 / j compared to the number m of data lines DL1 to DLm.

[0044] Fig. Figure 4 is a view showing a wiring structure of a hole border area according to an embodiment of the present invention. Fig. Figure 5 is a cross-sectional view showing the areas of the hole border region corresponding to cutouts “A” and “B” shown in Fig. 4 are shown, correspond to, and Fig. Figure 6 is a view showing a vertical spot that may be visible in a display area according to an embodiment of the present invention.

[0045] Referring to Fig. 4. The liquid crystal panel has a through-hole HL formed through the active region AA and an annular hole surround region HBZ provided between the through-hole HL and the active region AA. A sealant SA is applied to seal the liquid crystal layer between the first substrate and the second substrate at an interface between the through-hole HL and the hole surround region HBZ along the circumference of the through-hole HL. A black matrix is ​​arranged on the second substrate such that it overlaps the lines GL, DL, DLa, and DLb arranged on the first substrate of the hole surround region HBZ.

[0046] Gate lines GL, passing through the hole rim area HBZ, consisting of a plurality of gate lines extending in a first direction (the horizontal direction or the x-axis direction) in the active area, and data lines DL, passing through the hole rim area HBZ, consisting of a plurality of data lines extending in a second direction (the vertical direction or the y-axis direction) that intersects the first direction in the active area AA, are arranged in the hole rim area HBZ in the form of a semi-arc formed around the circumference of the through-hole HL.

[0047] The gate lines GL arranged in the hole perimeter area HBZ have a left straight section and a right straight section extending horizontally from the left active area AA and the right active area, respectively, and curved sections GLc arranged between the left straight section and the right straight section, each curved section being in the form of a semicircle convex upwards or downwards along the circumference of the through-hole HL. The straight sections and the curved sections GLc of the gate lines GL can be arranged on the outer circumferential region of the hole perimeter area HBZ adjacent to the active area AA.

[0048] The data lines DL arranged in the hole-rim region HBZ have an upper straight section and a lower straight section extending vertically from the upper active region AA and the lower active region AA, respectively, and curved sections DLc arranged between the upper straight section and the lower straight section, each curved section being in the form of a semicircle convex to the left or right along the circumference of the through-hole HL. The curved sections DLc of the data lines DL can be arranged on the inner circumferential region of the hole-rim region HBZ adjacent to the through-hole HL such that they do not overlap the gate lines GL.The straight sections of the data lines DL extend in the vertical direction through the outer circumferential area of ​​the hole border region HBZ, minimally overlap the curved sections GLc of the gate lines GL, which are arranged on the outer circumferential area thereof, and can extend to the inner circumferential area of ​​the hole border region HBZ in such a way that they contact the curved sections DLc of the data lines DL on the inner circumferential area thereof.

[0049] Since the arrangement area (the outer circumferential area) of the gate lines and the arrangement area (the inner circumferential area) of the bent section DLc of the data lines DL in the hole border area HBZ are separated from each other, as described above, it is possible to minimize a parallel adjacent area between the bent section GLc of each of the gate lines and the bent section DLc of a corresponding of the data lines DL in the narrow hole border area HBZ, thereby making it possible to reduce a parasitic capacitance between the gate lines GL and the data lines DL.

[0050] In order to ensure maximum spacing of the data lines DL within the narrow hole border area HBZ, the curved sections DLc of the data lines DL can be formed by alternately forming different metal layers DLa and DLb in the state in which a dielectric layer INS2 is inserted between them, as shown in Fig. 5 shown.

[0051] With reference to Fig. 4 and Fig. 5. The bent sections DLc of the data lines, which are arranged on the inner circumferential region of the hole rim area HBZ, can have a structure in which bent sections DLa of a first metal layer on a first dielectric layer INS1 and bent sections DLb of a second metal layer on a second dielectric layer INS2, which covers the bent sections DLa of the first metal layer on the first dielectric layer INS1, are arranged alternately, and a third dielectric layer INS3 can be arranged such that it covers the bent sections DLb of the second metal layer on the second dielectric layer INS2. The bent sections DLa of the first metal layer can be formed from the same gate metal layer as the gate lines GL, and the bent sections DLb of the second metal layer can be formed from the same source / drain metal layer as the data lines DL of the active area AA.The first dielectric layer INS1 can be a gate dielectric layer, the second dielectric layer INS2 can be an intermediate layer dielectric layer, and the third dielectric layer INS3 can be a passivation layer.

[0052] The curved section DLa of each data line of the first metal layer, which is located on the inner circumferential region of the hole rim area HBZ, can contact an upper straight section of the data line DL of the second metal layer, which is located on the second dielectric layer INS2, through a contact hole CNTa formed through the second dielectric layer INS2, and can contact a lower straight section of the data line DL of the second metal layer, which is formed on the second dielectric layer INS2, through another contact hole CNTb formed through the second dielectric layer INS2.

[0053] For the data lines DL located in the hole border region HBZ, a coupling capacitance effect can increase due to the smaller line spacing compared to the active region AA, which can lead to increased signal interference. As a result of the RC load difference between the data lines, a charge differential occurs between subpixels connected to the data lines DL extending in the vertical direction (the second direction) of the active region AA and passing through the hole border region HBZ, and subpixels connected to the other data lines extending along the active region AA but not passing through the hole border region HBZ. Therefore, a vertical spot 10 may be visible in the area where the subpixels are located, as shown in Fig. 6 shown.

[0054] To solve this problem, in the display device according to the embodiment of the present invention, the arrangement sequence of the data lines DL, which are arranged in the hole border area HBZ, is changed such that it is different from the active area AA through which the data lines DL extend.

[0055] In particular, in the display device according to the embodiment of the present invention, the arrangement of the data lines can be modified such that data lines having the same control timing sequence and connected to data signals having opposite polarities are arranged adjacent to one another in the hole border area HBZ, taking into account the control timing sequence of the data lines DL, which are controlled by means of the DEMUX matrix 150 time-division multiplexing, and the polarity of data signals, thereby making it possible to compensate for a coupling capacitance effect between the data lines DL in the hole border area HBZ and thus to solve a spotting problem.

[0056] To this end, as in Fig. Figure 4 shows a hole-border area HBZ according to an embodiment of the present invention, further comprising a first bridge area BA1, which is arranged at the input end (one end) of the hole-border area HBZ adjacent to a side of the active area AA (for example, adjacent to the active area on one side of the hole-border area) for changing the arrangement order of the data lines DL, and a second bridge area BA2, which is arranged at the output end (the other end) of the hole-border area HBZ adjacent to the other side of the active area AA (for example, adjacent to the active area on the other side, for example, the opposite side, of the hole-border area) for restoring the arrangement order of the data lines DL that has been changed in the hole-border area HBZ, such that it is the same as that of the active area AA.

[0057] The first bridge area BA1 and the second bridge area BA2 of the data lines DL are arranged in the hole border area HBZ such that they overlap the black matrix. The first bridge area BA1 and the second bridge area BA2 of the data lines DL are located between the outer perimeter of the hole border area HBZ, in which the gate lines GL are located, and the active area AA, and do not overlap the gate lines GL, thus reducing parasitic capacitance between the gate lines GL and the data lines DL.

[0058] The distance between the gate lines GL in the hole border area HBZ is reduced compared to the active area AA; however, the gate lines GL are driven simultaneously by the first gate driver 130 and the second gate driver 140, which are connected to both ends of the gate lines GL, thus making the RC time constant small, and therefore a spot due to capacitance coupling between the gate lines does not occur.

[0059] Fig. Figure 7 is a view showing a data line modification structure (for example, a changed arrangement of the data lines) in the hole border area compared to the active area according to the embodiment of the present invention.

[0060] Fig. Figure 7 illustrates the case in which the first to twelfth data lines DL1, DL2, DL3, ..., DL12, which are the data lines extending from an active area of ​​one side AA1, through the hole border area HBZ, and to the active area of ​​another side AA2, supply data signals R1(+), G1(-), B1(+), R2(-), G2(+), B2(-), R3(+), G3(-), B3(+), R4(-), G4(+), and B4(-) in a column inversion mode. The same applies equally to the following embodiments.

[0061] DL1[R1(+)], DL2[G1(-)], DL3[B1(+)], DL4[R2(-)], DL5[G2(+)], DL6[B2(-)], DL7[R3(+)], DL8[G3(-)], DL9[B3(+)], DL10[R4(-)], DL11[G4(+)] and DL12[B4(-)], which supply R, G and B data signals in column inversion mode, are arranged sequentially in the first active area AA1 and the second active area AA2.

[0062] The arrangement order of some data lines can be modified by the first bridge region BA1, which is located at the input end of the hole-bound region HBZ adjacent to the first active region AA1. This allows the data lines arranged in the hole-bound region HBZ to have an arrangement order that is modified to compensate for or reduce capacitance coupling between adjacent lines. Each data line arranged in the hole-bound region HBZ can be located on a layer different from an adjacent data line, thereby reducing the line spacing between the data lines.Data lines located adjacent to each other in the hole border area HBZ within a specific layer can carry data with opposite polarities at the same time, thus compensating for capacitance coupling between adjacent lines. Similarly, data lines located adjacent to each other in a different layer can carry data with opposite polarities at the same time, thereby compensating for capacitance coupling between adjacent lines.

[0063] For example, DL3[B1(+)] and DL4[R2(-)] are arranged in the hole border area HBZ in the state in which their arrangement order is changed by the first bridge area BA1 to the arrangement order of DL4'[R2(-)] and DL3'[B1(+)], and DL8[G3(-)], DL9[B3(+)], DL10[R4(-)], DL11[G4(+)] and DL12[B4(-)] are arranged in the hole border area HBZ in the state in which their arrangement order is changed to the arrangement order of DL11'[G4(+)], DL10'[R4(-)], DL12'[B4(-)], DL8'[G3(-)] and DL9'[B3(+)]. In contrast, DL1[R1(+)], DL2[G1(-)], DL5[G2(+)], DL6[B2(-)] and DL7[R3(+)] are arranged in the hole border area HBZ without any change in the arrangement order of DL1'[R1(+)], DL2'[G1(-)], DL5'[G2(+)], DL6'[B2(-)] and DL7'[R3(+)].

[0064] Accordingly, the data lines arranged in the hole border area HBZ have an arrangement structure that is modified to the sequence DL1'[R1(+)], DL2'[G1(-)], DL4'[R2(-)], DL3'[B1(+)], DL5'[G2(+)], DL6'[B2(-)], DL7'[R3(+)], DL11'[G4(+)], DL10'[R4(-)], DL12'[B4(-)], DL8'[G3(-)] and DL9'[B3(+)]. Each data line arranged in the hole border area HBZ and an adjacent data line are arranged in different layers. DL1'[R1(+)] and DL4'[R2(-)], which are arranged adjacent to each other in a certain layer, carry data that have opposite polarities at the same time, thus compensating for capacitance coupling between adjacent lines.DL3'[B1(+)] and DL6'[B2(-)], located adjacent to each other in a different layer, carry data with opposite polarities at the same time, thus compensating for capacitance coupling between adjacent lines. DL7'[R3(+)] and DL10'[R4(-)], located adjacent to each other in the given layer, carry data with opposite polarities at the same time, thus compensating for capacitance coupling between adjacent lines. DL12'[B4(-)] and DL9'[B3(+)], located adjacent to each other in the other layer, carry data with opposite polarities at the same time, thus compensating for capacitance coupling between adjacent lines.

[0065] Since the optical efficiency of the G-subpixels is relatively high and their brightness is therefore significantly influenced by coupling or other reasons, adjacent data lines, such as DL2'[G1(-)], DL5'[G2(+)], DL11'[G4(+)] and DL8'[G3(-)], which supply G-data signals to the hole border area HBZ and are addressed at the same time, can maintain the same polarity by means of two adjacent data lines, thus making it possible to minimize a change in the polarity of adjacent data lines supplying G-data signals.

[0066] The arrangement order of some data lines is changed from their original arrangement order by the second bridge area BA2, which is located at the output end of the hole border area HBZ adjacent to the second active area AA2, and therefore the arrangement order of the data lines in the second active area AA2 is identical to that in the first active area AA1.

[0067] For example, DL1'[R1(+)], DL2'[G1(-)], DL4'[R2(-)], DL3'[B1(+)], DL5'[G2(+)], DL6'[B2(-)], DL7'[R3(+)], DL11'[G4(+)], DL10'[R4(-)], DL12'[B4(-)], DL8'[G3(-)] and DL9'[B3(+)] of the hole border area HBZ are arranged in the second active area AA2 in the state in which their arrangement order is changed by the second bridge area BA2 to the arrangement order DL1[R1(+)], DL2[G1(-)], DL3[B1(+)], DL4[R2(-)], DL5[G2(+)], DL6[B2(-)], DL7[R3(+)], DL8[G3(-)], DL9[B3(+)], DL10[R4(-)], DL11[G4(+)] and DL12[B4(-)] have been changed, which is the same as in the first active area AA1.

[0068] Fig. Figure 8 is an equivalent circuit diagram representing a 1:3 DEMUX matrix according to an embodiment of the present invention. Fig. Figure 9 is a waveform diagram of data lines that are time-division multiplexed using the 1:3 DEMUX matrix according to the embodiment of the present invention, based on the arrangement order in the active area, and Fig. Figure 10 is a waveform diagram based on the changed arrangement order of the data lines in the hole border area.

[0069] Referring to Fig. 8, Fig. 9 to Fig. 10 divides the Fig. The DEMUX matrix shown in Figure 3 represents the outputs of four output channels CH1(+), CH2(-), CH3(+) and CH4(-) of the driver IC 200 in a ratio of 1:3 during each of the horizontal periods H1 and H2 using the 1:3 DEMUX matrix shown in Fig. As shown in Figure 8, the data is distributed over twelve data lines DL1 to DL12.

[0070] Referring to Fig. Figure 8 shows the 1:3 DEMUX matrix comprising a first TFT T1, a third TFT T3 and a fifth TFT T5 connected in parallel to a first output channel CH1, which is configured to output a positive (+) data signal; a second TFT T2, a fourth TFT T4 and a sixth TFT T6 connected in parallel to a second output channel CH2, which is configured to output a negative (-) data signal; a seventh TFT T7, a ninth TFT T9 and an eleventh TFT T11 connected in parallel to a third output channel CH3, which is configured to output a positive (+) data signal; and an eighth TFT T8, a tenth TFT T10 and a twelfth TFT T12 connected in parallel to a fourth output channel CH4, which is configured to output a negative (-) data signal.

[0071] The 1:3 DEMUX matrix receives a first control signal M1 to sixth control signal M6 from the driver IC 200. During each of the horizontal periods H1 and H2, the first to third positive control signals M1 to M3, which control the positive TFTs T1, T3, T5, T7, T9 and T11, are released sequentially, and the fourth to sixth negative control signals M4 to M6, which control the negative TFTs T2, T4, T6, T8, T10 and T12, are released sequentially in the same order as the first to third control signals M1 to M3.

[0072] During each of the horizontal periods H1 and H2, for a period t1, the first TFT T1 and the seventh TFT T7 are switched on in response to the first control signal M1, and the fourth TFT T4 and the tenth TFT T10 are switched on in response to the fourth control signal M4. During each of the horizontal periods H1 and H2, for a period t2, the fifth TFT T5 and the eleventh TFT T11 are switched on in response to the second control signal M2, and the second TFT T2 and the eighth TFT T8 are switched on in response to the fifth control signal M5. During each of the horizontal periods H01 and H2, for a period t3, the third TFT T3 and the ninth TFT T9 are switched on in response to the third control signal M3, and the sixth TFT T6 and the twelfth TFT T12 are switched on in response to the sixth control signal M6.

[0073] During each of the horizontal periods H1 and H2, for a period t1, the first TFT T1, the fourth TFT T4, the seventh TFT T7 and the tenth TFT T10, which are switched on by means of the 1:3-DEMUX matrix in response to the first control signal M1 and the fourth control signal M4, supply data signals R1(+), R2(-), R3(+) and R4(-) to the DL1, DL4, DL7 and DL10 respectively, which are output by the control IC 200 through the four output channels CH1, CH2, CH3 and CH4 ( Fig. 9) For the period t1, in the hole border area HBZ, a capacitance coupling between DL1'[R1(+)] and DL4'[R2(-)], which are arranged adjacent to each other in the same layer, can be compensated by means of the modified structure due to their opposite polarities, and a capacitance coupling between DL7'[R3(+)] and DL10'[R4(-)], which are arranged adjacent to each other, can be compensated due to the opposite polarities of red data signals that have the same color ( Fig. 10).

[0074] During each of the horizontal periods H1 and H2, for a period t2, the second TFT T2, the fifth TFT 5, the eighth TFT T8 and the eleventh TFT T11, which are switched on by means of the 1:3-DEMUX matrix in response to the second control signal M2 and the fifth control signal M5, supply data signals G1(-), G2(+), G3(1) and G4(+) to the DL2, DL5, DL8 and DL11 respectively, which are output by the control IC 200 through the four output channels CH1, CH2, CH3 and CH4 ( Fig. 9) For the period t2, in the hole boundary area HBZ, adjacent data lines, such as DL2'[G1(-)], DL5'[G2(+)], DL11'[G4(+)] and DL8'[G3(-)], can maintain the same polarity of green data signals of the same color by means of two adjacent data lines, thus making it possible to minimize a change in polarity.

[0075] During each of the horizontal periods H1 and H2, for a period t3, the third TFT T3, the sixth TFT T6, the ninth TFT T9 and the twelfth TFT T11, which are switched on by means of the 1:3-DEMUX matrix in response to the third control signal M3 and the sixth control signal M6, supply data signals B1(+), B2(-), B3(+) and B4(-) to the DL3, DL6, DL9 and DL11 respectively, which are output by the control IC 200 through the four output channels CH1, CH2, CH3 and CH4 ( Fig. 9) For the third period T3, in the hole border area HBZ, a capacitance coupling between DL3'[B1(+)] and DL6'[B2(-)], which are adjacent to each other in the same layer, can be compensated by means of the modified structure due to the opposite polarities of the blue data signals, which have the same color, and a capacitance coupling between DL12'[B4(-)] and DL9'[B3(+)], which are adjacent to each other, can be compensated due to their opposite polarities ( Fig. 10).

[0076] Fig. Figure 11 is an equivalent circuit diagram representing a 1:6 DEMUX matrix according to an embodiment of the present invention. Fig. Figure 12 is a waveform diagram of data lines that are time-division multiplexed using the 1:6 DEMUX matrix according to the embodiment of the present invention, based on the arrangement order in the active area, and Fig. Figure 13 is a waveform diagram based on the changed arrangement order of the data lines in the hole border area.

[0077] Referring to Fig. 11, Fig. 12 to Fig. 13 divides the Fig. Figure 3 shows the DEMUX matrix representing the outputs of two output channels CH1(+) and CH2(-) and the driver IC 200 in a ratio of 1:6 during a horizontal period H1 using the 1:6 DEMUX matrix shown in Fig. As shown in Figure 11, the data is distributed over twelve data lines DL1 to DL12.

[0078] Referring to Fig. Figure 11 shows the 1:6-DEMUX matrix comprising a first TFT T1, a third TFT T3, a fifth TFT T5, a seventh TFT T7, a ninth TFT T9 and an eleventh TFT T11, which are connected in parallel to a first output channel CH1, which is configured to output a positive (+) data signal, and a second TFT T2, a fourth TFT T4, a sixth TFT T6, an eighth TFT T8, a tenth TFT T10 and a twelfth TFT T12, which are connected in parallel to a second output channel CH2, which is configured to output a negative (-) data signal.

[0079] The 1:6 DEMUX matrix receives a first control signal M1 to twelfth control signal M12 from the control IC 200. During the horizontal period H1, the first to sixth positive control signals M1 to M6, which control the positive TFTs T1, T3, T5, T7, T9 and T11, are released sequentially, and the seventh to twelfth negative control signals M7 to M12, which control the negative TFTs T2, T4, T6, T8, T10 and T12, are released sequentially in the same order as the first to sixth positive control signals M1 to M6.

[0080] During the horizontal period H1, the first TFT T1 and the fourth TFT T4 are switched on for a period t1 in response to the first control signal M1 and the seventh control signal M7. During the horizontal period H1, the fifth TFT T5 and the second TFT T2 are switched on for a period t2 in response to the second control signal M2 and the eighth control signal M8. During the horizontal period H1, the third TFT T3 and the sixth TFT T6 are switched on for a period t3 in response to the third control signal M3 and the ninth control signal M9. During the horizontal period H1, the seventh TFT T7 and the tenth TFT T10 are switched on for a period t4 in response to the fourth control signal M4 and the tenth control signal M10. During the horizontal period H1, the eleventh TFT T11 and the eighth TFT T8 are switched on for a period t5 in response to the fifth control signal M5 and the eleventh control signal M11.During the horizontal period H1, the ninth TFT T9 and the twelfth TFT T12 are switched on for a period t6 in response to the sixth control signal M6 and the twelfth control signal M12.

[0081] During the horizontal period H1, for a period t1, the first TFT T1 and the fourth TFT T4, which are switched on by means of the 1:6-DEMUX matrix in response to the first control signal M1 and the seventh control signal M7, supply data signals R1(+) and R2(-) to the DL1 and DL4 of the active area, respectively, which are output by the control IC 200 through the two output channels CH1 and CH2 ( Fig. 12) For the period T1, in the hole border area HBZ, a capacitance coupling between DL1[R1(+)] and DL4'[R2(-)], which are arranged adjacent to each other in the same layer, can be compensated by means of the changed structure due to opposite polarities of red data signals that have the same color ( Fig. 13).

[0082] During the horizontal period H1, for a period t2, the second TFT T2 and the fifth TFT 5, which are switched on by means of the 1:6-DEMUX matrix in response to the eighth control signal M8 and the second control signal M2, supply data signals G1(-) and G2(+) to the DL2 and DL5 of the active area AA, respectively, which are output by the control IC 200 through the two output channels CH1 and CH2 ( Fig. 12) For the period t2, in the hole border area HBZ, a capacitance coupling between DL2'[G1(-)] and DL5'[G2(+)], which are arranged adjacent to each other in different layers, can also be compensated due to the opposite polarities of green data signals that have the same color ( Fig. 13).

[0083] During the horizontal period H1, for a period t3, the third TFT T3 and the sixth TFT T6, which are switched on by means of the 1:6-DEMUX matrix in response to the third control signal M3 and the ninth control signal M9, supply the DL3 and DL6 respectively with data signals B1(+) and B2(-), which are output by the control IC 200 through the two output channels CH1 and CH2 ( Fig. 12) For the period t3, in the hole border area HBZ, a capacitance coupling between DL3'[B1(+)] and DL6'[B2(-)], which are arranged adjacent to each other in the same layer, can be compensated by means of the modified structure due to the opposite polarities of the blue data signals, which have the same color ( Fig. 13).

[0084] During the horizontal period H1, for a period t4, the seventh TFT T7 and the tenth TFT T10, which are switched on by means of the 1:6-DEMUX matrix in response to the fourth control signal M4 and the tenth control signal M10, supply data signals R3(+) and R4(-) to the DL7 and DL10 of the active area AA, respectively, which are output by the control IC 200 through the two output channels CH1 and CH2 ( Fig. 12) For the period t4, in the hole border area HBZ, a capacitance coupling between DL7'[R3(+)] and DL10'[R4(-)], which are arranged adjacent to each other in the same layer, can be compensated by means of the modified structure due to the opposite polarities of the red data signals, which have the same color ( Fig. 13).

[0085] During the horizontal period H1, for a period t5, the eighth TFT T8 and the eleventh TFT T11, which are switched on by means of the 1:6-DEMUX matrix in response to the eleventh control signal M11 and the fifth control signal M5, supply data signals G3(-) and G4(+) to the DL8 and DL11 respectively of the active area AA, which are output by the control IC 200 through the two output channels CH1 and CH2 ( Fig. 12) For the period t5, in the hole border area HBZ, a capacitance coupling between DL11'[G4(+)] and DL8'[G3(-)], which are arranged adjacent to each other in different layers, can also be compensated due to opposite polarities of the green data signals, which have the same color ( Fig. 13).

[0086] During the horizontal period H1, for a period t6, the ninth TFT T9 and the twelfth TFT T12, which are switched on by means of the 1:6-DEMUX matrix in response to the sixth control signal M6 and the twelfth control signal M12, supply data signals B3(+) and B4(-) to the DL9 and DL12 respectively of the active area AA, which are output by the control IC 200 through the two output channels ( Fig. 12) For the period t6, in the hole border area HBZ, a capacitance coupling between DL12'[B4(-)] and DL9'[B3(+)], which are arranged adjacent to each other in the same layer, due to opposite polarities of the blue data signals, which have the same color, can be compensated by means of the modified structure ( Fig. 13).

[0087] Fig. Figure 14 is a top view showing a wiring structure of a bridge area of ​​the hole border area according to the embodiment of the present invention, and Fig. 15 is a cross-sectional view along a line II' of the Fig. 14 of the bridge area according to the embodiment of the present invention.

[0088] Fig. Figure 14 shows the wiring structure of the first bridge area BA1 of the hole border area according to the embodiment of the present invention, wherein DL1 to DL12, which extend from the active area AA, can be arranged successively from the right in the direction to the left.

[0089] Referring to Fig. 14 and Fig. 15 DL1, DL2, DL5, DL6 and DL7, which extend from the active area, to DL1', DL2', DL5', DL6' and DL7' of the hole perimeter area HBZ, while their arrangement order is maintained in the bridge area BA1 of the hole perimeter area HBZ.

[0090] DL3, extending from the active region, is connected in the bridge region BA1 of the hole rim region HBZ through a contact hole CNT11 of a dielectric layer INS2 to a bridge electrode BR1 located in another layer. Bridge electrode BR1 is connected through a contact hole CNT12 of the dielectric layer INS2 to DL3', located in the hole rim region HBZ between DL4' and DL5'. DL4, extending from the active region, overlaps bridge electrode BR1 when the dielectric layer INS2 is inserted between them and is connected to DL4', located in the hole rim region HBZ between DL2' and DL3'.

[0091] DL8, extending from the active area, is connected in the bridge region BA1 of the hole rim region HBZ through a contact hole CNT21 of the dielectric layer INS2 to a bridge electrode BR2, which is arranged in another layer, and the bridge electrode BR2 is connected through a contact hole CNT22 of the dielectric layer INS2 to DL8', which is arranged in the hole rim region HBZ between DL12' and DL9'.

[0092] DL9, which extends from the active area, is connected in the bridge region BA1 of the hole rim region HBZ through a contact hole CNT31 of the dielectric layer INS2 to a bridge electrode BR3, which is arranged in another layer, and the bridge electrode BR3 is connected through a contact hole CNT32 of the dielectric layer INS2 to DL9', which is arranged in the hole rim region HBZ after DL8'.

[0093] DL10, extending from the active region, overlaps a plurality of bridge electrodes BR3, BR4 and BR2 in the state in which the dielectric layer INS2 is inserted between them in the bridge region BA1 of the hole rim region HBZ, and is connected to DL10', which is located in the hole rim region HBZ between DL11' and DL12'.

[0094] DL11, which extends from the active area, is connected in the bridge region BA1 of the hole rim region HBZ through the contact hole CNT41 of the dielectric layer INS2 to the bridge electrode BR4, which is arranged in another layer, and the bridge electrode BR4 is connected through the contact hole CNT42 of the dielectric layer INS2 to DL11', which is arranged in the hole rim region HBZ between DL7' and DL10'.

[0095] DL12, which extends from the active area, overlaps the majority of bridge electrodes BR3 and BR2 in the state in which the dielectric layer INS2 is inserted between the bridge area BA1 of the hole rim area HBZ, and is connected to DL12', which is located in the hole rim area HBZ between DL10' and DL8'.

[0096] As can be seen from the above description, in a display device according to an embodiment of the present invention, data lines having the same control timing sequence and to which data signals having opposite polarities are applied, are arranged adjacent to one another in a hole border area which, taking into account the control timing sequence of data lines that are time-division multiplexed by means of a DEMUX matrix and the polarity of data signals, has a narrow line spacing, making it possible to reduce a coupling capacitance effect due to the small line spacing by means of offset compensation.As a result, it is possible to compensate for signal interference between the data lines due to the small line spacing in the hole border area, thereby reducing a vertical spot in an active area caused by a through-hole and thus improving image quality.

Claims

[1] A display device comprising: a panel (100, 1000) that has an active area (AA) in which a plurality of subpixels (SP) are arranged; a through hole (HL) formed by the active area (AA) of the panel (100, 1000); a hole surround area (HBZ) that is arranged between the through hole (HL) and the active area (AA) in such a way that it surrounds the through hole (HL); and a plurality of data lines (DL) extending from a first active area (AA1) of the active area (AA) across the hole border area (HBZ) to a second active area (AA2) of the active area (AA), wherein the plurality of data lines (DL) in the hole border area (HBZ) have a smaller line spacing than in the first active area (AA1) and the second active area (AA2), wherein a first arrangement order of the plurality of data lines (DL) arranged in the first active area (AA1) and a second arrangement order of the plurality of data lines (DL) arranged in the hole border area (HBZ) are different from each other, wherein the majority of data lines (DL) are time-division multiplexed by means of a demultiplexer matrix which is installed in the panel (100, 1000), wherein the second arrangement order of the majority of data lines (DL) in the hole border area (HBZ) is defined such that data lines from the time-division multiplexed data lines (DL) which have an identical control timing sequence and to which the data signals which have opposite polarities are applied are arranged adjacent to each other, and wherein data lines (DL) that apply green data signals in the hole border area (HBZ) apply data signals that have an identical polarity by means of two adjacent data lines. [2] The display device according to claim 1, wherein the hole border area (HBZ) comprises: a first bridge area (BA1) which is arranged to change the first arrangement order of the majority of data lines (DL) to a second arrangement order at an input end of the hole border area (HBZ) adjacent to the first active area (AA1); and a second bridge area (BA2) which is arranged to change the second arrangement order of the majority of data lines (DL) to the first arrangement order at an output end of the hole border area (HBZ) adjacent to the second active area (AA2). [3] The display device according to claim 1 or 2, wherein the plurality of data lines (DL) comprise data lines (DLa) of a first metal layer and data lines (DLb) of a second metal layer, which are arranged in the hole border area (HBZ), wherein the data lines (DLa) of the first metal layer and the data lines (DLb) of the second metal layer are arranged alternately. [4] The display device according to claim 3, wherein adjacent data lines (DLa) of the first metal layer, which are arranged adjacent to each other in a state in which the data lines (DLb) of the second metal layer are arranged in the hole border area (HBZ) between them, have the identical control timing sequence and apply the data signals which have opposite polarities. [5] The display device according to claim 3 or 4, wherein adjacent data lines (DLb) of the second metal layer, which are arranged adjacent to each other in a state in which the data lines (DLa) of the first metal layer are arranged in the hole border area (HBZ) between them, have the identical control timing sequence and apply the data signals which have opposite polarities. [6] The display device according to any one of claims 1 to 5, wherein the data signals applied to the adjacent data lines (DL) are data signals of an identical color. [7] The display device according to any one of claims 1 to 6, wherein a change in the arrangement order of the majority of data lines (DL) such that the majority of data lines (DL) exhibit the first arrangement sequence in which the first to twelfth data lines (DL1, ..., DL12) are arranged sequentially in both the first active area (AA1) and the second active area (AA2), and the majority of data lines (DL) the second arrangement order in which the first to twelfth data lines (DL1', ..., DL12') are arranged in the hole border area (HBZ) in an order of first data line, second data line, fourth data line, third data line, fifth data line, sixth data line, seventh data line, eleventh data line, tenth data line, twelfth data line, eighth data line and ninth data line. [8] The display device according to any one of claims 1 to 7, wherein the majority of data lines (DL) are time-division multiplexed in a ratio of 1:3 during each horizontal period (H1, H2), in the hole border area (HBZ) During each horizontal period (H1, H2), for a first period (t1), a first data line (DL1') and a fourth data line (DL4'), arranged adjacent to each other in an identical layer, supply a first red data signal (R1+) and a second red data signal (R2-), each having opposite polarities, and a seventh data line (DL7') and a tenth data line (DL10'), arranged adjacent to each other in an identical layer, supply a third red data signal (R3+) and a fourth red data signal (R4-), each having opposite polarities. During each horizontal period (H1, H2), for a second period (t2), a second data line (DL2') and a fifth data line (DL5'), arranged in different layers, supply a first green data signal (G1-) and a second green data signal (G2+), each having opposite polarities, and an eleventh data line (DL11') and an eighth data line (DL8'), arranged in different layers, supply a fourth green data signal (G4+) and a third green data signal (G3-), each having opposite polarities, the polarities of the second green data signal (G2+) and the fourth green data signal (G4+) being identical, and During each horizontal period (H1, H2), for a third period (t3), a third data line (DL3') and a sixth data line (DL6'), which are arranged adjacent to each other in an identical layer, supply a first blue data signal (B1+) and a second blue data signal (B2-), each having opposite polarities, and a twelfth data line (DL12') and a ninth data line (DL9'), which are arranged adjacent to each other in an identical layer, supply a fourth blue data signal (B4+) and a third blue data signal (B3-), each having opposite polarities. [9] The display device according to any one of claims 1 to 7, wherein the majority of data lines (DL) are time-division multiplexed in a ratio of 1:6 during each horizontal period (H1), in the hole border area (HBZ) During each horizontal period, for a first period (t1), a first data line (DL1') and a fourth data line (DL4'), which are arranged adjacent to each other in an identical layer, supply a first red data signal (R1+) and a second red data signal (R2-), each having opposite polarities, to a first data line (DL1') and a fourth data line (DL4'), which are arranged adjacent to each other in an identical layer, During each horizontal period (H1), for a second period (t2), a second data line (DL2') and a fifth data line (DL5'), arranged in different layers, supply a first green data signal (G1-) and a second green data signal (G2+), each having opposite polarities, to a second data line (DL2') and a fifth data line (DL5'), which are arranged in different layers. During each horizontal period (H1), for a third period (t3), a third data line (DL3') and a sixth data line (DL6'), arranged adjacent to each other in an identical layer, supply a first blue data signal (B1+) and a second blue data signal (B2-), each having opposite polarities, to a third data line (DL3') and a sixth data line (DL6'), which are arranged adjacent to each other in an identical layer. During each horizontal period (H1), for a fourth period (t4), a seventh data line (DL7') and a tenth data line (DL10'), arranged adjacent to each other in an identical layer, supply a third red data signal (R3+) and a fourth red data signal (R4-), each having opposite polarities, to a seventh data line (DL7') and a tenth data line (DL10'), which are arranged adjacent to each other in an identical layer. During each horizontal period (H1), for a fifth period (t5), an eleventh data line (DL11') and an eighth data line (DL8'), arranged in different layers, supply a fourth green data signal (G4+) and a third green data signal (G3-), each having opposite polarities, and During each horizontal period (H1), for a sixth period (t6), a twelfth data line (DL12') and a ninth data line (DL9'), which are arranged adjacent to each other in an identical layer, supply a fourth blue data signal (B4-) and a third blue data signal (B3+), each having opposite polarities. [10] The display device according to claim 7, wherein each of the first bridge section (BA1) and the second bridge section (BA2) further comprises: a first bridge electrode (BR1) configured to connect the third data line (DL3) extending from the active area (AA) and the third data line (DL3') having the modified arrangement sequence in the hole border area (HBZ); a second bridge electrode (BR2) configured to connect the eighth data line (DL8) extending from the active area (AA) and the eighth data line (DL8') having the modified arrangement sequence in the hole border area (HBZ); a third bridge electrode (BR3) configured to connect the ninth data line (DL9) extending from the active area (AA) and the ninth data line (DL9') having the modified arrangement sequence in the hole border area (HBZ); and a fourth bridge electrode (BR4) which is configured to connect the eleventh data line (DL11) extending from the active area (AA) and the eleventh data line (DL11') which has the modified arrangement sequence in the hole border area (HBZ). [11] The display device according to any one of claims 2 to 10, wherein the hole border area (HBZ) comprises: an outer circumferential region in which a plurality of gate lines (GL) extending from a third active area of ​​the active region (AA) across the hole border region (HBZ) to a fourth active area of ​​the active region (AA) are arranged; and an inner circumferential region in which bent sections (DLc) of the majority of data lines (DL) are arranged along the through-hole (HL) between the outer circumferential region and the through-hole (HL), and the first bridge area (BA1) is located between the first active area (AA1) and the outer circumferential area, and the second bridge area (BA2) is located between the second active area (AA2) and the outer circumferential area. [12] The display device according to any one of claims 2 to 7, wherein the display device is a liquid crystal display device and the first bridge area (BA1) and the second bridge area (BA2) are arranged such that they overlap a black matrix of the liquid crystal display device. [13] The display device according to any one of claims 1 to 12, wherein no subpixel is arranged in the hole border area (HBZ). [14] The display device according to any one of claims 1 to 13, wherein an optical module (160) is inserted into the through hole (HL).

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