Display device with multiplexer and method for controlling this display device

Abstract

A display device (110, 210) comprising: a timing control part (120) configured to generate image data, a data control signal and a gate control signal; a data drive part (130, 230) configured to generate a data voltage (Vdata) using the image data and the data control signal; a gate drive part (140) configured to generate a gate voltage using the gate control signal; a display panel (150, 250) having a plurality of subpixels (SPr, SPg, SPb) and configured to display an image using the data voltage (Vdata) and the gate voltage; and a plurality of first MUX switches (MT1) and a plurality of second MUX switches (MT2) configured to sequentially transmit the data voltage (Vdata) to two subpixels of a same color from the plurality of subpixels (SPr, SPg, SPb); wherein the data voltage comprises first to sixth red data voltages, first to sixth green data voltages and first to sixth blue data voltages, wherein the plurality of subpixels (SPr, SPg, SPb) comprises first red, first green, first blue, second red, second green and second blue subpixels (SPr1, SPg1, SPb1, SPr2, SPg2, SPb2) in a first horizontal pixel row, third red, third green, third blue, fourth red, fourth green and fourth blue subpixels (SPr3, SPg3, SPb3, SPr4, SPg4, SPb4) in a second horizontal pixel row, and fifth red, fifth green, fifth blue, sixth red, sixth green and sixth blue subpixels (SPr5, SPg5, SPb5, SPr6, SPg6, SPb6) in a third horizontal pixel row, wherein the display device (110, 210) is configured such that, according to a first MUX signal (MUX1), the plurality of first MUX switches (MT1) transmit the first, third, and fifth red data voltages to the first, third, and fifth red subpixels (SPr1, SPr3, SPr5), transmit the first, third, and fifth green data voltages to the first, third, and fifth green subpixels (SPg1, SPg3, SPg5), and transmit the first, third, and fifth blue data voltages to the first, third, and fifth blue subpixels (SPb1, SPb3, SPb5), and wherein the display device (110, 210) is configured such that, according to a second MUX signal (MUX2), the plurality of second MUX switches (MT2) transmit the second, fourth, and sixth red data voltages to the second, fourth, and sixth red subpixels (SPr2, SPr4, SPr6), transmit the second, fourth, and sixth green data voltages to the second, fourth, and sixth green subpixels (SPg2, SPg4, SPg6), and transmit the second, fourth, and sixth blue data voltages to the second, fourth, and sixth blue subpixels (SPb2, SPb4, SPb6); wherein the display device (110, 210) is further configured such that the plurality of first MUX switches (MT1) and the plurality of second MUX switches (MT2) successively transmit the first, second, fourth, third, fifth, and sixth red data voltages to the first, second, fourth, third, fifth, and sixth red subpixels (SPr1, SPr2, SPr4, SPr3, SPr5, SPr6), transmit the first, second, fourth, third, fifth, and sixth green data voltages to the first, second, fourth, third, fifth, and sixth green subpixels (SPg1, SPg2, SPg4, SPg3, SPg5, SPg6), and transmit the first, second, fourth, third, fifth, and sixth blue data voltages to the first, second, fourth, third, fifth, and sixth blue subpixels (SPb1, SPb2, SPb4, SPb3, SPb5, SPb6).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS BACKGROUND Technical field

[0001] The present disclosure relates to a display device, and more particularly to a display device having a multiplexer in which a data voltage of an output terminal of a data driving part is supplied to two subpixels of the same color using a multiplexer, and to a method of driving the display device. Discussion of related technology

[0002] With the advancement of the information age, display devices have evolved rapidly. In the field of display devices, the traditional cathode-ray tube (CRT) has been rapidly replaced by flat panel displays (FPDs), which feature a thin profile, light weight, and low power consumption. FPD devices include liquid crystal displays (LCDs), plasma display panels (PDPs), organic light-emitting displays (OLEDs), and field emission displays (FEDs).

[0003] US 2016 / 0322008 A1 discloses a display device in which each output channel of a source driver is connected to a respective pair of switches. The control terminals of the first switches are connected to a first MUX signal line, and the control terminals of the second switches are connected to a second MUX signal line. In conjunction with a scan pulse on a gate line of a corresponding pixel row, the first MUX signal line receives an on-signal pulse, and subsequently the second MUX signal line receives an on-signal pulse, so that the on-signal pulses from MUX1 and MUX2 occur in the same order during each on-time of a scan pulse on the gate lines.

[0004] The display device displays an image by supplying a data voltage output from a data driver to a pixel of a display panel. As the resolution increases, the number of pixels increases. As the number of output terminals of the data driver increases, the size and number of data driver components increase, and the manufacturing cost of the display device increases.

[0005] When the display panel is used in a touch-sensitive display device, the volume of the touch-sensitive display device increases due to the additional control part for touch sensing. In particular, it is difficult to create a flexible touch-sensitive display device because an additional touch control part and an additional display control part are required. OVERVIEW

[0006] Accordingly, the present disclosure is directed to a display device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

[0007] An object of the present disclosure is to provide a display device having a multiplexer in which the number of digital-to-analog converters decreases, and the size and number of data driving parts and the manufacturing costs are reduced, and to provide a method for driving the display device.

[0008] Another object of the present disclosure is to provide a display device having a multiplexer in which a luminance deviation is reduced and a quality deterioration such as a vertical line spot is prevented, and to provide a method for driving the display device.

[0009] Another object of the present disclosure is to provide a display device having a multiplexer in which luminance uniformity is improved, optical compensation is optimized and power consumption is reduced, and to provide a method for driving the display device.

[0010] Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description or may be learned by practice of the disclosure. These and other advantages of the disclosure will be realized and attained by the structure particularly pointed out in the written description and claims as well as the accompanying drawings.

[0011] To achieve these and other advantages, and in accordance with the purpose of the present disclosure as expressed and broadly described herein, a display device and a method for driving a display device are provided according to independent claims 1 and 8. Further embodiments are described in the dependent claims.

[0012] It is to be understood that both the foregoing general description and the following detailed description are explanatory and serve to further explain the claimed disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are included to aid in a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings: Fig. 1 is a view showing a display device according to a first embodiment of the present disclosure; Fig. 2 is a view showing a subpixel of a display device according to a first embodiment of the present disclosure; Fig. 3 is a view showing a data driving part and a display panel of a display device according to a first embodiment of the present disclosure; Fig. 4 is a view showing a plurality of signals of a data driving part and a display panel of a display device according to a first embodiment of the present disclosure; Fig. 5 is a view showing a supply sequence of a data voltage to a plurality of subpixels of a display device according to a first embodiment of the present disclosure; Fig. 6 is a view showing a parasitic capacitance between a transmission line and a data line of a display device according to a first embodiment of the present disclosure; Fig. 7 is a view showing a data driving part and a display panel of a display device according to a second embodiment of the present disclosure; Fig. 8 is a view showing a plurality of signals of a data driving part and a display panel of a display device according to a second embodiment of the present disclosure; Fig. 9 is a view showing a supply sequence of a data voltage to a plurality of subpixels of a display device according to a second embodiment of the present disclosure; Fig. 10 is a plan view showing red, green, and blue subpixels of a display device according to a second embodiment of the present disclosure; Fig. 11 is a view showing a parasitic capacitance between a transmission line and a data line of a display device according to a second embodiment of the present disclosure; Fig. 12A is a view showing a data driving part of a display device according to the first and second embodiments of the present disclosure; Fig. 12B is a view showing a display device according to the first and second embodiments of the present disclosure; and Fig. 12C is a view showing a flexible touch-sensitive display device having a display device according to the first and second embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] Advantages and features of the present disclosure and its implementation methods will become more apparent from the following embodiments, which are described with reference to the accompanying drawings. However, the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be sufficiently thorough and complete to aid those skilled in the art to fully understand the scope of the present disclosure. Further, the present disclosure is defined only by the scope of the claims.

[0015] A shape, a size, a ratio, an angle, and a number shown in the drawings for describing embodiments of the present disclosure are merely an example. Therefore, the present disclosure is not limited to the details shown. Like reference numerals refer to like elements throughout. In the following description, if it is determined that the detailed description of the corresponding known function or configuration unnecessarily obscures an important point of the present disclosure, the detailed description of such known function or configuration may be omitted. When the terms "comprise," "having," and "including" used in the present description are used, another part may be added unless a more limiting term such as "only" is used.Terms in the singular include the plural unless otherwise stated.

[0016] When designing an element, it is assumed that the element includes a range of error or tolerance, even if there is no explicit description of such error or tolerance.

[0017] When describing a positional relationship, if a positional relationship between two parts is described as, for example, "on", "over", "under", or "next to", one or more other parts may be arranged between the two parts, unless a more restrictive term such as "exactly" or "directly" is used.

[0018] It should be understood that while the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without departing from the scope of the present disclosure.

[0019] Features of various embodiments of the present disclosure may be partially or entirely coupled or combined with one another, and they may interact and technically operate in various ways, as will be readily understood by those skilled in the art. Embodiments of the present disclosure may be practiced independently of one another, or they may be practiced together in a codependent relationship.

[0020] A touch-sensitive display device according to embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In the following description, like reference numerals denote like elements throughout. If a detailed description of known functions or configurations associated with this document proves to unnecessarily obscure the essence of the inventive concept, the detailed description will be omitted or condensed.

[0021] Fig. Figure 1 is a view showing a display device according to a first embodiment of the present disclosure. The display device may include an organic light-emitting diode (OLED) display device.

[0022] In Fig. 1, a display device 110 according to a first embodiment of the present disclosure includes a timing control part 120, a data drive part 130, a gate drive part 140, and a display panel 150.

[0023] The timing control part 120 generates image data, a data control signal, and a gate control signal using an image signal and a plurality of timing signals, such as a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, and a clock, transmitted from an external system (not shown), such as a graphics card or a television system. The timing control part 120 transmits the image data and the data control signal to the data drive part 130 and transmits the gate control signal to the gate drive part 140.

[0024] The data driving part 130 generates a data voltage (a data signal) using the data control signal and the image data transmitted from the timing control part 120 and applies the data voltage to a data line DL of the display panel 150.

[0025] The gate drive part 140 generates a gate voltage (a gate signal) using the gate control signal transmitted from the timing control part 120 and applies the gate voltage to a gate line GL of the display panel 150.

[0026] The gate drive part 140 may be of a gate-in-panel (GIP) type, wherein the gate drive part 140 is arranged on a substrate of the display panel 150 with the gate line GL, the data line DL and a pixel P.

[0027] The display panel 150 displays an image using the gate voltage and the data voltage and includes a plurality of pixels P, a plurality of gate lines GL, and a plurality of data lines DL.

[0028] Each of the plurality of pixels P includes red, green, and blue subpixels SPr, SPg, SPb. The gate line GL and the data line DL intersect to define the red, green, and blue subpixels SPr, SPg, SPb, and each of the red, green, and blue subpixels SPr, SPg, SPb is connected to the gate line GL and the data line DL.

[0029] When the display device 110 is an OLED display device, each of the red, green, and blue subpixels SPr, SPg, SPb may include a plurality of thin film transistors (TFT Thin Film Transistor) such as a switching TFT, a driving TFT, and a scanning TFT, a storage capacitor, and a light-emitting diode.

[0030] Each subpixel of the display panel 150 is illustrated with reference to the drawings.

[0031] Fig. 2 is a view showing a subpixel of a display device according to a first embodiment of the present disclosure.

[0032] In Fig. 2, each of the red, green and blue subpixels SPr, SPg, SPb of the display panel 150 of the display device 110 according to a first embodiment of the present disclosure includes first to tenth transistors T1 to T10, a storage capacitor Cst and a light-emitting diode Del.

[0033] For example, the first to tenth transistors T1 to T10 may be formed as positive (P) type.

[0034] The first transistor T1, as a switching transistor, can be switched depending on an nth gate voltage Scan(n) to transmit a data voltage Vdata. A gate electrode of the first transistor T1 receives the nth gate voltage Scan(n) of an nth gate line, a source electrode of the first transistor T1 is connected to a data line DL, and a drain electrode of the first transistor T1 is connected to sources of the second and fourth transistors T2 and T4.

[0035] The second transistor T2, as a driver transistor, can be switched depending on a voltage of a first electrode of the storage capacitor Cst. A gate electrode of the second transistor T2 is connected to the first electrode of the storage capacitor Cst, a drain electrode of the fifth transistor T5, and a source electrode of the eighth transistor T8. A source electrode of the second transistor T2 is connected to a drain electrode of the first transistor T1 and a source electrode of the fourth transistor T4. A drain electrode of the second transistor T2 is connected to sources of the third and fifth transistors T3 and T5.

[0036] The third transistor T3 can be switched depending on an (n)th emission voltage Em(n). A gate electrode of the third transistor T3 receives the (n)th emission voltage Em(n), a source electrode of the third transistor T3 is connected to a drain electrode of the second transistor T2 and a source electrode of the fifth transistor T5, and a drain electrode of the third transistor T3 is connected to a source electrode of the sixth transistor T6 and an anode of the light-emitting diode Del.

[0037] The fourth transistor T4 can be switched depending on an (n)th emission voltage Em(n). A gate electrode of the fourth transistor T4 receives the (n)th emission voltage Em(n), a source electrode of the fourth transistor T4 is connected to a drain electrode of the first transistor T1 and a source electrode of the second transistor T2, and a drain electrode of the fourth transistor T4 receives a high-level voltage VDD and is connected to a source electrode of the seventh transistor T7.

[0038] The fifth transistor T5 can be switched depending on an (n)th gate voltage Scan(n). A gate electrode of the fifth transistor T5 receives the (n)th gate voltage Scan(n), a source electrode of the fifth transistor T5 is connected to a drain electrode of the second transistor T2 and a source electrode of the third transistor T3, and a drain electrode of the fifth transistor T5 is connected to a gate electrode of the second transistor T2, a first electrode of the storage capacitor Cst, and a source electrode of the eighth transistor T8.

[0039] The sixth transistor T6 can be switched depending on an (n)th gate voltage Scan(n). A gate electrode of the sixth transistor T6 receives the (n)th gate voltage Scan(n), a source electrode of the sixth transistor T6 is connected to a drain electrode of the third transistor T3 and an anode of the light-emitting diode Del, and a drain electrode of the sixth transistor T6 receives an initialization voltage Vini and is connected to a drain electrode of the eighth transistor T8.

[0040] The seventh transistor T7 can be switched depending on an (n)th emission voltage Em(n). A gate electrode of the seventh transistor T7 receives the (n)th emission voltage Em(n), a source electrode of the seventh transistor T7 receives a high-level voltage VDD, and a drain electrode of the seventh transistor T7 is connected to a second electrode of the storage capacitor Cst and sources of the ninth and tenth transistors T9 and T10.

[0041] The eighth transistor T8 can be switched depending on an (n-1)th gate voltage Scan(n-1). A gate electrode of the eighth transistor T8 receives the (n-1)th gate voltage Scan(n-1), a source electrode of the eighth transistor T8 is connected to a first electrode of the storage capacitor Cst, a gate electrode of the second transistor T2, and a drain electrode of the fifth transistor T5, and a drain electrode of the eighth transistor T8 receives an initialization voltage Vini and is connected to a drain electrode of the sixth transistor T6.

[0042] The ninth transistor T9 can be switched depending on an (n)th gate voltage Scan(n). A gate electrode of the ninth transistor T9 receives the (n)th gate voltage Scan(n), a source electrode of the ninth transistor T9 is connected to a second electrode of the storage capacitor Cst and a drain electrode of the seventh transistor T7, and a drain electrode of the ninth transistor T9 receives a reference voltage Vref.

[0043] The tenth transistor T10 can be switched depending on an (n-1)th gate voltage Scan(n-1). A gate electrode of the tenth transistor T10 receives the (n-1)th gate voltage Scan(n-1), a source electrode of the tenth transistor T10 is connected to a second electrode of the storage capacitor Cst and a drain electrode of the seventh transistor T7, and a drain electrode of the tenth transistor T10 receives a reference voltage Vref.

[0044] The light-emitting diode Del is connected between the third transistor T3 and a low-level voltage VSS and emits a light with a luminance proportional to a current of the second transistor T2.

[0045] The light-emitting diode Del emits light according to the operation of the first to tenth transistors T1 to T10 and the storage capacitor Cst to display an image. Furthermore, the display device 110 can compensate for fluctuations in a threshold voltage or degradation of the light-emitting diode depending on a time period using the subpixel. Furthermore, the display device 110 can control luminance by driving the light-emitting diode Del according to a duty cycle corresponding to an emission time.

[0046] The data driving part and the display panel of the display device 110 are explained with reference to the drawings.

[0047] Fig. 3 is a view showing a data driving part and a display panel of a display device according to a first embodiment of the present disclosure, Fig. 4 is a view showing a plurality of signals of a data driving part and a display panel of a display device according to a first embodiment of the present disclosure, and Fig. 5 is a view showing a supply sequence of a data voltage to a plurality of subpixels of a display device according to a first embodiment of the present disclosure.

[0048] In Fig. 3, the data drive part 130 of the display device 110 according to a first embodiment of the present disclosure may include a plurality of latches LT1 to LT6, a plurality of first source switches ST1, a plurality of second source switches ST2, a plurality of red digital-to-analog converters DACr1 and DACr2, a plurality of green digital-to-analog converters DACg1 and DACg2, a plurality of blue digital-to-analog converters DACb1 and DACb2, and a plurality of line drivers (buffers) BF1, BF2, BF3. The display panel 150 of the display device 110 according to a first embodiment of the present disclosure may include a plurality of first MUX switches MT1, a plurality of second MUX switches MT2, a plurality of red subpixels SPr, a plurality of green subpixels SPg, and a plurality of blue subpixels SPb.

[0049] The data drive part 130 may be connected to a non-display area surrounding a display area of ​​the display panel 150. The plurality of first MUX switches MT1 and the plurality of second MUX switches MT2 may be arranged in the non-display area of ​​the display panel 150.

[0050] The plurality of latches LT1 to LT6 sequentially receive image data of each color from the timing control part 120 and store the image data of each color for a time corresponding to one clock. Next, the plurality of latches LT1 to LT6 sequentially output the image data of each color to the plurality of red digital-to-analog converters DACr1 and DACr2, the plurality of green digital-to-analog converters DACg1 and DACg2, and the plurality of blue digital-to-analog converters DACb1 and DACb2 via the plurality of first source switches ST1 and the plurality of second source switches ST2.

[0051] For example, first, third and fifth red image data R1, R3 and R5 may be sequentially input to and output from the first latch LT1, first, third and fifth green image data G1, G3 and G5 may be sequentially input to and output from the second latch LT2, and first, third and fifth blue image data B1, B3, B5 may be sequentially input to and output from the third latch LT3.Second, fourth and sixth red image data R2, R4 and R6 can be sequentially input to and output from the fourth latch LT4, second, fourth and sixth green image data G2, G4 and G6 can be sequentially input to and output from the fifth latch LT5, and second, fourth and sixth blue image data B2, B4, B6 can be sequentially input to and output from the sixth latch LT6.

[0052] The plurality of first source switches ST1 and the plurality of second source switches ST2 sequentially transfer the image data of each color output from the adjacent latches LT1 to LT6 to the plurality of red digital-to-analog converters DACr1 and DACr2, the plurality of green digital-to-analog converters DACg1 and DACg2, and the plurality of blue digital-to-analog converters DACb1 and DACb2 at different timings according to first and second source enable signals SOE1 and SOE2.

[0053] For example, according to the first source enable signal SOE1, the plurality of first source switches ST1 may sequentially transmit the first, third, and fifth red image data R1, R3, and R5 of the first latch LT1 to the first red digital-to-analog converter DACr1, may sequentially transmit the first, third, and fifth blue image data B1, B3, B5 of the third latch LT3 to the first blue digital-to-analog converter DACb1, and may sequentially transmit the second, fourth, and sixth green image data G2, G4, and G6 of the fifth latch LT5 to the second green digital-to-analog converter DACg2.

[0054] According to the second source enable signal SOE2, the plurality of second source switches ST2 may sequentially transmit the first, third, and fifth green image data G1, G3, and G5 of the second latch LT2 to the first green digital-to-analog converter DACg1, may sequentially transmit the second, fourth, and sixth red image data R2, R4, and R6 of the fourth latch LT4 to the second red digital-to-analog converter DACr2, and may sequentially transmit the second, fourth, and sixth blue image data B2, B4, B6 of the sixth latch LT6 to the second blue digital-to-analog converter DACb2.

[0055] The plurality of red digital-to-analog converters DACr1 and DACr2, the plurality of green digital-to-analog converters DACg1 and DACg2, and the plurality of blue digital-to-analog converters DACb1 and DACb2 convert the image data input from the plurality of latches LT1 to LT6 into a data voltage and sequentially output the data voltage.

[0056] For example, the first red digital-to-analog converter DACr1 can convert the first, third, and fifth red image data R1, R3, and R5 of the first latch LT1 into first, third, and fifth red data voltages Vr1, Vr3, and Vr5, and can transmit the first, third, and fifth red data voltages Vr1, Vr3, and Vr5 to the first line driver BF1. The first green digital-to-analog converter DACg1 can convert the first, third, and fifth green image data G1, G3, and G5 of the second latch LT2 into first, third, and fifth green data voltages Vg1, Vg3, and Vg5, and can transmit the first, third, and fifth green data voltages Vg1, Vg3, and Vg5 to the first line driver BF1.The first blue digital-to-analog converter DACb1 can convert the first, third, and fifth blue image data B1, B3, and B5 of the third latch LT3 into first, third, and fifth blue data voltages Vb1, Vb3, and Vb5, and can transmit the first, third, and fifth blue data voltages Vb1, Vb3, and Vb5 to the second line driver BF2. The second red digital-to-analog converter DACr2 can convert the second, fourth, and sixth red image data R2, R4, and R6 of the fourth latch LT4 into second, fourth, and sixth red data voltages Vr2, Vr4, and Vr6, and can transmit the second, fourth, and sixth red data voltages Vr2, Vr4, and Vr6 to the second line driver BF2.The second green digital-to-analog converter DACg2 can convert the second, fourth, and sixth green image data G2, G4, and G6 of the fifth latch LT5 into second, fourth, and sixth green data voltages Vg2, Vg4, and Vg6, and can transmit the second, fourth, and sixth green data voltages Vg2, Vg4, and Vg6 to the third line driver BF3. The second blue digital-to-analog converter DACb2 can convert the second, fourth, and sixth blue image data B2, B4, and B6 of the sixth latch LT6 into second, fourth, and sixth blue data voltages Vb2, Vb4, and Vb6, and can transmit the second, fourth, and sixth blue data voltages Vb2, Vb4, and Vb6 to the third line driver BF3.

[0057] The plurality of line drivers BF1, BF2, BF3 stabilize the plurality of data voltages received from the plurality of red digital-to-analog converters DACr1 and DACr2, the plurality of green digital-to-analog converters DACg1 and DACg2, and the plurality of blue digital-to-analog converters DACb1 and DACb2, and output the plurality of data voltages sequentially through an output terminal (one channel).

[0058] For example, the first line driver BF1 can sequentially output the first red, first green, third red, third green, fifth red, and fifth green data voltages Vr1, Vg1, Vr3, Vg3, Vr5, and Vg5 of the first red digital-to-analog converter DACr1 and the first green digital-to-analog converter DACg1 via a first output terminal. The second line driver BF2 can sequentially output the first blue, second red, third blue, fourth red, fifth blue, and sixth red data voltages Vb1, Vr2, Vb3, Vr4, Vb5, and Vr6 of the first blue digital-to-analog converter DACb1 and the second red digital-to-analog converter DACr2 via a second output terminal. The third line driver BF3 can sequentially output the second green, second blue, fourth green, fourth blue, sixth green and sixth blue data voltages Vg2, Vb2, Vg4, Vb4, Vg6, Vb6 of the second green digital-to-analog converter DACg2 and the second blue digital-to-analog converter DACb2 via a third output terminal.

[0059] The plurality of first MUX switches MT1 and the plurality of second MUX switches MT2 sequentially transmit the plurality of data voltages output from the plurality of line drivers BF1, BF2, BF3 to the plurality of data lines DL according to first and second MUX signals MUX1 and MUX2.

[0060] For example, according to the first MUX signal MUX1, the plurality of first MUX switches MT1 may sequentially transmit the first, third, and fifth red data voltages Vr1, Vr3, and Vr5 of the first line driver BF1 to a first data line, may sequentially transmit the first, third, and fifth blue data voltages Vb1, Vb3, Vb5 of the second line driver BF2 to a third data line, and may sequentially transmit the second, fourth, and sixth green data voltages Vg2, Vg4, and Vg6 of the third line driver BF3 to a fifth data line.

[0061] According to the second MUX signal MUX2, the plurality of second MUX switches MT2 can sequentially transmit the first, third and fifth green data voltages Vg1, Vg3 and Vg5 of the first line driver BF1 to a second data line, can sequentially transmit the second, fourth and sixth red data voltages Vr2, Vr4 and Vr6 of the second line driver BF2 to a fourth data line, and can sequentially transmit the second, fourth and sixth blue data voltages Vb2, Vb4, Vb6 of the third line driver BF3 to a sixth data line.

[0062] The plurality of red subpixels SPr, the plurality of green subpixels SPg, and the plurality of blue subpixels SPb display an image using the plurality of data voltages transmitted through the plurality of first MUX switches MT1, the plurality of second MUX switches MT2, and the plurality of data lines DL.

[0063] Each of the red, green and blue subpixels SPr, SPg, SPb is connected to the data line DL and the gate line GL, so that the source electrode and the gate electrode of the first transistor T1 (of Fig. 2) in each of the red, green and blue subpixels SPr, SPg, SPb are connected to the data line DL and the gate line GL, respectively.

[0064] For example, the first red, first green, first blue, second red, second green, and second blue subpixels SPr1, SPg1, SPb1, SPr2, SPg2, SPb2 in a first horizontal pixel row may emit light with a luminance corresponding to the first red, first green, first blue, second red, second green, and second blue data voltages Vr1, Vg1, Vb1, Vr2, Vg2, Vb2, respectively. The third red, third green, third blue, fourth red, fourth green, and fourth blue subpixels SPr3, SPg3, SPb3, SPr4, SPg4, SPb4 in a second horizontal pixel row may emit light with a luminance corresponding to the third red, third green, third blue, fourth red, fourth green, and fourth blue data voltages Vr3, Vg3, Vb3, Vr4, Vg4, Vb4, respectively.The fifth red, fifth green, fifth blue, sixth red, sixth green and sixth blue subpixels SPr5, SPg5, SPb5, SPr6, SPg6, SPb6 in a third horizontal pixel row can emit light with a luminance corresponding to the fifth red, fifth green, fifth blue, sixth red, sixth green and sixth blue data voltages Vr5, Vg5, Vb5, Vr6, Vg6, Vb6, respectively.

[0065] In Fig. 4, during a first time period TP1, the (n-1)th gate voltage Scan(n-1) has a low level voltage, and the eighth and tenth transistors T8 and T10 are turned on, so that the first and second electrodes of the storage capacitor Cst have the initialization voltage Vini and the reference voltage Vref, respectively. As a result, the storage capacitor Cst is initialized.

[0066] During a second time period TP2 following the first time period TP1, the nth gate voltage Scan(n) has a low level voltage, and the first, fifth, sixth, and ninth transistors T1, T5, T6, and T9 are turned on, so that the first electrode of the storage capacitor Cst has a sum (Vdata+Vth) of the data voltage Vdata and a threshold voltage Vth, and the second electrode of the storage capacitor Cst has the reference voltage Vref. As a result, the storage capacitor Cst stores a compensated data voltage.

[0067] During a third time period TP3 between the first and second time periods TP1 and TP2, the first MUX signal MUX1 has a low voltage level, and the plurality of first MUX transistors MT1 are turned on. During a fifth time period TP5, which is longer than and overlaps the third time period TP3, the first, third, and fifth red image data R1, R3, and R5 (RGB1 (R)) of the first latch LT1 are input. As a result, during the fifth time period TP5, the first, third, and fifth red data voltages Vr1, Vr3, and Vr5 are sequentially transmitted to the first, third, and fifth red subpixels SPr1, SPr3, and SPr5 of the first, second, and third horizontal pixel rows.

[0068] During a fourth time period TP4, which follows the third time period TP3 and overlaps the second time period TP2, the second MUX signal MUX2 has a low voltage level, and the plurality of second MUX transistors MT2 are turned on. During a sixth time period TP6, which is longer than and overlaps the fourth time period TP4, the first, third, and fifth green image data G1, G3, and G5 (RGB2(G)) of the second latch LT2 are input. As a result, during the sixth time period TP6, the first, third, and fifth green data voltages Vg1, Vg3, and Vg5 are sequentially transmitted to the first, third, and fifth green subpixels SPg1, SPg3, and SPg5 of the first, second, and third horizontal pixel rows, respectively.

[0069] Accordingly, in the first horizontal pixel row, during the fifth time period TP5, the first red, first blue, and second green data voltages Vr1, Vb1, and Vg2 are simultaneously transmitted to the first red, first blue, and second green subpixels SPr1, SPb1, and SPg2. In the first horizontal pixel row, during the sixth time period TP6 after the fifth time period TP5, the first green, second red, and second blue data voltages Vg1, Vr2, and Vb2 are simultaneously transmitted to the first green, second red, and second blue subpixels SPg1, SPr2, and SPb2.

[0070] In the second horizontal pixel row, during the fifth time period TP5, the third red, third blue, and fourth green data voltages Vr3, Vb3, Vg4 are simultaneously transmitted to the third red, third blue, and fourth green subpixels SPr3, SPb3, SPg4. In the second horizontal pixel row, during the sixth time period TP6 after the fifth time period TP5, the third green, fourth red, and fourth blue data voltages Vg3, Vr4, Vb4 are simultaneously transmitted to the third green, fourth red, and fourth blue subpixels SPg3, SPr4, SPb4.

[0071] In the third horizontal pixel row, during the fifth time period TP5, the fifth red, fifth blue, and sixth green data voltages Vr5, Vb5, Vg6 are simultaneously transmitted to the fifth red, fifth blue, and sixth green subpixels SPr5, SPb5, SPg6, respectively. In the third horizontal pixel row, during the sixth time period TP6, after the fifth time period TP5, the fifth green, sixth red, and sixth blue data voltages Vg5, Vr6, Vb6 are simultaneously transmitted to the fifth green, sixth red, and sixth blue subpixels SPg5, SPr6, SPb6, respectively.

[0072] In Fig. 5, for each of the plurality of horizontal pixel rows, first, the data voltage is transmitted to a left subpixel of two adjacent subpixels of the red, green and blue subpixels SPr, SPg, SPb, and second, the data voltage is transmitted to a right subpixel of two adjacent subpixels of the red, green and blue subpixels SPr, SPg, SPb.

[0073] In the display device 110 according to a first embodiment of the present disclosure, the plurality of data voltages sequentially output from one output terminal (one channel) of the data driving part 130 are sequentially transmitted to the two adjacent subpixels in one horizontal pixel row through the plurality of first MUX switches MT1 and the plurality of second MUX switches MT2 of the display panel 150.

[0074] Accordingly, since a number of output terminals (a number of pins) of the data driving part 130 is reduced, a number of required data driving parts (integrated circuits) 130 is reduced and the manufacturing cost is reduced.

[0075] In the display device 110 according to a first embodiment of the present disclosure, the data voltages are applied to the subpixels of the two adjacent pixels of the plurality of horizontal pixel lines in a zigzag shape, as shown in the Fig. 3 and Fig. 5 is shown.

[0076] In all of the plurality of horizontal pixel rows, the data voltage is first applied to the left subpixel of the two adjacent subpixels and second applied to the right subpixel of the two adjacent subpixels. Since a charging time of the data voltage first applied to the left subpixel is longer than a charging time of the data voltage second applied to the right subpixel, the data voltage first applied to the left subpixel can emit light with a luminance higher than the luminance of the light emitted by the data voltage second applied to the right subpixel.

[0077] Since a difference in the supply sequence of the data voltage causes a difference in the charging level of the data voltage and a deviation in the luminance, deterioration such as a vertical line spot may occur.

[0078] When performing optical compensation using a luminance detection device such as a camera for the display device 110 according to a first embodiment of the present disclosure, it is necessary to consider luminance unevenness due to luminance deviation, as shown in Fig. 5. Consequently, there is a limitation that a luminance detector has a first resolution corresponding to the subpixel.

[0079] Fig. 6 is a view showing a parasitic capacitance between a transmission line and a data line of a display device according to a first embodiment of the present disclosure.

[0080] In Fig. 6, to simplify the control elements of each subpixel, first nodes N1 of adjacent red, green, and blue subpixels SPr, SPg, SPb are connected to each other via a transmission line TL, and the reference voltage Vref is applied to a pair of ninth and tenth transistors T9 and T10 of the red, green, and blue subpixels SPr, SPg, SPb. As a result, the transmission line TL and the data line DL of each subpixel overlap, forming a parasitic capacitance Cpara.

[0081] During a period in which the light-emitting diode Del does not emit light due to a duty cycle, the seventh transistor T7 is turned off according to the emission voltage Em(n) corresponding to an off state, and the high level voltage VDD is not applied to the first node N1, so that the first node N1 has a floating state.

[0082] Accordingly, after the first red, first blue, and second green data voltages Vr1, Vb1, Vg2 are transmitted via the data line DL during the third time period TP3, during the fourth time period TP4 in which the first green, second red, and second blue data voltages Vg1, Vr2, Vb2 are transmitted via the data line DL, the first red, first blue, and second green data voltages Vr1, Vb1, Vg2 charged in the subpixel are changed due to coupling of the first green, second red, and second blue data voltages Vg1, Vr2, Vb2 by the parasitic capacitance Cpara to cause a difference in color perception.

[0083] In a display device according to a second embodiment of the present disclosure, the above disadvantages can be improved by sequentially transmitting a data voltage to subpixels of the same color via first and second MUX switches.

[0084] Fig. 7 is a view showing a data driving part and a display panel of a display device according to a second embodiment of the present disclosure, Fig. 8 is a view showing a plurality of signals of a data driving part and a display panel of a display device according to a second embodiment of the present disclosure, and Fig. 9 is a view showing a supply sequence of a data voltage to a plurality of subpixels of a display device according to a second embodiment of the present disclosure. Explanation of parts identical to those of the first embodiment will be omitted.

[0085] In Fig. 7, a data control part 230 of a display device 210 (see Fig. 12B) according to a second embodiment of the present disclosure, a plurality of latches LT1 to LT6, a plurality of first source switches ST1, a plurality of second source switches ST2, a red digital-to-analog converter DACr1, a green digital-to-analog converter DACg1, a blue digital-to-analog converter DACb1, and a plurality of line drivers BF1, BF2, BF3, each connected between the plurality of digital-to-analog converters DACr1, DACg1, and DACb1 and a plurality of output terminals. The display panel 250 of the display device 210 according to a second embodiment of the present disclosure may include a plurality of first MUX switches MT1, a plurality of second MUX switches MT2, a plurality of red subpixels SPr, a plurality of green subpixels SPg, and a plurality of blue subpixels SPb.

[0086] The data drive part 230 may be connected to a non-display area surrounding a display area of ​​the display panel 250. The plurality of first MUX switches MT1 and the plurality of second MUX switches MT2 may be arranged in the non-display area of ​​the display panel 250.

[0087] The plurality of latches LT1 to LT6 sequentially receive image data of each color from a timing control section and store the image data of each color for a time corresponding to one clock. Next, the plurality of latches LT1 to LT6 sequentially output the image data of each color to the red digital-to-analog converter DACr1, the green digital-to-analog converter DACg1, and the blue digital-to-analog converter DACb1, respectively, via the plurality of first source switches ST1 and the plurality of second source switches ST2.

[0088] For example, first, third and fifth red image data R1, R3 and R5 may be sequentially input to and output from the first latch LT1, second, fourth and sixth red image data R2, R4 and R6 may be sequentially input to and output from the second latch LT2, and first, third and fifth green image data G1, G3 and G5 may be sequentially input to and output from the third latch LT3.Second, fourth and sixth green image data G2, G4 and G6 can be sequentially inputted into and outputted from the fourth latch LT4, first, third and fifth blue image data B1, B3, B5 can be sequentially inputted into and outputted from the fifth latch LT5, and second, fourth and sixth blue image data B2, B4, B6 can be sequentially inputted into and outputted from the sixth latch LT6.

[0089] The plurality of first source switches ST1 and the plurality of second source switches ST2 sequentially transfer the image data of each color output from the adjacent latches LT1 to LT6 to the red digital-to-analog converter DACr1, the green digital-to-analog converter DACg1, and the blue digital-to-analog converter DACb1 at different timings according to the first and second source enable signals SOE1 and SOE2, respectively.

[0090] For example, the plurality of first source switches ST1 may sequentially transmit the first, third, and fifth red image data R1, R3, and R5 of the first latch LT1 to the first red digital-to-analog converter DACr1 according to the first source enable signal SOE1, may sequentially transmit the first, third, and fifth green image data G1, G3, and G5 of the third latch LT3 to the first green digital-to-analog converter DACg1, and may sequentially transmit the first, third, and fifth blue image data B1, B3, B5 of the fifth latch LT5 to the first blue digital-to-analog converter DACb1.

[0091] According to the second source enable signal SOE2, the plurality of second source switches ST2 may sequentially transmit the second, fourth, and sixth red image data R2, R4, and R6 of the second latch LT2 to the first red digital-to-analog converter DACr1, may sequentially transmit the second, fourth, and sixth green image data G2, G4, and G6 of the fourth latch LT4 to the first green digital-to-analog converter DACg1, and may sequentially transmit the second, fourth, and sixth blue image data B2, B4, B6 of the sixth latch LT6 to the first blue digital-to-analog converter DACb1.

[0092] The red digital-to-analog converter DACr1, the green digital-to-analog converter DACg1, and the blue digital-to-analog converter DACb1 convert the image data input from the plurality of latches LT1 to LT6 into a data voltage and output the data voltage sequentially.

[0093] For example, the first red digital-to-analog converter DACr1 may convert the first, second, fourth, third, fifth, and sixth red image data R1, R2, R4, R3, R5, and R6 of the first and second latches LT1 and LT2 into first, second, third, fifth, and sixth red data voltages Vr1, Vr2, Vr4, Vr3, Vr5, Vr6, and transmit the first, second, fourth, third, fifth, and sixth red data voltages Vr1, Vr2, Vr4, Vr3, Vr5, Vr6 to the first line driver BF1. The first green digital-to-analog converter DACg1 can convert the first, second, fourth, third, fifth, and sixth green image data G1, G2, G4, G3, G5, and G6 of the third and fourth latches LT3 and LT4 into first, second, fourth, third, fifth, and sixth green data voltages Vg1, Vg2, Vg4, Vg3, Vg5, Vg6, and transmit the first, second, fourth, third, fifth, and sixth green data voltages Vg1, Vg2, Vg4, Vg3, Vg5, Vg6 to the second line driver BF2.The first blue digital-to-analog converter DACb1 can convert the first, second, fourth, third, fifth, and sixth blue image data B1, B2, B4, B3, B5, B6 of the fifth and sixth latches LT5 and LT6 into first, second, fourth, third, fifth, and sixth blue data voltages Vb1, Vb2, Vb4, Vb3, Vb5, Vb6, and can transmit the first, second, fourth, third, fifth, and sixth blue data voltages Vb1, Vb2, Vb4, Vb3, Vb5, Vb6 to the third line driver BF3.

[0094] The plurality of line drivers BF1, BF2, BF3 stabilize the plurality of data voltages received from the red digital-to-analog converter DACr1, the green digital-to-analog converter DACg1, and the blue digital-to-analog converter DACb1, and output the plurality of data voltages sequentially through an output terminal (one channel).

[0095] For example, the first line driver BF1 can sequentially output the first, second, fourth, third, fifth, and sixth red data voltages Vr1, Vr2, Vr4, Vr3, Vr5, Vr6 of the first red digital-to-analog converter DACr1 via a first output terminal. The second line driver BF2 can sequentially output the first, second, fourth, third, fifth, and sixth green data voltages Vg1, Vg2, Vg4, Vg3, Vg5, Vg6 of the first green digital-to-analog converter DACg1 via a second output terminal. The third line driver BF3 can sequentially output the first, second, fourth, third, fifth, and sixth blue data voltages Vb1, Vb2, Vb4, Vb3, Vb5, Vb6 of the first blue digital-to-analog converter DACb1 via a third output terminal.

[0096] The plurality of first MUX switches MT1 and the plurality of second MUX switches MT2 sequentially transmit the plurality of data voltages output from the plurality of line drivers BF1, BF2, BF3 to the plurality of data lines DL according to the first and second MUX signals MUX1 and MUX2. In one embodiment, the plurality of first MUX switches MT1 and the plurality of second MUX switches MT2 may sequentially transmit the first, second, third, fourth, fifth, and sixth red image data R1 to R6 to the first red digital-to-analog converter DACr1, may sequentially transmit the first, second, third, fourth, fifth, and sixth green image data G1 to G6 to the first green digital-to-analog converter DACg1, and may sequentially transmit the first, second, third, fourth, fifth, and sixth blue image data B1 to B6 to the first blue digital-to-analog converter DACb1.

[0097] For example, the plurality of first MUX switches MT1 may sequentially transmit the first, third, and fifth red data voltages Vr1, Vr3, Vr5 of the first line driver BF1 to a first data line according to the first MUX signal MUX1, may transmit the first, third, and fifth green data voltages Vg1, Vg3, Vg5 of the second line driver BF2 to a second data line, and may transmit the first, third, and fifth blue data voltages Vb1, Vb3, Vb5 of the third line driver BF3 to a third data line.

[0098] According to the second MUX signal MUX2, the plurality of second MUX switches MT2 can sequentially transmit the second, fourth and sixth red data voltages Vr2, Vr4, Vr6 of the first line driver BF1 to a fourth data line, can sequentially transmit the second, fourth and sixth green data voltages Vg2, Vg4, Vg6 of the second line driver BF2 to a fifth data line, and can sequentially transmit the second, fourth and sixth blue data voltages Vb2, Vb4, Vb6 of the third line driver BF3 to a sixth data line.

[0099] The plurality of red subpixels SPr, the plurality of green subpixels SPg, and the plurality of blue subpixels SPb display an image using the plurality of data voltages transmitted via the plurality of first MUX switches MT1, the plurality of second MUX switches MT2, and the plurality of data lines DL.

[0100] For example, the first red, first green, first blue, second red, second green, and second blue subpixels SPr1, SPg1, SPb1, SPr2, SPg2, SPb2 in a first horizontal pixel row may emit light with a luminance corresponding to the first red, first green, first blue, second red, second green, and second blue data voltages Vr1, Vg1, Vb1, Vr2, Vg2, Vb2, respectively. The third red, third green, third blue, fourth red, fourth green, and fourth blue subpixels SPr3, SPg3, SPb3, SPr4, SPg4, SPb4 in a second horizontal pixel row may emit light with a luminance corresponding to the third red, third green, third blue, fourth red, fourth green, and fourth blue data voltages Vr3, Vg3, Vb3, Vr4, Vg4, Vb4, respectively.The fifth red, fifth green, fifth blue, sixth red, sixth green and sixth blue subpixels SPr5, SPg5, SPb5, SPr6, SPg6, SPb6 in a third horizontal pixel row can emit light with a luminance corresponding to the fifth red, fifth green, fifth blue, sixth red, sixth green and sixth blue data voltages Vr5, Vg5, Vb5, Vr6, Vg6, Vb6, respectively.

[0101] In Fig. During a first time period TP1, the (n-1)th gate voltage Scan(n-1) of the transistor 8 has a low level voltage, and the eighth and tenth transistors T8 and T10 are turned on, so that the first and second electrodes of a storage capacitor Cst have an initialization voltage Vini and a reference voltage Vref, respectively. As a result, the storage capacitor Cst is initialized.

[0102] During a second time period TP2 following the first time period TP1, an nth gate voltage Scan(n) has a low voltage level, and the first, fifth, sixth, and ninth transistors T1, T5, T6, and T9 are turned on, so that the first electrode of the storage capacitor Cst has a sum (Vdata+Vth) of the data voltage Vdata and a threshold voltage Vth, and the second electrode of the storage capacitor Cst has the reference voltage Vref. As a result, the storage capacitor Cst stores a compensated data voltage.

[0103] During a third time period TP3, which is longer than and overlaps the first time period TP1, the first MUX signal MUX1 has a low voltage level, and the plurality of first MUX transistors MT1 are turned on. During a fifth time period TP5, which overlaps the third time period TP3, the first, third, and fifth red image data R1, R3, and R5 (RGB1(R)) of the first latch LT1 are input. As a result, during the fifth time period TP5, the first, third, and fifth red data voltages Vr1, Vr3, Vr5 are sequentially transmitted to the first, third, and fifth red subpixels SPr1, SPr3, and SPr5 of the first, second, and third horizontal pixel rows, respectively.

[0104] During a fourth time period TP4, which follows the third time period TP3 and overlaps the second time period TP2, the second MUX signal MUX2 has a low voltage level, and the plurality of second MUX transistors MT2 are turned on. During a sixth time period TP6, which overlaps the fourth time period TP4, the second, fourth, and sixth red image data R2, R4, and R6 (RGB2(R)) of the second latch LT2 are input. As a result, the second, fourth, and sixth red data voltages Vr2, Vr4, and Vr6 are sequentially transmitted to the second, fourth, and sixth red subpixels SPr2, SPr4, and SPr6 of the first, second, and third horizontal pixel rows, respectively.

[0105] Accordingly, in the first horizontal pixel row, during the fifth time period TP5, the first red, first green, and first blue data voltages Vr1, Vg1, Vb1 are simultaneously transmitted to the first red, first green, and first blue subpixels SPr1, SPg1, SPb1. In the first horizontal pixel row, during the sixth time period TP6 after the fifth time period TP5, the second red, second green, and second blue data voltages Vr2, Vg2, Vb2 are simultaneously transmitted to the second red, second green, and second blue subpixels SPr2, SPg2, SPb2.

[0106] In the second horizontal pixel row, during the fifth time period TP5, the fourth red, fourth green, and fourth blue data voltages Vr4, Vg4, Vb4 are simultaneously transmitted to the fourth red, fourth green, and fourth blue subpixels SPr4, SPg4, SPb4. In the second horizontal pixel row, during the sixth time period TP6 after the fifth time period TP5, the third red, third green, and third blue data voltages Vr3, Vg3, Vb3 are simultaneously transmitted to the third red, third green, and third blue subpixels SPr3, SPg3, SPb3.

[0107] In the third horizontal pixel row, during the fifth time period TP5, the fifth red, fifth green, and fifth blue data voltages Vr5, Vg5, Vb5 are simultaneously transmitted to the fifth red, fifth green, and fifth blue subpixels SPr5, SPg5, SPb5. In the third horizontal pixel row, during the sixth time period TP6, after the fifth time period TP5, the sixth red, sixth green, and sixth blue data voltages Vr6, Vg6, Vb6 are simultaneously transmitted to the sixth red, sixth green, and sixth blue subpixels SPr6, SPg6, SPb6.

[0108] In the display device 210 according to a second embodiment of the present disclosure, the data voltages are applied to the subpixels of the two adjacent pixels of the plurality of horizontal pixel lines with a rectangular waveform, as shown in the Fig. 7 and Fig. 9 shown.

[0109] For an odd-numbered horizontal pixel row comprising a first, third, and fifth horizontal pixel row, the data voltage is first transmitted to the red, green, and blue subpixels SPr, SPg, SPb of a left pixel of two adjacent pixels, and the data voltage is second transmitted to the red, green, and blue subpixels SPr, SPg, SPb of a right pixel of two adjacent pixels. For an even-numbered horizontal pixel row comprising a second, fourth, and sixth horizontal pixel row, the data voltage is first transmitted to the red, green, and blue subpixels SPr, SPg, SPb of a right pixel of two adjacent pixels, and the data voltage is second transmitted to the red, green, and blue subpixels SPr, SPg, SPb of a left pixel of two adjacent pixels.

[0110] Since a charging time of the first applied data voltage is longer than a charging time of the second applied data voltage, the first applied data voltage can emit light with a luminance greater than the luminance of light emitted by the second applied data voltage. However, since the data voltage application sequences are opposite to each other with respect to the odd horizontal pixel row and the even horizontal pixel row, high luminance and low luminance are evenly mixed throughout the display panel 250, and luminance variation is minimized.

[0111] In the display device 210 according to a second embodiment of the present disclosure, the plurality of data voltages sequentially output from one output terminal (one channel) of the data driving part 230 are sequentially transmitted to the two subpixels of the same color of the two adjacent pixels in the same horizontal pixel row via the plurality of first MUX switches MT1 and the plurality of second MUX switches MT2 of the display panel 250.

[0112] Since a number of output terminals (a number of pins) of the data driving part 230 is reduced and a number of digital-to-analog converters is reduced, a number of required data driving parts (integrated circuits) 230 is reduced and the manufacturing cost is reduced.

[0113] Since in Fig. 9 The application sequence of the data voltage to the two subpixels of the same color of the two adjacent pixels of the odd horizontal pixel row is opposite to the application sequence of the data voltage to the two subpixels of the same color of the two adjacent pixels of the even horizontal pixel row, the application sequences of the data voltage to the entire display panel 250 become uniform. As a result, the luminance deviation is reduced, and deterioration such as vertical line spot is prevented.

[0114] Furthermore, when optical compensation is performed using a luminance detection device such as a camera for the display device 210 according to a second embodiment of the present disclosure, it is not necessary to compensate for luminance unevenness due to luminance deviation as shown in Fig. 9. As a result, a luminance detector having a second resolution lower than a first resolution corresponding to the subpixel can be used for optical compensation, and a limitation on a luminance detector is removed.

[0115] Fig. 10 is a plan view showing red, green, and blue subpixels of a display device according to a second embodiment of the present disclosure, and Fig. 11 is a view showing a parasitic capacitance between a transmission line and a data line of a display device according to a second embodiment of the present disclosure.

[0116] In the Fig. 10 and Fig. 11, the display device 210 according to a second embodiment of the present disclosure includes the red, green, and blue subpixels SPr, SPg, SPb, and each of the red, green, and blue subpixels SPr, SPg, SPb includes first to tenth transistors T1 to T10, a storage capacitor Cst, and a light-emitting diode Del.

[0117] The first transistor T1 as a switching transistor can be connected between the data voltage Vdata and the second and fourth transistors T2 and T4 and can be switched according to an (n)-th gate voltage Scan(n).

[0118] The second transistor T2 as a driver transistor can be connected between the first and fourth transistors T1 and T4 and the third and fifth transistors T3 and T5 and can be switched depending on a voltage of a first electrode of the storage capacitor Cst.

[0119] The third transistor T3 may be connected between the second and fifth transistors T2 and T5 and the sixth transistor T6 and the light-emitting diode Del and may be switched in dependence on an (n)-th emission voltage Em(n).

[0120] The fourth transistor T4 may be connected between the first and second transistors T1 and T2 and the seventh transistor T7 and the high level voltage VDD and may be switched according to an (n)-th emission voltage Em(n).

[0121] The fifth transistor T5 may be connected between the second and third transistors T2 and T3 and the eighth transistor T8 and may be switched according to an (n)-th gate voltage Scan(n).

[0122] The sixth transistor T6 may be connected between the third transistor T3 and the eighth transistor T8 and may be switched according to an (n)-th gate voltage Scan(n).

[0123] The seventh transistor T7 may be connected between the fourth transistor T4 and the high level voltage VDD and the storage capacitor Cst and the ninth and tenth transistors T9 and T10 and may be switched according to an (n)-th emission voltage Em(n).

[0124] The eighth transistor T8 can be connected between the storage capacitor Cst and the sixth transistor T6 and the initialization voltage Vini and can be switched according to an (n-1)-th gate voltage Scan(n-1).

[0125] The ninth transistor T9 may be connected between the storage capacitor Cst, the seventh and tenth transistors T7 and T10 and the reference voltage Vref and may be switched according to an (n)-th gate voltage Scan(n).

[0126] The tenth transistor T10 may be connected between the storage capacitor Cst, the seventh and ninth transistors T7 and T9 and the reference voltage Vref and may be switched according to an (n-1)-th gate voltage Scan(n-1).

[0127] In the display device 210, to simplify the control elements, first nodes N1 of the adjacent red, green, and blue subpixels SPr, SPg, SPb are connected via a transmission line TL, and the reference voltage Vref is supplied to the red, green, and blue subpixels SPr, SPg, SPb via a pair of ninth and tenth transistors T9 and T10. As a result, the transmission line TL and the data line DL of each of the red, green, and blue subpixels SPr, SPg, SPb overlap, forming a parasitic capacitance Cpara.

[0128] Here, the first node N1 is in a floating state during a period in which the LED Del does not emit light due to a duty cycle. However, after the first red, first green, and first blue data voltages Vr1, Vg1, Vb1 are simultaneously transmitted to the first red, first green, and first blue subpixels SPr1, SPg1, SPb1, respectively, via the data line DL during the third time period TP3, the second red, second green, and second blue data voltages Vr2, Vg2, Vb2 are simultaneously transmitted to the second red, second green, and second blue subpixels SPr2, SPg2, SPb2, respectively, via the data line DL during the fourth time period TP4. This prevents a situation in which the data voltage charged in the subpixel changes due to coupling of the current data voltage via the parasitic capacitance Cpara.Because the data voltage is transmitted simultaneously to the red, green, and blue subpixels SPr, SPg, SPb of a pixel, coupling via the parasitic capacitance Cpara between the transmission line TL, which is typically connected to the pixel, and the data line DL of the red, green, and blue subpixels SPr, SPg, SPb is prevented. This prevents fluctuations in the charged data voltage and minimizes differences in color perception.

[0129] Furthermore, in the display device 210 according to a second embodiment of the present disclosure, a period of the first and second MUX signals MUX1 and MUX2 is lengthened because the application sequences of the data voltage corresponding to the horizontal pixel row are opposite. As a result, power consumption is reduced and the scanning period is shortened.

[0130] A flexible touch-sensitive display device incorporating the display device according to the first and second embodiments of the present disclosure will be explained below.

[0131] Fig. 12A is a view showing a data driving part of a display device according to the first and second embodiments of the present disclosure, Fig. 12B is a view showing a display device according to the first and second embodiments of the present disclosure, and Fig. 12C is a view showing a flexible touch-sensitive display device having a display device according to the first and second embodiments of the present disclosure.

[0132] In Fig. 12A, the data driving part 130 of the display device 110 according to a first embodiment of the present disclosure includes a display driving circuit DIC in the form of a single integrated circuit (IC) and a chip on film (COF) on which the integrated circuit is mounted, and the data driving part 230 of the display device 210 according to a second embodiment of the present disclosure includes a display driving circuit DIC and a touch driving circuit TIC in the form of a single integrated circuit (IC) and a chip on film (COF) on which the integrated circuit is mounted.

[0133] Since the display drive circuit DIC of the data drive section 230 according to a second embodiment has a smaller number of digital-to-analog converters compared to the display drive circuit DIC of the data drive section 130 according to a first embodiment, the display drive circuit DIC of the data drive section 230 according to a second embodiment has a smaller size compared to the display drive circuit DIC of the data drive section 130 according to a first embodiment. As a result, a remaining space can be utilized for the touch drive circuit TIC, and the display drive circuit DIC and the touch drive circuit TIC can be formed as a single integrated circuit.

[0134] In the display device 110 according to a first embodiment of the present disclosure of Fig. 12B, the display driver, which includes the data driver 130 for image display and a first printed circuit board PCB1, is connected to an upper portion of the display panel, and the touch driver, which includes a touch driver for touch sensing and a second printed circuit board PCB2, is connected to a lower portion of the display panel. The first and second printed circuit boards PCB1 and PCB2 are electrically connected to each other for signal transmission.

[0135] In the display device 210 according to a second embodiment of the present disclosure of Fig. 12B, the touch display driving part including the data driving part 230 for image display and touch detection and a first printed circuit board PCB1 is connected to an upper portion of the display panel, and no printed circuit board is connected to a lower portion of the display panel.

[0136] In Fig. 12C, when the display device 110 according to a first embodiment of the present disclosure is applied to a roll-up type touch-sensitive display device, the first circuit board PCB1 is connected to a rolled-up end portion of the display panel, and the second circuit board PCB2 is connected to a non-roll-up end portion of the display panel.

[0137] The second circuit board PCB2 connected to a rolled-up end portion of the display panel may hinder the function of the roll-up touch-sensitive display device, and difficulties may arise in connecting the first and second circuit boards PCB1 and PCB2.

[0138] When the display device 210 according to a second embodiment of the present disclosure is applied to a rollable touch-sensitive display device, the first circuit board PCB1 may be connected to the rolled-up end portion of the display panel, and no circuit board may be connected to the unrolled end portion of the display panel. As a result, the rollable touch-sensitive display device can operate freely, and the electrical connection of two separate circuit boards can be eliminated.

[0139] Consequently, in the display device according to the present disclosure, since the data voltages sequentially output from an output terminal of the data driving part are supplied to two subpixels of the same color of the display panel using a multiplexer, the number of digital-to-analog converters of the data driving part is reduced, and the size and number of the data driving parts are reduced. As a result, the manufacturing cost is reduced.

[0140] Furthermore, since the data voltages output from the data drive section are sequentially supplied to the subpixels of the same color in the first row and first column, the first row and second column, the second row and second column, and the second row and first column of the display panel using a multiplexer, luminance deviation is reduced and degradation such as vertical line spot is prevented. As a result, luminance uniformity is improved, optical compensation is optimized, and power consumption is reduced by reducing input signal switching to the multiplexer.

Claims

[1] A display device (110, 210) comprising: a timing control part (120) configured to generate image data, a data control signal and a gate control signal; a data drive part (130, 230) configured to generate a data voltage (Vdata) using the image data and the data control signal; a gate drive part (140) configured to generate a gate voltage using the gate control signal; a display panel (150, 250) having a plurality of subpixels (SPr, SPg, SPb) and configured to display an image using the data voltage (Vdata) and the gate voltage; and a plurality of first MUX switches (MT1) and a plurality of second MUX switches (MT2) configured to sequentially transmit the data voltage (Vdata) to two subpixels of a same color from the plurality of subpixels (SPr, SPg, SPb); wherein the data voltage comprises first to sixth red data voltages, first to sixth green data voltages and first to sixth blue data voltages, wherein the plurality of subpixels (SPr, SPg, SPb) comprises first red, first green, first blue, second red, second green and second blue subpixels (SPr1, SPg1, SPb1, SPr2, SPg2, SPb2) in a first horizontal pixel row, third red, third green, third blue, fourth red, fourth green and fourth blue subpixels (SPr3, SPg3, SPb3, SPr4, SPg4, SPb4) in a second horizontal pixel row, and fifth red, fifth green, fifth blue, sixth red, sixth green and sixth blue subpixels (SPr5, SPg5, SPb5, SPr6, SPg6, SPb6) in a third horizontal pixel row, wherein the display device (110, 210) is configured such that, according to a first MUX signal (MUX1), the plurality of first MUX switches (MT1) transmit the first, third, and fifth red data voltages to the first, third, and fifth red subpixels (SPr1, SPr3, SPr5), transmit the first, third, and fifth green data voltages to the first, third, and fifth green subpixels (SPg1, SPg3, SPg5), and transmit the first, third, and fifth blue data voltages to the first, third, and fifth blue subpixels (SPb1, SPb3, SPb5), and wherein the display device (110, 210) is configured such that, according to a second MUX signal (MUX2), the plurality of second MUX switches (MT2) transmit the second, fourth, and sixth red data voltages to the second, fourth, and sixth red subpixels (SPr2, SPr4, SPr6), transmit the second, fourth, and sixth green data voltages to the second, fourth, and sixth green subpixels (SPg2, SPg4, SPg6), and transmit the second, fourth, and sixth blue data voltages to the second, fourth, and sixth blue subpixels (SPb2, SPb4, SPb6); wherein the display device (110, 210) is further configured such that the plurality of first MUX switches (MT1) and the plurality of second MUX switches (MT2) successively transmit the first, second, fourth, third, fifth, and sixth red data voltages to the first, second, fourth, third, fifth, and sixth red subpixels (SPr1, SPr2, SPr4, SPr3, SPr5, SPr6), transmit the first, second, fourth, third, fifth, and sixth green data voltages to the first, second, fourth, third, fifth, and sixth green subpixels (SPg1, SPg2, SPg4, SPg3, SPg5, SPg6), and transmit the first, second, fourth, third, fifth, and sixth blue data voltages to the first, second, fourth, third, fifth, and sixth blue subpixels (SPb1, SPb2, SPb4, SPb3, SPb5, SPb6). [2] The display device (110, 210) according to claim 1, wherein the data drive part (130) comprises: a plurality of latch registers (LT1, ..., LT6) configured to receive and output the image data; a plurality of first source switches (ST1) and a plurality of second source switches (ST2) configured to sequentially transfer the image data output from the plurality of latches (LT1, ..., LT6); and a plurality of digital-to-analog converters (DACr1, DACg1, DACb1, DACr2, DACg2, DACb2) configured to convert the image data transmitted through the plurality of first source switches (ST1) and the plurality of second source switches (ST2) into the data voltage (Vdata) and output the data voltage (Vdata) sequentially. [3] The display device (110, 210) according to claim 2, wherein the data driving part (130, 230) further comprises a plurality of line drivers (BF1, BF2, BF3) connected between the plurality of digital-to-analog converters (DACr1, DACg1, DACb1, DACr2, DACg2, DACb2) and a plurality of output terminals. [4] The display device (110, 210) according to claim 2 or 3, wherein the image data comprises first to sixth red image data (R1, ..., R6), first to sixth green image data (G1, ..., G6), and first to sixth blue image data (B1, ..., B6), and wherein the plurality of digital-to-analog converters comprises a first red digital-to-analog converter (DACr1) configured to receive the first to sixth red image data (R1, ..., R6), a first green digital-to-analog converter (DACg1) configured to receive the first to sixth green image data (G1, ..., G6), and a first blue digital-to-analog converter (DACb1) configured to receive the first to sixth blue image data (B1, ..., B6). [5] The display device (110, 210) according to claim 4, wherein the plurality of latches comprises a first latch (LT1) configured to receive and sequentially output the first, third, and fifth red image data (R1, R3, R5), a second latch (LT2) configured to receive and sequentially output the second, fourth, and sixth red image data (R2, R4, R6), a third latch (LT3) configured to receive and sequentially output the first, third, and fifth green image data (G1, G3, G5), a fourth latch (LT4) configured to receive and sequentially output the second, fourth, and sixth green image data (G2, G4, G6), a fifth latch (LT5) configured to receive the first, third, and fifth blue image data (B1, B3, B5) and output them one after the other, and has a sixth latch (LT6),which is configured to receive and sequentially output the second, fourth and sixth blue image data (B2, B4, B6), wherein the first red digital-to-analog converter (DACr1) is configured to receive the first, third and fifth red image data (R1, R3, R5) of the first latch (LT1) via a first of the first source switches (ST1) and to receive the second, fourth and sixth red image data (R2, R4, R6) of the second latch (LT2) via a first of the second source switches (ST2), wherein the first green digital-to-analog converter (DACg1) is configured to receive the first, third, and fifth green image data (G1, G3, G5) of the third latch (LT3) via a second of the first source switches (ST1) and to receive the second, fourth, and sixth green image data (G2, G4, G6) of the fourth latch (LT4) via a second of the second source switches (ST2), and wherein the first blue digital-to-analog converter (DACb1) is configured to receive the first, third, and fifth blue image data (B1, B3, B5) of the fifth latch (LT5) via a third of the first source switches (ST1) and to receive the second, fourth, and sixth blue image data (B2, B4, B6) of the sixth latch (LT6) via a third of the second source switches (ST2). [6] The display device (110, 210) according to any one of claims 2 to 5, further configured such that the plurality of first source switches (ST1) and the plurality of second source switches (ST2) successively transmit the first, second, third, fourth, fifth, and sixth red image data (R1, ... R6) to the first red digital-to-analog converter (DACr1), successively transmit the first, second, third, fourth, fifth, and sixth green image data (G1, ..., G6) to the first green digital-to-analog converter (DACg1), and successively transmit the first, second, third, fourth, fifth, and sixth blue image data (B1, ..., B6) to the first blue digital-to-analog converter (DACb1). [7] Display device (110, 210) according to one of claims 1 to 6, wherein each of the plurality of subpixels (SPr, SPg, SPb) comprises first to tenth transistors (T1,...,T10), a storage capacitor (Cst) and a light-emitting diode (Del). [8] A method for controlling a display device (110, 210), comprising: Generating image data, a data control signal and a gate control signal; Generating a data voltage (Vdata) using the image data and the data control signal; generating a gate voltage using the gate control signal; sequentially transmitting the data voltage (Vdata) to two subpixels of the same color from the plurality of subpixels (SPr, SPg, SPb) via a plurality of first MUX switches (MT1) and a plurality of second MUX switches (MT2); and Displaying an image using the data voltage (Vdata) and the gate voltage; wherein the data voltage comprises first to sixth red data voltages, first to sixth green data voltages and first to sixth blue data voltages, wherein the plurality of subpixels (SPr, SPg, SPb) comprises first red, first green, first blue, second red, second green and second blue subpixels (SPr1, SPg1, SPb1, SPr2, SPg2, SPb2) in a first horizontal pixel row, third red, third green, third blue, fourth red, fourth green and fourth blue subpixels (SPr3, SPg3, SPb3, SPr4, SPg4, SPb4) in a second horizontal pixel row, and fifth red, fifth green, fifth blue, sixth red, sixth green and sixth blue subpixels (SPr5, SPg5, SPb5, SPr6, SPg6, SPb6) in a third horizontal pixel row, wherein, according to a first MUX signal (MUX1), the plurality of first MUX switches (MT1) transmit the first, third, and fifth red data voltages to the first, third, and fifth red subpixels (SPr1, SPr3, SPr5), the first, third, and fifth green data voltages to the first, third, and fifth green subpixels (SPg1, SPg3, SPg5), and the first, third, and fifth blue data voltages to the first, third, and fifth blue subpixels (SPb1, SPb3, SPb5), and wherein, according to a second MUX signal (MUX2), the plurality of second MUX switches (MT2) transmit the second, fourth, and sixth red data voltages to the second, fourth, and sixth red subpixels (SPr2, SPr4, SPr6), transmit the second, fourth, and sixth green data voltages to the second, fourth, and sixth green subpixels (SPg2, SPg4, SPg6), and transmit the second, fourth, and sixth blue data voltages to the second, fourth, and sixth blue subpixels (SPb2, SPb4, SPb6); wherein the plurality of first MUX switches (MT1) and the plurality of second MUX switches (MT2) sequentially transmit the first, second, fourth, third, fifth and sixth red data voltages to the first, second, fourth, third, fifth and sixth red subpixels (SPr1, SPr2, SPr4, SPr3, SPr5, SPr6), transmit the first, second, fourth, third, fifth and sixth green data voltages to the first, second, fourth, third, fifth and sixth green subpixels (SPg1, SPg2, SPg4, SPg3, SPg5, SPg6), and transmit the first, second, fourth, third, fifth and sixth blue data voltages to the first, second, fourth, third, fifth and sixth blue subpixels (SPb1, SPb2, SPb4, SPb3, SPb5, SPb6).

Images